Analog-to-digital converter and semiconductor storage device having the same

Abstract

An analog-to-digital converter includes a first analog-to-digital conversion unit, which is configured to: during a first analog-to-digital conversion operation: in response to a differential sampling signal pair and a corresponding pair of the first differential signal pair to the n-th differential signal pair among n differential signal pairs, sequentially charge each pair of n first differential node pairs; in response to each pair of the n first differential node pairs being sequentially charged, sequentially generate each pair of n first differential data pairs; and in response to the corresponding pair of the sequentially generated n first differential data pairs, sequentially generate each pair of n upper differential data pairs to be used as n-bit high-order digital data. The first analog-to-digital conversion unit is also configured to: in a second analog-to-digital conversion operation, in response to the n-th differential signal pair among the n differential signal pairs, simultaneously discharge each pair of the n first differential node pairs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0036062 filed on March 25, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to an analog-to-digital converter and a semiconductor memory device having the same. Background Art

[0004] An analog-to-digital converter (ADC) receives an analog signal and converts it into digital data. There are two types of ADCs: successive approximation register (SAR) ADCs and flash ADCs.

[0005] Compared with the flash ADC, the SAR ADC has the advantage of simple configuration, but has the disadvantage of slow operation speed; compared with the SAR ADC, the flash ADC has the advantage of fast operation speed, but has the disadvantage of complex configuration.

[0006] Therefore, various types of ADCs are being developed to improve the respective disadvantages of the SAR ADC and the flash ADC. Summary of the invention

[0007] According to an example embodiment of the inventive concept, an analog-to-digital converter includes a first analog-to-digital conversion unit, which is configured to: during a first analog-to-digital conversion operation: in response to a differential sampling signal pair and a corresponding pair of a first differential signal pair to an n-1th differential signal pair among n differential signal pairs, sequentially charge each of n first differential node pairs; in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs; and in response to the corresponding pair of the sequentially generated n first differential data pairs, sequentially generate each of n upper differential data pairs to be used as n-bit high-order digital data. The first analog-to-digital conversion unit is also configured to: in a second analog-to-digital conversion operation, in response to an nth differential signal pair among the n differential signal pairs, simultaneously discharge each of the n first differential node pairs; and in response to each of the n first differential node pairs being simultaneously discharged, generate n second differential data pairs with different phases or the same phase. The analog-to-digital converter further includes a second analog-to-digital conversion unit, wherein the second analog-to-digital conversion unit is configured to: perform a plurality of phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate (2 n +m) digit thermometer code, m is less than 2 n ; and for the said (2 n+m)-bit thermometer code is encoded to generate at least (n+1)-bit low-order digital data.

[0008] According to an example embodiment of the inventive concept, an analog-to-digital converter includes a sampling and charging and discharging unit, which is configured to: during a sampling operation: sample a differential input signal pair to generate a differential sampling signal pair, and generate the differential sampling signal pair to a first differential node pair; and during a first analog-to-digital conversion operation: in response to each of n upper differential data pairs used as n-bit high-bit digital data and sequentially generated, charge and discharge the first differential node pair to sequentially generate n differential signal pairs from the differential sampling signal pair. The analog-to-digital converter further includes a first analog-to-digital conversion unit, which is configured to: during the first analog-to-digital conversion operation, in response to the differential sampling signal pair and the corresponding pair of the first differential signal pair to the n-1th differential signal pair among the n differential signal pairs, sequentially charge each of the n second differential node pairs; in response to each of the n second differential node pairs being sequentially charged, sequentially generate each of the n first differential data pairs; and in response to the corresponding pair of the sequentially generated n first differential data pairs, sequentially generate each of the n upper differential data pairs. The first analog-to-digital conversion unit is also configured to: during the second analog-to-digital conversion operation, in response to the nth differential signal pair among the n differential signal pairs, simultaneously discharge each of the n second differential node pairs; and in response to each of the n second differential node pairs being simultaneously discharged, generate n second differential data pairs with different phases or the same phase. The analog-to-digital converter further includes a second analog-to-digital conversion unit, wherein the second analog-to-digital conversion unit is configured to: perform a plurality of phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate (2 n +m) digit thermometer code, m is less than 2 n ; and for the said (2 n +m)-bit thermometer code is encoded to generate at least (n+1)-bit low-order digital data.

[0009] According to an example embodiment of the inventive concept, a semiconductor device includes a predetermined number of analog-to-digital converters, each of which is configured to receive a corresponding differential input signal pair of a predetermined number of differential input signal pairs from an external source to generate 2n-bit digital data respectively. Each of the analog-to-digital converters includes a sampling and charging and discharging unit, which is configured to: in a sampling operation: sample the differential input signal pair to generate a differential sampling signal pair; and generate the differential sampling signal pair to a first differential node pair; and during a first analog-to-digital conversion operation: in response to each of the n upper differential data pairs used as n-bit high-bit digital data and sequentially generated, charge and discharge the first differential node pair to sequentially generate n differential signal pairs from the differential sampling signal pair. Each of the analog-to-digital converters further includes a first analog-to-digital conversion unit, which is configured to: during the first analog-to-digital conversion operation, in response to the differential sampling signal pair and the corresponding pair of the first differential signal pair to the n-1th differential signal pair among the n differential signal pairs, sequentially charge each of the n second differential node pairs; in response to each of the n second differential node pairs being sequentially charged, sequentially generate each of the n first differential data pairs; and in response to the corresponding pair of the sequentially generated n first differential data pairs, sequentially generate each of the n upper differential data pairs. The first analog-to-digital conversion unit is also configured to: in the second analog-to-digital conversion operation, in response to the nth differential signal pair among the n differential signal pairs, simultaneously discharge each of the n second differential node pairs; and in response to each of the n second differential node pairs being simultaneously discharged, generate n second differential data pairs with different phases or the same phase. Each of the analog-to-digital converters further includes a second analog-to-digital conversion unit, wherein the second analog-to-digital conversion unit is configured to: perform a plurality of phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate (2 n +m) digit thermometer code, m is less than 2 n ; and for the said (2 n The analog-to-digital converter is configured to encode the n-bit high-order digital data and the at least (n+1)-bit low-order digital data by using the n-bit high-order digital data and the at least (n+1)-bit low-order digital data to generate the 2n-bit digital data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a configuration of an analog-to-digital converter according to an example embodiment of the inventive concept.

[0011] Figure 2 is a circuit diagram illustrating a configuration of a first charger and a second charger and a discharger according to an example embodiment of the inventive concept.

[0012] Figure 3 is a circuit diagram illustrating a configuration of a voltage-to-time converter according to an example embodiment of the inventive concept.

[0013] Figure 4A and Figure 4B are diagrams illustrating configurations and truth tables of latches according to example embodiments of the inventive concepts.

[0014] Figure 5 is an operation timing diagram for describing the operation of an analog-to-digital converter according to an example embodiment of the inventive concept.

[0015] Figure 6 is a conceptual diagram for describing a second analog-to-digital conversion operation and an error correction operation according to an example embodiment of the inventive concept.

[0016] Fig. 7A is a diagram illustrating a configuration of a thermometer code generator according to an example embodiment of the inventive concept.

[0017] Figure 7B is a diagram illustrating a configuration of a phase interpolator according to an example embodiment of the inventive concept.

[0018] Fig. 8A and Figure 8B is a diagram illustrating configurations of fifth and sixth latches according to example embodiments of the inventive concepts.

[0019] Fig. 9 is a block diagram illustrating a configuration of a system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Example embodiments of the present disclosure provide an analog-to-digital converter (ADC) having a simple configuration and a fast operation speed, and a semiconductor memory device having the same.

[0021] Hereinafter, an ADC and a semiconductor memory device having the same according to example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0022] Figure 1 is a block diagram illustrating a configuration of an analog-to-digital converter according to an example embodiment of the inventive concept.

[0023] The analog-to-digital converter 100 may include a sampling and charging and discharging unit 10, a first analog-to-digital conversion unit 20, a second analog-to-digital conversion unit 30, and an error correction unit 40. The sampling and charging and discharging unit 10 may include a first switch SW1 and a second switch SW2, a first charger 10-2 and a second charger 10-4. The first analog-to-digital conversion unit 20 may include first to fourth voltage-time converters (VTC4 to VTC1) 20-22 to 20-28, first to fourth latches (LA4 to LA1) 22-22 to 22-28, and a timing generation unit. The timing generation unit may include first to fourth timing generators (TG4 to TG1) 24-22 to 24-28. The second analog-to-digital conversion unit 30 may include a thermometer code generator 30-2 and an encoder 30-4.

[0024] The following will describe Figure 1 The function of each box is shown.

[0025] The sampling and charge-discharge unit 10 can sample the differential input signal pair VINP, VINM during the sampling operation to generate the differential sampling signal pair VP, VM to the first differential node pair n1p, n1m, and perform charging and discharging operations on the first differential node pair n1p, n1m in response to each of the four upper differential data pairs (CP4, CM4) to (CP1, CM1) generated sequentially during the first analog-to-digital conversion operation, and sequentially generate four differential signal pairs changed from the differential sampling signal pair VP, VM through the first differential node pair n1p, n1m.

[0026] The first switch SW1 and the second switch SW2 may be turned on in response to the sampling clock signal CKS during a sampling operation and transmit the differential input signal pair VINP, VINM to the first differential node pair n1p, n1m to generate a differential sampling signal pair VP, VM.

[0027] The first charger and discharger 10-2 can be connected to one node n1p of the first differential node pair n1p, n1m, and perform a charging operation or a discharging operation in response to each of the four upper differential data pairs (CP4, CM4) to (CP1, CM1) to increase or decrease the level of one node n1p of the first differential node pair n1p, n1m by a level corresponding to the binary weight of each pair.

[0028] The second charger and discharger 10-4 can be connected to the other node n1m of the first differential node pair n1p, n1m, and perform a discharge operation or a charge operation in response to each of the four upper differential data pairs (CP4, CM4) to (CP1, CM1) to reduce or increase the level of the other node n1m of the first differential node pair n1p, n1m by a level corresponding to the binary weight of each pair.

[0029] Here, the ratio of the binary weights of the four upper differential data pairs (CP4, CM4) to (CP1, CM1) may be 8:4:2:1.

[0030] When the first charger and discharger 10 - 2 performs a charging operation, the second charger and discharger 10 - 4 may perform a discharging operation, and when the first charger and discharger 10 - 2 performs a discharging operation, the second charger and discharger 10 - 4 may perform a charging operation.

[0031] During the first analog-to-digital conversion operation, the first analog-to-digital conversion unit 20 may sequentially perform a charging operation on each of the four second differential node pairs in response to the differential sampling signal pair and each of the first differential signal pair to the third differential signal pair among the four differential signal pairs sequentially generated through the first differential node pair n1p, n1m to sequentially generate each of the four first differential data pairs (DP4, DM4) to (DP1, DM1), and sequentially generate each of the four upper differential data pairs (CP4, CM4) to (CP1, CM1) in response to each of the four first differential data pairs (DP4, DM4) to (DP1, DM1). During the second analog-to-digital conversion operation, the first analog-to-digital conversion unit 20 may perform a discharging operation on each of the four second differential node pairs in response to the fourth differential signal pair among the four differential signal pairs to generate four second differential data pairs (dp4, dm4) to (dp1, dm1) having different phases (delay times) or the same phase (delay time).

[0032] Before the sampling operation, each of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 can reset the n second differential node pairs in response to the pull-down reset clock signal CKNR. During the first analog-to-digital conversion operation after the sampling operation, each of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 can respond to each of the sequentially generated n pull-up clock signals CKP4 to CKP1 and the differential sampling signal pair and each of the first differential signal pair to the third differential signal pair among the four sequentially generated differential signal pairs, and sequentially perform a charging operation on each of the four second differential node pairs to sequentially generate each of the four first differential data pairs (DP4, DM4) to (DP1, DM1). After the first analog-to-digital conversion operation, each of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 can reset the four second differential node pairs to the power supply voltage in response to the pull-up reset clock signal CKPR, and during the second analog-to-digital conversion operation, each of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 can simultaneously perform a discharge operation on each of the four second differential node pairs in response to the pull-down clock signals CKN4 to CKN1 and the fourth differential signal pair among the four differential signal pairs to generate four second differential data pairs (dp4, dm4) to (dp1, dm1).

[0033] Each latch of the first latch 22-22 to the fourth latch 22-28 can sequentially latch each of the four first differential data pairs (DP4, DM4) to (DP1, DM1) to sequentially generate four upper differential data pairs (CP4, CM4) to (CP1, CM1). The data CP4, CP3, CP2 and CP1 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1) can be generated as 4-bit high-order digital data d8 to d5.

[0034] During the sampling operation, the timing generation unit may generate a sampling clock signal CKS based on an external clock signal CK. During the first analog-to-digital conversion operation, the timing generation unit may generate a first pull-up clock signal CKP4 among four pull-up clock signals CKP4 to CKP1 (e.g., by detecting a transition of the sampling clock signal CKS to generate the first pull-up clock signal CKP4), sequentially generate second pull-up clock signals CKP3 to fourth pull-up clock signals CKP1 by detecting a transition of each of the first data pair to the third data pair among four first differential data pairs (DP4, DM4) to (DP1, DM1), and generate a pull-up reset clock signal CKPR in response to the fourth pull-up clock signal CKP1. During the second analog-to-digital conversion operation, the timing generation unit may simultaneously generate pull-down clock signals CKN4 to CKN1 in response to the pull-up reset clock signal CKPR. In addition, after the second analog-to-digital conversion operation (before the sampling operation), the timing generation unit may generate a pull-down reset clock signal CKNR in response to the pull-down clock signals CKN4 to CKN1.

[0035] The second analog-to-digital conversion unit 30 may perform a plurality of phase interpolation operations on at least two adjacent data of the four second differential data pairs (dp4, dm4) to (dp1, dm1) to generate 2 4 (=16)+m-bit thermometer codes I(16+m) to I1, and the (16+m)-bit thermometer codes are encoded to generate at least 5-bit low-order digital data d5 to d1 (when the high-order digital data is 4-bit data, the low-order digital data may be 5-bit data). According to an embodiment, when there are n second differential data pairs (as an example, n=4), the second analog-to-digital conversion unit 30 may perform a plurality of phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate (2 n +m) digit thermometer code, m is less than 2 n .

[0036] The thermometer code generator 30 - 2 may perform a plurality of phase interpolation operations on at least two adjacent data of the four second differential data pairs ( dp4 , dm4 ) to ( dp1 , dm1 ) to generate a (16+m)-bit thermometer code (eg, I(16+m) to I1 ).

[0037] The encoder 30 - 4 may encode the (16+m)-bit thermometer code to generate at least 5-bit lower digital data d5 to d1.

[0038] The error correction unit 40 may perform calculation, that is, perform an error correction operation, on the 4-bit upper digital data d8 to d5 and the at least 5-bit lower digital data d5 to d1 , and generate 8-bit digital data D8 to D1 .

[0039] Figure 2is a circuit diagram illustrating a configuration of a first charger and a second charger and a discharger according to an example embodiment of the inventive concept.

[0040] The first charger and discharger 10-2 may include a first discharger 10-22 and a first charger 10-24, the first discharger 10-22 includes first inverters I11 to I16 and first capacitors C11 to C16, and the first charger 10-24 includes seventh inverters I21 to I26 and seventh capacitors C21 to C26. The capacitances of the first capacitors C11 to C16 may be 16C, 8C, 4C, 2C, C, C, respectively, and the capacitances of the seventh capacitors C21 to C26 may be 16C, 8C, 4C, 2C, C, C, respectively.

[0041] The first inverter I11 and the first capacitor C11 may be connected in series between the node n1p and the data CP4 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), the second inverter I12 and the second capacitor C12 may be connected in series between the node n1p and the data CP3 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), and the third inverter I13 and the third capacitor C13 may be connected in series between the node n1p and the data CP3 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1). The fourth inverter I14 and the fourth capacitor C14 can be connected in series between the node n1p and the data CP1 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), the fifth inverter I15 and the fifth capacitor C15 can be connected in series between the node n1p and the power supply voltage VDD, and the sixth inverter I16 and the sixth capacitor C16 can be connected in series between the node n1p and the ground voltage GND. The seventh inverter I21 and the seventh capacitor C21 may be connected in series between the node n1p and the data CM4 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), the eighth inverter I22 and the eighth capacitor C22 may be connected in series between the node n1p and the data CM3 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), the ninth inverter I23 and the ninth capacitor C23 may be connected in series between the node n1p and the data CM3 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), , CM4) to (CP1, CM1) data CM2, the tenth inverter I24 and the tenth capacitor C24 can be connected in series between the node n1p and the data CM1 of the four upper differential data pairs (CP4, CM4) to (CP1, CM1), the eleventh inverter I25 and the eleventh capacitor C25 can be connected in series between the node n1p and the ground voltage GND, and the twelfth inverter I26 and the twelfth capacitor C26 can be connected in series between the node n1p and the power supply voltage VDD.

[0042] The second charger and discharger 10 - 4 may have the same configuration as the first charger and discharger 10 - 2 except that the second charger and discharger 10 - 4 is connected to the node n1m instead of the node n1p and receives data CM4 to CM1 instead of data CP4 to CP1 and receives data CPB4 to CPB1 instead of data CMB4 to CMB1.

[0043] exist Figure 2 In the embodiment, the data CMB4 to CMB1 may be inverted data of the data CM4 to CM1 , and the data CPB4 to CPB1 may be inverted data of the data CP4 to CP1 .

[0044] Figure 2The first charger and discharger 10 - 2 and the second charger and discharger 10 - 4 shown are both capacitor digital-to-analog converters.

[0045] The following will describe Figure 2 The operations of the first charger and discharger 10 - 2 and the second charger and discharger 10 - 4 are shown.

[0046] Reference Figure 2 During the sampling operation, the first charger and discharger 10 - 2 may receive a differential input signal pair through the first differential node pair n1p, n1m to generate a differential sampling signal pair VP, VM.

[0047] During the first analog-to-digital conversion operation, the first charger and discharger 10-2 and the second charger and discharger 10-4 may perform a charging operation and a discharging operation that increase and decrease the level of the sampled differential signal pair by a level corresponding to the binary weight of each of the first differential data pairs (CP4, CM4) to (CP1, CM1). For example, when the first charger and discharger 10-2 performs a charging operation that increases the level of the differential sampled signal pair by a level corresponding to the binary weight of the first differential data pair CP4, CM4 (i.e., (16 / 64) VDD), the second charger and discharger 10-4 may perform a discharging operation that decreases the level of the differential sampled signal pair by a level corresponding to the binary weight of the first differential data pair CP4, CM4 (i.e., (16 / 64) VDD). On the other hand, when the first charger and discharger 10-2 performs a discharging operation, the second charger and discharger 10-4 may perform a charging operation. In addition, when the first charger and discharger 10-2 performs a charging operation to increase the level of the first differential node pair n1p, n1m by a level corresponding to the binary weight of the first differential data pair CP3, CM3 (i.e., (8 / 64) VDD), the second charger and discharger 10-4 may perform a discharging operation to reduce the level of the first differential node pair n1p, n1m by a level corresponding to the binary weight of the first differential data pair CP3, CM3 (i.e., (8 / 64) VDD). On the other hand, when the first charger and discharger 10-2 performs a discharging operation, the second charger and discharger 10-4 may perform a charging operation.

[0048] Figure 3 is a circuit diagram illustrating a configuration of a voltage-to-time converter according to an example embodiment of the inventive concept.

[0049] Figure 3 The voltage-to-time converter shown shows Figure 1The configuration of each voltage-to-time converter in the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 is shown, and n2p and n2m can correspond to each pair of the second differential node pairs (n2p4, n2m4) to (n2p1, n2m1), DP / dp and DM / dm can correspond to one pair of the first differential data pairs (DP4, DM4) to (DP1, DM1) of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28, or one pair of the second differential data pairs (dp4, dm4) to (dp1, dm1), and CKP can correspond to one pull-up clock signal among the pull-up clock signals CKP4 to CKP1. Although not shown, the second differential node pairs (n2p4, n2m4) to (n2p1, n2m1) can be as shown. Figure 3 The shown ones are respectively located in the first voltage-to-time converter 20 - 22 to the fourth voltage-to-time converter 20 - 28 .

[0050] The voltage-to-time converter may include first to fourth pull-up transistors P1 to P4, first pull-up reset transistors P5 and second pull-up reset transistors P6, first to fourth pull-down transistors N1 to N4, first pull-down reset transistors N5 and second pull-down reset transistors N6, and thirteenth and fourteenth inverters I13 and I14. The first to fourth pull-up transistors P1 to P4 and the first pull-up reset transistors P5 and P6 may be PMOS transistors, and the first to fourth pull-down transistors N1 to N4 and the first pull-down reset transistors N5 and second pull-down reset transistors N6 may be NMOS transistors.

[0051] The first pull-up transistor P1 and the second pull-up transistor P2 may be connected in series between a power supply voltage VDD and one node n2m of the second differential node pair n2p, n2m, and perform a charging operation on one node n2m of the second differential node pair n2p, n2m in response to one VM of the differential sampling signal pair VP, VM and the pull-up clock signal CKP.

[0052] The third pull-up transistor P3 and the fourth pull-up transistor P4 may be connected in series between the power supply voltage VDD and the other node n2p of the second differential node pair n2p, n2m, and perform a charging operation on the other node n2p of the second differential node pair n2p, n2m in response to the other VP of the differential sampling signal pair VP, VM and the pull-up clock signal CKP.

[0053] The first pull-up reset transistor P5 can be connected between the power supply voltage VDD and one node n2m of the second differential node pair n2p, n2m, the second pull-up reset transistor P6 can be connected between the power supply voltage VDD and the other node n2p of the second differential node pair n2p, n2m, and the first pull-up reset transistor P5 and the second pull-up reset transistor P6 reset the second differential node pair n2m, n2p to the power supply voltage VDD in response to the pull-up reset clock signal CKPR.

[0054] The first pull-down transistor N1 and the second pull-down transistor N2 may be connected in series between one n2m of the second differential node pair n2p, n2m and a ground voltage and perform a discharge operation on one n2m of the second differential node pair n2p, n2m in response to the pull-down clock signal CKN and the other VP of the differential sampling signal pair VP, VM.

[0055] The third pull-down transistor N3 and the fourth pull-down transistor N4 may be connected between the other n2p of the second differential node pair n2p, n2m and the ground voltage and perform a discharge operation on the other n2p of the second differential node pair n2p, n2m in response to the pull-down clock signal CKN and one VM of the differential sampling signal pair VP, VM.

[0056] The first pull-down reset transistor N5 can be connected between one n2m of the second differential node pair n2p, n2m and the ground voltage, the second pull-down reset transistor N6 can be connected between the other n2p of the second differential node pair n2p, n2m and the ground voltage, and the first pull-down reset transistor N5 and the second pull-down reset transistor N6 reset the second differential node pair n2m, n2p to the ground voltage in response to the pull-down reset clock signal CKNR.

[0057] The thirteenth inverter I13 can invert the level of the signal SM of the node n2m to generate data DM of the first differential data pair DM, DP or data dm of the second differential data pair dm, dp, and the fourteenth inverter I14 can invert the level of the signal SP of the node n2p to generate data DP of the first differential data pair DM, DP or data dp of the second differential data pair dm, dp.

[0058] The following will describe Figure 3 The operation of the first voltage-to-time converter 20 - 22 is shown.

[0059] Before the sampling operation, the first and second pull-down reset transistors N5 and N6 may be turned on in response to the pull-down reset clock signal CKNR to reset the second differential node pair n2m, n2p to the ground voltage.

[0060] During the first analog-to-digital conversion operation, the second pull-up transistor P2 and the fourth pull-up transistor P4 may be turned on in response to the pull-up clock signal CKP, and when the sampling signal VP has a level smaller than the sampling signal VM, the first pull-up transistor P1 and the third pull-up transistor P3 may operate to charge the node n2p faster than the node n2m. Therefore, the signal SP may reach the threshold voltage of the fourteenth inverter I14 faster than the signal SM, the thirteenth inverter I13 may generate data DM having a power supply voltage, and the fourteenth inverter I14 may generate data DP having a ground voltage. Thereafter, the node n2m may be charged, the signal SM may also reach the threshold voltage of the thirteenth inverter I13, and then the thirteenth inverter I13 may generate data DM having a ground voltage. On the other hand, when the sampling signal VM has a level smaller than the sampling signal VP, the first pull-up transistor P1 and the third pull-up transistor P3 may operate to charge the node n2m faster than the node n2p. Therefore, the signal SM can reach the threshold voltage of the thirteenth inverter I13 faster than the signal SP, the thirteenth inverter I13 can generate data DM having a ground voltage, and the fourteenth inverter I14 can generate data DP having a power supply voltage. Thereafter, the node n2p can be charged, the signal SP can also reach the threshold voltage of the fourteenth inverter I14, and then the fourteenth inverter I14 can generate data DP having a ground voltage.

[0061] Furthermore, after the first analog-to-digital conversion operation, the first and second pull-up reset transistors P5 and P6 may be turned on in response to the pull-up reset clock signal CKPR to reset the second differential node pair n2m, n2p to the power supply voltage.

[0062] During the second analog-to-digital conversion, the first pull-down transistor N1 and the third pull-down transistor N3 may be turned on in response to the pull-down clock signal CKN, and when the sampling signal VP is greater than the sampling signal VM, the second pull-down transistor N2 and the fourth pull-down transistor N4 may operate to discharge the node n2m faster than the node n2p. Therefore, the signal SM may reach the threshold voltage of the thirteenth inverter I13 faster than the signal SP, the thirteenth inverter I13 may generate data dm having a power supply voltage, and then the fourteenth inverter I14 may generate data dp having a power supply voltage. On the other hand, when the sampling signal VM is greater than the sampling signal VP, the second pull-down transistor N2 and the fourth pull-down transistor N4 may operate to discharge the node n2p faster than the node n2m. Therefore, the signal SP may reach the threshold voltage of the fourteenth inverter I14 faster than the signal SM, the fourteenth inverter I14 may generate data dp having a power supply voltage, and then the thirteenth inverter I13 may generate data dm having a power supply voltage.

[0063] Figure 3The first voltage-to-time converter 20-22 shown can perform a charging operation by the first pull-up transistor P1 to the fourth pull-up transistor P4 to perform a first analog-to-digital conversion operation after the first pull-up transistor P1 to the fourth pull-up transistor P4 are reset to the ground voltage, and perform a discharging operation by the first pull-down transistor N1 to the fourth pull-down transistor N4 to perform a second analog-to-digital conversion operation after the first pull-down transistor N1 to the fourth pull-down transistor N4 are reset to the power supply voltage.

[0064] The second to fourth voltage-to-time converters 20 - 24 to 20 - 28 may each have the same configuration as the first voltage-to-time converter 20 - 22 and perform the same operation as that of the first voltage-to-time converter 20 - 22 .

[0065] Reference Figures 1 to 3 , the ratio of the size of the second pull-down transistor N2 of each voltage-to-time converter 20-22 to the size of the fourth pull-down transistor N4 of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 may be different from each other. For example, the ratio of the size of the second pull-down transistor N2 of the first voltage-to-time converter 20-22 to the size of the fourth pull-down transistor N4 may be i:j, the ratio of the size of the second pull-down transistor N2 of the second voltage-to-time converter 20-24 to the size of the fourth pull-down transistor N4 may be x:y, the ratio of the size of the second pull-down transistor N2 of the third voltage-to-time converter 20-26 to the size of the fourth pull-down transistor N4 may be y:x, and the ratio of the size of the second pull-down transistor N2 of the fourth voltage-to-time converter 20-28 to the size of the fourth pull-down transistor N4 may be j:i. Here, the difference between i and j may be greater than the difference between x and y, and i+j may be equal to x+y. For example, i is 3, j is 7, x is 4, and y is 6. Therefore, the second pull-down transistor N2 and the fourth pull-down transistor N4 of the first to fourth voltage-to-time converters 20 - 22 to 20 - 28 may have different reference voltages.

[0066] Figure 4A and Figure 4B are diagrams illustrating configurations and truth tables of latches according to example embodiments of the inventive concepts.

[0067] Figure 4A The latch shown shows Figure 1 In the configuration of each of the four latches LA4 to LA1 shown, DP, DM can be one of the first differential data pairs (DP4, DM4) to (DP1, DM1) output from the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28, and CP, CM can be one of the four upper differential data pairs (CP4, CM4) to (CP1, CM1). Figure 4AThe latch shown may include four NAND gates NA1 to NA4.

[0068] Reference Figure 4A and Figure 4B , the latch can latch the first differential data pair DP, DM to generate the upper differential data pair CP, CM. When the first differential data pair DP, DM is "0", "0", the latch can maintain the previous state of the upper differential data pair CP, CM. When the first differential data pair DP, DM is "0", "1", the latch can generate the upper differential data pair CP, CM of "0" and "1", and when the first differential data pair DP, DM is "1", "0", the latch can generate the upper differential data pair CP, CM of "1", "0". In addition, when the first differential data pair DP, DM is "1", "1", the latch can generate the upper differential data pair CP, CM of "1", "1".

[0069] Figure 5 is an operation timing diagram for describing the operation of an analog-to-digital converter according to an example embodiment of the inventive concept.

[0070] Compared with the level changes of other signals CKS, CKP4 to CKP1, CKPR, CKN, CKNR, DP / DM, CP / CM, Figure 5 The level change of the differential sampling signal pair VP and VM of the first differential node pair n1p and n1m is amplified. Figure 5 The operation of generating the upper digital data CP4 to CP1 of "0100" by converting the sampling signal VP of one voltage section (e.g., the fifth voltage section P5 between (1 / 4) VDD and (5 / 16) VDD) among the first voltage section P1 to the sixteenth voltage section P16 between the ground voltage 0V and the power supply voltage VDD is shown. Figure 5 , the first voltage portion P1 between 0V and (1 / 16)VDD may be a portion corresponding to the upper digital data "0000", the fifth voltage portion P5 between (1 / 4)VDD and (5 / 16)VDD may be a portion corresponding to the upper digital data "0100", and the sixteenth voltage portion P16 between (15 / 16)VDD and VDD may be a portion corresponding to the upper digital data "1111". That is, the first voltage portion to the sixteenth voltage portion may be portions corresponding to different upper digital data from each other.

[0071] Reference Figures 1 to 5, before the sampling operation period T1, the first timing generator 24-22 to the fourth timing generator 24-28 may generate a pull-down reset clock signal CKNR of a "high" level. The first pull-down reset transistor N5 and the second pull-down reset transistor N6 of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 may be turned on to reset all second differential node pairs (n2m4, n2p4) to (n2m1, n2p1) to the ground voltage to generate a first differential data pair (DP4, DM4) to (DP1, DM1) of a "high" level (data "1").

[0072] During the sampling operation period T1, the first timing generator 24-22 may generate a sampling clock signal CKS. The first switch SW1 and the second switch SW2 may be turned on in response to the sampling clock signal CKS and transmit the differential input signal pair VINP, VINM to the first differential node pair n1p, n1m.

[0073] During the first analog-to-digital conversion operation period T2, the first timing generator 24-22 can generate a pull-up clock signal CKP4 of a "low" level. The second pull-up transistor P2 and the fourth pull-up transistor P4 of the first voltage-to-time converter 20-22 can be turned on in response to the pull-up clock signal CKP4 of a "low" level. In addition, because the level of the sampling signal VP is less than the level of the sampling signal VM, the third pull-up transistor P3 and the fourth pull-up transistor P4 can be charged faster than the first pull-up transistor P1 and the second pull-up transistor P2. The thirteenth inverter I13 and the fourteenth inverter I14 can invert the level of the signal of the second differential node pair n2m4, n2p4 to generate the first differential data pair DP4, DM4 of "0", "1". The first latch 22-22 can latch the first differential data pair DP4, DM4 of "0", "1" to generate the upper differential data pair CP4, CM4 of "0" and "1". Therefore, the first charger and discharger 10 - 2 may perform a charging operation to increase the sampling signal VP by (1 / 4) VDD, and the second charger and discharger 10 - 4 may perform a discharging operation to decrease the sampling signal VM by (1 / 4) VDD.

[0074] When a transition of the first differential data pair DP4, DM4 is detected (for example, when a transition of one of the first differential data pairs DP4, DM4 from a "high" level to a "low" level is detected), the second timing generator 24-24 can generate a pull-up clock signal CKP3 of a "low" level. The second pull-up transistor P2 and the fourth pull-up transistor P4 of the second voltage-to-time converter 20-24 can be turned on in response to the pull-up clock signal CKP3 of a "low" level. In addition, because the level of the sampling signal VM is less than the level of the sampling signal VP, the first pull-up transistor P1 and the second pull-up transistor P2 can charge the node n2m3 faster than the third pull-up transistor P3 and the fourth pull-up transistor P4. The thirteenth inverter I13 and the fourteenth inverter I14 can invert the level of the signal of the second differential node pair n2m3, n2p3 to generate the first differential data pair DP3, DM3 of "1", "0". The second latches 22-24 can latch the first differential data pair DP3, DM3 of "1", "0" to generate the upper differential data pair CP3, CM3 of "1", "0". Therefore, the first charger and discharger 10-2 can perform a discharge operation to reduce the sampling signal VP by (1 / 8) VDD, and the second charger and discharger 10-4 can perform a charge operation to increase the sampling signal VM by (1 / 8) VDD.

[0075] When the transition of the first differential data pair DP3, DM3 is detected, the third timing generator 24-26 can generate a pull-up clock signal CKP2 of a "low" level. The third voltage-to-time converter 20-26 can perform the same operation as the above-mentioned first voltage-to-time converter 20-22 to generate the first differential data pair DP2, DM2 of "0", "1". The third latch 22-26 can perform the same operation as the above-mentioned first latch 22-22 to generate the upper differential data pair CP2, CM2 of "0", "1". Therefore, the first charger and discharger 10-2 can perform a charging operation to increase the sampling signal VP by (1 / 16) VDD, and the second charger and discharger 10-4 can perform a discharging operation to reduce the sampling signal VM by (1 / 16) VDD.

[0076] When the transition of the first differential data pair DP2, DM2 is detected, the fourth timing generator 24-28 can generate a pull-up clock signal CKP1 of a "low" level. The fourth voltage-to-time converter 20-28 can perform the same operation as the above-mentioned first voltage-to-time converter 20-22 to generate the first differential data pair DP1, DM1 of "0", "1". The fourth latch 22-28 can perform the same operation as the above-mentioned first latch 22-22 to generate the upper differential data pair CP1, CM1 of "0", "1". Therefore, the first charger and discharger 10-2 can perform a charging operation to increase the signal VP by (1 / 32) VDD, and the second charger and discharger 10-4 can perform a discharging operation to reduce the signal VM by (1 / 32) VDD.

[0077] During the pull-up reset period T3 after the first analog-to-digital conversion operation period T2, when the transition of the first differential data pair DP1, DM1 is detected, the first timing generator 24-22 to the fourth timing generator 24-28 can generate a pull-up reset clock signal CKPR of a "low" level. Therefore, the first pull-up reset transistor P5 and the second pull-up reset transistor P6 of each voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 can be turned on, and the four second differential node pairs (n2p4, n2m4) to (n2p1, n2m1) are reset to the power supply voltage. Therefore, since the reset operation is performed during the pull-up reset period T3 in a state where the second differential node pairs (n2p4, n2m4) to (n2p1, n2m1) have been reset to the power supply voltage, the power consumed by the reset operation can be reduced.

[0078] During the second analog-to-digital conversion operation period T4, the first timing generator 24-22 to the fourth timing generator 24-28 may generate a pull-down clock signal CKN of a "high" level. The first pull-down transistor N1 and the third pull-down transistor N3 of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 may be turned on, and the second pull-down transistor N2 and the fourth pull-down transistor N4 may perform a discharge operation using the remaining differential level pair vp, vm of the differential sampling signal pair VP, VM. In each of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28, because the level vm of the sampling signal VM is greater than the level vp of the sampling signal VP, the level of the node n2p may be discharged faster through the third pull-down transistor N3 and the fourth pull-down transistor N4 than the level of the node n2m may be discharged through the first pull-down transistor N1 and the second pull-down transistor N2, and the fourteenth inverter I14 may generate a "high" level signal faster than the thirteenth inverter I13. Because the size of the second pull-down transistor N2 and the size of the fourth pull-down transistor N4 of each voltage-to-time converter in the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 are different from each other, four second differential data pairs (dp4, dm4) to (dp1, dm1) with different phases (delay times) or the same phase (delay times) can be simultaneously generated using the remaining differential level pairs vp, vm of the differential sampling signal pair VP, VM.

[0079] During the pull-down reset period T5 after the second analog-to-digital conversion operation period T4, the first timing generator 24-22 to the fourth timing generator 24-28 can generate a pull-down reset clock signal CKNR of a "high" level. Therefore, the first pull-down reset transistor N5 and the second pull-down reset transistor N6 of the first voltage-to-time converter 20-22 to the fourth voltage-to-time converter 20-28 can be turned on to reset the four second differential node pairs (n2p4, n2m4) to (n2p1, n2m1) to the ground voltage. Since the reset operation is performed during the pull-down reset period T5 in a state where the second differential node pairs (n2p4, n2m4) to (n2p1, n2m1) have been reset to the ground voltage, the power consumed by the reset operation can be reduced.

[0080] Figure 6 is a conceptual diagram for describing a second analog-to-digital conversion operation and an error correction operation according to an example embodiment of the inventive concept.

[0081] Reference Figure 5 and Figure 6After performing the first analog-to-digital conversion operation, the remaining differential level pair vp, vm of the differential sampling signal pair VP, VM may exist between (15 / 32) VDD and (17 / 32) VDD. The level between (15 / 32) VDD and (17 / 32) VDD may be divided into 16 levels, and these 16 levels may be represented by different 5-bit low-order digital data d5-d1.

[0082] During the second analog-to-digital conversion operation, when the sampling signal VP or VM is present in one of the 16 levels between (15 / 32)VDD and (17 / 32)VDD, the thermometer code generator 30-2 can generate a thermometer code corresponding to a corresponding level among the 16 different 25-bit thermometer codes I1-I25. The encoder 30-4 can convert the 16 25-bit thermometer codes I1-I25 into 16 erroneous 5-bit low-order digital data d5-d1 during the second analog-to-digital conversion operation. For example, the 16 erroneous 5-bit low-order digital data d5-d1 can be data from "00000" to "01111".

[0083] In addition, when the remaining differential level pair vp, vm of the differential sampling signal pair VP, VM exists between (15 / 32) VDD and (29 / 64) VDD and between (17 / 32) VDD and (35 / 64) VDD, the remaining differential level pair vp, vm can be considered as an error and can be corrected. The level between (17 / 32) VDD and (35 / 64) VDD can be divided into 4 levels, and these 4 levels can be represented by different 5-bit error digital data.

[0084] During the second analog-to-digital conversion operation, when the signal VP or VM exists in one of the four levels between (15 / 32)VDD and (29 / 64)VDD, the thermometer code generator 30-2 can generate a thermometer code corresponding to a corresponding level among the four different 25-bit thermometer codes I1~I25. The encoder 30-4 can convert the four 25-bit thermometer codes I1~I25 into four 5-bit first error digital data d5 to d1 during the second analog-to-digital conversion operation. For example, the four 5-bit first error digital data d5~d1 can be data from "11100" to "11111". In addition, during the second analog-to-digital conversion operation, when the signal VP or VM exists in one of the four levels between (17 / 32)VDD and (35 / 64)VDD, the thermometer code generator 30-2 can generate a thermometer code corresponding to a corresponding level among the four different 25-bit thermometer codes I1~I25. The encoder 30 - 4 may convert the four 25-bit thermometer codes I1 ˜ I25 into four 5-bit second error digital data d5 to d1 during the second analog-to-digital conversion operation. For example, the four 5-bit second error digital data d5 ˜ d1 may be data from “10000” to “10011”.

[0085] During the error correction operation, the final digital data D8D7D6D5D4D3D2D1 may be generated by adding the 4-bit upper digital data d8D7D6D5 and the 5-bit lower digital data or the first error digital data d5D4D3D2D1, or by adding the 4-bit upper digital data d8D7D6D5 and the data 1d5D4D3D2D1 obtained by adding "1" to the upper bits of the second error digital data d5D4D3D2D1. During the error correction operation, when the upper bit (e.g., D9) of "1" is generated, the upper data (e.g., D9) may be truncated.

[0086] Fig. 7A is a diagram illustrating a configuration of a thermometer code generator according to an example embodiment of the inventive concept.

[0087] Fig. 7A The thermometer code generator shown shows Figure 1 The configuration of the thermometer code generator 30 - 2 is shown. The thermometer code generator 30 - 2 may include three first interpolation units 30 - 22 , three second interpolation units 30 - 24 , and three latch units 30 - 26 .

[0088] Reference Fig. 7A, one of the three first interpolation units 30-22 may include a first phase interpolator PI1 to a fourth phase interpolator PI4 and (for example, when it is assumed that dp4 to dp1 have positive polarity and dm4 to dm1 have negative polarity) a fifth phase interpolator PI5 and a sixth phase interpolator PI6, the first phase interpolator PI1 to the fourth phase interpolator PI4 perform phase interpolation operations on corresponding data of two second differential data pairs (dp4, dm4), (dp3, dm3), the fifth phase interpolator PI5 and the sixth phase interpolator PI6 perform phase interpolation operations on two data dm4, dm3 having the same polarity and corresponding two data of the two data dp4, dp3. One of the three second interpolation units 30-24 may include a seventh phase interpolator PI7 to a tenth phase interpolator PI10, which respectively perform interpolation operations on the following corresponding two data: the output data of the first phase interpolator PI1 and the output data of the sixth phase interpolator PI6, the output data of the sixth phase interpolator PI6 and the output data of the third phase interpolator PI3, the output data of the second phase interpolator PI2 and the output data of the fifth phase interpolator PI5, and the output data of the fifth phase interpolator PI5 and the output data of the fourth phase interpolator PI4.

[0089] One latch unit among the three latch units 30-26 may include 9 latches, and LA5 and LA6 among the 9 latches are alternately arranged and latched to output the following corresponding two data: the output data of the first phase interpolator PI1 and the output data of the second phase interpolator PI2, the output data of the second phase interpolator PI2 and the output data of the seventh phase interpolator PI7, the output data of the second phase interpolator PI2 and the output data of the fifth phase interpolator PI5, the output data of the second phase interpolator PI2 and the output data of the eighth phase interpolator PI8, the output data of the second phase interpolator PI2 and the output data of the third phase interpolator PI3, the output data of the ninth phase interpolator PI9 and the output data of the third phase interpolator PI3, the output data of the sixth phase interpolator PI6 and the output data of the third phase interpolator PI3, the output data of the tenth phase interpolator PI10 and the output data of the third phase interpolator PI3, and the output data of the third phase interpolator PI3 and the output data of the fourth phase interpolator PI4.

[0090] The remaining two first interpolation units 30-22 may have the same configuration as the above-mentioned first interpolation unit 30-22, the remaining two second interpolation units 30-24 may have the same configuration as the above-mentioned second interpolation unit 30-24, and the remaining two latch units 30-26 may have the same configuration as the above-mentioned latch unit 30-26.

[0091] Figure 7B is a diagram illustrating a configuration of a phase interpolator according to an example embodiment of the inventive concept.

[0092] Reference Fig. 7A and Figure 7B , the first phase interpolator PI1 to the fourth phase interpolator PI4 may each include a fifteenth inverter I15 and a sixteenth inverter I16 connected in parallel, and the fifth phase interpolator PI5 to the tenth phase interpolator PI10 may each include a seventeenth inverter I17 and an eighteenth inverter I18 connected in parallel.

[0093] Reference Figure 7B , the first phase interpolator PI1 to the fourth phase interpolator PI4 can invert the phase of the same signal through the fifteenth inverter I15 and the sixteenth inverter I16, and generate an output signal by interpolating the phase of the inverted signal. The fifth phase interpolator PI5 to the tenth phase interpolator PI10 can invert each of the phases of different signals through the seventeenth inverter I17 and the eighteenth inverter I18, and generate an output signal by interpolating the phase of the inverted signal.

[0094] Fig. 8A and Figure 8B 2 are diagrams respectively illustrating configurations of a fifth latch and a sixth latch according to example embodiments of the inventive concepts.

[0095] Reference Fig. 7A , Fig. 8A and Figure 8B , the fifth latch LA5 may include four NOR gates NR1 to NR4, and the sixth latch LA6 may include four NAND gates ND5 to ND8.

[0096] The fifth latch LA5 may be a NOR type SR latch, and the sixth latch LA6 may be a NAND type SR latch. Fig. 7A , the reason why the fifth latch LA5 and the sixth latch LA6 are used alternately may be because the second differential data pair applied to the fifth latch LA5 is generated by one inverter of the first interpolation unit 30-22 and the second differential data pair applied to the sixth latch LA6 is generated by two inverters connected in series of the first interpolation unit 30-22 and the second interpolation unit 30-24. In example embodiments, the fifth latch LA5 may receive data IN1 and IN2 and output data Q1 and Q1B, and the sixth latch LA6 may receive data IN3 and IN4 and output data Q2 and Q2B, wherein data Q1B may be inverted data of Q1 and data Q2B may be inverted data of Q2.

[0097] Fig. 7A The thermometer code generator 30-2 shown is described in detail in an article entitled “A65-nm CMOS 6-bit 2.5-GS / s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration” published by two co-inventors of the present invention in IEEE Journal Solid-State Circuits, Vol. 54, No. 1, pp. 288-297, January 2019. As an example, the time domain interpolator TDI disclosed in FIG. 4(a) of the article corresponds to Figure 7B The phase interpolator PI shown in FIG. 4( b ) of the article discloses a voltage-to-time converter VTC having a different Figure 3 The voltage-to-time converters 20-22 and 20-24 are configured and perform differently than Figure 3 The operation of the voltage-to-time converters 20-22 and 20-24 shown in FIG. 4(b) of the article, however, is similar to the operation of the voltage-to-time converters 20-22 and 20-24 shown in FIG. 4(b) of the article, but the two adjacent differential data pairs (DL 1_8 + , DL 1_8 - )、(DL 1_0 + , DL 1_0 - )) corresponds to Figure 3 The voltage-to-time converters 20 - 22 and 20 - 24 are shown to generate two adjacent differential data pairs ( DP4 , DM4 ), ( DP3 , DM3 ). Fig. 8A The fifth latch LA5 shown corresponds to the NOR type SR latch shown in FIG. 4( d ) of the article, and Figure 8B The sixth latch LA6 shown corresponds to the NAND type SR latch shown in FIG. 4( d ) of the article. Fig. 7A , Figure 7B , Fig. 8A and Figure 8B A detailed description of the illustrated configuration will be understood with reference to that article.

[0098] Fig. 9 is a block diagram illustrating a configuration of a system according to an exemplary embodiment of the inventive concept. The system 900 may include a transmitting unit 100 and a receiving unit 200, and the receiving unit 200 may include k analog-to-digital converters ADC1 to ADCk.

[0099] Reference Fig. 9, the transmitting unit 100 can transmit k differential input signal pairs (VINP1, VINM1) to (VINPk, VINMk). The k analog-to-digital converters ADC1 to ADCk can receive the k differential input signal pairs (VINP1, VINM1) to (VINPk, VINMk) to generate k 8-bit digital data (D81-D11) to (D8k-D1k).

[0100] The k analog-to-digital converters ADC1 to ADCk may have the same Figures 1 to 8B The analog-to-digital converter described herein has the same configuration and performs the same operation as the analog-to-digital converter described herein.

[0101] For example, the transmitting unit 100 may be the control unit 100, and the receiving unit 200 may be a semiconductor memory device. When the receiving unit 200 is a semiconductor memory device, the semiconductor memory device may receive the level of a differential input signal pair applied through one pin and internally generate 8-bit digital data to be stored in a memory cell array.

[0102] Refer to above Figures 1 to 8B The analog-to-digital converter described and Fig. 9 The system 900 shown can be applied to various units (devices, apparatuses) that convert analog signals into digital data.

[0103] According to an analog-to-digital converter and a semiconductor device having the analog-to-digital converter according to an example embodiment conceived in the present invention, a first analog-to-digital conversion unit can be used to sequentially generate each bit of n-bit high-bit digital data, and a second analog-to-digital conversion unit can be used to simultaneously generate n-bit low-bit digital data, so that the analog-to-digital conversion operation can be performed at a higher speed.

[0104] According to an analog-to-digital converter and a semiconductor device having the same according to an example embodiment conceived in the present invention, the second analog-to-digital conversion unit can generate n-bit low-bit digital data using n differential data pairs generated from four voltage-to-time converters of the first analog-to-digital conversion unit, thereby simplifying the configuration.

[0105] In addition, according to the analog-to-digital converter and the semiconductor device having the analog-to-digital converter according to the example embodiments conceived in the present invention, n-bit high-bit digital data can be generated by performing a charging operation of four voltage-to-time converters, and n-bit low-bit digital data can be generated by performing a discharging operation of four voltage-to-time converters, thereby reducing the power consumed by the reset operation.

[0106] Although the present disclosure has been shown and described with reference to the exemplary embodiments of the present disclosure, it is obvious to those skilled in the art that various changes in form and details may be made without departing from the spirit and features of the present disclosure. Therefore, the above embodiments are to be interpreted in all aspects as illustrative and not restrictive.

Claims

1. An analog-to-digital converter, comprising: A first analog-to-digital conversion unit, wherein the first analog-to-digital conversion unit is configured as: During the first analog-to-digital conversion operation: In response to the differential sampling signal pair and corresponding pairs of the first differential signal pair to the n-1st differential signal pair among the n differential signal pairs, sequentially charging each of the n first differential node pairs; In response to each of the n first differential node pairs being sequentially charged, sequentially generating each of the n first differential data pairs; and sequentially generating each of n upper differential data pairs to be used as n-bit upper digital data in response to corresponding pairs of the n first differential data pairs sequentially generated; During the second analog-to-digital conversion operation: In response to an nth differential signal pair among the n differential signal pairs, discharging each of the n first differential node pairs simultaneously; and In response to each of the n first differential node pairs being discharged simultaneously, generating n second differential data pairs having different phases or the same phase; as well as A second analog-to-digital conversion unit, wherein the second analog-to-digital conversion unit is configured as: Perform multiple phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate 2 n +m-digit thermometer code, m is less than 2 n ; and Regarding the 2 n +m-bit thermometer code is encoded to generate at least n+1 bits of low-order digital data.

2. The analog-to-digital converter according to claim 1, further comprising a sampling and charging and discharging unit, wherein the sampling and charging and discharging unit is configured as follows: In the sampling operation: Sampling a differential input signal pair to generate the differential sampled signal pair; and generating the differential sampling signal pair to a second differential node pair; and During the first analog-to-digital conversion operation: charging and discharging the second differential node pair in response to each of the n upper differential data pairs generated sequentially; and Each of the n differential signal pairs varying from the differential sampling signal pair is sequentially generated.

3. The analog-to-digital converter according to claim 2, wherein: The sampling and charging and discharging unit comprises: a first charger and discharger connected to a first node of the second differential node pair and configured to charge and discharge the first node to a level corresponding to a binary weight of each of the n upper differential data pairs; and A second charger and discharger is connected to a second node of the second differential node pair and configured to discharge and charge the second node to the level corresponding to the binary weight of each of the n upper differential data pairs.

4. The analog-to-digital converter according to claim 1, wherein: The first analog-to-digital conversion unit comprises: n voltage-to-time converters, wherein the n voltage-to-time converters are configured as follows: Before the sampling operation, in response to a pull-down reset clock signal, resetting the n first differential node pairs to a ground voltage; During the first analog-to-digital conversion operation, in response to a corresponding pull-up clock signal among the sequentially generated n pull-up clock signals and the differential sampling signal pair and the corresponding pair among the sequentially generated first differential signal pair to the n-1th differential signal pair, sequentially charging each of the n first differential node pairs to sequentially generate each of the n first differential data pairs; After the first analog-to-digital conversion operation, resetting the n first differential node pairs to a power supply voltage in response to a pull-up reset clock signal; and During the second analog-to-digital conversion operation, in response to the pull-down clock signal and the nth differential signal pair, each of the n first differential node pairs is discharged simultaneously to generate the n second differential data pairs; and n latches are configured to sequentially latch each of the n first differential data pairs to generate the n upper differential data pairs.

5. The analog-to-digital converter according to claim 4, wherein: Each of the n voltage-to-time converters comprises: a first pull-up reset transistor and a second pull-up reset transistor, the first pull-up reset transistor and the second pull-up reset transistor being connected between the power supply voltage and a corresponding pair of the n first differential node pairs and configured to reset the corresponding pair of the n first differential node pairs to the power supply voltage in response to the pull-up reset clock signal; a first pull-up transistor and a second pull-up transistor, the first pull-up transistor and the second pull-up transistor being connected in series between the power supply voltage and a first node in the corresponding pair of the n first differential node pairs, and configured to charge the first node in the corresponding pair of the n first differential node pairs in response to a first differential signal in the corresponding pair of the n differential signal pairs and a first pull-up clock signal in the n pull-up clock signals; a third pull-up transistor and a fourth pull-up transistor, the third pull-up transistor and the fourth pull-up transistor being connected in series between the power supply voltage and the second node in the corresponding pair of the n first differential node pairs and configured to charge the second node in the corresponding pair of the n first differential node pairs in response to a second differential signal in the corresponding pair of the n differential signal pairs and a second pull-up clock signal in the n pull-up clock signals; a first pull-down reset transistor and a second pull-down reset transistor, the first pull-down reset transistor and the second pull-down reset transistor connected between a corresponding pair of the n first differential node pairs and the ground voltage and configured to reset the corresponding pair of the n first differential node pairs to the ground voltage in response to the pull-down reset clock signal; a first pull-down transistor and a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first node in the corresponding pair of the n first differential node pairs and the ground voltage and configured to discharge the first node in the corresponding pair of the n first differential node pairs in response to the pull-down clock signal and the second differential signal in the corresponding pair of the n differential signal pairs; and a third pull-down transistor and a fourth pull-down transistor, wherein the third pull-down transistor and the fourth pull-down transistor are connected in series between the second node in the corresponding pair of the n first differential node pairs and the ground voltage, and are configured to discharge the second node in the corresponding pair of the n first differential node pairs in response to the pull-down clock signal and the first differential signal in the corresponding pair of the n differential signal pairs.

6. The analog-to-digital converter according to claim 5, wherein: A ratio between a size of the second pull-down transistor and a size of the fourth pull-down transistor of each of the n voltage-to-time converters is different from each other.

7. The analog-to-digital converter according to claim 5, wherein: The ratio of the size of the second pull-down transistor to the size of the fourth pull-down transistor of the first voltage-to-time converter among the n voltage-to-time converters is i:j, The ratio of the size of the second pull-down transistor to the size of the fourth pull-down transistor of the second voltage-to-time converter among the n voltage-to-time converters is x:y. The ratio of the size of the second pull-down transistor to the size of the fourth pull-down transistor of the third voltage-to-time converter among the n voltage-to-time converters is y:x. The ratio of the size of the second pull-down transistor to the size of the fourth pull-down transistor of the fourth voltage-to-time converter among the n voltage-to-time converters is j:i. where the difference between i and j is greater than the difference between x and y, and Among them, i+j equals x+y.

8. The analog-to-digital converter according to claim 4, wherein: Each of the n latches is a first NAND-type SR latch.

9. The analog-to-digital converter according to claim 4, further comprising a timing generation unit, wherein the timing generation unit is configured to: generating the pull-down reset clock signal before the sampling operation; During the first analog-to-digital conversion operation: generating a first pull-up clock signal among the n pull-up clock signals; and generating a second pull-up clock signal to an n-th pull-up clock signal among the n pull-up clock signals by detecting a transition of each of a first data pair to an n-1-th data pair among the n first differential data pairs; generating the pull-up reset clock signal in response to the nth pull-up clock signal after the first analog-to-digital conversion operation; as well as The pull-down clock signal is generated during the second analog-to-digital conversion operation.

10. The analog-to-digital converter according to claim 1, wherein: The second analog-to-digital conversion unit comprises: A first phase interpolation unit, wherein the first phase interpolation unit is configured to: performing a phase interpolation operation on corresponding data of two adjacent pairs among the n second differential data pairs to generate first to fourth interpolation data; and performing the phase interpolation operation on corresponding two data with the same polarity in the two adjacent pairs among the n second differential data pairs to generate fifth interpolation data and sixth interpolation data; A second phase interpolation unit, wherein the second phase interpolation unit is configured as: performing the phase interpolation operation on the first interpolation data and the fifth interpolation data to generate seventh interpolation data; performing the phase interpolation operation on the fifth interpolation data and the third interpolation data to generate eighth interpolation data; performing the phase interpolation operation on the second interpolation data and the sixth interpolation data to generate ninth interpolation data; and performing the phase interpolation operation on the sixth interpolation data and the fourth interpolation data to generate tenth interpolation data; and A latch unit, wherein the latch unit is configured to latch and output the following corresponding two data: the first interpolation data and the second interpolation data, the second interpolation data and the seventh interpolation data, the second interpolation data and the fifth interpolation data, the second interpolation data and the eighth interpolation data, the second interpolation data and the third interpolation data, the ninth interpolation data and the third interpolation data, the sixth interpolation data and the third interpolation data, the tenth interpolation data and the third interpolation data, and the third interpolation data and the fourth interpolation data.

11. The analog-to-digital converter according to claim 10, wherein: The latch unit includes: a NOR type SR latch and a second NAND type SR latch.

12. The analog-to-digital converter according to claim 1, wherein: The at least (n+1) bits of low-order digital data include 2 n erroneous data, k first error digital data and k second error digital data, k is less than 2 n ,and Wherein, the analog-to-digital converter further includes an error correction unit, and the error correction unit is configured as follows: The n-bit high-order digital data and the 2 n one of the k erroneous digital data or one of the k first error digital data is added to generate the final n-bit digital data; or The n-bit upper digital data is added to data obtained by adding "1" to the upper bit of one of the k first error data to generate the final n-bit digital data.

13. An analog-to-digital converter, comprising: A sampling and charging and discharging unit, wherein the sampling and charging and discharging unit is configured as follows: During sampling operation: sampling the differential input signal pair to generate a differential sampled signal pair; and generating the differential sampling signal pair to a first differential node pair; and During the first analog-to-digital conversion operation: charging and discharging the first differential node pair in response to each of n upper differential data pairs used as n-bit upper digital data and sequentially generated; and Sequentially generate n differential signal pairs derived from the differential sampling signal pairs; A first analog-to-digital conversion unit, wherein the first analog-to-digital conversion unit is configured as: During the first analog-to-digital conversion operation: In response to the differential sampling signal pair and corresponding pairs of the first differential signal pair to the n-1th differential signal pair among the n differential signal pairs, sequentially charging each pair of the n second differential node pairs; In response to each of the n second differential node pairs being sequentially charged, sequentially generating each of the n first differential data pairs; and sequentially generating each of the n upper differential data pairs in response to a corresponding pair of the n first differential data pairs generated sequentially; During the second analog-to-digital conversion operation: In response to an nth differential signal pair among the n differential signal pairs, simultaneously discharging each of the n second differential node pairs; and In response to each of the n second differential node pairs being discharged simultaneously, generating n second differential data pairs having different phases or the same phase; as well as A second analog-to-digital conversion unit, wherein the second analog-to-digital conversion unit is configured as: Perform multiple phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate 2 n +m-digit thermometer code, m is less than 2 n ; and Regarding the 2 n +m-bit thermometer code is encoded to generate at least n+1 bits of low-order digital data.

14. The analog-to-digital converter according to claim 13, wherein: The at least n+1 bits of low-order digital data include 2 n erroneous data, k first error digital data and k second error digital data, k is less than 2 n ,and Wherein, the analog-to-digital converter further includes an error correction unit, and the error correction unit is configured as follows: The n-bit high-order digital data and the 2 n one of the k erroneous digital data or one of the k first error digital data is added to generate the final n-bit digital data; or The n-bit upper digital data is added to data obtained by adding "1" to the upper bit of one of the k first error data to generate the final n-bit digital data.

15. The analog-to-digital converter according to claim 14, wherein: The first analog-to-digital conversion unit comprises: n voltage-to-time converters, wherein the n voltage-to-time converters are configured as follows: Before the sampling operation, in response to a pull-down reset clock signal, resetting the n second differential node pairs to a ground voltage; During the first analog-to-digital conversion operation, in response to a corresponding pull-up clock signal among the sequentially generated n pull-up clock signals and the differential sampling signal pair and the corresponding pair among the sequentially generated first differential signal pair to the n-1th differential signal pair, sequentially charging each of the n second differential node pairs to generate each of the n first differential data pairs; After the first analog-to-digital conversion operation, resetting the n second differential node pairs to a power supply voltage in response to a pull-up reset clock signal; and During the second analog-to-digital conversion operation, in response to the pull-down clock signal and the nth differential signal pair, each of the n second differential node pairs is discharged simultaneously to generate the n second differential data pairs; n latches configured to sequentially latch each of the n first differential data pairs to generate the n upper differential data pairs; and A timing generation unit, wherein the timing generation unit is configured to: generating the pull-down reset clock signal before the sampling operation; During the first analog-to-digital conversion operation: generating a first pull-up clock signal among the n pull-up clock signals; and generating a second pull-up clock signal to an n-th pull-up clock signal among the n pull-up clock signals by detecting a transition of each of a first data pair to an n-1-th data pair among the n first differential data pairs; generating the pull-up reset clock signal in response to the nth pull-up clock signal after the first analog-to-digital conversion operation; and The pull-down clock signal is generated during the second analog-to-digital conversion operation.

16. The analog-to-digital converter according to claim 15, wherein: Each of the n voltage-to-time converters comprises: a first pull-up reset transistor and a second pull-up reset transistor, the first pull-up reset transistor and the second pull-up reset transistor being connected between the power supply voltage and a corresponding pair of the n second differential node pairs and configured to reset the corresponding pair of the n second differential node pairs to the power supply voltage in response to the pull-up reset clock signal; a first pull-up transistor and a second pull-up transistor, the first pull-up transistor and the second pull-up transistor being connected in series between the power supply voltage and a first node in the corresponding pair of the n second differential node pairs, and configured to charge the first node in the corresponding pair of the n second differential node pairs in response to a first differential signal in the corresponding pair of the n differential signal pairs and a first pull-up clock signal in the n pull-up clock signals; a third pull-up transistor and a fourth pull-up transistor, the third pull-up transistor and the fourth pull-up transistor being connected in series between the power supply voltage and the second node in the corresponding pair of the n second differential node pairs and configured to charge the second node in the corresponding pair of the n second differential node pairs in response to a second differential signal in the corresponding pair of the n differential signal pairs and a second pull-up clock signal in the n pull-up clock signals; a first pull-down reset transistor and a second pull-down reset transistor, the first pull-down reset transistor and the second pull-down reset transistor being connected between a corresponding pair of the n second differential node pairs and the ground voltage and configured to reset the corresponding pair of the n second differential node pairs to the ground voltage in response to the pull-down reset clock signal; a first pull-down transistor and a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first node in the corresponding pair of the n second differential node pairs and the ground voltage, and configured to discharge the first node in the corresponding pair of the n second differential node pairs in response to the pull-down clock signal and the second differential signal in the corresponding pair of the n differential signal pairs; and a third pull-down transistor and a fourth pull-down transistor, wherein the third pull-down transistor and the fourth pull-down transistor are connected in series between the second node in the corresponding pair of the n second differential node pairs and the ground voltage, and are configured to discharge the second node in the corresponding pair of the n second differential node pairs in response to the pull-down clock signal and the first differential signal in the corresponding pair of the n differential signal pairs.

17. A semiconductor device comprising: a predetermined number of analog-to-digital converters, each of the analog-to-digital converters being configured to receive a corresponding differential input signal pair of the predetermined number of differential input signal pairs from an external source to generate 2n-bit digital data, respectively, Wherein, each of the analog-to-digital converters comprises: A sampling and charging and discharging unit, wherein the sampling and charging and discharging unit is configured as follows: In the sampling operation: sampling the differential input signal pair to generate a differential sampled signal pair; and generating the differential sampling signal pair to a first differential node pair; and During the first analog-to-digital conversion operation: charging and discharging the first differential node pair in response to each of n upper differential data pairs used as n-bit upper digital data and sequentially generated; and Sequentially generate n differential signal pairs derived from the differential sampling signal pairs; A first analog-to-digital conversion unit, wherein the first analog-to-digital conversion unit is configured as: During the first analog-to-digital conversion operation: In response to the differential sampling signal pair and corresponding pairs of the first differential signal pair to the n-1th differential signal pair among the n differential signal pairs, sequentially charging each pair of the n second differential node pairs; In response to each of the n second differential node pairs being sequentially charged, sequentially generating each of the n first differential data pairs; and sequentially generating each of the n upper differential data pairs in response to a corresponding pair of the n first differential data pairs generated sequentially; In the second analog-to-digital conversion operation: In response to an nth differential signal pair among the n differential signal pairs, simultaneously discharging each of the n second differential node pairs; and In response to each of the n second differential node pairs being discharged simultaneously, generating n second differential data pairs having different phases or the same phase; and A second analog-to-digital conversion unit, wherein the second analog-to-digital conversion unit is configured as: Perform multiple phase interpolation operations on at least two adjacent data in the n second differential data pairs to generate 2 n +m-digit thermometer code, m is less than 2 n ;and Regarding the 2 n +m-bit thermometer code is encoded to generate at least n+1 bits of low-order digital data, Each of the analog-to-digital converters is configured to generate the 2n-bit digital data using the n-bit high-order digital data and the at least n+1-bit low-order digital data.

18. The semiconductor device according to claim 17, wherein: The at least n+1 bits of low-order digital data include 2 n erroneous data, k first error digital data and k second error digital data, k is less than 2 n ,and Wherein, the analog-to-digital converter further includes an error correction unit, and the error correction unit is configured as follows: The n-bit high-order digital data and the 2 n one of the k erroneous digital data or one of the k first error digital data is added to generate the final n-bit digital data; or The n-bit upper digital data is added to data obtained by adding "1" to the upper bit of one of the k first error data to generate the final n-bit digital data.

19. The semiconductor device according to claim 17, wherein: The first analog-to-digital conversion unit comprises: n voltage-to-time converters, wherein the n voltage-to-time converters are configured as follows: Before the sampling operation, in response to a pull-down reset clock signal, resetting the n second differential node pairs to a ground voltage; During the first analog-to-digital conversion operation, in response to a corresponding pull-up clock signal among the sequentially generated n pull-up clock signals and the differential sampling signal pair and the corresponding pair among the sequentially generated first differential signal pair to the n-1th differential signal pair, sequentially charging each of the n second differential node pairs to sequentially generate each of the n first differential data pairs; After the first analog-to-digital conversion operation, resetting the n second differential node pairs to a power supply voltage in response to a pull-up reset clock signal; and During the second analog-to-digital conversion operation, in response to the pull-down clock signal and the nth differential signal pair, each of the n second differential node pairs is discharged simultaneously to generate the n second differential data pairs; n latches, the n latches sequentially latching each of the n first differential data pairs to generate the n upper differential data pairs; and A timing generation unit, wherein the timing generation unit is configured to: generating the pull-down reset clock signal before the sampling operation; During the first analog-to-digital conversion operation: generating a first pull-up clock signal among the n pull-up clock signals; and generating a second pull-up clock signal to an n-th pull-up clock signal among the n pull-up clock signals by detecting a transition of each of a first data pair to an n-1-th data pair among the n first differential data pairs; generating the pull-up reset clock signal in response to the nth pull-up clock signal after the first analog-to-digital conversion operation; and The pull-down clock signal is generated during the second analog-to-digital conversion operation.

20. The semiconductor device according to claim 19, wherein Each of the n voltage-to-time converters comprises: a first pull-up reset transistor and a second pull-up reset transistor, the first pull-up reset transistor and the second pull-up reset transistor being connected between the power supply voltage and a corresponding pair of the n second differential node pairs and configured to reset the corresponding pair of the n second differential node pairs to the power supply voltage in response to the pull-up reset clock signal; a first pull-up transistor and a second pull-up transistor, the first pull-up transistor and the second pull-up transistor being connected in series between the power supply voltage and a first node in the corresponding pair of the n second differential node pairs, and configured to charge the first node in the corresponding pair of the n second differential node pairs in response to a first differential signal in the corresponding pair of the n differential signal pairs and a first pull-up clock signal in the n pull-up clock signals; a third pull-up transistor and a fourth pull-up transistor, the third pull-up transistor and the fourth pull-up transistor being connected in series between the power supply voltage and the second node in the corresponding pair of the n second differential node pairs and configured to charge the second node in the corresponding pair of the n second differential node pairs in response to a second differential signal in the corresponding pair of the n differential signal pairs and a second pull-up clock signal in the n pull-up clock signals; a first pull-down reset transistor and a second pull-down reset transistor, the first pull-down reset transistor and the second pull-down reset transistor being connected between a corresponding pair of the n second differential node pairs and the ground voltage and configured to reset the corresponding pair of the n second differential node pairs to the ground voltage in response to the pull-down reset clock signal; a first pull-down transistor and a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first node in the corresponding pair of the n second differential node pairs and the ground voltage, and configured to discharge the first node in the corresponding pair of the n second differential node pairs in response to the pull-down clock signal and the second differential signal in the corresponding pair of the n differential signal pairs; and a third pull-down transistor and a fourth pull-down transistor, the third pull-down transistor and the fourth pull-down transistor being connected in series between the second node in the corresponding pair of the n second differential node pairs and the ground voltage, and being configured to discharge the second node in the corresponding pair of the n second differential node pairs in response to the pull-down clock signal and the first differential signal in the corresponding pair of the n differential signal pairs, The ratio between the size of the second pull-down transistor and the size of the fourth pull-down transistor of each of the n voltage-to-time converters is different from each other.

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