Multi-level voltage detector

Abstract

A voltage detector (100) comprises: an input (103); a resistor divider circuit (102) having: resistors (R1, R2, R3, ..., RN, RN+1) coupled in series with each other between the input (103) and a reference node (115); and N intermediate nodes (111, 112, 113, 114) connecting adjacent resistor pairs. The voltage detector (100) has: N switches (S1, S2, S3, S4) coupled to respective intermediate nodes (111, 112, 113, 114); and a comparator (106) having an input (108) coupled to the switches (S1, S2, S3, S4); a state machine (110) having an input coupled to an output (109) of the comparator (106); and a decoder (120) having N decoder outputs (121, 122, 123, 124) coupled to respective control terminals of the N switches (S1, S2, S3, S4).

Description

Background Art

[0001] Voltage detector circuits can be used in a variety of applications to track changes in voltage signals. Voltage tracking can be used for feedback adjustment of DC to DC converters or other applications for generating multi-level signals to represent or track the amplitude of a voltage signal. Selecting from different types of multi-level voltage detectors involves trade-offs between speed, accuracy, size, and complexity. One type of multi-level voltage detector uses a flash analog-to-digital converter (ADC) with multiple comparators and resistor divider circuits. Flash ADC designs occupy a large amount of die and / or board area and consume a lot of power. In addition, the flash ADC approach suffers from mismatches between the input offsets of all comparators, especially for small voltage level intervals. In addition, the complexity and area of ​​the encoding logic increase significantly as the number of comparators increases. Although the flash ADC voltage detector can provide a converted value in a single clock cycle, this form of voltage detector suffers from increasing parasitic load capacitance as the number of comparators increases, which limits the speed of operation. Another type of multi-level voltage detector uses a successive approximation register (SAR) ADC, which has a single comparator that operates according to a slow binary search algorithm. SAR ADC designs consume less power and take up less space than flash ADC designs. Additionally, SAR ADC voltage converters do not suffer from comparator mismatch issues associated with flash ADC designs. However, the binary search algorithm used in SAR ADCs produces only a single bit per converter clock cycle and may require a sample-and-hold circuit, which increases power and area. Summary of the invention

[0002] In one aspect, a voltage detector includes: a resistor divider circuit having N intermediate nodes connecting adjacent pairs of voltage-dividing resistors, a switch circuit having N switches coupled to respective intermediate nodes, and a comparator having inputs coupled to the switches, and a state machine having inputs coupled to outputs of the comparator, and having a decoder having N decoder outputs coupled to respective control terminals of the N switches.

[0003] The state machine in one example has a current state in each cycle of the clock signal, and the current state has one of N possible state values. The decoder in one example is configured to activate only one of the decoder outputs to turn on the corresponding single switch in the switch according to the current state in each cycle of the clock signal. In one example, the state machine is configured to selectively update the current state to the next state value in response to the clock signal and in response to the comparator output signal at the comparator output. In one example, the state machine is configured to set the next state value to the current state value or the intermediate state value adjacent to the current state value according to the comparator output signal of the current state with the first state value or the Nth state value. For the current state with the intermediate state value, the state machine is configured to set the next state value to one of two adjacent state values ​​according to the comparator output signal.

[0004] In one example, the state machine includes a second decoder having N+1 second decoder outputs, and the second decoder is configured to activate only one of the second decoder outputs at a time. The second decoder is configured to activate one of the second decoder outputs in each cycle of the clock signal according to the current state and the next state of the state machine. For the current state and the next state with the first state value, the second decoder is configured to activate the first output in the second decoder output. For the current state and the next state with the Nth state value and the next state value with the Nth state value, the second decoder is configured to activate the N+1th output in the second decoder output. For the current state with the i-th state value and the next state value with the i+1th state value, the second decoder is configured to activate the i+1th output in the second decoder output. For the current state with the i+1th state value and the next state value with the i-th state value, the second decoder is configured to activate the i-th output in the second decoder output.

[0005] In another aspect, a method includes coupling a single node of an integer number N of intermediate nodes of a resistor divider circuit to an input of a comparator according to a current state of a state machine having one of N possible state values ​​in each cycle of a clock signal. The method further includes selectively updating a state value of the current state to a next state value in response to the clock signal and in response to a comparator output signal at the comparator output, and activating a single output of N+1 decoder outputs in a given cycle of the clock signal according to the state value of the current state and the next state value. In one example, the method further includes adjusting an operating condition of a power converter according to the decoder output.

[0006] In one example, updating the state value of the current state to the next state value includes setting the next state value to the current state value or an intermediate state value adjacent to the current state value according to a comparator output signal for a current state having a first state value or an Nth state value. For a current state having an intermediate state value, updating the state value includes setting the next state value to one of two adjacent state values ​​according to a comparator output signal.

[0007] In one example, activating a single output of the N+1 decoder outputs in a given cycle of the clock signal includes activating the first output for a current state and a next state having a first state value, and activating the N+1th output of the second decoder output for a current state and a next state having an Nth state value. For a current state having an i-th state value and a next state value having an i+1th state value, the method includes activating the i+1th output of the second decoder output, and for a current state having an i+1th state value and a next state value having an i-th state value, activating the i-th output of the second decoder output.

[0008] In yet another aspect, a power converter includes an inductor coupled to a switch node, a switch having a terminal coupled to the switch node and a control input, a current sensor coupled to the switch node, and a current reference circuit having an integer N+1 current reference inputs and a current reference output. The power converter further includes a converter comparator having a first input coupled to the current sensor, a second input (618) coupled to the output of the current reference circuit and an output, and a controller and a voltage detector. The controller has an input coupled to the output of the converter comparator and an output coupled to the control input of the switch. The voltage detector includes a voltage detector input coupled to the converter output, a state machine having a state, and N+1 decoder outputs coupled to corresponding current reference inputs of the N+1 current reference inputs, the state having N possible state values.

[0009] In one example, the voltage detector includes a resistor divider circuit, a switch circuit having N switches coupled to respective intermediate nodes of the resistor divider, and a second terminal and a control terminal. The voltage detector further includes a comparator having a first input coupled to a voltage reference, a second input coupled to the switch, and an output. The state machine has an input coupled to the output of the comparator, a first decoder having N first decoder outputs coupled to respective control terminals of the switches, and a second decoder having N+1 decoder outputs coupled to respective current reference inputs of the N+1 current reference inputs.

[0010] In one example, the state machine has a current state having one of N possible state values ​​in each cycle of a clock signal, and the first decoder is configured to activate only a single output in the first decoder output to turn on a corresponding single switch in the switch according to the current state in each cycle of the clock signal. The first decoder is configured to activate the i-th output in the decoder output in a given cycle of the clock signal in which the current state is the i-th possible state value among the N possible state values, and the state machine is configured to selectively update the current state to a next state value in response to the clock signal and in response to a comparator output signal at the comparator output. In one example, the state machine is configured to set the next state value to the current state value or to an adjacent intermediate state value for a current state having a first state value or an N-th state value, and for a current state having an intermediate state value, the state machine is configured to set the next state value to one of two adjacent state values ​​adjacent to the current state value according to the comparator output signal.

[0011] In one example, the second decoder is configured to activate only a single output in the decoder output at a time. In one example, for a current state and a next state having a first state value, the second decoder is configured to activate the first output in the decoder output. For a current state and a next state having an Nth state value, the second decoder is configured to activate the N+1th output in the decoder output. For a current state having an i-th state value and a next state value having an i+1th state value, the second decoder is configured to activate the i+1th output in the decoder output, and for a current state having an i+1th state value and a next state value having an i-th state value, the second decoder is configured to activate the i-th output in the decoder output. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of a voltage detector having an N-state state machine, an N-bit first decoder that controls the connection of a resistor divider node to a comparator, and an N+1-bit second decoder.

[0013] Figure 2 N = 4 Figure 1 A state diagram for an example of a state machine.

[0014] Figure 3 N = 4 Figure 1 An example state table of a voltage detector.

[0015] Figure 4 yes Figure 1 A schematic diagram of an example of a state machine.

[0016] Figure 5 is a flow chart of a method for adjusting a peak current reference of a boost power converter.

[0017] Figure 6 Is has Figure 1 Schematic diagram of a DC to DC boost power converter using a voltage detector to adjust the peak current reference.

[0018] Figure 7-Figure 9 yes Figure 6 Signal diagram of a power converter. DETAILED DESCRIPTION

[0019] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In addition, the term "couple" or "couples" includes indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled with a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intermediate devices and connections. One or more operating characteristics of various circuits, systems, and / or components are described below in the context of functionality, which in some cases results from the configuration and / or interconnection of various structures when the circuits are powered and operated.

[0020] Initial reference Figure 1-Figure 4 , an example multi-level voltage detector 100 is illustrated and described below using a state machine with an integer number of N states, a resistor divider circuit, and a single comparator, where N is greater than 2. The state machine has N+1 decoder outputs that provide a converted value or representation of the tracked voltage in each cycle of the clock signal. Unlike SAR ADC designs, the voltage detector 100 provides fast voltage tracking without adding excessive parasitic load capacitance. In addition, compared to flash ADC designs, the single comparator voltage detector 100 provides a compact, low-complexity solution with a smaller circuit area and improved power efficiency, and no mismatch issues.

[0021] Figure 1An example of a voltage detector 100 is shown having a resistor divider circuit 102 coupled to an input 103, a switch circuit 104, and a single comparator 106 having respective first and second inputs 107, 108, and an output 109. The voltage detector 100 also includes a state machine 110. The resistor divider circuit 102 has an integer number N+1 of resistors R1, R2, R3, ..., RN, and RN+1 coupled in series with each other between the input 103 and a reference node. The example voltage detector 100 is described below in the context of a 4-state state machine 110, where N=4. In other examples, N is any integer greater than 2. The resistor divider circuit 102 includes N=4 intermediate nodes 111, 112, 113, and 114, where respective ones of the intermediate nodes 111, 112, 113, and 114 connect adjacent pairs of resistors R1, R2, R3, ..., RN, and RN+1. In this example, a first intermediate node 111 connects resistors R1 and R2, a second intermediate node 112 connects adjacent resistors R2 and R3, a third intermediate node 113 connects resistors R3 and RN, and a fourth intermediate node 114 connects resistors RN and RN+1. The series-connected resistors R1, R2, R3, ..., RN, and RN+1 are connected in series with each other between the input 103 and a reference node 115 (e.g., a ground reference or other reference voltage node). The resistor divider circuit 102 provides a voltage divider circuit with intermediate node voltages V1, V2, V3, and V4 at respective intermediate nodes 111, 112, 113, and 114.

[0022] The switch circuit 104 includes N switches S1, S2, S3, and S4, each having a first terminal coupled to a respective one of the intermediate nodes 111, 112, 113, 114. The switches S1, S2, S3, and S4 each have a second terminal coupled to a second input 108 of the comparator 106. Each of the switches S1, S2, S3, and S4 also has a control terminal. Any suitable switch, such as a transistor, may be used. The voltage detector 100 in one example tracks the boost converter voltage VBST of the power converter circuit, as described below in conjunction with Figure 6 In one example, the state machine 110 provides an output to the N+1 bit decoder that represents the magnitude of the boost converter voltage VBST relative to the voltage of the reference node 115. In the example shown, the first input 107 of the comparator 106 is connected to the reference voltage VB, and the comparator output 109 provides a comparator output signal CMP having one of two possible states or ranges (e.g., "1" or "0"), depending on whether the voltage V1, V2, V3, or V4 connected to the second comparator input 108 is greater than or less than the reference voltage VB.

[0023] Figure 1The resistors R1, R2, R3, ..., RN and RN+1 in have values ​​of 250 kΩ, 98 kΩ, 75 kΩ, 77 kΩ and 500 kΩ, respectively, and a reference voltage VB=1.5 V to track a boost voltage VBST in the range of 0-3.6 V, the threshold voltage of the boost voltage VBST being associated with different switch circuit states of approximately 2.0, 2.3, 2.6 and 3.0 V. In other examples, other resistor values ​​and reference voltage values ​​are used. In the illustrated embodiment, the voltage detector 100 tracks the voltage VBST at the input 103 relative to the voltage of the reference node 115. In another example, a constant reference voltage is connected to the input 103, and the voltage detector 100 tracks the voltage at the first comparator input 107.

[0024] Unlike the Flash ADC voltage detector method, Figure 1 The voltage detector 100 in FIG. 1 uses only a single comparator 106. Furthermore, unlike a successive approximation register converter, the voltage detector 100 does not use a slow binary search algorithm, but rather uses an N=4 state machine 110 and a novel fast search algorithm that provides a converted state or decoder output that characterizes the channel voltage VBST in each cycle of the clock signal.

[0025] The state machine 110 includes an input coupled to the output 109 of the comparator 106. In addition, the state machine 110 has a current state 118, which has one of N possible state values ​​in each cycle of the clock signal CLK. In one example, the state machine 110 includes a register storing the state value of the current state 118. The state machine 110 also includes a first decoder 120 having N decoder outputs 121, 122, 123, and 124 coupled to the corresponding control terminals of the N switches S1, S2, S3, and S4. The collective decoder outputs 121, 122, 123, and 124 form an N-bit decoder output 125. The first decoder 120 is configured to activate only a single output of the decoder outputs 121, 122, 123, or 124 to turn on the corresponding single switch of the switches S1, S2, S3, or S4 according to the current state 118 in each cycle of the clock signal CLK.

[0026] In the illustrated embodiment, the first decoder 120 provides switch control signals SW1, SW2, SW3, and SW4 at the corresponding decoder outputs 121, 122, 123, and 124 with appropriate voltages so that only one of the corresponding switches S1, S2, S3, or S4 is activated (i.e., turned on) at a time. In one embodiment, the switch S1, S2, S3, or S4 is an n-channel field effect transistor (FET), and the first decoder 120 provides a single signal of the switch control signals SW1, SW2, SW3, and SW4 in a high active state to turn on the corresponding one of the switches S1, S2, S3, or S4, while the other switch control signals remain low. The N-bit first decoder 120 controls the connection of the resistor divider node 111, 112, 113, or 114 to the input 108 of the comparator 106.

[0027] State machine 110 also includes a second decoder 130 having an N+1-bit decoder output 136 having five second decoder outputs 131, 132, 133, 134, and 135. In one example, second decoder output 136 is coupled to a boost converter (e.g., Figure 6 ) in a peak current selection circuit, and the second decoder 130 provides corresponding current selection second decoder output signals CS1, CS2, CS3, CS4 and CS5 at corresponding second decoder outputs 131, 132, 133, 134 and 135. In this example, the second decoder 130 provides a single signal of the switch control signals CS1, CS2, CS3, CS4 and CS5 in a high active state, while the other switch control signals remain low. The voltage detector 100 has a clock input 140 configured or otherwise adapted to receive a clock signal CLK, and an enable input 141 adapted to receive an enable signal EN.

[0028] Figure 2 shows a system with N=4 states Figure 1 1. The state diagram 200 of the state machine 110 is shown. The state machine 110 is configured to maintain and selectively update the current state 118 with one of N possible state values ​​210, 220, 230, and 240 in each cycle of the clock signal CLK at the clock input 140. The possible state values ​​include a first state value 210 (state 1), N-2 intermediate state values ​​220 (state 2) and 230 (state 3), and a final or Nth state value 240 (state 4). The state machine 110 maintains and updates the current state 118 with one of N=4 possible state values ​​210, 220, 230, or 240 in each cycle of the clock signal CLK at the clock input 140 ( Figure 1 ).

[0029] Figure 1 The first decoder 120 in the state machine 110 is configured to activate an i-th output among the decoder outputs 121, 122, 123, or 124 in a given cycle of the clock signal CLK, wherein the current state 118 is the i-th state among the N corresponding possible state values ​​210, 220, 230, or 240. The state machine 110 is configured to selectively update the current state 118 to a next state value 210, 220, 230, or 240 in response to the clock signal CLK and in response to the comparator output signal CMP at the output 109 of the comparator 106.

[0030] Figure 2 The state diagram 200 in FIG. 1 illustrates the state update of the state machine 110. In operation in one example, the state machine 110 starts at the first state value 210 (state 1) in response to the valid signal EN at the enable input 141. In operation, when the current state 118 has the first state value 210 or the Nth (e.g., 4th) state value 240, the state machine 110 is configured to set the next state value to the current state value (e.g., no change) in response to the comparator output signal having the same value as in the previous cycle of the clock signal CLK. Figure 2 As shown, when the current state is the first state 210 and the comparator output signal CMP=0, the state diagram transitions back to the first state 210 (the first switch S1 is turned on) along path 211. The first switch control signal SW1=1, and the second decoder provides a first decoder signal CS1=1 (valid). Otherwise, if the comparator output signal CMP=1, the converter boost voltage VBST has transitioned through the first threshold (discussed further below), and the state machine 110 sets the next state value to the adjacent intermediate state value 220.

[0031] As used herein, adjacent states are sequentially adjacent, as the first state 210 and the second state 220 are adjacent to each other, the first state 210 and the third state 230 are adjacent to the second state 220, the second state 220 and the fourth state 240 are adjacent to the third state 230, and the third state 230 and the fourth state 240 are adjacent to each other. Figure 2 In the example of FIG. 2 , in response to the comparator output signal CMP=1, the state diagram 200 transitions from the first state 210 to the second state 220 along the path 212. This indicates that the converted boost voltage VBST has transitioned through the first threshold (e.g., the following Figure 7 ). The state machine activates the second switch control signal SW2=1 to turn on the second switch S2 in the second state 220, and the second decoder output activates the second decoder output (eg, current select) signal CS2=1.

[0032] When the current state has one of the intermediate state values ​​220 or 230, the state machine 110 is configured to set the next state value to one of the two state values ​​adjacent to the current state value according to the comparator output signal CMP. Figure 2 In the example in FIG. 1 , when the state machine 110 is currently in the second state 220, the next state value will be the first state 210 or the third state 230 (e.g., the state machine does not remain in any of the intermediate states 220 or 230 in two consecutive cycles of the clock signal CLK). In this example, if the comparator output signal CMP=0 (indicating that the converted boost voltage VBST has not yet transitioned through the second threshold), the state machine 110 transitions along the first path 221 to set the next state to the first state 210. For the transition along the path 221, the state machine sets the first switch control signal SW1=1 by the first decoder 120 to turn the first switch S1 into the conductive state again. In addition, in this example, the second decoder 130 activates its second output again by setting the second current selection signal CS2=1. In this way, when the state machine transitions back and forth between the first state 210 and the second state 220, the second decoder 130 maintains the current selection signaling in its second state.

[0033] continue Figure 2 , when the current state is the second state 220 and the comparator output signal CMP=1, the state diagram 200 transitions from the second state 220 to the third state 230 along the second path 222. The comparator output condition indicates that the converted boost voltage VBST has transitioned through the second threshold. In response, the first decoder 120 activates its third switch control signal SW3=1 to turn on the third switch S3. In addition, the second decoder 130 activates its third output to set the third current selection signal CS3=1.

[0034] When the current state is the third state 230, the state machine 110 selectively transitions to one of its adjacent states 220 or 240 according to the comparator output signal CMP. If the comparator output signal CMP=0 (indicating that the converted boost voltage VBST has not transitioned through another threshold), the state diagram 200 transitions back to the second state 220 along the first path 231. In this case, the first decoder 120 activates its second output again to set the second switch control signal SW2=1 to turn on the second switch S2 again, and the second decoder 130 activates its third output again to set the third current selection signal CS3=1. On the contrary, if the comparator output signal CMP=1 (indicating that the converted boost voltage VBST has transitioned to be higher than the fourth threshold), the state diagram 200 transitions from the third state 230 to the fourth state 240 along the second path 232. In this transition along path 232 , the first decoder 120 activates its fourth output 124 to set the fourth switch control signal SW4 =1, and the second decoder 130 activates its fourth output to set the fourth current select signal CS4 =1.

[0035] When the current state is the fourth state 240, the state machine 110 is configured to set the next state value to the current state value 240 (along the transition path 242) in response to the comparator output signal (CMP=1) having the same value as in the previous cycle of the clock signal CLK, or to transition along the path 241 in response to the change of the comparator output signal CMP=0 indicating that the converted boost voltage VBST has transitioned below the fourth threshold to transition to the adjacent third state 234. In the first case (CMP=1), the first decoder 120 activates its fourth output 124 again to set the fourth switch control signal SW4=1, and the second decoder 130 activates its fourth output to set the fourth current selection signal CS4=1. In the latter case (CMP=0), the first decoder 120 activates its third switch control signal SW3=1 to turn on the third switch S3, and the second decoder 130 activates its third output to set the third current selection signal CS3=1.

[0036] like Figure 2As shown in the example state diagram 200 of , the second decoder 130 is configured to activate one of the second decoder outputs 131, 132, 133, 134, or 135 in a given cycle of the clock signal CLK according to the state value of the current state 118 and the next state value. For the current state 118 having the first state value 210 and the next state value having the first state value 210, the second decoder 130 is configured to activate the decoder output 131, and for the current state 118 having the Nth state value 240 and the next state value having the Nth state value 240, the second decoder 130 is configured to activate the N+1th output among the second decoder outputs 135. For the current state 118 having the i-th state value 210, 220, 230 and the next state value having the i+1th state value 220, 230, 240, the second decoder 130 is configured to activate the i+1th output among the second decoder outputs 132, 133, 134, 135. Furthermore, for a current state 118 having an i+1th state value 210, 220, 230 and a next state value having an i-th state value 220, 230, 240, the second decoder 130 is configured to activate an i-th output among the second decoder outputs 132, 133, 134, 135. In all cases, the second decoder 130 is configured to activate only a single output among the second decoder outputs 131, 132, 133, 134, 135 at a time.

[0037] Figure 3 Shows Figure 1 The state table of the state machine 110 in the voltage detector 100 further illustrates Figure 2 2. The state table 300 includes a first row in which the converted boost voltage VBST is less than a first threshold TH1=2.0V of a first state 301 corresponding to N+1 states (e.g., 5 different current selection states) of the second decoder 130. The second current selection state 302 includes two rows of the table 300, which correspond to the transitions between the first state 210 and the second state 220 of the state machine 110. The second current selection state 302 corresponds to the converted boost voltage signal VBST between the first threshold TH1 and the second threshold TH2=2.3V (e.g., 2.0<VBST<2.3). The third current selection state 303 includes the next two rows of the table 300, which correspond to the state machine 110 transitioning back and forth between the second state 220 and the third state 230. Figure 3The third current selection state 303 in the table 300 includes two rows corresponding to the state machine 110 transitioning back and forth between the second state 220 and the third state 230. The third current selection state 303 corresponds to the boost voltage signal VBST after transition between the second threshold TH2 and the third threshold TH3 = 2.6V (e.g., 2.3 < VBST < 2.6).

[0038] The fourth current selection state 304 includes two rows of the table 300, which correspond to the state machine 110 transitioning back and forth between the third state 230 and the fourth state 240. The fourth current selection state 304 corresponds to the boost voltage signal VBST after transition between the third threshold TH3 and the fourth threshold TH4=3.0V (e.g., 2.6<VBST<3.0). The fifth current selection state 305 includes the last row of the table 300, which corresponds to the state machine 110 remaining in the fourth state 240, in which VBST remains above the fourth threshold TH4 (e.g., VBST>3.0V).

[0039] The state table 300 includes a first column 311 showing the voltage range of the converted boost voltage signal VBST, a second column 312 indicating the corresponding state of the state machine 110, and a third column 313 showing the corresponding first decoder valid output signal (e.g., switch control signal). The fourth column 314 shows the corresponding action value of the comparator output signal CMP (e.g., LOW corresponds to the "0" state as described above, and HIGH corresponds to the "1" state). The fifth column 315 shows the valid output signal of the second decoder 130 (e.g., the valid current selection signal), and the sixth column 316 indicates the current selection signal as described below in conjunction with Figure 6 The corresponding peak current value is selected as a result of the second decoder output in the discussed example boost converter.

[0040] Figure 4 Shows Figure 1An example circuit implementation of a state machine 110 is shown in FIG. 1. The state machine 110 includes a register or a set of D flip-flops 401, 402, 403, and 404 that store and maintain states 118 as corresponding state output signals STD1, STD0, ST0, and ST1. The flip-flops 401-404 have clock inputs coupled to the clock input 140 of the state machine 110, and clear inputs coupled to the enable input 141 of the state machine 110. The comparator output 109 is coupled to a logic circuit formed by 2-input AND gates 411, 412, 413, 415, and 416 and 3-input OR gates 414 and 417. The OR gates 414 and 417 of the logic circuits 411-417 provide data input signals to corresponding data inputs of the flip-flops 403 and 404 based on the comparator output signal CMP and the current and next state signals ST0 and ST1. The first decoder 120 receives the state output signals STD1, STD0, ST0 and ST1 from the current state 118 and provides the switch control signals SW1, SW2, SW3 and SW4 at the first decoder outputs 121, 122, 123 and 124, respectively. The first decoder 120 also provides the reverse switch signals SWD1, SWD2, SWD3 and SWD4 to the second decoder 130.

[0041] The second decoder 130 receives the state output signals STD1, STD0, ST0 and ST1, and the inverted switching signals SWD1, SWD2, SWD3 and SWD4, and generates current selection signals CS1, CS2, CS3, CS4 and CS5 at corresponding second decoder outputs 131, 132, 133, 134 and 135. The second decoder 130 includes an AND gate 420, NAND gates 421, 422, 423, 424, 425, 426, 427, 428 and 429, and a Figure 4 Another AND gate 430 is shown interconnected. NAND gates 420, 423, 426, 429 and 430 have outputs coupled to each providing a corresponding second decoder output 131, 132, 133, 134 and 135. The first decoder 120 includes a first circuit having inverters 441 and 442 and a two-input NOR gate 443 and AND gates 444, 445 and 446, which generate switch control signals SW1, SW2, SW3 and SW4 at corresponding first decoder outputs 121, 122, 123 and 124 according to state output signals ST0 and ST1. The second circuit of the first decoder 120 includes inverters 451 and 452, a dual-input NOR gate 453 and AND gates 454, 455 and 456, which generate switch control signals SW1, SW2, SW3 and SW4 at corresponding first decoder outputs 121, 122, 123 and 124 according to state output signals STD0 and STD1.

[0042] The voltage detector 100 implements fast voltage tracking via the N+1 level second decoder output 136, which allows peak current selection from 5 different peak current values ​​to adjust the power converter circuit in an application, as shown below in conjunction with Figure 6 Further described. The voltage detector 100 provides fast conversion or tracking within a single clock signal cycle and uses less power and board / die area without comparator offset mismatch effects. In one possible application, VB is a reference voltage and VBST is a varying input voltage for detection. In another possible application, VBST is a fixed reference voltage and VB is a varying input voltage for detection. In another possible application, both VBST and VB are varying voltages and the voltage detector 100 converts the voltage ratio of VB / VBST. Compared to the binary search method of the successive approximation register voltage detector, the low complexity fast tracking search algorithm of the state machine 110 facilitates fast operation using a single comparator 106 without any sample and hold circuits.

[0043] Also refer to Figure 5 , Figure 5 A method 500 for adjusting a peak current reference of a power converter is described. The method 500 includes coupling a single node of an integer number N of intermediate nodes 111, 112, 113, 114 of the resistor divider circuit 102 to an input 108 of the comparator 106 at 502 according to a current state 118 of the state machine 110. In the above example, the current state 118 in one implementation has one of the N possible state values ​​210, 220, 230, 240 in each cycle of the clock signal CLK.

[0044] At 504, the method 500 continues to selectively update the state value of the current state 118 to a next state value in response to the clock signal CLK and the comparator output signal CMP. In one example, the state value is used to generate switch control signals SW1-SW4 to connect one of the intermediate nodes of the resistor divider circuit to the next state value. Figure 1 In one example, the state update at 504 includes, if the current state 118 has the first state value 210 or the Nth state value 240, setting the next state value to the current state value or to the adjacent intermediate state value according to the comparator output signal CMP; and if the current state 118 has one of the intermediate state values ​​220 or 230, setting the next state value to one of the two adjacent state values ​​according to the comparator output signal CMP.

[0045] The method 500 continues at 506 by activating a single output (e.g., 131, 132, 133, 134, or 135) of the N+1 second decoder outputs in a given cycle of the clock signal CLK according to the current and next state values. In one example, the decoder output activation at 506 includes: activating a first output (e.g., output 131) of the second decoder outputs for a current state 118 having a first state value 210 and a next state value having the first state value 210, and activating an N+1th output (135) of the second decoder outputs for a current state 118 having an Nth state value 240 and a next state. In this example, the decoder output activation at 506 also includes: activating an i+1th output of the second decoder outputs for a current state 118 having an ith state value and a next state value having an i+1th state value, and activating an ith output of the second decoder outputs for a current state 118 having an i+1th state value and a next state value having an ith state value. In one embodiment, method 500 continues at 508 by adjusting operating conditions of the power converter (eg, peak inductor current IPEAK) based on the activated output 131, 132, 133, 134, or 135 of second decoder 130. In another embodiment, the second decoder output is used for another purpose.

[0046] Figure 6 Shows that there is Figure 1An example of a fast tracking voltage detector 100 to adjust a peak current reference hysteretic boost DC to DC power converter 600. In one embodiment, the boost converter 600 is configured to provide a regulated DC voltage VBST ranging from 0 to 3.6V, and the reference voltage VB is 1.5V. In the illustrated embodiment, the clock signal CLK provided to the voltage detector clock input 140 is or is derived from the low-side switch off signal TOFF to allow the voltage detector 100 to autonomously adjust the inductor peak current during the stable period of the hysteretic boost power converter 600. The boost power converter 600 includes a converter input 601, which is suitable for connecting to an input source (e.g., a battery, not shown) to receive a DC input voltage signal VBAT. The power converter 600 further includes an inductor 602 having an inductance L. The inductor 602 is coupled between the input 601 and a switch node 604 having a switch node voltage VSW. The power converter 600 also includes an output that transmits a boosted output voltage signal VBST. The converter output is connected to a voltage detector input 103 in a voltage feedback loop that selectively adjusts the peak current of the inductor 602. A diode 606 has an anode connected to the switch node 604 and a cathode connected to the converter output. An output capacitor 608 having a capacitance C is connected between the converter output and a reference node. In another embodiment, the diode 606 is replaced by a transistor or other switch (not shown).

[0047] The power converter 600 includes a switch 610 (e.g., an n-channel FET) having a first terminal (e.g., a drain) coupled to a switch node 604, a second terminal (e.g., a source) connected to a reference node, and a control input 611 (e.g., a gate terminal). The switch 610 operates according to a gate control signal to control the connection of the switch node 604 to the reference node and, therefore, controls the current IIND through the inductor 602. The switch 610 is Figure 6 In one example, the power converter 600 is used as a low-side switch in the boost converter configuration of the example in FIG. In other configurations, the switch 610 is configured as a low-side or high-side switch in different converter topologies, such as a buck converter, a buck-boost converter, a cuk converter, a flyback converter, etc. In one example, the power converter 600 is a DC-DC converter. In other examples, the power converter is an AC-DC converter.

[0048] Figure 6The boost power converter 600 also includes a current sensor 612 coupled to the switch node 604 to sense the inductor current when the switch 610 is turned on. In one example, the current sensor 612 is or includes a sense FET coupled to the switch 610, for example, having a size ratio of 1000 or greater. The comparator 614 includes a first (e.g., non-inverting or "+") input 616 connected to the output of the current sensor 612. The comparator 614 also includes an inverting (e.g., "-") input 618 and an output 619 that provides a current limit signal CUR_LIM. The inverting input 618 of the comparator 614 is coupled to the output of the peak current reference circuit 620. The current reference circuit 620 has N+1 current reference inputs that are respectively coupled to the N+1 second decoder outputs 131-135 of the voltage detector 100. In this configuration, the second decoder output 136 of the voltage detector 100 selects the current reference signal of the current reference circuit 620 used by the comparator 614. The comparator 614 compares the current feedback signal from the current sensor 612 with a selected reference current from the current reference circuit 622 to generate a current limit signal CUR_LIM at the comparator output 619 .

[0049] The power converter 600 also includes a controller 622 including an input coupled to an output 619 of the converter comparator 614 and an output 624 coupled to provide a switch control signal SC to a control input 611 of the switch 610 through a driver circuit 626. In one example, a second comparator 630 includes a first (e.g., non-inverting) input 632 coupled to an intermediate node connected to resistors 634 and 636 connected to each other between the switch node 604 and a reference node. A second input (e.g., inverting) of the second comparator 630 is connected to a second intermediate node connected to resistors 640 and 642 connected in series to each other between the converter output and the reference node. The comparator 630 has an output 639 that provides a switch to turn off a signal TOFF to a second input of the controller 622. In one example, the second comparator 630 operates as a zero-crossing detector with respect to the inductor current IIND so that the turn-off signal TOFF turns off the converter switch 610. The third comparator 644 has a first input 646 (e.g., non-inverting) coupled to receive the voltage reference signal VREF and a second input 648 coupled to the second input 638 of the second comparator 630. The third comparator 644 has an output 649 that provides a high output signal BST_HI to a third input of the controller 622, e.g., in response to the boost converter output voltage VBST exceeding a target or set point value set by the reference voltage VREF.

[0050] Also refer to Figure 7-Figure 9The controller 622 activates the switch control signal SC to turn on the switch 610 in each switching control cycle of the boost power converter 600 in response to the current limit signal CUR_LIM from the first comparator 614, and turns off the switch 610 in response to the rising edge of the shutdown signal TOFF from the second comparator 630. Figure 7 A graph 700 is shown having a first curve 702 showing the boost converter output voltage VBST as a function of time during operation of the power converter 600. Curve 704 shows the turn-off signal TOFF, and curve 706 shows the inductor current IIND. At time T1, as the voltage detector 100 operates in the first current selection state 301, the turn-off signal (curve 704) undergoes a rising transition caused by the second comparator 630, and the controller 622 turns off the converter switch 610. In response, the inductor current (curve 706) rises and the converter output voltage VBST drops. The controller 622 turns on the converter switch 610 again at time T2, causing the inductor current curve 7062 to decrease and the output voltage curve 702 to increase. The switching operation continues at times T3 and T4, after which the rising output voltage curve 702 exceeds the first threshold TH1. This causes the state machine 110 of the voltage detector 100 to assert the second current select decoder output 132 (current select signal CS2=1), and the voltage detector 100 operates in the second current select state 302. This increases the output of the current reference circuit 622 provided to the inverting input 618 of the first comparator 614. At time T5, the controller 622 again turns off the converter switch 610, and the switching operation is monitored by the first comparator 614 at T7, T8, T9, T10 and T11 for transitions above the second threshold ( Figure 7 ) continue.

[0051] Figure 8 The graph 800 shows various signals in the power converter 600 as a function of time, wherein the converter 600 has a varying output voltage VBST and the state machine 110 of the voltage detector 100 transitions through five current selection states 301, 302, 303, 304, and 305 as a function of time. In one example, the state machine 110 of the voltage detector 100 operates using a clock source having a fixed frequency. The graph 800 includes a first graph 802 showing the converter output voltage VBST, and a second graph 803 showing the state machine 110 of the voltage detector 100. Figure 1Graph 800 also includes curves 812, 814, 816, 818, and 820 showing corresponding current selection signals CS1, CS2, CS3, CS4, and CS5 provided by the second decoder 130. Graph 800 begins from T0 to T1 in the first current selection state 301, where SW1 and CS2 are active (corresponding to curves 804 and 812, respectively).

[0052] exist Figure 8 At time T1 in the example, VBST exceeds the first threshold TH1, the state machine 110 transitions the second decoder 132 to the second current selection state 302, and the first decoder 120 switches back and forth between its first state and the second state (alternatingly activating SW1 and SW2). In this example, at time T2, VBST exceeds the second threshold TH2, and the second decoder 130 transitions to the third current selection state 303 in which the first decoder 120 alternately activates SW2 and SW3. At T3, the converter output voltage VBST exceeds the third threshold TH3, which causes the second decoder 130 to operate in the fourth current selection state 304 thereafter, and the first decoder 120 alternately activates SW3 and SW4. At T4 in this example, the converter output voltage VBST exceeds the fourth threshold TH4, and the state machine 110 causes the decoders 130 and 120 to operate in the fifth current selection state 305 when the fourth switch control signal SW4 is activated.

[0053] The graph 800 further illustrates the operation for steadily reducing VBST, where VBST drops below the fourth threshold TH4 at T5, causing the second decoder 130 to operate in the fourth current selection state 304 again, and the first decoder 120 alternately activates SW3 and SW4. At T6, VBST drops below the third threshold TH3. In response, the second decoder 130 transitions to the third current selection state 303, and the first decoder 120 alternately activates SW2 and SW3. At T7, the converter output voltage VBST drops below the second threshold TH2, causing the second decoder 130 to transition to the second current selection state 302, and the first decoder 120 alternately activates SW1 and SW2. At T8, the converter output voltage drops below the first threshold TH1, which causes the second decoder 130 to transition to the first current selection state 301, and the first decoder 120 activates the first switch control signal SW1.

[0054] Fig. 9A graph 900 of a signal and power converter 600 for an increasing output voltage VBST is shown. In this example, the boost converter low-side shutdown signal TOFF is used as a clock signal CLK for the state machine 110 of the voltage detector 100. This allows the voltage detector 100 to operate autonomously without requiring a separate clock source. Graph 900 includes operation over time of gradually increasing VBST in current selection states 301, 302, 303, 304, and 3054, as shown in curve 902. Curve 904 shows the inductor current IIND, while curve 906 shows the clock signal (e.g., TOFF or CLK) in the state machine 110. Fig. 9 Curves 908, 910, 912, and 914 in FIG. 1 show the respective switch control signals SW1, SW2, SW3, and SW4 provided by the first decoder 120. In this example, the boost converter output voltage VBST (curve 902) transitions above the first threshold TH1 at time T1 and transitions above the second threshold TH2 at time T2. With each threshold transition, the voltage from Figure 6 The second decoder output 136 of the voltage detector 100 selects a gradually increasing reference current from the reference current circuit 624 compared to the current feedback signal of the current sensor 612 in FIG. Fig. 9 At time T3 in FIG. 8 , VBST exceeds the third threshold value TH3 , and thereafter exceeds the fourth threshold value TH4 at time T4 .

[0055] Modifications in the described examples are possible, and other implementations are possible, within the scope of the claims.

Claims

1. A voltage detector, comprising: enter; a resistor divider circuit having resistors coupled in series with each other between the input and reference nodes and an integer number N of intermediate nodes, respective ones of the intermediate nodes connecting adjacent pairs of resistors, N being greater than 2; a switching circuit having N switches, respective ones of the switches having first terminals, second terminals, and control terminals coupled to respective ones of the intermediate nodes; a comparator having a first input coupled to a reference voltage, a second input coupled to the second terminal of the switch, and an output; as well as a state machine having: an input coupled to the output of the comparator; a first decoder having N first decoder outputs coupled to respective control terminals of the N switches; and a second decoder having N+1 second decoder outputs, the second decoder outputs having at least a first decoder state and a second decoder state representing different power converter reference current levels, and the state machine is configured to transition from the first decoder state to the second decoder state in response to the input having the first state, and to transition from the second decoder state to the first decoder state in response to the input having the second state.

2. The voltage detector of claim 1 , further comprising a clock input, the state machine having a current state in each cycle of a clock signal at the clock input, the current state having one of N possible state values; in, The decoder is configured to activate only a single one of the first decoder outputs to turn on a corresponding single one of the switches according to the current state in each cycle of the clock signal.

3. The voltage detector according to claim 2, wherein: The N possible state values ​​include a first state value, an Nth state value and N-2 intermediate state values; the first decoder being configured to activate an i-th output among the first decoder outputs in a given cycle of the clock signal in which the current state is an i-th state value among the N possible state values; the state machine being configured to selectively update the current state to a next state value in response to the clock signal and in response to a comparator output signal at the output of the comparator; For the current state having the first state value or the Nth state value, the state machine is configured to set the next state value to the current state value or to an intermediate state value adjacent to the current state value according to the comparator output signal; as well as For the current state having one of the intermediate state values, the state machine is configured to set the next state value to one of two state values ​​adjacent to the current state value according to the comparator output signal.

4. The voltage detector according to claim 3, wherein: the second decoder being configured to activate one of the second decoder outputs in a given cycle of the clock signal based on a state value of the current state and the next state value; for the current state having the first state value and the next state value having the first state value, the second decoder is configured to activate a first output among the second decoder outputs; for the current state having the Nth state value and the next state value having the Nth state value, the second decoder is configured to activate an N+1th output of the second decoder output; For the current state having an i-th state value and the next state value having an i+1-th state value, the second decoder is configured to activate an i+1-th output of the second decoder outputs; as well as For the current state having the (i+1)th state value and the next state value having the (i)th state value, the second decoder is configured to activate an (i)th output among the second decoder outputs.

5. The voltage detector according to claim 2, wherein: The N possible state values ​​include a first state value, an Nth state value and N-2 intermediate state values; the state machine being configured to selectively update the current state to a next state value in response to the clock signal and in response to a comparator output signal at the output of the comparator; the second decoder being configured to activate one of the second decoder outputs in a given cycle of the clock signal based on a state value of the current state and the next state value; for the current state having the first state value and the next state value having the first state value, the second decoder is configured to activate a first output among the second decoder outputs; for the current state having the Nth state value and the next state value having the Nth state value, the second decoder is configured to activate an N+1th output of the second decoder output; for the current state having an i-th state value and the next state value having an i+1-th state value, the second decoder is configured to activate an i+1-th output of the second decoder outputs; as well as For the current state having the (i+1)th state value and the next state value having the (i)th state value, the second decoder is configured to activate an (i)th output among the second decoder outputs.

6. The voltage detector according to claim 1, wherein: The second decoder is configured to activate only a single one of the second decoder outputs at a time.

7. The voltage detector of claim 1 , further comprising a clock input, the state machine having a current state in each cycle of a clock signal at the clock input, the current state having one of N possible state values; in, The decoder is configured to activate only a single one of the decoder outputs to turn on a corresponding single one of the switches according to the current state in each cycle of the clock signal.

8. The voltage detector according to claim 7, wherein: The N possible state values ​​include a first state value, an Nth state value and N-2 intermediate state values; the decoder being configured to activate an i-th output among the decoder outputs in a given cycle of the clock signal in which the current state is an i-th state value among the N possible state values; the state machine being configured to selectively update the current state to a next state value in response to the clock signal and in response to a comparator output signal at the output of the comparator; For the current state having the first state value or the Nth state value, the state machine is configured to set the next state value to the current state value or to an intermediate state value adjacent to the current state value according to the comparator output signal; as well as For the current state having one of the intermediate state values, the state machine is configured to set the next state value to one of two state values ​​adjacent to the current state value according to the comparator output signal.

9. A method for detecting voltage, comprising: coupling a single intermediate node of an integer number N of intermediate nodes of the resistor divider circuit to an input of the comparator according to a current state of the state machine, the current state having one of N possible state values ​​in each cycle of the clock signal; selectively updating the state value of the current state from a first state value to a second state value in response to the clock signal and in response to a comparator output signal at an output of the comparator having a first state; In response to the clock signal and in response to the comparator output signal having a second state, selectively updating the state value of the current state from the second state value back to the first state value; as well as A single one of the N+1 decoder outputs is activated in a given cycle of the clock signal according to the state value and the next state value of the current state, the activated N+1 decoder outputs representing a power converter reference current level.

10. The method according to claim 9, wherein: The N possible state values ​​include a first state value, an Nth state value and N-2 intermediate state values; as well as Selectively updating the state value of the current state to the next state value includes: For the current state having the first state value or the Nth state value, setting the next state value to the current state value or to an intermediate state value adjacent to the current state value according to the comparator output signal, and For the current state having one of the intermediate state values, the next state value is set to one of two state values ​​adjacent to the current state value according to the comparator output signal.

11. The method according to claim 10, wherein: Activating the single one of the N+1 decoder outputs during a given cycle of the clock signal comprises: for the current state having the first state value and the next state value having the first state value, activating a first output of the second decoder outputs; for the current state having the Nth state value and the next state value having the Nth state value, activating an N+1th output of the second decoder output; For the current state having an i-th state value and the next state value having an i+1-th state value, activating an i+1-th output of the second decoder output; and For the current state having the (i+1)th state value and the next state value having the (i)th state value, an (i)th output among the second decoder outputs is activated.

12. The method of claim 9, further comprising adjusting operating conditions of a power converter based on the decoder output.

13. A power converter comprising: Converter input; Converter output; an inductor coupled to the switch node; a switch having terminals coupled to the switch node and a control input; a current sensor coupled to the switch node; A current reference circuit having an integer number N+1 of current reference inputs and a current reference output, N being greater than 2; a converter comparator having a first input coupled to the current sensor, a second input (618) coupled to the output of the current reference circuit, and an output; a controller having an input coupled to the output of the converter comparator and an output coupled to the control input of the switch; as well as a voltage detector having a voltage detector input coupled to the converter output, a state machine having states, and N+1 decoder outputs coupled to corresponding ones of the N+1 current reference inputs, the states having N possible state values, the decoder outputs having at least a first decoder state and a second decoder state, and the state machine being configured to transition from the first decoder state to the second decoder state in response to the output of the converter comparator having a first state, and to transition from the second decoder state to the first decoder state in response to the output of the converter comparator having a second state.

14. The power converter according to claim 13, wherein: The voltage detector comprises: a resistor divider circuit having resistors coupled in series with each other between the voltage detector input and a reference node and an integer number N of intermediate nodes, respective ones of the intermediate nodes connecting adjacent pairs of resistors; a switch circuit having N switches, respective ones of the switches having first terminals, second terminals, and control terminals coupled to respective ones of the intermediate nodes; and a comparator having a first input coupled to a reference voltage, a second input coupled to the second terminal of the switch, and an output; The state machine has: an input coupled to the output of the comparator, a first decoder having N first decoder outputs coupled to corresponding control terminals of the N switches, and a second decoder having the N+1 decoder outputs coupled to corresponding current reference inputs of the N+1 current reference inputs.

15. The power converter of claim 14, wherein: The voltage detector further includes a clock input, the state machine having a current state in each cycle of a clock signal at the clock input, the current state having one of N possible state values; as well as The first decoder is configured to activate only a single one of the first decoder outputs to turn on a corresponding single one of the switches according to the current state in each cycle of the clock signal.

16. The power converter of claim 15, wherein: The N possible state values ​​include a first state value, an Nth state value and N-2 intermediate state values; the first decoder being configured to activate an i-th output among the decoder outputs in a given cycle of the clock signal in which the current state is an i-th state value among the N possible state values; the state machine being configured to selectively update the current state to a next state value in response to the clock signal and in response to a comparator output signal at the output of the comparator; For the current state having the first state value or the Nth state value, the state machine is configured to set the next state value to the current state value or to an intermediate state value adjacent to the current state value according to the comparator output signal; as well as For the current state having one of the intermediate state values, the state machine is configured to set the next state value to one of two state values ​​adjacent to the current state value according to the comparator output signal.

17. The power converter of claim 16, wherein: the second decoder being configured to activate one of the decoder outputs in a given cycle of the clock signal according to a state value of the current state and the next state value; for the current state having the first state value and the next state value having the first state value, the second decoder is configured to activate a first output among the decoder outputs; for the current state having the Nth state value and the next state value having the Nth state value, the second decoder is configured to activate an N+1th output among the decoder outputs; For the current state having an i-th state value and the next state value having an i+1-th state value, the second decoder is configured to activate an i+1-th output among the decoder outputs; as well as For the current state having the (i+1)th state value and the next state value having the (i)th state value, the second decoder is configured to activate an (i)th output among the decoder outputs.

18. The power converter of claim 15, wherein: The N possible state values ​​include a first state value, an Nth state value and N-2 intermediate state values; the state machine being configured to selectively update the current state to a next state value in response to the clock signal and in response to a comparator output signal at the output of the comparator; the second decoder being configured to activate one of the decoder outputs in a given cycle of the clock signal according to a state value of the current state and the next state value; for the current state having the first state value and the next state value having the first state value, the second decoder is configured to activate a first output among the decoder outputs; for the current state having the Nth state value and the next state value having the Nth state value, the second decoder is configured to activate an N+1th output among the decoder outputs; For the current state having an i-th state value and the next state value having an i+1-th state value, the second decoder is configured to activate an i+1-th output among the decoder outputs; as well as For the current state having the (i+1)th state value and the next state value having the (i)th state value, the second decoder is configured to activate an (i)th output among the decoder outputs.

19. The power converter according to claim 14, wherein: The second decoder is configured to activate only a single one of the decoder outputs at a time.

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