semiconductor devices

Abstract

A semiconductor device is provided, comprising: a drift region of a first conductivity type, which is arranged in a semiconductor substrate; and a buffer region of a first conductivity type, which is arranged between the drift region and the lower surface of the semiconductor substrate and has three or more concentration peaks in the depth direction of the semiconductor substrate whose doping concentration is higher than the doping concentration of the drift region, the three or more concentration peaks including: a shallowest peak, which is closest to the lower surface of the semiconductor substrate; a high concentration peak, which is arranged at a position farther from the lower surface of the semiconductor substrate than the shallowest peak; and a low concentration peak, which is arranged at a position farther from the lower surface of the semiconductor substrate than the high concentration peak, and whose doping concentration is less than 1 / 5 of the doping concentration of the high concentration peak.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a structure in which an N+ type buffer region is provided below a drift region in a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) (for example, see Patent Document 1).

[0003] Patent Document 1: WO2013 / 147275 Summary of the Invention

[0004] Technical issues

[0005] It is preferable to alleviate the electric field concentration in the buffer zone.

[0006] Technical Solution

[0007] In order to solve the above-mentioned problems, in one embodiment of the present invention, a semiconductor device is provided. The semiconductor device may include a drift region of a first conductivity type arranged in a semiconductor substrate. The semiconductor device may include a buffer region of the first conductivity type arranged between the drift region and the lower surface of the semiconductor substrate and having three or more concentration peaks in the depth direction of the semiconductor substrate, wherein the doping concentration of the three or more concentration peaks is higher than the doping concentration of the drift region. The three or more concentration peaks may include a shallowest peak closest to the lower surface of the semiconductor substrate. The three or more concentration peaks may include a high concentration peak arranged at a position farther from the lower surface of the semiconductor substrate than the shallowest peak. The three or more concentration peaks may include one or more low concentration peaks arranged at a position farther from the lower surface of the semiconductor substrate than the high concentration peak and having a doping concentration of less than 1 / 5 of the doping concentration of the high concentration peak.

[0008] The buffer region may have a hydrogen concentration peak corresponding to the concentration peak. The semiconductor device may include a collector region of the second conductivity type provided between the buffer region and the lower surface of the semiconductor substrate.

[0009] The low concentration peak may be the deepest peak among the concentration peaks that is arranged farthest from the lower surface of the semiconductor substrate.

[0010] The three or more concentration peaks may include a deepest peak located farthest from the lower surface of the semiconductor substrate, and the low concentration peak may be located between the high concentration peak and the deepest peak.

[0011] Three or more concentration peaks may include two or more low-concentration peaks.

[0012] The two or more low-concentration peaks may be two or more concentration peaks that are located farthest from the lower surface of the semiconductor substrate among the concentration peaks.

[0013] The doping concentration of the low-concentration peak may be 50 times or less the bulk donor concentration of the semiconductor substrate.

[0014] The doping concentration of the low-concentration peak may be 50 times or less the doping concentration of the central portion in the depth direction of the semiconductor substrate.

[0015] The three or more concentration peaks may include a first peak located farthest from the lower surface of the semiconductor substrate and a second peak adjacent to the first peak in the depth direction. The average of the peak values ​​of the doping concentrations of the first and second peaks may be less than 1 / 5 of the peak value of the doping concentration of the high-concentration peak.

[0016] The average value of the peak values ​​of the doping concentrations of the first peak and the second peak may be 50 times or less the bulk donor concentration of the semiconductor substrate.

[0017] The average value of the peak values ​​of the doping concentrations of the first peak and the second peak may be 50 times or less the doping concentration of the central portion in the depth direction of the semiconductor substrate.

[0018] The buffer zone can contain the recombination center. The density peak in the depth direction of the recombination center can be arranged between the shallowest peak and the high concentration peak.

[0019] The density peak may be arranged between the shallowest peak and the high concentration peak, close to the shallowest peak.

[0020] The doping concentration of the deepest peak located farthest from the lower surface of the semiconductor substrate among the concentration peaks may be 1.1 to 5 times greater than the doping concentration of the concentration peak adjacent to the deepest peak in the depth direction.

[0021] The doping concentration of the deepest peak located farthest from the bottom surface of the semiconductor substrate among the concentration peaks may be 1.0×10 14 atoms / cm 3 Above and 5.0×10 14 atoms / cm 3 the following.

[0022] The buffer region may be disposed between the lower surface of the semiconductor substrate and the center of the semiconductor substrate in the depth direction.

[0023] The deepest peak of the concentration peaks, which is located farthest from the lower surface of the semiconductor substrate, may be located between the upper surface of the semiconductor substrate and the center in the depth direction of the semiconductor substrate.

[0024] It should be noted that the above summary of the invention does not list all the essential features of the present invention, and that subcombinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 11 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0026] Figure 2 yes Figure 1 Magnified view of area A in FIG.

[0027] Figure 3 It shows Figure 2 A diagram showing an example of the bb cross section in FIG.

[0028] Figure 4 It shows Figure 3 A diagram showing an example of the doping concentration distribution in the depth direction at the position of the dd line.

[0029] Figure 5 is an enlarged view of the doping concentration distribution in the buffer region 20 .

[0030] Figure 6 1 is a diagram showing an example of a gate voltage waveform when the semiconductor device 100 is in a short-circuited state and is turned on.

[0031] Figure 7 1 is a diagram showing an example of the electric field distribution in the depth direction of the semiconductor substrate 10 according to the embodiment.

[0032] Figure 8 It is a diagram showing an example of the electric field intensity distribution in the short-circuit state in the example and the comparative example.

[0033] Figure 9 This is a diagram showing the electric field distribution of the semiconductor device 100 according to the embodiment for each voltage applied between the emitter and the collector.

[0034] Figure 10 1 is a diagram showing an example of the chemical concentration distribution of hydrogen in the buffer area 20 .

[0035] Figure 11 1 is a diagram showing another example of the bb cross section of the semiconductor device 100 .

[0036] Figure 12 It shows Figure 11 An example of the doping concentration distribution at the dd line.

[0037] Figure 13 It shows Figure 11 FIG. 1 is another example of the doping concentration distribution at the dd line.

[0038] Figure 14 1 is a diagram showing another example of the doping concentration distribution in the buffer region 20 .

[0039] Figure 15 1 is a diagram showing another example of the bb cross section of the semiconductor device 100 .

[0040] Figure 16 It shows Figure 15 FIG. 1 is a diagram showing an example of the doping concentration distribution in the buffer region 20 shown.

[0041] Explanation of symbols

[0042] 10: Semiconductor substrate, 11: Well region, 12: Emitter region, 14: Base region, 15: Contact region, 16: Accumulation region, 18: Drift region, 20: Buffer region, 21: Upper surface, 22: Collector region, 23: Lower surface, 24: Collector electrode, 25: Concentration peak, 29: Straight line portion, 30: Dummy trench portion, 31: Front end portion, 32: Dummy insulating film, 34: Dummy conductive portion, 38: Interlayer insulating film, 39: Straight line portion, 40: Gate trench portion, 41: Front end portion, 42: Gate insulating film, 44: Gate conductive portion Electrical portion, 52: Emitter electrode, 54: Contact hole, 60, 61: Mesa portion, 70: Transistor portion, 80: Diode portion, 81: Extension region, 82: Cathode region, 90: Edge termination structure portion, 92: Lifetime control region, 94: Density peak, 96: Density distribution, 98: Concentration peak, 100: Semiconductor device, 102: End, 112: Gate pad, 125: Concentration peak, 126: Hydrogen concentration peak, 128: High concentration region, 130: Peripheral gate wiring, 131: Active-side gate wiring, 160: Active portion DETAILED DESCRIPTION

[0043] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention as claimed. Furthermore, not all combinations of features described in the embodiments are necessarily essential for the solution provided by the invention.

[0044] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." One of the two principal surfaces of a substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the orientation when a semiconductor device is mounted.

[0045] In this specification, technical matters are sometimes described using the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. These axes merely determine the relative positions of components and do not define specific directions. For example, the Z-axis is not necessarily defined as indicating the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is not indicated, it refers to a direction parallel to the +Z and -Z axes.

[0046] In this specification, the axes perpendicular to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0047] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0048] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, the term "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to produce an N-type or P-type semiconductor.

[0049] In this specification, the doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the net doping concentration refers to the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, if the donor concentration is N D , set the acceptor concentration to N A , then the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0050] Donors donate electrons to semiconductors. Acceptors accept electrons from semiconductors. Donors and acceptors are not limited to impurities per se. For example, VOH defects, formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron donors. In this specification, VOH defects are sometimes referred to as hydrogen donors.

[0051] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type. In addition, in this specification, when described as P++ type or N++ type, it means that the doping concentration is higher than the doping concentration of P+ type or N+ type.

[0052] In this specification, chemical concentration refers to the concentration of impurities measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance determination (CV method). In addition, the carrier concentration measured by the spreading resistance determination method (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be used as a value under thermal equilibrium. In addition, in the N-type region, the donor concentration is much larger than the acceptor concentration, so the carrier concentration in this region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be used as the acceptor concentration. In this specification, the N-type doping concentration is sometimes referred to as the donor concentration, and the doping concentration of the P-type region is sometimes referred to as the acceptor concentration.

[0053] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor, or net doping in the region. When the concentration of the donor, acceptor, or net doping is approximately uniform, the average value of the concentration of the donor, acceptor, or net doping in the region can be used as the concentration of the donor, acceptor, or net doping.

[0054] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. In the range of current flow during spreading resistance measurement, the carrier mobility of a semiconductor substrate may be lower than that of a crystalline state. This reduction in carrier mobility is caused by carrier scattering due to crystal structure disorder caused by lattice defects and other factors.

[0055] The concentration of donors or acceptors calculated based on the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic that acts as a donor in a silicon semiconductor, or the acceptor concentration of boron that acts as an acceptor, is about 99% of their chemical concentrations. On the other hand, the donor concentration of hydrogen that acts as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen. Unless otherwise specified, the units used in this specification are SI units. Although units of length are sometimes expressed in cm, etc., each calculation can be performed after conversion to meters (m).

[0056] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 , only some components of the semiconductor device 100 are shown, and some components are omitted.

[0057] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has an edge 102 when viewed from above. In this specification, the term "viewed from above" refers to the state viewed from the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edge 102 facing each other when viewed from above. Figure 1 In FIG. 1 , the X-axis and the Y-axis are parallel to one end side 102 . In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10 .

[0058] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but Figure 1 Omitted in .

[0059] The active portion 160 includes at least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Figure 1 In the example, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. In another example, only one of the transistor portion 70 and the diode portion 80 may be provided in the active portion 160.

[0060] exist Figure 1 In FIG. 1 , the region where the transistor portion 70 is configured is marked with a symbol “I”, and the region where the diode portion 80 is configured is marked with a symbol “F”. In this specification, the direction perpendicular to the arrangement direction in a plan view is sometimes referred to as the extension direction (in FIG. Figure 1 The Y-axis direction is the Y-axis direction in the figure. The transistor portion 70 and the diode portion 80 may each have a long side in the direction in which they extend. That is, the length of the transistor portion 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each trench portion described later.

[0061] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided in an area other than the cathode region on the lower surface of the semiconductor substrate 10. In this specification, an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0062] The transistor portion 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor portion 70 has gate structures periodically arranged on the upper surface side of the semiconductor substrate 10. The gate structure includes an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film.

[0063] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 112. Semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near edge 102. The area near edge 102 refers to the area between edge 102 and the emitter electrode when viewed from above. When semiconductor device 100 is mounted, each pad can be connected to an external circuit via wiring such as a wire.

[0064] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion. Figure 1 , the gate wiring is marked with oblique hatching.

[0065] The gate wiring of this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. Peripheral gate wiring 130 is arranged between active portion 160 and edge 102 of semiconductor substrate 10 when viewed from above. Peripheral gate wiring 130 of this example surrounds active portion 160 when viewed from above. Alternatively, the area surrounded by peripheral gate wiring 130 when viewed from above may be defined as active portion 160. Furthermore, peripheral gate wiring 130 is connected to gate pad 112. Peripheral gate wiring 130 is arranged above semiconductor substrate 10. Peripheral gate wiring 130 may be a metal wiring made of aluminum or the like.

[0066] The active-side gate wiring 131 is provided in the active portion 160 . By providing the active-side gate wiring 131 in the active portion 160 , variations in wiring length from the gate pad 112 can be reduced in each region of the semiconductor substrate 10 .

[0067] The active-side gate wiring 131 is connected to the gate trench portion of the active portion 160. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0068] The active-side gate wiring 131 can be connected to the peripheral gate wiring 130. In this example, the active-side gate wiring 131 is provided approximately at the center in the Y-axis direction, extending from one peripheral gate wiring 130 to the other peripheral gate wiring 130 in the X-axis direction so as to traverse the active portion 160. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0069] Furthermore, the semiconductor device 100 may include a temperature sensing portion (not shown) that is a PN junction diode formed of polysilicon or the like, and / or a current detecting portion (not shown) that simulates the operation of a transistor portion provided in the active portion 160 .

[0070] The semiconductor device 100 of this embodiment includes an edge termination structure 90 between the active portion 160 and the edge 102. The edge termination structure 90 of this embodiment is disposed between the peripheral gate wiring 130 and the edge 102. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may further include at least one of a guard ring, a field plate, and a resurface electric field structure, disposed in an annular shape surrounding the active portion 160.

[0071] Figure 2 yes Figure 1 is an enlarged view of region A in FIG. Region A includes the transistor portion 70, the diode portion 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, all disposed within the upper surface of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131, both disposed above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0072] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but Figure 1 In this embodiment, the interlayer insulating film is provided with a contact hole 54 so as to penetrate the interlayer insulating film. Figure 2 In FIG. 1 , each contact hole 54 is marked with an oblique hatching line.

[0073] Emitter electrode 52 is provided above gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 contacts emitter region 12, contact region 15, and base region 14 on the upper surface of semiconductor substrate 10 through contact hole 54. Furthermore, emitter electrode 52 is connected to a dummy conductive portion within dummy trench 30 through a contact hole provided in the interlayer insulating film. Emitter electrode 52 can be connected to the dummy conductive portion of dummy trench 30 at the front end of dummy trench 30 in the Y-axis direction.

[0074] The active-side gate wiring 131 is connected to the gate trench 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench 40 at its front end portion 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench 30.

[0075] The emitter electrode 52 is formed of a material containing metal. Figure 2 The figure shows the area where emitter electrode 52 is provided. For example, at least a portion of emitter electrode 52 is formed from a metal such as aluminum or a metal alloy containing aluminum. Examples of metal alloys include aluminum-silicon alloys and aluminum-silicon-copper alloys. Emitter electrode 52 may include a barrier metal formed from titanium and / or a titanium compound below the area formed from aluminum. Furthermore, a plug formed by embedding tungsten or the like may be provided within the contact hole. The plug is provided in contact with the barrier metal and the aluminum or the like.

[0076] The well region 11 is provided so as to overlap with the active-side gate wiring 131. The well region 11 is provided to extend to a predetermined width even in the area not overlapping with the active-side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active-side gate wiring 131. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is of the P- type, and the well region 11 is of the P+ type.

[0077] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged along the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In this example, the diode section 80 is not provided with a gate trench section 40.

[0078] The gate trench portion 40 of this example may include two straight portions 39 extending in an extending direction perpendicular to the arrangement direction (portions forming a straight trench along the extending direction) and a front end portion 41 connecting the two straight portions 39 . Figure 2 The extension direction is the Y-axis direction.

[0079] At least a portion of the tip portion 41 is preferably curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39.

[0080] In the transistor portion 70, the dummy trench portion 30 is provided between the respective straight portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between each straight portion 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a straight shape extending in the extension direction, or may have a straight portion 29 and a front end portion 31 similar to the gate trench portion 40. Figure 2 The semiconductor device 100 shown includes both a linear dummy trench portion 30 without a front end portion 31 and a dummy trench portion 30 with a front end portion 31 .

[0081] The diffusion depth of the well region 11 can be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This can alleviate electric field concentration at the bottom of each trench portion.

[0082] A mesa portion is provided between each groove portion in the arrangement direction. The mesa portion refers to an area sandwiched by the groove portion inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the groove portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the groove portion. In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when referred to simply as a mesa portion, it refers to each mesa portion 60 and mesa portion 61.

[0083] A base region 14 is provided in each mesa portion. A region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion and located closest to the active-side gate wiring 131 is referred to as a base region 14-e. Figure 2In the figure, a base region 14-e is shown as being located at one end of each mesa portion in the direction in which it extends. However, a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of an emitter region 12 of the first conductivity type and a contact region 15 of the second conductivity type can be provided in the region sandwiched between the base region 14-e when viewed from above. In this example, emitter region 12 is of the N+ type, and contact region 15 is of the P+ type. Emitter region 12 and contact region 15 can be provided in the depth direction between base region 14 and the upper surface of semiconductor substrate 10.

[0084] Mesa portion 60 of transistor portion 70 includes emitter region 12 exposed on the upper surface of semiconductor substrate 10. Emitter region 12 is provided in contact with gate trench portion 40. Mesa portion 60 in contact with gate trench portion 40 may include contact region 15 exposed on the upper surface of semiconductor substrate 10.

[0085] The contact regions 15 and emitter regions 12 in the mesa portion 60 are arranged from one groove portion to the other groove portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion 60 are alternately arranged along the extending direction of the groove portion (Y-axis direction).

[0086] In another example, the contact regions 15 and emitter regions 12 of the mesa portion 60 may be arranged in a stripe pattern along the extending direction of the groove portion (the Y-axis direction). For example, the emitter regions 12 may be provided in the region contacting the groove portion, and the contact regions 15 may be provided in the region sandwiched by the emitter regions 12.

[0087] Emitter region 12 is not provided in mesa portion 61 of diode portion 80. Base region 14 and contact region 15 may be provided on the upper surface of mesa portion 61. Contact region 15 may be provided in the region of the upper surface of mesa portion 61 sandwiched between base regions 14-e, in contact with each base region 14-e. Base region 14 may be provided in the region of the upper surface of mesa portion 61 sandwiched between contact regions 15. Base region 14 may be provided throughout the region sandwiched between contact regions 15.

[0088] Contact holes 54 are provided above each mesa portion. Contact holes 54 are located in the region sandwiched between base regions 14-e. In this example, contact holes 54 are located above each of contact region 15, base region 14, and emitter region 12. Contact holes 54 are not located in the region corresponding to base region 14-e and well region 11. Contact holes 54 can be located at the center of the mesa portion 60 in the arrangement direction (X-axis direction).

[0089] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. On the lower surface of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20 described later. Figure 2 In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0090] Cathode region 82 is positioned away from well region 11 in the Y-axis direction. This ensures a sufficient distance between the P-type region (well region 11), which has a high doping concentration and is formed deep, and cathode region 82, thereby improving the breakdown voltage. In this example, the end of cathode region 82 in the Y-axis direction is positioned farther from well region 11 than the end of contact hole 54 in the Y-axis direction. In another example, the end of cathode region 82 in the Y-axis direction may be positioned between well region 11 and contact hole 54.

[0091] Figure 3 It shows Figure 2 FIG. bb cross section is an example of a diagram of a cross section of FIG. bb cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example has, in this cross section, a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with Figure 2 The contact hole 54 is described in detail.

[0092] Emitter electrode 52 is provided above interlayer insulating film 38. Emitter electrode 52 contacts upper surface 21 of semiconductor substrate 10 through contact hole 54 in interlayer insulating film 38. Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0093] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.

[0094] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0095] Emitter region 12 is exposed on upper surface 21 of semiconductor substrate 10 and is provided in contact with gate trench 40. Emitter region 12 may be in contact with the trenches on both sides of mesa portion 60. The doping concentration of emitter region 12 is higher than that of drift region 18.

[0096] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided so as to be in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0097] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. Providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14 enhances the carrier injection enhancement effect (IE effect) and reduces the on-state voltage. The accumulation region 16 can be provided to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0098] A P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10 in the mesa portion 61 of the diode portion 80. A drift region 18 is provided below the base region 14. An accumulation region 16 may also be provided below the base region 14 in the mesa portion 61.

[0099] An N+ type buffer zone 20 can be provided below the drift region 18 in each of the transistor portion 70 and the diode portion 80. The doping concentration of the buffer zone 20 is higher than that of the drift region 18. The buffer zone 20 has a concentration peak 25 having a higher doping concentration than that of the drift region 18. The doping concentration of the concentration peak 25 refers to the doping concentration at the top of the concentration peak 25. In addition, the doping concentration of the drift region 18 can be the average value of the doping concentration in the region where the doping concentration distribution is substantially flat. The region where the doping concentration distribution is substantially flat can be a region where the doping concentration fluctuates within ±10%. The buffer zone 20 of this example has three or more concentration peaks 25 in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak 25 of the buffer zone 20 can be provided at the same depth position as, for example, the concentration peak of hydrogen (protons) or phosphorus. The buffer zone 20 can function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0100] In transistor portion 70, a P+ type collector region 22 is provided below buffer region 20. The acceptor concentration in collector region 22 is higher than the acceptor concentration in base region 14. Collector region 22 may contain the same acceptor as base region 14 or a different acceptor. The acceptor in collector region 22 is, for example, boron.

[0101] In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that serve as donors and acceptors in each region are not limited to the above examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0102] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least one of the emitter region 12, the contact region 15 and the storage region 16 is provided, each groove portion also penetrates these doped regions and reaches the drift region 18. The structure in which the groove portion penetrates the doped region is not limited to the structure in which the groove portion is formed after the doped region is formed. The structure in which the groove portion penetrates the doped region is also included in the structure in which the groove portion penetrates the doped region.

[0103] As described above, transistor portion 70 is provided with gate trench portion 40 and dummy trench portion 30. Diode portion 80 is provided with dummy trench portion 30, but no gate trench portion 40 is provided. In this example, the boundary between diode portion 80 and transistor portion 70 in the X-axis direction is the boundary between cathode region 82 and collector region 22.

[0104] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided within the gate trench at a position further inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0105] The gate conductive portion 44 can be longer in depth than the base region 14. The gate trench portion 40 in this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface between the base region 14 and the gate trench portion 40.

[0106] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 includes a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length as the gate conductive portion 44 in the depth direction.

[0107] In this example, gate trench 40 and dummy trench 30 are covered by interlayer insulating film 38 on upper surface 21 of semiconductor substrate 10. The bottoms of dummy trench 30 and gate trench 40 may be curved (curved in cross section) and convex downward.

[0108] Figure 4 It shows Figure 3 FIG. 1 is a diagram showing an example of a doping concentration distribution in the depth direction at the position of the dd line. As described above, the carrier concentration distribution can be used as the doping concentration distribution. The dd line passes from the emitter region 12 to the collector region 22 in the transistor portion 70. Figure 4 The vertical axis is a logarithmic axis. Figure 4 Hereinafter, the doping concentration distribution of the buffer region 20 in the transistor portion 70 will be described, but the buffer region 20 in the diode portion 80 also has the same doping concentration distribution.

[0109] The doping concentration of the drift region 18 in this example is a bulk donor concentration (bulk donor) Db. The bulk donor of the first conductive type (N-type) is distributed throughout the semiconductor substrate 10 in this example. The bulk donor is a donor formed by a dopant that is roughly uniformly contained in the ingot when manufacturing the ingot that forms the basis of the semiconductor substrate 10. The bulk donor in this example is an element other than hydrogen. The dopant of the bulk donor is, for example, antimony, arsenic, selenium, and sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donor is also contained in the P-type region. The semiconductor substrate 10 can be a wafer cut from a semiconductor ingot or a chip obtained by singulating a wafer. The semiconductor ingot can be manufactured using any of the Czochralski method (CZ method), the magnetron crystal pulling method (MCZ method), and the floating zone melting method (FZ method). The ingot in this example is manufactured using the MCZ method. The bulk donor concentration Db may use the chemical concentration of donors distributed throughout the semiconductor substrate 10 , or may be a value between 90% and 100% of the chemical concentration.

[0110] The doping concentration distribution in the buffer region 20 of this example has three or more concentration peaks 25 arranged at different positions in the depth direction. Figure 4 In the example, four concentration peaks 25-1, 25-2, 25-3, and 25-4 are shown, but the number of concentration peaks 25 is not limited thereto. In this example, the concentration peak 25 is a peak of donor concentration. A plurality of concentration peaks 25 can be formed by injecting impurities such as hydrogen or phosphorus into a plurality of depth positions of the buffer region 20. The buffer region 20 may have a concentration peak of an impurity such as hydrogen or phosphorus at a position corresponding to the concentration peak 25. The concentration peak of an impurity is a peak in the chemical concentration distribution of the impurity. By providing a plurality of concentration peaks 25, it is possible to further suppress the depletion layer from reaching the collector region 22.

[0111] In this example, all concentration peaks 25 of the buffer zone 20 are located on the lower surface 23 side of the semiconductor substrate 10. The lower surface 23 side refers to the region between the lower surface 23 and the center Zc in the depth direction of the semiconductor substrate 10. In another example, at least one concentration peak 25 may be located on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side refers to the region between the upper surface 21 and the center Zc in the depth direction of the semiconductor substrate 10.

[0112] Figure 5 is an enlarged view of the doping concentration distribution in the buffer zone 20. Figure 5 , the solid line shows the embodiment of the semiconductor device 100 , and the dotted line shows the comparative example. The buffer region 20 of the embodiment has three or more concentration peaks 25 , while the buffer region 20 of the comparative example has three or more concentration peaks 125 .

[0113] The multiple concentration peaks 25 include the shallowest peak closest to the lower surface 23 of the semiconductor substrate 10. In this example, concentration peak 25-1 corresponds to the shallowest peak. Concentration peak 25-1 in this example is the concentration peak 25 closest to the collector region 22. In the buffer region 20 of the diode portion 80, concentration peak 25-1 is the concentration peak 25 closest to the cathode region 82. The cathode region 82 can be formed by implanting impurities different from those of the concentration peak 25. For example, the cathode region 82 has a concentration peak of an impurity such as phosphorus, while the buffer region 20 has a concentration peak of an impurity such as hydrogen.

[0114] The plurality of concentration peaks 25 include a high concentration peak located farther from the lower surface 23 than the shallowest peak (concentration peak 25-1). The high concentration peak may be the concentration peak 25-2 closest to the shallowest peak or another concentration peak 25. Figure 5 In the example, the concentration peak 25-2 closest to the concentration peak 25-1 corresponds to the high concentration peak.

[0115] The plurality of concentration peaks 25 include a low-concentration peak located further from the lower surface 23 than the high-concentration peak, and having a peak doping concentration that is less than one-fifth of the peak of the high-concentration peak. The low-concentration peak may be the deepest peak (in this example, concentration peak 25-4) located furthest from the lower surface 23 among the plurality of concentration peaks 25. The low-concentration peak may also be a concentration peak 25 other than the deepest peak. That is, the low-concentration peak may be a concentration peak 25 between the high-concentration peak and the deepest peak.

[0116] In addition, the number of low concentration peaks may be two or more. The low concentration peaks are preferably arranged adjacent to each other in the depth direction. Among the multiple concentration peaks 25, the two or more concentration peaks arranged farthest from the lower surface 23 may be low concentration peaks. Figure 5 In the example, the concentration peak 25-4, which is the deepest peak, and the concentration peak 25-3, which is located at a position next to the deepest peak and away from the lower surface 23, are low concentration peaks. Figure 5 In the example, the peak value D3 of the doping concentration of the concentration peak 25 - 3 and the peak value D4 of the doping concentration of the concentration peak 25 - 4 are both less than 1 / 5 of the peak value D2 of the doping concentration of the concentration peak 25 - 2 .

[0117] In a short-circuit state, where two series-connected semiconductor devices 100 are simultaneously turned on, a high voltage may be applied between the emitter and collector of each semiconductor device 100. In this case, the electric field tends to concentrate near the deepest peaks in the buffer zone 20 (in this example, concentration peaks 25-4 and 125-4). Therefore, increasing the doping concentration near the deepest peaks, such as concentration peaks 125-3 and 125-4, promotes electric field concentration. This electric field concentration can easily cause the gate voltage to fluctuate during shutdown of the semiconductor device 100.

[0118] The concentration peak 25 of this example is provided with a low concentration peak having a much lower doping concentration at a position deeper than the high concentration peak (concentration peak 25-2). Therefore, the electric field concentration at a deep position of the buffer zone 20 can be alleviated. As described above, multiple low concentration peaks can also be provided. Thus, a relatively wide buffer zone 20 with a relatively low concentration can be formed on the side of the drift region 18. Figure 5 In the example shown, the buffer region 20 has two low-concentration peaks. However, in other examples, the buffer region 20 may have three or more low-concentration peaks. Furthermore, the deepest peak may be located on the upper surface 21 side of the semiconductor substrate 10. By providing a low-concentration region on the drift region 18 side of the buffer region 20 and forming a low-concentration region that is wide in the depth direction, electric field concentration is mitigated while maintaining the field stop function.

[0119] The peak value of the doping concentration of the low-concentration peak may be less than 1 / 5 of the peak value of the doping concentration of the high-concentration peak, or less than 1 / 10 of the peak value of the doping concentration of the high-concentration peak, or less than 1 / 20 of the peak value of the doping concentration of the high-concentration peak. By reducing the doping concentration of the low-concentration peak, the electric field concentration can be further relaxed.

[0120] In addition, the peak value of the doping concentration of the low concentration peak is higher than the body donor concentration Db. The peak value of the doping concentration of the low concentration peak can be less than 50 times the body donor concentration Db of the semiconductor substrate 10. The doping concentration of the drift region 18 can be used as the body donor concentration Db. The peak value of the doping concentration of the low concentration peak can be less than 20 times the body donor concentration Db, less than 10 times the body donor concentration Db, less than 8 times the body donor concentration Db, less than 5 times the body donor concentration Db, less than 3 times the body donor concentration Db, or less than 2 times the body donor concentration Db.

[0121] The depth-direction positions of concentration peaks 25-1, 25-2, 25-3, and 25-4 are designated as Z1, Z2, Z3, and Z4, respectively. The depth-direction distance between concentration peak 25-4 and concentration peak 25-2 is designated as Z4-Z2. Furthermore, the depth-direction distance between concentration peak 25-1 and concentration peak 25-2 is designated as Z2-Z1. Distance Z4-Z2 may be greater than distance Z2-Z1. Furthermore, the distance between concentration peak 25-3 and concentration peak 25-4 is designated as Z4-Z3. The distance between concentration peak 25-3 and concentration peak 25-2 is designated as Z3-Z2. Distance Z4-Z3 may be greater than distance Z3-Z2. Furthermore, distance Z4-Z3 may be greater than distance Z2-Z1.

[0122] Furthermore, the average value of the peak values ​​of the doping concentrations of the concentration peaks 25-4 and 25-3 may be less than 1 / 5 of the peak value of the doping concentration of the high concentration peak, or less than 1 / 10 of the peak value of the doping concentration of the high concentration peak, or less than 1 / 20 of the peak value of the doping concentration of the high concentration peak. The average value of the peak values ​​of the doping concentrations may be the additive average (D3+D4) / 2 or the multiplicative average (D3×D4). 1 / 2. The average value of the peak values ​​of the doping concentrations of the concentration peak 25-4 and the concentration peak 25-3 is higher than the body donor concentration Db. The average value of the peak values ​​of the doping concentrations of the concentration peak 25-4 and the concentration peak 25-3 can be less than 50 times the body donor concentration Db, less than 20 times the body donor concentration Db, less than 10 times the body donor concentration Db, less than 8 times the body donor concentration Db, less than 5 times the body donor concentration Db, less than 3 times the body donor concentration Db, or less than 2 times the body donor concentration Db. By reducing the average value of the doping concentrations of the two deepest concentration peaks 25, the electric field concentration in the buffer zone 20 near the drift region 18 can be alleviated.

[0123] Figure 6 : is a diagram showing an example of a gate voltage waveform when the semiconductor device 100 is turned on in a short-circuited state. Figure 6 In the figure, a comparative example and an embodiment are shown. The comparative example and the embodiment have Figure 5 The structures of the buffer region 20 other than the doping concentration distribution are the same in the comparative example and the embodiment. In this example, 200 V is applied between the emitter electrode 52 and the collector electrode 24.

[0124] In the comparative example, oscillation occurs immediately after the gate voltage rises at time t0. This is considered to be due to Figure 5 As shown, the doping concentrations of the concentration peaks 125-4 and 125-3 are high, and the electric field is concentrated in the portion of the buffer region 20 on the drift region 18 side. In contrast, in the embodiment, it is found that the oscillation of the gate voltage is suppressed.

[0125] Figure 7 : is a diagram showing an example of the electric field distribution in the depth direction of the semiconductor substrate 10 of the embodiment. In the semiconductor substrate 10 of this embodiment, 200 V is applied between the emitter electrode 52 and the collector electrode 24. Figure 7 , the electric field distribution in the short-circuit state and the electric field distribution in the static operation (eg, a state where the voltage and current have stabilized after switching) of the semiconductor device 100 are shown.

[0126] The electric field intensity distribution in the static state gradually decreases from the upper surface 21 side toward the lower surface 23 side. In the static state, the depletion layer does not extend to the position Z4 of the deepest peak of the buffer region 20.

[0127] On the other hand, the electric field intensity distribution in the short-circuit state has approximately equal concentrations of electrons and holes, and therefore rises slightly from the upper surface 21 toward position Z4, with an electric field peak near position Z4. In the short-circuit state, the depletion layer extends to near position Z2.

[0128] Figure 8: is a graph showing an example of the electric field intensity distribution in the short-circuit state in the embodiment and the comparative example. Figure 7 In the comparative example, Figure 5 As shown in FIG. 1 , the doping concentration of the concentration peak 125-4 is relatively high. Therefore, in the comparative example, the hole concentration injected from the collector region 22 is relatively low compared to the electron concentration, and the electric field peak near the position Z4 becomes larger. In addition, the electric field on the upper surface 21 side becomes smaller. As a result, as shown in FIG. Figure 6 As shown, the gate voltage waveform of the comparative example swings. In the embodiment, the electric field peak near the position Z4 can be relaxed. In addition, the electric field intensity distribution from the upper surface 21 side to the position Z4 is substantially uniform. Therefore, as shown in FIG. Figure 6 It is shown that the swing in the gate voltage waveform can be suppressed.

[0129] Figure 9 This diagram shows the electric field distribution of semiconductor device 100 according to an embodiment for each voltage applied between the emitter and collector. In this example, the emitter-collector voltage is increased from 100 V to 800 V in 100 V increments. In all cases, the difference between the electric field intensity near position Z4 and the electric field intensity on the upper surface 21 side decreases. This suppresses gate voltage oscillation.

[0130] Figure 10 This diagram illustrates an example of the chemical concentration distribution of hydrogen in buffer zone 20. In this example, each concentration peak 25 is formed by implanting hydrogen ions, such as protons, from the lower surface 23. In this case, buffer zone 20 has hydrogen concentration peaks 126 at depths corresponding to each concentration peak 25. Corresponding depths of two peaks means, for example, that the apex of one peak is located within the full width at half maximum of the other peak. The number of concentration peaks 25 and hydrogen concentration peaks 126 in buffer zone 20 may be the same.

[0131] In this example, hydrogen ions are implanted from the lower surface 23 side of the semiconductor substrate 10. Therefore, in the hydrogen concentration distribution, the descending side S2 extending from the apex of each hydrogen concentration peak 126 toward the lower surface 23 side is more gradual than the descending side S1 extending from the apex of each hydrogen concentration peak 126 toward the upper surface 21 side. In other words, the inclination of the descending side S2 is less than the inclination of the descending side S1.

[0132] In the area where the hydrogen ions injected from the lower surface 23 pass through, lattice defects with vacancies as the main body, such as single-atom vacancies (V) and diatomic vacancies (VV), are formed. The atoms adjacent to the vacancies have dangling bonds. Although lattice defects also include interstitial atoms and / or dislocations, and in a broad sense can also include donors and / or acceptors, in this specification, lattice defects with vacancies as the main body are sometimes referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In addition, by injecting hydrogen ions into the semiconductor substrate 10, a large number of lattice defects are formed, so that the crystal properties of the semiconductor substrate are sometimes strongly disordered. In this specification, the disorder of the crystal properties is sometimes referred to as disorder. In addition, hydrogen (H), vacancies (V) and oxygen (O) injected into the buffer zone 20 combine to form VOH defects. Further, hydrogen is diffused due to thermal annealing, thereby promoting the formation of VOH defects. VOH defects function as donors that supply electrons.

[0133] By forming VOH defects, the doping concentration between the two concentration peaks 25 is also easily increased. Therefore, even if the concentration peak 25 includes a low concentration peak, it is easy to set the region between the concentration peaks 25 to a region with a higher concentration than the drift region 18. In this specification, VOH defects are sometimes simply referred to as hydrogen donors. The buffer zone 20 in this example includes hydrogen donors. The hydrogen donors may also be included in the region between the two concentration peaks 25. The doping concentration of the hydrogen donor is lower than the chemical concentration of hydrogen. If the ratio of the doping concentration of the hydrogen donor to the chemical concentration of hydrogen is set as the activation rate, the activation rate can be a value of 0.1% to 30%. In this example, the activation rate is 1% to 5%.

[0134] Figure 11 This is a diagram showing another example of the bb cross section of the semiconductor device 100. The lengths of the buffer region 20 and the drift region 18 in the depth direction of the semiconductor device 100 of this example are Figure 3 The examples shown are different. Other structures are Figure 3 Same as the example.

[0135] In this embodiment, a portion of the buffer region 20 is disposed on the upper surface 21 side of the semiconductor substrate 10. For example, among the plurality of concentration peaks 25, at least the deepest peak is disposed on the upper surface 21 side. The remaining concentration peaks 25 are disposed on the upper surface 21 side. Figure 3 The example is similarly arranged on the lower surface 23 side of the semiconductor substrate 10.

[0136] Figure 12 It shows Figure 11 An example of the doping concentration distribution at the dd line of FIG. Regarding the doping concentration distribution of this example, the lengths of the buffer region 20 and the drift region 18 in the depth direction are Figure 4 The examples shown are different. Other areas are Figure 4 Same as the example.

[0137] In the buffer region 20 of this embodiment, the deepest concentration peak 25-5 is located on the upper surface 21 side of the semiconductor substrate 10. Furthermore, the concentration peak 25-4 can be located on the lower surface 23 side of the semiconductor substrate 10. A high-concentration region 128 having a higher doping concentration than that of the drift region 18 is provided between the concentration peaks 25-5 and 25-4. The doping concentration profile of the high-concentration region 128 can be a substantially flat region. As described above, the concentration peaks 25 are formed by implanting hydrogen ions, thereby forming a VOH defect between the two concentration peaks 25. Therefore, the high-concentration region 128 can be formed between the concentration peaks 25-5 and 25-4.

[0138] In this case, the doping concentration of the low concentration peak is also Figure 4 and Figure 5 The same as the example described in . Concentration peak 25-5 can be a low concentration peak. Concentration peak 25-4 can also be a low concentration peak.

[0139] In this example, the doping concentration at the center Zc in the depth direction of the semiconductor substrate 10 is set to Dc. The center Zc is included in the high-concentration region 128. The doping concentration Dc is higher than the body doping concentration Db. The peak doping concentration of the low-concentration peak in this example can be less than 50 times the doping concentration Dc, less than 20 times the doping concentration Dc, less than 10 times the doping concentration Dc, less than 8 times the doping concentration Dc, less than 5 times the doping concentration Dc, less than 3 times the doping concentration Dc, or less than 2 times the doping concentration Dc. It should be noted that the average value of the peak doping concentrations of the concentration peaks 25-5 and 25-4 can be less than 50 times the doping concentration Dc, less than 20 times the doping concentration Dc, less than 10 times the doping concentration Dc, less than 8 times the doping concentration Dc, less than 5 times the doping concentration Dc, less than 3 times the doping concentration Dc, or less than 2 times the doping concentration Dc.

[0140] Figure 13 It shows Figure 11 Another example of the doping concentration distribution at the dd line is shown in FIG. As for the doping concentration distribution of this example, the shape of the concentration peak 25-5 is similar to Figure 12 The other distributions are different from Figure 12 Same as the example.

[0141] In this example, the concentration peak 25-5 does not have a distinct peak shape. For example, the high concentration region 128 may have a substantially constant or slightly increasing doping concentration distribution from the lower surface 23 side toward the upper surface 21 side. The doping concentration distribution decreases from the doping concentration of the high concentration region 128 to the doping concentration of the drift region 18 on the upper surface 21 side of the semiconductor substrate 10. In this example, the maximum doping concentration on the upper surface 21 side of the semiconductor substrate 10 in the buffer region 20 may be set to the doping concentration D4 of the concentration peak 25-5. In this example, the concentration peak 25-5 may also be a low concentration peak. The concentration peak 25-4 may also be a low concentration peak.

[0142] Figure 14 is a diagram showing another example of the doping concentration distribution in the buffer zone 20. The buffer zone 20 of this example has five or more concentration peaks 25. The average value of the peak values ​​of the doping concentrations of the two concentration peaks 25-2 and 25-3 closest to the shallowest peak 25-1 among the concentration peaks 25 is set as Da1. The average value of the peak values ​​of the doping concentrations of the two concentration peaks 25-4 and 25-5 located farthest from the lower surface 23 among the concentration peaks 25 is set as Da2. Any of the average values ​​may be an additive average or a multiplicative average.

[0143] The average value Da2 can be less than 1 / 5 of the average value Da1, less than 1 / 10 of the average value Da1, or less than 1 / 20 of the average value Da1. The average value Da2 can be less than 50 times the bulk donor concentration Db, less than 20 times the bulk donor concentration Db, less than 10 times the bulk donor concentration Db, less than 8 times the bulk donor concentration Db, less than 5 times the bulk donor concentration Db, less than 3 times the bulk donor concentration Db, or less than 2 times the bulk donor concentration Db. This structure can also alleviate electric field concentration in the buffer zone 20 near the drift region 18.

[0144] Figure 15 bb is a diagram showing another example of the cross section of the semiconductor device 100. The semiconductor device 100 of this example is Figures 1 to 14 The semiconductor device 100 described in the above also includes a lifetime control region 92. Other structures are similar to those in Figures 1 to 14 The same as any semiconductor device 100 described in .

[0145] The recombination center of carriers (electrons or holes) in the lifetime control region 92 is a region where the concentration is higher than that of the surrounding region. Figure 15In the figure, crosses are used to schematically indicate recombination centers. Recombination centers can be lattice defects primarily consisting of vacancies and / or divacancies, dislocations, interstitial atoms, or transition metals. In this example, lifetime control region 92 is provided within buffer region 20. Lifetime control region 92 can be provided in either transistor portion 70 or diode portion 80.

[0146] The lifetime controlled region 92 can be formed by irradiating the buffer region 20 with charged particles such as helium from the lower surface 23. Recombination centers of carriers are formed at a high density near the range of the charged particles such as helium.

[0147] Since the recombination centers in the lifetime controlled region 92 combine with carriers, the lifetime of carriers is shortened near the lifetime controlled region 92. This shortens the switching time of the semiconductor device 100, such as when the semiconductor device 100 is turned off, and thus reduces switching loss.

[0148] Figure 16 It shows Figure 15 The doping concentration distribution in the buffer area 20 is shown in FIG. Figure 10 The example shown is the same. Figure 16 In FIG. 9 , the chemical concentration distribution of hydrogen and helium and the density distribution of recombination centers are schematically shown. The chemical concentration distribution of hydrogen and helium is shown in FIG. Figure 10 The example shown also has a plurality of hydrogen concentration peaks 126. In the present specification, a recombination center may be a lattice defect mainly composed of a vacancy.

[0149] Density distribution 96 of recombination centers has density peak 94. The depth position of density peak 94 is defined as Zv. Particles other than hydrogen (e.g., helium) that form recombination centers may also have concentration peak 98 at the same depth position as density peak 94. In vacancies near hydrogen concentration peak 126, dangling bonds are terminated by hydrogen. Therefore, the width of density distribution 96 of recombination centers in the Z-axis direction is narrower than the width of the helium concentration distribution in the Z-axis direction. The width of each distribution can be expressed using the full width at half maximum (FWHM).

[0150] In this example, density peak 94 is located between concentration peak 25-1, the shallowest peak, and concentration peak 25-2, the highest concentration peak. Recombination centers form in regions where particles such as helium pass through. If density peak 94 were located between high-concentration peak 25-2 and low-concentration peaks 25-3 or 25-4, the depletion layer might reach density peak 94, increasing leakage current.

[0151] In contrast, by setting the lifetime control region 92 at a position closer to the lower surface 23 than the high concentration peak, the depletion layer can be prevented from reaching the lifetime control region 92, or even if the depletion layer reaches the lifetime control region 92, the lifetime control region 92 and the depletion layer have little overlap, thereby suppressing the increase in leakage current.

[0152] It should be noted that the high-concentration peak and the shallowest peak are formed by injecting high-concentration hydrogen ions. Therefore, even if helium or other particles are injected between the high-concentration peak and the shallowest peak, the doping concentration in this region is highly dependent on the hydrogen concentration and is not easily affected by the helium or other concentration. In this example, the dose of hydrogen ions for the high-concentration peak (concentration peak 25-2) is more than 10 times the dose of helium or other particles. The dose of hydrogen ions can also be more than 20 times the dose of helium or other particles, and can also be more than 50 times the dose of helium or other particles.

[0153] It is also believed that by making the lattice defects in the density peak 94 into VOH defects, a small concentration peak appears in the doping concentration distribution at a position corresponding to the density peak 94. However, the hydrogen concentration peak 126 is not provided at the same depth position as this small concentration peak.

[0154] The center position in the depth direction between concentration peaks 25-1 and 25-2 is defined as Zm. Density peak 94 can be positioned at position Zv between position Z1 and position Zm. That is, density peak 94 can be positioned closer to the shallowest peak between the shallowest peak and the high-concentration peak. This further suppresses the increase in doping concentration closer to upper surface 21 than the high-concentration peak due to helium irradiation.

[0155] exist Figures 1 to 16 In each example described in the above, the deepest peak in the concentration peak 25 (at Figure 16 The peak value of the doping concentration of the concentration peak 25-4 in the depth direction may be the concentration peak 25 adjacent to the deepest peak (in the depth direction). Figure 16 The doping concentration of the deepest peak is 1.1 times or more and 5 times or less of the peak value of the doping concentration of the concentration peak 25-3). That is, the doping concentration of the deepest peak is slightly higher than the doping concentration of the adjacent concentration peak 25. As a result, a large number of lattice defects are formed between the deepest peak and the adjacent concentration peak 25. Therefore, the doping concentration of this area can be increased. As a result, the depletion layer extending from the lower end of the base region 14 can be suppressed from reaching the area on the side of the lower surface 23 of the buffer region 20. As a result, surges during switching operations can be suppressed.

[0156] For example, the peak doping concentration of the deepest peak is 1.0×10 14 atoms / cm 3 Above and 5.0×10 14 atoms / cm 3The peak value of the doping concentration of the deepest peak can also be 2.0×10 14 atoms / cm 3 In addition, the peak value of the doping concentration of the deepest peak can also be 4.0×10 14 atoms / cm 3 the following.

[0157] While the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. Embodiments in which such modifications or improvements are apparent from the claims are also encompassed within the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that: have: A drift region of the first conductivity type is disposed in the semiconductor substrate; and a buffer zone of the first conductivity type, which is provided between the drift region and the lower surface of the semiconductor substrate and has four or more concentration peaks in the depth direction of the semiconductor substrate whose doping concentration is higher than that of the drift region; The four or more concentration peaks include: a shallowest peak, which is closest to the lower surface of the semiconductor substrate; a high concentration peak disposed at a position farther from the lower surface of the semiconductor substrate than the shallowest peak; and Two or more low-concentration peaks are arranged at positions farther from the lower surface of the semiconductor substrate than the high-concentration peak, The peak values ​​of at least two of the two or more low-concentration peaks are 1 / 5 or less of the peak value of the high-concentration peak, The doping concentration of the shallowest peak is higher than the doping concentration of the high concentration peak, The shallowest peak is set as the first peak, and the depth position of the first peak from the lower surface is set as Z1, The high concentration peak is defined as the second peak, and the depth position of the second peak from the lower surface is defined as Z2. The deepest peak of the low-concentration peaks that is located farthest from the lower surface is defined as a fourth peak, and the depth position of the fourth peak from the lower surface is defined as Z4. The peak of the low-concentration peak located on the lower surface side of the fourth peak is defined as the third peak, and the depth position of the third peak from the lower surface is defined as Z3. The distance Z4-Z3 is greater than the distance Z3-Z2.

2. The semiconductor device according to claim 1, wherein The buffer zone has a hydrogen concentration peak corresponding to the concentration peak.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device further includes a collector region of a second conductivity type, and the collector region of the second conductivity type is provided between the buffer region and the lower surface of the semiconductor substrate.

4. The semiconductor device according to claim 1 or 2, wherein: The fourth peak, which is the deepest peak among the low-concentration peaks and is located furthest from the lower surface of the semiconductor substrate, is a peak adjacent to the upper surface side of the third peak. The distance Z4-Z3 is greater than the distance Z2-Z1, and the distance Z4-Z2 is greater than the distance Z2-Z1.

5. The semiconductor device according to claim 1 or 2, wherein: The two or more low-concentration peaks are two or more concentration peaks that are located farthest from the lower surface of the semiconductor substrate among the concentration peaks.

6. The semiconductor device according to claim 1 or 2, wherein: The doping concentration of the low-concentration peak is 50 times or less of a bulk donor concentration of the semiconductor substrate.

7. The semiconductor device according to claim 1 or 2, wherein: The doping concentration of the low-concentration peak is 50 times or less the doping concentration of the central portion in the depth direction of the semiconductor substrate.

8. The semiconductor device according to claim 1 or 2, wherein: The average value of the peak values ​​of the doping concentrations of the fourth peak and the third peak is less than 1 / 5 of the peak value of the doping concentration of the high-concentration peak. The distance Z4-Z3 is greater than the distance Z2-Z1.

9. The semiconductor device according to claim 8, wherein An average value of the peak values ​​of the doping concentrations of the fourth peak and the third peak is 50 times or less of the bulk donor concentration of the semiconductor substrate.

10. The semiconductor device according to claim 8, wherein The average value of the peak values ​​of the doping concentrations of the fourth peak and the third peak is 50 times or less of the doping concentration in the central portion in the depth direction of the semiconductor substrate. The distance Z4-Z2 is greater than the distance Z2-Z1.

11. The semiconductor device according to claim 1 or 2, wherein: The buffer zone contains a recombination center, The density peak of the recombination center in the depth direction is arranged between the shallowest peak and the high concentration peak.

12. The semiconductor device according to claim 11, wherein The density peak is arranged between the shallowest peak and the high concentration peak and close to the shallowest peak.

13. The semiconductor device according to claim 1 or 2, wherein: The doping concentration of the deepest peak among the concentration peaks, which is located farthest from the lower surface of the semiconductor substrate, is 1.1 to 5 times greater than the doping concentration of the concentration peak adjacent to the deepest peak in the depth direction.

14. The semiconductor device according to claim 1 or 2, wherein: The doping concentration of the deepest peak of the concentration peaks, which is located farthest from the lower surface of the semiconductor substrate, is 1.0×10 14 atoms / cm 3 Above and 5.0×10 14 atoms / cm 3 the following.

15. The semiconductor device according to claim 1 or 2, wherein: The buffer zone is arranged between the lower surface of the semiconductor substrate and the center of the semiconductor substrate in the depth direction.

16. The semiconductor device according to claim 1 or 2, wherein: The deepest peak of the concentration peaks, which is located farthest from the lower surface of the semiconductor substrate, is located between the upper surface of the semiconductor substrate and the center of the semiconductor substrate in the depth direction.

17. The semiconductor device according to claim 1 or 2, wherein: The low-concentration peak and the high-concentration peak are the concentration peaks arranged to be adjacent to each other in the depth direction.

18. The semiconductor device according to claim 1 or 2, wherein: Between the fourth peak and the third peak, there is a high-concentration region having a doping concentration higher than that of the drift region and a substantially flat doping concentration distribution.

19. The semiconductor device according to claim 18, wherein The high concentration region includes the center of the semiconductor substrate in the depth direction.

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