Circuit for Calibrating Chopping Switch Mismatch in Time-Interleaved Analog-to-Digital Converters

Abstract

An analog-to-digital converter (ADC) circuit (400) and operating method are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudo-random bit sequence (PRBS) circuit (550) for providing a pseudo-random number (PN) to the switch (510), the calibration device (530), and the multiplier (540). In some embodiments, the calibration device (530) may include a first offset calibration circuit and a second offset calibration circuit (531-532) coupled in parallel between a demultiplexer (D1) and a multiplexer (M1), the demultiplexer (D1) and the multiplexer (M1) alternately routing signals to the first offset calibration circuit and the second offset calibration circuit (531-532) based on a pseudo-random number (PN).

Description

Technical Field

[0001] Aspects of the present disclosure relate generally to integrated circuits, and particularly to differential offset calibration of chopping switches in a time-interleaved analog-to-digital converter (ADC). Background Art

[0002] Circuits and systems utilizing analog-to-digital converters (ADCs) can increase bandwidth without significantly increasing power consumption by using time-interleaved ADCs. A typical time-interleaved ADC circuit includes multiple ADC channels, each of which is configured to sample an analog input signal to generate a corresponding digital output signal. The digital output signals provided by the ADC channels can be combined to generate a combined output signal having a sampling bandwidth equal to an integer multiple of the sampling bandwidth of the individual ADC channels. For example, a time-interleaved ADC circuit including N ADC channels can generate a sampling bandwidth (f BW ) is equal to the sampling bandwidth of the individual ADC channel (f s ) is N times the digital output signal (so that f BW =N*f s ).

[0003] Time skew mismatch, gain mismatch, frequency offset, and phase offset between individual channels of a time-interleaved ADC circuit may adversely affect the performance of the time-interleaved ADC circuit. Calibration circuits may be used to compensate for these mismatches and offsets between individual ADC channels. Summary of the Invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0005] Various aspects of the present disclosure relate to time-interleaved analog-to-digital converter (ADC) circuits and operating methods. The time-interleaved ADC circuit disclosed herein can perform background calibration operations to remove offsets associated with ADCs provided in one or more channels of a chopping circuit and an ADC circuit. An example time-interleaved ADC circuit may include at least a plurality of channels, a gain calibration circuit, and a time skew calibration circuit. Each of the plurality of channels may include an ADC, a switch configured to provide a differential input signal to the ADC, a calibration device coupled to the output of the ADC, a multiplier coupled to the output of the calibration device, and a pseudo-random bit sequence (PRBS) circuit for providing pseudo-random numbers to the switch, the calibration device, and the multiplier. In some embodiments, the pseudo-random number generated by the PRBS circuit may be provided to the time skew calibration circuit. The calibration device within each channel may include selection logic that routes a digital signal output from the ADC to a first offset calibration circuit or a second offset calibration circuit based on the pseudo-random number. The ADC circuit may also include a control circuit configured to adjust a clock signal provided to the plurality of channels based at least in part on a control signal generated by the time skew calibration circuit.

[0006] In some embodiments, the selection logic may include a demultiplexer and a multiplexer. The demultiplexer may include an input coupled to the output of the ADC, a control terminal for receiving a pseudo-random number, and a first output and a second output. The multiplexer may include a first input and a second input, a control terminal for receiving a pseudo-random number, and an output coupled to the multiplier. The first offset calibration circuit may be coupled between the first output of the demultiplexer and the first input of the multiplexer, and the second offset calibration circuit may be coupled between the second output of the demultiplexer and the second input of the multiplexer. In some aspects, the selection logic may be configured to route the digital signal output from the ADC through the first offset calibration circuit based on the first value of the pseudo-random number, and to route the digital signal output from the ADC through the second offset calibration circuit based on the second value of the pseudo-random number. In this way, the selection logic may alternately allow the first offset calibration circuit to remove the offset from the digital signal (e.g., during a first time period) and allow the second offset calibration circuit to remove the offset from the digital signal (e.g., during a second time period).

[0007] The switches within each channel can be any suitable circuit or logic that can scramble the differential input signal based on a pseudo-random number. The switch can be a chopping circuit that is configured to alternately couple the positive and negative components of the differential input signal to the inverting input terminal and the non-inverting input terminal of the ADC based on the pseudo-random number. In some embodiments, the chopping circuit can include a plurality of "pass-through" switches that pass the differential input signal to the ADC without polarity reversal, and can include a plurality of "chopping" switches that pass the differential input signal to the ADC with polarity reversal. In some aspects, the pass-through switches and the chopping switches can be controlled by pseudo-random numbers. In some embodiments, the first offset calibration circuit can be configured to remove the offset associated with the pass-through switch and remove the offset of the ADC, and the second offset calibration circuit can be configured to remove the offset associated with the chopping switch and remove the offset of the ADC.

[0008] The example method disclosed herein can be used to calibrate a time-interleaved ADC circuit. The method can include scrambling a differential input signal based on a pseudorandom number; converting the scrambled differential input signal into a digital signal; calibrating the digital signal for an offset based on the pseudorandom number using a first offset calibration circuit or a second offset calibration circuit; descrambling the calibrated digital signal based on the pseudorandom number using a multiplier; and removing a time skew offset from the descrambled calibrated digital signal. In some embodiments, the removal of the time skew offset can be based at least in part on the pseudorandom number. The method can also include alternately coupling a positive component and a negative component of the scrambled differential input signal to an inverting input terminal and a non-inverting input terminal of the ADC based on the pseudorandom number. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The exemplary embodiments are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings. Throughout the drawings and the specification, like numerals represent like elements.

[0010] Figure 1 is a block diagram of an example system in which aspects of the present disclosure may be implemented.

[0011] Figure 2 is a block diagram of an example time-interleaved analog-to-digital converter (ADC) circuit.

[0012] Figure 3 is a block diagram of an example ADC channel.

[0013] Figure 4 is a block diagram of an example time-interleaved ADC circuit in accordance with some embodiments.

[0014] Figure 5 is a block diagram of an example ADC channel according to some embodiments.

[0015] Figure 6is an illustrative flow chart depicting example operations for operating a time-interleaved ADC circuit, according to some embodiments.

[0016] Figure 7 The architecture of an example field programmable gate array (FPGA) is shown in which aspects of the present disclosure may be implemented. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure can improve the performance of a time-interleaved ADC circuit by compensating for differences in gain, switching offset, and time skew between individual ADC channels across the entire frequency spectrum of the time-interleaved ADC circuit. In some implementations, the time-interleaved ADC circuit disclosed herein can also remove flicker noise, offset spurs, and other interference when converting analog signals to digital signals without signal degradation or performance sacrifice, even for input signal components with frequencies equal to multiples of the sampling frequency of the individual ADC channels. In some aspects, the time-interleaved ADC circuit disclosed herein can utilize the full-rate Nyquist spectrum by removing harmonic noise and offset associated with chopping circuits and ADCs.

[0018] In the following description, many specific details are set forth, such as examples of specific components, circuits, and processes, to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" means directly coupled to or coupled through one or more intermediate components or circuits. In addition, in the following description and for illustrative purposes, specific nomenclature and / or details are set forth to provide a thorough understanding of the example embodiments. However, it will be clear to those skilled in the art that these specific details may not be necessary to practice the example embodiments. In other cases, well-known circuits and devices are shown in block diagram form to avoid obscuring the present disclosure. Any signal provided via the various buses described herein can be time-multiplexed with other signals and provided via one or more common buses. In addition, the interconnections between circuit elements or software blocks can be shown as buses or single signal lines. Each of the buses can alternatively be a single signal line, and each of the single signal lines can alternatively be a bus, and a single line or bus can represent any one or more of the countless physical or logical mechanisms for communication between components. The example embodiments should not be construed as limited to the specific examples described herein, but rather all embodiments defined by the appended claims are included within their scope.

[0019] Figure 1is a block diagram of an example system 100 in which aspects of the present disclosure may be implemented. System 100 includes analog circuitry 102, analog-to-digital converter (ADC) circuitry 104, and digital circuitry 106. In other embodiments, system 100 may include any suitable number of analog circuitry 102 and digital circuitry 106. Analog circuitry 102 (which may be any suitable circuitry or device capable of processing analog signals, such as a temperature sensor, a voltage sensor, a current sensor, a radio frequency (RF) circuit, etc.) may process signals, data, or other information to generate one or more analog signals. ADC circuitry 104 (which includes an input coupled to analog circuitry 104 and an output coupled to digital circuitry 106) may convert the analog signals provided by analog circuitry 102 into one or more digital signals as outputs, for example, by sampling the analog signals using one or more ADCs. Digital circuitry 106 (which may be any suitable circuitry or device capable of processing digital signals, such as a digital signal processor (DSP), a microprocessor, etc.) may process the one or more digital signals provided by ADC circuitry 104. In some embodiments, ADC circuitry 104 and digital circuitry 106 may be configured to monitor, analyze, interpret, or perform some other action or operation on the analog signal output by analog circuitry 102 .

[0020] for Figure 1 In an example, the ADC circuit 104 may be a time-interleaved ADC circuit including a plurality of ADC channels (not shown for simplicity) and an offset calibration circuit 108. The offset calibration circuit 108 may be configured to calibrate one or more of the ADC channels to compensate for a plurality of offsets between the ADC channels, for example, as described with respect to FIG. Figure 2 and 3 As stated.

[0021] Figure 2is a block diagram of an example time-interleaved analog-to-digital converter (ADC) circuit 200. The ADC circuit 200, which can receive a differential analog input signal (IN) having a positive component (INp) and a negative component (INn), includes a plurality of ADC channels 202(1)-202(N), a gain calibration circuit 204, a time skew calibration (TSC) circuit 206, and a control circuit 208. Each of the ADC channels 202(1)-202(N) includes a first input for receiving the positive component INp of the input signal, a second input for receiving the negative component INn of the input signal, an output coupled to the gain calibration circuit 204, and a control terminal coupled to a corresponding output of the control circuit 208. Each of the ADC channels 202(1)-202(N) can also include a corresponding one of the offset calibration circuits 108(1)-108(N). Gain calibration circuit 204 includes an output coupled to an input of TSC circuit 206 and may be configured to adjust output signals provided by ADC channels 202 ( 1 )- 202 (N) based on a reference value.

[0022] The TSC circuit 206 includes a first output for providing a digital output signal (Dout) and a second output for providing a clock calibration (CAL_clk) signal to the control circuit 208. In some embodiments, the TSC circuit 206 can adjust the gain calibration signal provided by the gain calibration circuit 204 to compensate for time skew between the ADC channels 202(1)-202(N). Additionally or alternatively, the TSC circuit 206 can embed information indicative of the time skew between the ADC channels 202(1)-202(N) into the clock calibration signal (CAL_clk).

[0023] In operation, each of the ADC channels 202(1)-202(N) samples the differential analog input signal IN in a time-interleaved manner using one or more clock signals (CLK) provided by the control circuit 208. In some embodiments, each of the ADC channels 202(1)-202(N) may sample the differential analog input signal IN at a different phase of a particular clock signal. Each of the offset calibration circuits 108(1)-108(N) may measure or otherwise determine an average value of an output signal generated by a corresponding one of the ADC channels 202(1)-202(N) and may remove the determined average value from the corresponding output signal. The gain calibration circuit 204 may compensate for gain offsets between the ADC channels 202(1)-202(N), for example, by comparing the root mean square (RMS) power of each of the ADC channel output signals to a reference value and then adjusting the ADC channel output signals based on the comparison.

[0024] The TSC circuit 206 can compensate for time skew offsets between the ADC channels 202(1)-202(N). In some embodiments, the TSC circuit 206 can be configured to measure the difference (or delta) between consecutive samples of the signal provided by the gain calibration circuit 204 and can generate a clock calibration signal (CAL_clk) indicating the measured difference. The control circuit 208 can selectively adjust or delay the clock signals provided to the ADC channels 202(1)-202(N) based on the clock calibration signal (CAL_clk) provided by the TSC circuit 206.

[0025] Figure 3 is a block diagram of an example ADC channel 300. The ADC channel 300 (which may be Figure 2 1 ) includes a chopping circuit 302, an ADC 304, a first offset calibration circuit 306, a multiplier 308, a second offset calibration circuit 310, and a pseudo-random binary sequence (PRBS) circuit 312. The chopping circuit 302 includes an input for receiving a differential analog input signal IN and includes an output coupled to the differential input of the ADC 304. The chopping circuit 302 can be any suitable switch, coupling circuit, logic, or signal routing circuit capable of selectively providing a negative component (INn) of the input signal IN to a non-inverting terminal (+) of the ADC 304 and capable of selectively providing a positive component (INp) of the input signal IN to an inverting terminal (-) of the ADC 304. In some embodiments, the chopping circuit 302 can include a plurality of pass switches and a plurality of chopping switches (the pass switches and the chopping switches are not shown for simplicity). In this manner, chopping circuit 302 may dynamically, periodically, or programmably invert the polarity of the analog input signal provided to ADC 304 .

[0026] ADC 304 can be any suitable circuit or device capable of converting an analog signal into a digital signal. In some embodiments, ADC 304 can be configured to convert a differential analog signal into a single-ended digital signal, such as Figure 3 In other embodiments, ADC 304 may be configured to convert a single-ended analog signal into a single-ended digital signal. Although not shown for simplicity, ADC 304 may receive one or more clock signals (such as a sampling clock for sampling a differential analog input signal).

[0027] A first offset calibration circuit 306 includes an input coupled to the output of ADC 304 and an output coupled to the input of multiplier 308. A second offset calibration circuit 310 includes an input coupled to the output of multiplier 308 and an output for providing an output signal (OUT) for ADC channel 300. A PRBS circuit 312 (which may be any suitable circuit for generating a pseudorandom number or binary sequence) includes an output coupled to a control terminal of chopping circuit 302 and a control terminal of multiplier 308. In some embodiments, chopping circuit 302 may provide a pseudorandom number (PN) to chopping circuit 302 and multiplier 308.

[0028] The chopping circuit 302 can sample the differential analog input signal IN and can dynamically switch the input signal components INp and INn between the inverting terminal (-) and the non-inverting terminal (+) of the ADC 304 based on a pseudo-random number (PN) provided by the PRBS circuit 312. In some implementations, the chopping circuit 302 can use the pseudo-random number (PN) to randomize or scramble the input signal so that flicker noise is spread across the entire frequency spectrum rather than appearing primarily at harmonics of the sampling frequency of the ADC channel 300. Additionally or alternatively, the chopping circuit 302 can prevent components of the analog input signal IN at the sampling frequency of the ADC channel 300 from appearing as noise (e.g., a DC signal) to the ADC 304.

[0029] The first offset calibration circuit 306 can condition the digital signal generated by the ADC 304 to remove the offset associated with the ADC 304. The multiplier 308 can descramble the input signal components output from the first offset calibration circuit 306, for example, to preserve components of the input signal at the sampling frequency and / or to reduce flicker noise caused by the chopping circuit 302. The first offset calibration circuit 306 may be unable to remove the offset of the ADC 304 between the sampling intervals of the chopping circuit 302. As a result, the differential offset between the sampling intervals of multiple instances of the ADC channel 300 can pass through the first offset calibration circuit 306 and the multiplier 308 and appear as time-interleaved residual spurs in the frequency spectrum associated with the time-interleaved ADC circuit 200.

[0030] The second offset calibration circuit 310 can process the descrambled (or unchopped) input signal to remove the residual differential offset introduced by the chopping circuit 302. As described above, the first offset calibration circuit 306 may not be able to sense, for example, offsets and mismatches associated with the chopping circuit 302 because these offsets and mismatches are spectrally scrambled. Because the second offset calibration circuit 310 is downstream of the multiplier 308 (and thus receives the descrambled input signal rather than the scrambled input signal), the second offset calibration circuit 310 can sense and compensate for the offsets and mismatches associated with the chopping circuit 302.

[0031] The second offset calibration circuit 310 can adjust the sampling frequency f of the ADC channel 300. s To support operation under these stringent conditions, when the differential input signal IN contains the sampling frequency f of the ADC channel 300, s When the differential input signal IN contains a signal component that is an integer multiple of the sampling frequency f, the accumulator (not shown for simplicity) within the second offset calibration circuit 310 can be frozen. In some embodiments, a freeze signal (FRZ) can be used to selectively freeze or stop the operation of the accumulator within the second offset calibration circuit 310. In some aspects, when the differential input signal IN contains a signal component that is an integer multiple of the sampling frequency f, the accumulator (not shown for simplicity) within the second offset calibration circuit 310 can be frozen. In some embodiments, a freeze signal (FRZ) can be used to selectively freeze or stop the operation of the accumulator within the second offset calibration circuit 310. s The freeze signal FRZ may be asserted (e.g., logic high) to freeze or stop the operation of the accumulator when the signal component of the differential input signal IN is an integer multiple of the sampling frequency f. s When the sampling frequency is an integer multiple of the signal component, the freeze signal FRZ can be de-asserted (e.g., logic low) to allow normal operation of the accumulator. As a result, even for the sampling frequency f s The second offset calibration circuit 310 can also continue to remove the residual differential offset introduced by the chopping circuit 302 at an input signal frequency that is an integer multiple of .

[0032] In some embodiments, a foreground calibration operation may be used to remove residual differential offsets for input signal components at any frequency with the bandwidth of the ADC circuit 200. In some aspects, the foreground calibration operation may include the following steps or operations:

[0033] • Disable the input signal and continue to operate the first offset calibration circuit 306 and the second offset calibration circuit 310. In some aspects, the input signal can be disabled by setting its value to zero.

[0034] After a period of time, the first offset calibration circuit 306 may operate to remove the total common-mode offset from the chopping circuit 302 and the ADC 304 , and the second offset calibration circuit 310 may operate to remove the differential offset of the chopping circuit 302 .

[0035] • Freeze the accumulator within the second offset calibration circuit 310 (not shown for simplicity).

[0036] Enable input signal.

[0037] According to some aspects of the present disclosure, a time-interleaved ADC circuit is disclosed that can also remove time-interleaved offset spurs (including flicker noise and offset associated with chopping circuits). In some embodiments, the time-interleaved ADC circuit disclosed herein can also allow for the acquisition and sampling of input signal components having frequencies equal to integer multiples of the sampling frequency of each channel without adversely affecting the performance of the offset calibration circuit and without signal corruption. In some embodiments, the time-interleaved ADC circuit disclosed herein can also employ a foreground calibration operation to provide full controllability independent of the input signal.

[0038] Figure 4 is a block diagram of an example time-interleaved ADC circuit 400 according to some embodiments. The ADC circuit 400 can receive a differential analog input signal (IN) having a positive component (INp) and a negative component (INn), and can generate a digital output signal (Dout) based on the differential analog input signal IN. In some embodiments, the ADC circuit 400 can include a plurality of ADC channels 410(1)-410(N), a gain calibration circuit 420, a time skew calibration (TSC) circuit 430, and a control circuit 440. Each of the ADC channels 410(1)-410(N) includes a first input for receiving the positive component INp of the input signal IN, a second input for receiving the negative component INn of the input signal IN, an output coupled to an input of the gain calibration circuit 420, and a clock terminal coupled to a corresponding output of the control circuit 440. Each of the ADC channels 410(1)-410(N) can also include a corresponding PRBS circuit from a plurality of PRBS circuits 412(1)-412(N). PRBS circuits 412(1)-412(N) may be any suitable circuit or device capable of generating a pseudo-random number or binary sequence. Figure 4 In an example embodiment, the PRBS circuit 412(1) in the first ADC channel 410(1) may generate a first binary number (PN_1), the PRBS circuit 412(2) in the second ADC channel 410(2) may generate a second binary number (PN_2), and so on, and the PRBS circuit 412(N) in the Nth ADC channel 410(N) may generate an Nth binary number (PN_N). In other embodiments, each of the ADC channels 410(1)-410(N) may share a common PRBS circuit 412.

[0039] The gain calibration circuit 420 includes an output coupled to an input of the TSC circuit 430 and can be configured to adjust the gain of the output signal provided by the ADC channels 410(1)-410(N) based on a reference value, for example, to compensate for a gain offset between the ADC channels 410(1)-410(N). The TSC circuit 430 includes an input coupled to the output of the gain calibration circuit 420, includes a first output for providing a digital output signal (Dout), and includes a second output for providing a control signal (CTRL). The control signal (CTRL) generated by the TSC circuit 430 can include information that can be used to compensate for a time skew between the ADC channels 410(1)-410(N). In some implementations, the control signal (CTRL) can be used to adjust or delay one or more clock signals (such as clock signals CLK_1-CLK_N) provided to or associated with the ADC channels 410(1)-410(N). In some aspects, the control circuit 440 may adjust the clock signal to calibrate the sampling period and / or sampling interval of one or more of the ADC channels 410(1)-410(N) in a manner that reduces or eliminates time skew, frequency offset, and / or phase offset between the ADC channels 410(1)-410(N).

[0040] The pseudo-random numbers PN_1 to PN_N generated by the corresponding PRBS circuits 412(1)-412(N) can be used to scramble the differential input signal before conversion to a digital signal to spread the flicker noise over the spectrum of the ADC circuit 400, and can be used to descramble the calibrated digital signal. In some embodiments, one or more of the pseudo-random numbers PN_1 to PN_N can be used to select one of a set of offset calibration circuits in a corresponding one of the ADC channels 410(1)-410(N) to remove one or more offsets from the analog input signal IN. In some aspects, the pseudo-random numbers PN_1 to PN_N can alternately select different offset calibration circuits to remove one or more offsets from the differential input signal, such as with respect to Figure 5 As stated.

[0041] Gain calibration circuit 420 can compensate for gain mismatches between ADC channels 410(1)-410(N). In some embodiments, gain calibration circuit 420 can compensate for gain mismatches between ADC channels 410(1)-410(N) by comparing the root mean square (RMS) power of each of the ADC channel output signals to a reference value and adjusting the ADC channel output signals based on the comparison. In other embodiments, gain calibration circuit 420 can use other suitable techniques to compensate for gain mismatches between ADC channels 410(1)-410(N).

[0042] The TSC circuit 430 can compensate for time skew between the ADC channels 410(1)-410(N). In some embodiments, the TSC circuit 430 can be configured to measure the difference (or delta) between consecutive samples output by the gain calibration circuit 420 and generate a control signal (CTRL) indicative of the measured difference. In other embodiments, the TSC circuit 430 can generate the control signal (CTRL) using other suitable techniques. Figure 4 In an example embodiment, TSC circuit 430 is shown as including inputs coupled to receive pseudo-random numbers PN_1 through PN_N generated by respective PRBS circuits 412(1)-412(N). In some embodiments, TSC circuit 430 may use pseudo-random numbers PN_1 through PN_N to ensure accurate time skew compensation of digital signals output from ADC channels 410(1)-410(N). In other embodiments, TSC circuit 430 may use any other suitable pseudo-random number or signal to ensure accurate time skew compensation.

[0043] The control circuit 440 may include an input for receiving a control signal (CTRL) generated by the TSC circuit 430 and may include a plurality of outputs coupled to the ADC channels 410(1)-410(N). In some embodiments, the control circuit 440 may selectively adjust or delay the clock signals CLK_1-CLK_N provided to the respective ADC channels 410(1)-410(N) based on the control signal (CTRL) provided by the TSC circuit 430, for example, to compensate for time skew, frequency offset, and / or phase offset between the ADC channels 410(1)-410(N).

[0044] Figure 5 is a block diagram of an example ADC channel 500 according to some embodiments. Figure 4 One or more embodiments of the ADC channels 410(1)-410(N) of the embodiment of the present invention include a chopping circuit 510, an ADC 520, a calibration device 530, a multiplier 540, and a PRBS circuit 550. The chopping circuit 510 (which may be Figure 3The chopping circuit 302 of FIG. 5 includes an input for receiving a differential input signal IN and an output coupled to a differential input of the ADC 520. The chopping circuit 510 can be any suitable switch, coupling circuit, logic, or crossbar matrix capable of alternately coupling the positive component (INp) and the negative component (INn) of the differential input signal IN to the non-inverting terminal (+) and the inverting terminal (-) of the ADC 520 based on a pseudo-random number PN, such that, for example, the ADC 520 can alternately sample the positive component (INp) and the negative component (INn) of the differential input signal IN. In this manner, the chopping circuit 510 can ensure that the digital signal generated by the ADC 520 is randomized.

[0045] In some embodiments, the chopping circuit 510 may include a plurality of switches that alternately couple the positive and negative signal components of the differential input signal to the non-inverting and inverting terminals of the ADC 520 in a manner that scrambles or randomizes the differential input signal. Figure 5 One embodiment of a chopper circuit 510 is depicted as including four switches SW1-SW4 coupled between a pair of positive and negative input terminals (in+ and in-) and a pair of positive and negative output terminals (out+ and out-). Switch SW1 is coupled between the positive input terminal (in+) and the positive output terminal (out+) of the chopper circuit 510, switch SW2 is coupled between the negative input terminal (in-) and the negative output terminal (out-) of the chopper circuit 510, switch SW3 is coupled between the positive input terminal (in+) and the negative output terminal (out-) of the chopper circuit 510, and switch SW4 is coupled between the negative input terminal (in-) and the positive output terminal (out+) of the chopper circuit 510.

[0046] When the pseudo-random number PN is one of a plurality of first values, the chopping circuit 510 may be in a first state in which switches SW1-SW2 are closed (such as in a conductive state) and switches SW3-SW4 are open (such as in a non-conductive state). In this first state, the chopping circuit 510 routes the positive component of the differential input signal IN to the non-inverting terminal (+) of the ADC 520 via switch SW1, and routes the negative component of the differential input signal IN to the inverting terminal (-) of the ADC 520 via switch SW2. In this manner, the chopping circuit 510 may pass the differential input signal “through” (such as without polarity inversion) to the ADC 520. Therefore, switches SW1-SW2 may be referred to herein as “through” switches of the chopping circuit 510.

[0047] When the pseudo-random number PN is one of a plurality of second values, the chopping circuit 510 may be in a second state in which switches SW1-SW2 are open (e.g., in a non-conducting state) and switches SW3-SW4 are closed (e.g., in a conducting state). In this second state, the chopping circuit 510 routes the positive component of the differential input signal IN to the inverting terminal (-) of the ADC 520 via switch SW3, and routes the negative component of the differential input signal IN to the non-inverting terminal (+) of the ADC 520 via switch SW4. In this manner, the chopping circuit 510 may chop (e.g., by polarity inversion) the differential input signal provided to the ADC 520. Therefore, switches SW3-SW4 may be referred to herein as "chopping" switches of the chopping circuit 510.

[0048] ADC 520 can be any suitable circuit or device capable of converting an analog signal into a digital signal. In some embodiments, ADC 520 can be configured to convert a differential analog signal into a single-ended digital signal, such as Figure 5 In other embodiments, ADC 520 may be configured to convert a single-ended analog signal into a single-ended digital signal.

[0049] The calibration device 530 is coupled between the ADC 520 and the multiplier 540 and includes a demultiplexer (DEMUX) D1, a first offset calibration circuit 531, a second offset calibration circuit 532, and a multiplexer (MUX) M1. The demultiplexer D1 includes an input coupled to the output of the ADC 520, a first output coupled to the input of the first OC circuit 531, a second output coupled to the input of the second OC circuit 532, and a control terminal coupled to the output of the PRBS circuit 550. The multiplexer M1 includes a first input coupled to the output of the first OC circuit 531, a second input coupled to the output of the second OC circuit 532, an output coupled to the input of the multiplier 540, and a control terminal coupled to the output of the PRBS circuit 550.

[0050] A first offset calibration circuit 531 and a second offset calibration circuit 532 are coupled in parallel with each other between the demultiplexer D1 and the multiplexer M1. The first offset calibration circuit 531 can be configured to remove offsets caused by or associated with one or more pass switches in the chopping circuit 510 (and / or offsets caused by or associated with other circuit elements within the chopping circuit 510 that maintain the polarity of the differential input signal IN when routed to the ADC 520) from the digital signal output by the ADC 520. The first offset calibration circuit 531 can also be configured to remove offsets caused by or associated with the ADC 520. The second offset calibration circuit 532 can be configured to remove offsets caused by or associated with one or more chopping switches in the chopping circuit 510 (and / or offsets caused by or associated with other circuit elements within the chopping circuit 510 that invert the polarity of the differential input signal IN when routed to the ADC 520) from the digital signal output by the ADC 520. The second offset calibration circuit 532 may also be configured to remove an offset caused by or associated with the ADC 520. Figure 3 The ADC channel 300 is depicted as including two offset calibration circuits 306 and 310 coupled in series with each other, but with respect to Figure 5 The depicted ADC channel 500 includes a first offset calibration circuit 531 and a second offset calibration circuit 531 coupled in parallel to each other.

[0051] In some embodiments, one or more freeze signals may be used to selectively freeze or stop the operation of accumulators (not shown for simplicity) disposed within the first offset calibration circuit 531 and the second offset calibration circuit 532. Figure 5 In the example embodiment shown, the first offset calibration circuit 531 may include an input for receiving a first freeze signal (FRZ_1), and the second offset calibration circuit 532 may include an input for receiving a second freeze signal (FRZ_2). In some aspects, when the differential input signal IN includes a sampling frequency f as the sampling frequency of the ADC channel 500, s The first freeze signal FRZ_1 may be asserted (e.g., logic high) to freeze or stop the operation of the accumulator within the first offset calibration circuit 531 when the differential input signal IN contains a signal component that is an integer multiple of the sampling frequency f of the ADC channel 500. s When the differential input signal IN does not contain a signal component that is an integer multiple of the sampling frequency f, the second freeze signal FRZ_2 may be asserted (eg, logic high) to freeze or stop the operation of the accumulator within the second offset calibration circuit 532. s, the first freeze signal FRZ_1 and the second freeze signal FRZ_2 may be de-asserted (e.g., logic low) to allow normal operation of the accumulators within the first offset calibration circuit 531 and the second offset calibration circuit 532, respectively. In this way, even if the frequency component of the differential input signal IN is equal to the sampling frequency f of the ADC channel 500, the first freeze signal FRZ_1 and the second freeze signal FRZ_2 may be de-asserted (e.g., logic low) to allow normal operation of the accumulators within the first offset calibration circuit 531 and the second offset calibration circuit 532, respectively. s In other embodiments, the first offset calibration circuit 531 and the second offset calibration circuit 532 may receive the same freeze signal.

[0052] Multiplier 540 includes an output for providing a digital output signal Dout and includes a control terminal coupled to an output of PRBS circuit 550. In some embodiments, multiplier 540 can descramble the calibrated digital signal output from calibration device 530, e.g., to reduce flicker noise caused by chopping circuit 510.

[0053] PRBS circuit 550 (which may be Figure 4 In some embodiments, one or more of the PRBS circuits 412(1)-412(N) may provide a pseudo-random number (PN) to the chopping circuit 510, the demultiplexer D1, the multiplexer M1, and the multiplier 540. In some embodiments, the PRBS circuit 550 may also provide a pseudo-random number (PN) to the chopping circuit 510, the demultiplexer D1, the multiplexer M1, and the multiplier 540. Figure 4 The TSC circuit 430 provides a pseudo-random number (PN).

[0054] The chopping circuit 510 can sample the differential input signal and can alternately switch the positive signal component INp and the negative signal component INn of the differential input signal IN between the non-inverting terminal (+) and the inverting terminal (-) of the ADC 520 based on a pseudo-random number (PN). In some embodiments, the chopping circuit 510 can sample the differential input signal and can alternately switch the positive signal component INp and the negative signal component INn of the differential input signal IN between the non-inverting terminal (+) and the inverting terminal (-) of the ADC 520 based on a pseudo-random number (PN). In this way, the chopping circuit 510 can ensure that the digital signal generated by the ADC 520 is randomized.

[0055] When the first offset calibration circuit 531 is selected by the selection logic formed by the demultiplexer D1 and the multiplexer M1 in response to a pseudo-random number (PN), the first offset calibration circuit 531 can adjust the digital signal generated by the ADC 520 to remove the offset associated with the ADC 520 and the offset associated with the pass switch provided in the chopping circuit 510. When the second offset calibration circuit 532 is selected by the selection logic formed by the demultiplexer D1 and the multiplexer M1 in response to the pseudo-random number (PN), the second offset calibration circuit 532 can adjust the digital signal generated by the ADC 520 to remove the offset associated with the ADC 520 and the offset associated with the chopping switch provided in the chopping circuit 510. The multiplier 540 can "undo-chop" the adjusted digital signal provided by the first offset calibration circuit 531 or the second offset calibration circuit 532 based on the pseudo-random number (PN), for example, to reduce flicker noise caused by the ADC 520. Note that if the frequency response of the first offset calibration circuit 531 is less than a value, the first offset calibration circuit 531 cannot follow the flicker noise caused by the ADC 520, which allows the flicker noise to be scrambled over the frequency bandwidth of the ADC channel 500 (rather than appearing at multiples of the sampling frequency of the ADC channel 500).

[0056] Figure 6 is an illustrative flow chart depicting example operations 600 for operating a time-interleaved ADC circuit according to some embodiments. Figure 4-5 ADC circuit 400 is described, but the example operation 600 can be performed by any other suitable ADC circuit. In some embodiments, operation 600 can be performed as a foreground calibration operation.

[0057] ADC circuit 400 may scramble the differential input signal based on a pseudo-random number (601). In some embodiments, chopping circuit 510 may scramble the differential input signal using the pseudo-random number provided by PRBS circuit 550 so that flicker noise is spread across the entire frequency spectrum of ADC circuit 400 rather than appearing primarily at harmonics of the sampling frequency of ADC channels 410(1)-410(N).

[0058] The ADC circuit 400 may alternately couple the positive and negative components of the scrambled differential input signal to the inverting and non-inverting input terminals (602) of the ADC based on the pseudo-random number. In some embodiments, the chopping circuit 510 may prevent components of the differential input signal at the sampling frequency of the ADC channels 410(1)-410(N) from appearing as noise (e.g., a DC signal) to the ADC.

[0059] The ADC circuit 400 may convert the scrambled differential input signal into a digital signal (603). In some embodiments, the ADC 520 may be configured to convert the differential analog signal into a single-ended digital signal, such as Figure 5 In other embodiments, ADC 520 may be configured to convert a single-ended analog signal into a single-ended digital signal.

[0060] The ADC circuit 400 can calibrate the digital signal for offset based on the pseudo-random number using the first offset calibration circuit or the second offset calibration circuit (604). Figure 5 , a first offset calibration circuit 531 and a second offset calibration circuit 532 may be coupled in parallel with each other between the demultiplexer D1 and the multiplexer M1. The first offset calibration circuit 531 may remove the ADC offset from the digital signal output by the ADC 520 and may remove the offset from the pass switch from the differential input signal. The second offset calibration circuit 532 may remove the ADC offset from the digital signal output by the ADC 520 and may remove the offset from the chopping circuit 510. In some embodiments, the selection circuit formed by the demultiplexer D1 and the multiplexer M1 may route the digital signal output from the ADC 520 through the first offset calibration circuit 531A based on the first value of the pseudorandom number, and may route the digital signal output from the ADC 520 through the second offset calibration circuit 531B based on the second value of the pseudorandom number.

[0061] ADC circuit 400 can use a multiplier to descramble the calibrated digital signal based on the pseudo-random number (605). In some embodiments, multiplier 540 can descramble the calibrated digital signal output from calibration device 530, for example, to reduce flicker noise caused by chopping circuit 510.

[0062] The ADC circuit 400 may remove the time skew offset from the descrambled calibrated digital signal (606). In some embodiments, the TSC circuit 430 may generate a control signal that may be used to compensate for time skew between the ADC channels 410(1)-410(N). In some aspects, the control signal may be used to adjust or delay one or more clock signals provided to or associated with the ADC channels 410(1)-410(N), for example, to calibrate a sampling period and / or sampling interval of one or more of the ADC channels 410(1)-410(N) in a manner that reduces or eliminates time skew, frequency offset, and / or phase offset between the ADC channels 410(1)-410(N).

[0063] Figure 7The architecture 700 of a field programmable gate array (FPGA) implementation of a programmable IC 1 is shown, which includes a number of different programmable blocks, including transceivers 37, configurable logic blocks ("CLBs") 33, random access memory blocks ("BRAMs") 34, input / output blocks ("IOBs") 36, configuration and clock logic ("CONFIG / CLOCK") 42, digital signal processing blocks ("DSPs") 35, specialized input / output blocks ("I / Os") 41 (e.g., configuration ports and clock ports), and other programmable logic 39, such as a digital clock manager, analog-to-digital converters, system monitoring logic, etc. The FPGA may also include a PCIe interface 40, an analog-to-digital converter (ADC) 38, etc.

[0064] In some FPGAs, each programmable block may include at least one programmable interconnect element ("INT") 43 having connections to input and output terminals 48 of programmable logic elements within the same block, such as Figure 7 . Each programmable interconnect element 43 may also include a connection to an interconnect segment 49 of (multiple) adjacent programmable interconnect elements in the same block or (multiple) other blocks. Each programmable interconnect element 43 may also include a connection to an interconnect segment 50 of a general wiring resource between logic blocks (not shown). The general wiring resources may include wiring channels between logic blocks (not shown), the wiring channels including tracks of interconnect segments (e.g., interconnect segments 50) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments (e.g., interconnect segments 50) of the general wiring resources may span one or more logic blocks. The programmable interconnect elements 43, together with the general wiring resources, implement a programmable interconnect structure ("programmable interconnect") for the FPGA shown.

[0065] In an example implementation, the CLB 33 may include a configurable logic element ("CLE") 44 that can be programmed to implement user logic plus a single programmable interconnect element ("INT") 43. In addition to one or more programmable interconnect elements, the BRAM 34 may also include a BRAM logic element ("BRL") 45. Typically, the number of interconnect elements included in a block depends on the height of the block. In the illustrated example, the BRAM block has the same height as the five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements, the DSP block 35 may also include a DSP logic element ("DSPL") 46. In addition to one instance of the programmable interconnect element 43, the IOB 36 may also include, for example, two instances of an input / output logic element ("IOL") 47. As will be apparent to those skilled in the art, the actual I / O pads that connect to the I / O logic element 47 are generally not limited to the area of ​​the input / output logic element 47.

[0066] In the example shown, close to the die ( Figure 7 The horizontal area in the center of the FPGA (as shown) is used for configuration, clock, and other control logic. Vertical columns 51 extending from this horizontal area or column are used to distribute clock and configuration signals across the width of the FPGA.

[0067] use Figure 7 Some FPGAs of the illustrated architecture include additional logic blocks that disrupt the conventional columnar structure that makes up the bulk of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic.

[0068] Notice, Figure 7 This is intended to illustrate only an exemplary FPGA architecture. For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and Figure 7 The interconnect / logic implementation included at the top of FIG is purely exemplary. For example, in a real FPGA, where CLBs appear, they typically include more than one adjacent row of CLBs to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

[0069] Those skilled in the art will appreciate that any of a variety of different methods and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0070] In addition, it will be understood by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above according to their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Technicians can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of this disclosure.

[0071] The methods, sequences, or algorithms described in conjunction with the various aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM latch, a flash memory latch, a ROM latch, an EPROM latch, an EEPROM latch, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor.

[0072] In the foregoing description, the exemplary embodiments have been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader scope of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A device for analog-to-digital conversion, comprising: Multiple channels, each channel includes: Analog-to-digital converter ADC; a switch configured to provide a differential input signal to the ADC; a calibration device coupled to an output of the ADC; a multiplier coupled to an output of the calibration device; and a pseudo-random bit sequence (PRBS) circuit configured to provide pseudo-random numbers to the switch, the calibration device, and the multiplier; a gain calibration circuit comprising an input coupled to the calibration device in each of the plurality of channels; and a time skew calibration circuit coupled to the gain calibration circuit and configured to provide an output signal based at least in part on the differential input signal and the pseudorandom number, The calibration device includes a first offset calibration circuit, a second offset calibration circuit, and selection logic, and the selection logic is configured to select one of the first offset calibration circuit and the second offset calibration circuit based on the pseudo random number.

2. The device according to claim 1, wherein at least one of the following: The switch includes a chopping circuit configured to scramble the differential input signal based on the pseudo-random number; The switch is configured to alternately couple the positive and negative components of the differential input signal to the inverting and non-inverting inputs of the ADC based on the pseudo-random number; or The time skew calibration circuit is coupled to the gain calibration circuit and the PRBS circuit in each of the plurality of channels.

3. The apparatus of claim 1 , wherein the selection logic comprises: a demultiplexer comprising an input coupled to the output of the ADC, a control terminal for receiving the pseudorandom number, and a plurality of outputs; as well as a multiplexer comprising a plurality of inputs, a control terminal for receiving the pseudo-random number, and an output coupled to the multiplier, The first offset calibration circuit and the second offset calibration circuit are coupled in parallel with each other between the multiple outputs of the demultiplexer and the multiple inputs of the multiplexer.

4. The apparatus of claim 3 , wherein the demultiplexer and the multiplexer are configured to: routing a digital signal output from the ADC through the first offset calibration circuit based on a first value of the pseudorandom number; and A digital signal output from the ADC is routed through the second offset calibration circuit based on a second value of the pseudorandom number.

5. The apparatus of claim 3 , wherein the switch comprises a chopping circuit, the chopping circuit comprising a plurality of pass switches and a plurality of chopping switches, wherein: the first offset calibration circuit being configured to remove an offset associated with the pass switch and to remove an offset of the ADC; as well as The second offset calibration circuit is configured to remove an offset associated with the chopping switch and to remove an offset of the ADC.

6. The apparatus according to claim 1, further comprising: A control circuit is configured to adjust clock signals provided to the plurality of channels based at least in part on a control signal generated by the time deskew circuit.

7. An integrated circuit comprising: an analog circuit configured to generate a differential input signal; as well as The analog-to-digital converter (ADC) circuit includes multiple channels, each of which includes: an ADC comprising an inverting input terminal, a non-inverting input terminal, and one or more outputs; a pseudo-random bit sequence (PRBS) circuit configured to generate a pseudo-random number; a chopping circuit configured to alternately couple a positive component and a negative component of the differential input signal between the inverting input terminal and the non-inverting input terminal of the ADC based on the pseudo random number; a calibration device coupled to the one or more outputs of the ADC and responsive to the pseudorandom number; and a multiplier coupled to the calibration device and responsive to the pseudo-random number, wherein the calibration device comprises: a first offset calibration circuit, a second offset calibration circuit, and selection logic, and wherein the selection logic is configured to select one of the first offset calibration circuit and the second offset calibration circuit based on the pseudo-random number.

8. The integrated circuit of claim 7, further comprising: a gain calibration circuit coupled to an output of the calibration device in each of the plurality of channels; as well as A time skew calibration circuit is coupled to the gain calibration circuit and includes an output for providing a digital output signal indicative of the differential input signal.

9. The integrated circuit of claim 8, wherein at least one of the following: The time skew calibration circuit further includes an input coupled to the PRBS circuit in each of the plurality of channels; The integrated circuit further includes a control circuit configured to adjust a clock signal provided to the plurality of channels based at least in part on a control signal generated by the time skew calibration circuit; or The chopping circuit is configured to scramble the differential input signal based at least in part on the pseudorandom number.

10. The integrated circuit of claim 8, wherein the selection logic comprises: a demultiplexer comprising an input coupled to the one or more outputs of the ADC, a control terminal for receiving the pseudorandom number, and a first output and a second output; as well as a multiplexer comprising a first input and a second input, a control terminal for receiving the pseudo-random number, and an output coupled to the multiplier, wherein the first offset calibration circuit is coupled between the first output of the demultiplexer and the first input of the multiplexer, wherein the second offset calibration circuit is coupled between the second output of the demultiplexer and the second input of the multiplexer, and wherein the first offset calibration circuit and the second offset calibration circuit are coupled in parallel to each other.

11. The integrated circuit of claim 10 , wherein at least one of the following: The demultiplexer and the multiplexer are configured to: routing a digital signal output from the ADC through the first offset calibration circuit based on a first value of the pseudorandom number; and routing a digital signal output from the ADC through the second offset calibration circuit based on a second value of the pseudorandom number; or The chopping circuit includes a plurality of pass switches and a plurality of chopping switches, and: the first offset calibration circuit being configured to remove an offset associated with the pass switch from the differential input signal and to remove an offset of the ADC from a digital signal provided to the calibration device; and The second offset calibration circuit is configured to remove an offset associated with the chopping switch from the differential input signal and to remove an offset of the ADC from a digital signal provided to the calibration device.

12. A method for calibrating an analog-to-digital converter (ADC) circuit, comprising: Using a chopping circuit to scramble the differential input signal based on a pseudo-random number; Use ADC to convert the scrambled differential input signal into a digital signal; calibrating the digital signal for offset using a first offset calibration circuit or a second offset calibration circuit based on the pseudo-random number; descrambling the calibrated digital signal based on the pseudorandom number using a multiplier; as well as removing the time skew offset from the descrambled, calibrated digital signal, Calibrating the digital signal for offset using the first offset calibration circuit or the second offset calibration circuit based on the pseudo-random number includes selecting, by selection logic, one of the first offset calibration circuit and the second offset calibration circuit based on the pseudo-random number.

13. The method of claim 12, wherein removing the time skew offset is based at least in part on the pseudorandom number.

14. The method according to claim 12, further comprising: Positive and negative components of the scrambled differential input signal are alternately coupled to an inverting input terminal and a non-inverting input terminal of the ADC based on the pseudo random number.

15. The method of claim 12, wherein the chopping circuit comprises a plurality of pass switches and a plurality of chopping switches, and wherein: the first offset calibration circuit being configured to remove an offset associated with the pass switch from the differential input signal and to remove an offset of the ADC; as well as The second offset calibration circuit is configured to remove an offset associated with the chopping switch from the differential input signal and to remove an offset of the ADC.

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