semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes a first unit region and a filling region adjacent to each other in a first direction. The semiconductor device includes: an active pattern extending in the first direction within the first unit region; a gate electrode extending in a second direction intersecting the first direction on the active pattern; a gate contact electrically connected to the upper surface of the gate electrode; a source / drain contact electrically connected to the source / drain region of the active pattern, the source / drain contact being adjacent to one side of the gate electrode; a connecting line extending in the first direction above the first unit region and the filling region and electrically connected to one of the gate contact or the source / drain contact; and a filling line located within the filling region. A related layout design method and manufacturing method are also provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0038316, filed on March 30, 2020, and Korean Patent Application No. 10-2020-0079973, filed on June 30, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] Semiconductor devices have gained attention as an important factor in the electronics industry due to their characteristics such as miniaturization, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that perform arithmetic processing on logic data, and hybrid semiconductor devices that include memory elements and logic elements.

[0005] With the rapid development of the electronics industry, the requirements for the performance of semiconductor devices are gradually increasing. For example, the demand for high reliability, high speed, and / or multifunctionality of semiconductor devices is gradually increasing. To meet these requirements, the structures in semiconductor devices have become increasingly complex and highly integrated. Summary of the Invention

[0006] Aspects of the inventive concept provide a semiconductor device in which use of high-level wiring is reduced, and power consumption and PnR (Place and Routing) resource loss are reduced.

[0007] Aspects of the present inventive concept also provide a layout design method for a semiconductor device in which use of high-level wiring is reduced, and power consumption and PnR resource loss are reduced.

[0008] Aspects of the present inventive concept also provide a method for manufacturing a semiconductor device in which use of high-level wiring is reduced, and power consumption and PnR resource loss are reduced.

[0009] However, aspects of the present invention are not limited to the aspects set forth herein. The above and other aspects of the present invention will become more apparent to those skilled in the art by referring to the detailed description of the present invention given below.

[0010] According to one aspect of the present inventive concept, a semiconductor device is provided, comprising a first cell region and a filling region adjacent to each other in a first direction, the semiconductor device comprising: an active pattern extending in the first direction within the first cell region; a gate electrode extending on the active pattern in a second direction intersecting the first direction; a gate contact located on an upper surface of the gate electrode and electrically connected to the upper surface of the gate electrode; a source / drain contact electrically connected to a source / drain region of the active pattern, the source / drain contact being in contact with the gate electrode. adjacent to one side of the electrode; a connecting line, which extends in the first direction above the first cell region and the filling region, is located on one of the gate contact or the source / drain contacts and is electrically connected to the gate contact or the source / drain contacts; and a filling line, which extends in the second direction inside the filling region, is located on the connecting line and is electrically connected to the connecting line, wherein the upper surface of the gate contact and the upper surface of the source / drain contact are coplanar, and the height of the upper surface of the filling line is equal to or lower than the height of the upper surface of the connecting line.

[0011] According to one aspect of the present invention, a semiconductor device is provided, comprising a first cell region and a second cell region spaced apart from each other in a first direction, and a filling region located between the first cell region and the second cell region, the semiconductor device comprising: a gate electrode extending in a second direction intersecting the first direction within the first cell region; a source / drain contact adjacent to one side of the gate electrode; a first connecting line extending in the first direction above the first cell region and the filling region, and located on and electrically connected to the source / drain contact; a second gate electrode, the first connecting line extending in the first direction above the first cell region and the filling region, and located on the source / drain contact; and a second gate electrode extending in a second direction intersecting the first direction. Two gate electrodes extend in the second direction within the second cell area; a gate contact, the gate contact being located on the upper surface of the second gate and electrically connected to the upper surface of the second gate; a second connecting line, the second connecting line extending in the first direction above the filling area and the second cell area, being located on the gate contact and electrically connected to the gate contact; and a filling line extending in the second direction within the filling area to connect the first connecting line and the second connecting line, wherein the first connecting line and the second connecting line are at a first wiring level, and the level of the filling line is lower than the first wiring level.

[0012] According to one aspect of the present inventive concept, a semiconductor device is provided, comprising: a first power supply line and a second power supply line, the first power supply line and the second power supply line extending in parallel in a first direction; a first cell isolation film, a second cell isolation film, and a third cell isolation film, the first cell isolation film, the second cell isolation film, and the third cell isolation film being spaced apart from each other in the first direction and extending in parallel in a second direction intersecting the first direction; a first active pattern, the first active pattern extending in the first direction between the first power supply line and the second power supply line; a first gate electrode, the first gate electrode extending in the second direction between the first cell isolation film and the second cell isolation film; a first source / drain contact, the first source / drain contact being located on a first source / drain region of the first active pattern and electrically connected to the first source / drain region of the first active pattern, the first source / drain contact being adjacent to one side of the first gate electrode; and a first connection contact, the first connection contact being located on the first source / drain region. a first wiring path, the first wiring path being located on the upper surface of the first connection contact and being electrically connected to the upper surface of the first connection contact; a first wiring line, the first wiring line extending in the first direction and being located on the upper surface of the first wiring path and being electrically connected to the upper surface of the first wiring path; a second wiring path, the second wiring path being located on the upper surface of the first wiring line and being electrically connected to the upper surface of the first wiring line; a second wiring line, the second wiring line extending in the second direction and being located on the upper surface of the second wiring path and being electrically connected to the upper surface of the second wiring path; and a filling line extending in the second direction between the second unit isolation film and the third unit isolation film and being located on the first wiring line and being electrically connected to the first wiring line, wherein the height of the upper surface of the filling line is equal to or lower than the height of the upper surface of the first wiring line. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present inventive concepts will become more apparent by describing in detail example embodiments of the present inventive concepts with reference to the accompanying drawings, in which:

[0014] Figure 1 is a layout diagram for illustrating a semiconductor device according to some embodiments.

[0015] Figure 2 is a top view illustrating a semiconductor device according to some embodiments.

[0016] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA.

[0017] Figure 4 It is along Figure 2 A cross-sectional view taken along line BB.

[0018] Figure 5 It is along Figure 2 A cross-sectional view taken along line CC.

[0019] Figure 6 It is along Figure 2 A cross-sectional view taken along line DD.

[0020] Figure 7 and Figure 8 is a cross-sectional view for illustrating a semiconductor device according to some embodiments.

[0021] Figure 9 is a layout diagram for illustrating a semiconductor device according to some embodiments.

[0022] Figure 10 It is along Figure 9 A cross-sectional view taken along line EE.

[0023] Figure 11 is a layout diagram for illustrating a semiconductor device according to some embodiments.

[0024] Figure 12 It is along Figure 11 A cross-sectional view taken along line FF.

[0025] Figure 13 is an example layout diagram for explaining the function of a fill line of a semiconductor device according to some embodiments.

[0026] Figures 14 to 17 1 and 2 are diagrams illustrating various layouts of semiconductor devices according to some embodiments.

[0027] Figure 18 is an example layout diagram for explaining the function of a fill line of a semiconductor device according to some embodiments.

[0028] Figures 19 to 21 1 are various example layout diagrams for explaining the functionality of fill lines of a semiconductor device according to some embodiments.

[0029] Figure 22 is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments.

[0030] Figure 23is a flowchart for explaining a layout design method for a semiconductor device and a method for manufacturing a semiconductor device according to some embodiments.

[0031] Figures 24 to 27 is a layout diagram for illustrating a layout design method for a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0032] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, first component, or first part discussed below may be referred to as a second element, second component, or second part without departing from the teachings of the present invention.

[0033] The following will refer to Figures 1 to 6 Semiconductor devices according to some embodiments are described.

[0034] Although a fin-type transistor (FinFET) including a channel region having a fin-shaped pattern is shown as an example, the present disclosure is not limited thereto. According to some embodiments, the semiconductor device may include, for example, a tunnel FET, a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. In addition, the semiconductor device according to some embodiments of the present invention may include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), etc.

[0035] Figure 1 is a layout diagram for illustrating a semiconductor device according to some embodiments.

[0036] Reference Figure 1 , a semiconductor device according to some embodiments includes a first cell region CR1 and a first filling region FR1 .

[0037] The standard cells provided by the cell library may be disposed in the first cell region CR1. Figure 1 In the embodiment, the standard cell disposed in the first cell region CR1 may be a NAND cell. However, this is merely an example, and in some embodiments, the standard cell disposed in the first cell region CR1 may be one of various types of cells such as a NOR cell or an XOR cell. The first fill region FR1 may be a dummy cell region located in an empty space between cell regions where standard cells are disposed (e.g., filling the empty space).

[0038] The first cell region CR1 and the first filling region FR1 may be adjacent to each other. Hereinafter, the first cell region CR1 and the first filling region FR1 will be described as being arranged along the first direction X.

[0039] In some embodiments, the first cell region CR1 and the first filling region FR1 may be defined by a first cell isolation film I1a, a second cell isolation film I1b, and a third cell isolation film I1c sequentially arranged (e.g., spaced apart from each other) along a first direction X. For example, the first cell isolation film I1a, the second cell isolation film I1b, and the third cell isolation film I1c may extend side by side (i.e., parallel) in a second direction Y intersecting the first direction X. The first cell region CR1 may be defined between the first cell isolation film I1a and the second cell isolation film I1b. The first filling region FR1 may be defined between the second cell isolation film I1b and the third cell isolation film I1c. The second cell isolation film I1b may isolate the first cell region CR1 from the first filling region FR1.

[0040] In some embodiments, the second cell isolation film I1b and the third cell isolation film Ic may be spaced apart by one gate pitch (one contacted poly pitch (CPP)). For example, the spacing between the second cell isolation film I1b and the third cell isolation film I1c may be the same as the spacing between adjacent gate electrodes (e.g., the first gate electrode G1 and the second gate electrode G2 described below). In this specification, the term "same" refers not only to the same thing, but also to minor differences that may occur due to process margins, etc.

[0041] In some embodiments, the second cell isolation film I1b and the third cell isolation film Ic may be adjacent to each other. For example, another gate electrode or another cell isolation film may not be placed between the second cell isolation film I1b and the third cell isolation film I1c.

[0042] In some embodiments, the spacing distance between the second cell isolation film I1b and the third cell isolation film I1c may be 60 nanometers (nm) or less. As an example, the spacing distance between the second cell isolation film I1b and the third cell isolation film I1c may be 50 nm to 60 nm.

[0043] The semiconductor device according to some embodiments may include a first active region AR1, a second active region AR2, a first gate electrode G1, a second gate electrode G2, a plurality of source / drain contacts CA11 to CA16, a plurality of gate contacts CB11 and CB12, a plurality of connection contacts CM11 to CM17, a first power line V DD , the second power supply line V SS , a plurality of first wiring lines OW1 , IW1 , IW2 , and CW1 , a second wiring line DW1 , and a first filling line FW1 .

[0044] The first active area AR1 and the second active area AR2 may be spaced apart from each other and extend side by side. For example, the first active area AR1 and the second active area AR2 may each extend in the first direction X. The second active area AR2 may be spaced apart from the first active area AR1 in the second direction Y. In some embodiments, the first active area AR1 and the second active area AR2 may be formed above each of the first cell region CR1 and the first fill region FR1.

[0045] In some embodiments, semiconductor elements (e.g., transistors) of different conductivity types may be formed on the first active area AR1 and the second active area AR2. Hereinafter, it will be described that the first active area AR1 is a PFET region and the second active area AR2 is an NFET region. However, this is merely an example, and in some embodiments, the first active area AR1 may be an NFET region and the second active area AR2 may be a PFET region.

[0046] The first gate electrode G1 and the second gate electrode G2 may be interposed between the first cell isolation film I1a and the second cell isolation film I1b. The first gate electrode G1 and the second gate electrode G2 may intersect each of the first active region AR1 and the second active region AR2. For example, the first gate electrode G1 and the second gate electrode G2 may extend side by side in the second direction Y.

[0047] In some embodiments, the first gate electrode G1 and the second gate electrode G2 may be spaced apart by one gate pitch (1 CPP). That is, the first gate electrode G1 and the second gate electrode G2 may be adjacent gate electrodes. For example, another gate electrode or another cell isolation film may not be disposed between the first gate electrode G1 and the second gate electrode G2.

[0048] In some embodiments, the spacing distance between adjacent gate electrodes and unit isolation films (for example, between the first gate electrode G1 and the first unit isolation film I1a, or between the second gate electrode G2 and the second unit isolation film I1b) can be the same as the spacing distance between adjacent gate electrodes (for example, the first gate electrode G1 and the second gate electrode G2).

[0049] A plurality of source / drain contacts CA11 to CA16 may be disposed on both sides (e.g., opposite sides) of the first gate electrode G1 or the second gate electrode G2 or adjacent to both sides (e.g., opposite sides) of the first gate electrode G1 or the second gate electrode G2. The plurality of source / drain contacts CA11 to CA16 may be connected to the source / drain regions of the first active region AR1 or the second active region AR2. As used herein, the term "connect" may refer to an electrical connection.

[0050] For example, a first source / drain contact CA11 may be formed on the first active area AR1 between the first gate electrode G1 and the first cell isolation film I1a. A second source / drain contact CA12 may be formed on the first active area AR1 between the first gate electrode G1 and the second gate electrode G2. A third source / drain contact CA13 may be formed on the first active area AR1 between the second gate electrode G2 and the second cell isolation film I1b. A fourth source / drain contact CA14 may be formed on the second active area AR2 between the first gate electrode G1 and the first cell isolation film I1a. A fifth source / drain contact CA15 may be formed on the second active area AR2 between the first gate electrode G1 and the second gate electrode G2. A sixth source / drain contact CA16 may be formed on the second active area AR2 between the second gate electrode G2 and the second cell isolation film I1b.

[0051] The source / drain contacts CA11 to CA16 may be formed in an MOL (middle-of-line) process step, that is, the source / drain contacts CA11 to CA16 may be formed before a BEOL (back-end-of-line) process step.

[0052] The plurality of gate contacts CB11 and CB12 may be arranged to overlap with the first gate electrode G1 or the second gate electrode G2. Here, overlapping refers to overlapping in a direction Z that intersects the first direction X and the second direction Y. The plurality of gate contacts CB11 and CB12 may be connected to the first gate electrode G1 or the second gate electrode G2. For example, the first gate contact CB11 may be connected to and overlap with the first gate electrode G1, and the second gate contact CB12 may be connected to and overlap with the second gate electrode G2.

[0053] The gate contacts CB11 and CB12 may be formed in an MOL (middle of the line) process step, that is, the gate contacts CB11 and CB12 may be formed before a BEOL (back end of the line) process step.

[0054] The plurality of connection contacts CM11 to CM17 may be connected to some of the source / drain contacts CA11 to CA16 or some of the gate contacts CB11 and CB12, respectively. For example, the plurality of connection contacts CM11 to CM17 may be arranged to overlap with some of the source / drain contacts CA11 to CA16 or some of the gate contacts CB11 and CB12, respectively.

[0055] For example, the first connection contact CM11 may be connected to and overlap the first source / drain contact CA11. The second connection contact CM12 may be connected to and overlap the second source / drain contact CA12. The third connection contact CM13 may be connected to and overlap the third source / drain contact CA13. The fourth connection contact CM14 may be connected to and overlap the first gate contact CB11. The fifth connection contact CM15 may be connected to and overlap the second gate contact CB12. The sixth connection contact CM16 may be connected to and overlap the fourth source / drain contact CA14. The seventh connection contact CM17 may be connected to and overlap the sixth source / drain contact CA16.

[0056] The connection contacts CM11 to CM17 may be formed in the MOL process step. That is, the connection contacts CM11 to CM17 may be formed before the BEOL process step.

[0057] The first power supply line V DD and the second power supply line V SS They can be spaced apart from each other and extend in parallel. For example, the first power supply line V DD and the second power supply line V SS Each of the second power supply lines V SS The first power supply line V can be connected to the second direction Y DD In some embodiments, the first power supply line V DD and the second power supply line V SS may be formed over each of the first cell region CR1 and the first fill region FR1 .

[0058] The first power supply line V DD and the second power supply line V SS In some embodiments, the drain voltage may be applied to a first power supply line V DD , and the source voltage can be applied to the second power supply line V SS For example, although a positive (+) voltage may be applied to the first power supply line V DD , and a ground voltage or a negative (-) voltage may be applied to the second power supply line V SS , but the present disclosure is not limited thereto.

[0059] In some embodiments, the first power supply line V DD It can be connected to some of the source / drain contacts CA11 to CA16. For example, at least a portion of the first connection contact CM11 can be arranged to be connected to the first power supply line V DD overlap, and may form a connection between the first connection contact CM11 and the first power supply line VDD Therefore, the first source / drain contact CA11 can be connected to the first power supply line V DD .

[0060] In some embodiments, the second power supply line V SS The sixth connection contact CM16 may be connected to some other source / drain contacts among the source / drain contacts CA11 to CA16. For example, at least a portion of the sixth connection contact CM16 may be arranged to be connected to the second power supply line V SS overlap, and can form a connection between the sixth connection contact CM16 and the second power supply line V SS Therefore, the fourth source / drain contact CA14 can be connected to the second power supply line V SS .

[0061] The first power supply line V DD and the second power supply line V SS It can be formed in the BEOL process step. In some embodiments, the first power line V DD and the second power supply line V SS The first power supply line V may be formed at the same routing level as the first wiring lines OW1, IW1, IW2, and CW1 to be described below. DD and the second power supply line V SS It can be routed at a first wiring level M1 which will be described below.

[0062] Each of the plurality of first wiring lines OW1, IW1, IW2, and CW1 may extend in the first direction X to overlap with some of the source / drain contacts CA11 to CA16 or some of the gate contacts CB11 and CB12. For example, the plurality of first wiring lines OW1, IW1, IW2, and CW1 may be routed to overlap with some of the source / drain contacts CA11 to CA16 or some of the gate contacts CB11 and CB12, respectively.

[0063] A plurality of first wiring lines OW1, IW1, IW2, and CW1 may be laid on the first power supply line V DD With the second power supply line V SS For example, the wiring area RA may be defined between the first power supply line V DD With the second power supply line V SS For example, the first wiring region I to the fourth wiring region IV sequentially arranged along the second direction Y can be formed in the first power supply line V DD With the second power supply line V SSThe corresponding first wiring lines OW1, IW1, IW2, and CW1 may be routed in one of the first to fourth wiring regions I to IV.

[0064] For example, the first output line OW1 may be arranged in the first wiring region I to overlap with the second connection contact CM12. Furthermore, a first wiring via VA1 may be formed to connect the second connection contact CM12 and the first output line OW1. Thus, the second source / drain contact CA12 may be connected to the first output line OW1.

[0065] The first input line IW1 may be arranged in the second wiring region II to overlap with the fourth connection contact CM14. Furthermore, a first wiring via VA1 may be formed to connect the fourth connection contact CM14 and the first input line IW1. Thus, the first gate contact CB11 may be connected to the first input line IW1. The first input line IW1 may function as an input line for providing a first input signal to the first cell region CR1.

[0066] The second input line IW2 may be arranged in the third wiring region III to overlap with the fifth connection contact CM15. Furthermore, a first wiring via VA1 may be formed connecting the fifth connection contact CM15 and the second input line IW2. Consequently, the second gate contact CB12 may be connected to the second input line IW2. The second input line IW2 may function as an input line for providing a second input signal to the first cell region CR1.

[0067] The first connection wire CW1 may be arranged in the fourth wiring region IV to overlap with the seventh connection contact CM17. Furthermore, a first wiring via VA1 may be formed to connect the seventh connection contact CM17 and the first connection wire CW1. Thus, the sixth source / drain contact CA16 may be connected to the first connection wire CW1. The first connection wire CW1 may function as an output wire for providing an output signal of the first cell region CR1.

[0068] The first wiring lines OW1, IW1, IW2, and CW1 may be formed during a back-end (BEOL) process. The first wiring lines OW1, IW1, IW2, and CW1 may be formed at the same wiring level. For example, the first wiring lines OW1, IW1, IW2, and CW1 may be arranged at a first wiring level M1. In some embodiments, the first wiring level M1 may be the lowest wiring level among the lines formed during the back-end (BEOL) process.

[0069] The second wiring line DW1 may extend in the second direction Y and be connected to some of the first wiring lines OW1, IW1, IW2, and CW1. For example, the second wiring line DW1 may be routed to overlap with some of the first wiring lines OW1, IW1, IW2, and CW1.

[0070] For example, the second wiring line DW1 may extend in the second direction Y to overlap with the first output line OW1 and the first connection line CW1. Furthermore, a second wiring via VB1 connecting the first output line OW1 and the second wiring line DW1, as well as a second wiring via VB1 connecting the first connection line CW1 and the second wiring line DW1, may be formed. Thus, the second source / drain contact CA12 may be connected to the sixth source / drain contact CA16. Furthermore, the first connection line CW1 (and the second wiring line DW1) may function as an output line for providing output signals of the first cell region CR1.

[0071] The second wiring line DW1 may be formed in a BEOL process step. The second wiring line DW1 may be formed at a higher level than the first wiring lines OW1, IW1, IW2, and CW1. For example, the second wiring line DW1 may be arranged at a second wiring level M2 that is higher than the first wiring level M1.

[0072] The first filling line FW1 may be arranged in the first filling region FR1 (e.g., may be confined to the first filling region FR1). For example, the first filling line FW1 may be interposed between the second cell isolation film I1b and the third cell isolation film I1c. The first filling line FW1 may extend in the second direction Y and be connected to some of the first wiring lines OW1, IW1, IW2, and CW1. For example, the first filling line FW1 may extend in the second direction Y to overlap with the first connection line CW1.

[0073] The first filling line FW1 may be formed at the same level as or lower than the first wiring lines OW1, IW1, IW2, and CW1. For example, the first filling line FW1 may be arranged at a level lower than the first wiring level M1.

[0074] The first wiring lines OW1, IW1, IW2, and CW1 of the first cell region CR1 can be routed to other cell regions via the first filling line FW1. For example, the first filling line FW1 may extend in the second direction Y above the third wiring region III and the fourth wiring region IV. Furthermore, a second connection line CW2 connected to the first filling line FW1 may be formed in the third wiring region III. Thus, the first cell region CR1 can provide output signals to other cell regions via the first filling line FW1 and the second connection line CW2.

[0075] although Figure 1 The second connection line CW2 is shown as being arranged only in the third wiring region III, but this is merely an example. For example, the second connection line CW2 may be arranged in the first wiring region I or the second wiring region II. Thus, the output signal of the first cell region CR1 may be provided to other cell regions in each wiring region.

[0076] although Figure 1 The first fill line FW1 is shown connected only to the first connection line CW1 of the first cell region CR1, but this is merely an example. For example, the first fill line FW1 may be connected to the first input line IW1 or the second input line IW2 of the first cell region CR1. In this case, the first cell region CR1 can receive an input signal from another cell region via the first fill line FW1 and the second connection line CW2.

[0077] In some embodiments, the second connection wire CW2 may be formed at the same wiring level as the first wiring wires OW1, IW1, IW2, and CW1. For example, the second connection wire CW2 may be arranged at the first wiring level M1.

[0078] In some embodiments, the first filling line FW1 may include a filling contact Fa, a first filling via Fb, and a second filling via Fc. The filling contact Fa may extend in the second direction Y to overlap the first connecting line CW1. The first filling via Fb may connect the first connecting line CW1 and the first filling line FW1. The second filling via Fc may connect the first filling line FW1 and the second connecting line CW2. Figures 2 to 6 The filling contacts Fa, the first filling vias Fb, and the second filling vias Fc will be described in more detail in the description of FIG.

[0079] Figure 2 is a top view illustrating a semiconductor device according to some embodiments. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA. Figure 4 It is along Figure 2 A cross-sectional view taken along line BB. Figure 5 It is along Figure 2 A cross-sectional view taken along line CC. Figure 6 It is along Figure 2 A cross-sectional view taken along line DD.

[0080] Figures 2 to 6 The semiconductor device shown is used Figure 1 For the sake of convenience, the above-mentioned semiconductor device may be briefly described or omitted. Figure 1 Repeating portion of the description.

[0081] Reference Figures 2 to 6 , a semiconductor device according to some embodiments may be formed on a substrate 100 .

[0082] The substrate 100 may be bulk silicon or SOI (silicon on insulator). Alternatively, the substrate 100 may be a silicon substrate, or may include, but is not limited to, other materials such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0083] The substrate 100 may include a first active region AR1 and a second active region AR2. For ease of explanation, the first active region AR1 is a PFET region and the second active region AR2 is an NFET region.

[0084] In some embodiments, the first active region AR1 and the second active region AR2 may be isolated by an element isolation film I2. Figure 4 and Figure 5 As shown, the element isolation film I2 may extend in the first direction X to isolate the first active region AR1 and the second active region AR2.

[0085] A plurality of active patterns F1 to F4 may be formed on the substrate 100. For example, the first active pattern F1 and the second active pattern F2 may be formed on the first active region AR1, and the third active pattern F3 and the fourth active pattern F4 may be formed on the second active region AR2. In some embodiments, each of the active patterns F1 to F4 may include a fin pattern protruding from the upper surface of the substrate 100.

[0086] The first to fourth active patterns F1 to F4 may be spaced apart from each other and extend side by side. For example, the first to fourth active patterns F1 to F4 may each extend in the first direction X. Alternatively, the first to fourth active patterns F1 to F4 may be arranged side by side in the second direction Y. In some embodiments, the first to fourth active patterns F1 to F4 may be formed over both the first cell region CR1 and the first fill region FR1.

[0087] like Figure 3 and Figure 4 As shown, in some embodiments, the first cell isolation film I1a, the second cell isolation film I1b, and the third cell isolation film I1c may intersect the first to fourth active patterns F1 to F4. The first cell isolation film I1a and the second cell isolation film I1b may define a first cell region CR1 across the first to fourth active patterns F1 to F4. The second cell isolation film I1b and the third cell isolation film I1c may define a first filling region FR1 across the first to fourth active patterns F1 to F4.

[0088] A field insulating film 105 may be formed on the substrate 100. In some embodiments, the field insulating film 105 may surround a portion (eg, a lower portion) of the side surfaces of the first to fourth active patterns F1 to F4. Figures 4 to 6 As shown, portions (eg, upper portions of side surfaces) of the first to fourth active patterns F1 to F4 may protrude upward from the field insulating film 105 .

[0089] The field insulating film 105 may include, for example but not limited to, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0090] The first gate electrode G1 and the second gate electrode G2 may intersect each of the first to fourth active patterns F1 to F4. The first gate electrode G1 and the second gate electrode G2 may each include a gate conductive film 130. The gate conductive film 130 may include, for example, but not limited to, at least one of the following: titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), and combinations thereof. The gate conductive film 130 may include, for example, silicon or silicon germanium in addition to metal.

[0091] Although the gate conductive film 130 is formed as a single film, the present disclosure is not limited thereto. Unlike the example shown, the gate conductive film 130 can be formed by stacking multiple conductive materials. For example, the gate conductive film 130 may include a work function adjustment film that adjusts the work function and a filling conductive film that fills the space formed by the work function adjustment film. The work function adjustment film may include, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), and combinations thereof. The filling conductive film may include, for example, W or Al. The gate conductive film 130 may be formed by, for example, but not limited to, a replacement process.

[0092] The gate dielectric film 120 may be interposed between the first to fourth active patterns F1 to F4 and the gate conductive film 130. For example, the gate dielectric film 120 may extend along the sidewalls and bottom surface of the gate conductive film 130. However, the present disclosure is not limited thereto, and the gate dielectric film 120 may extend only along the bottom surface of the gate conductive film 130.

[0093] In some embodiments, a portion of the gate dielectric film 120 may be interposed between the field insulating film 105 and the gate conductive film 130. For example, Figure 4 As shown, the gate dielectric film 120 may also extend along the upper surface of the field insulating film 105 .

[0094] The gate dielectric film 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, but is not limited to, hafnium oxide.

[0095] The gate spacer 140 may be formed on the substrate 100 and the field insulating film 105. The gate spacer 140 may extend along both sides (e.g., opposite sides) of the gate conductive film 130. For example, the gate spacer 140 may extend in the second direction Y and intersect the first to fourth active patterns F1 to F4.

[0096] The gate spacer 140 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0097] The gate capping pattern 150 may extend along the upper surface of the gate conductive film 130. For example, the gate capping pattern 150 may extend in the second direction Y to cover the upper surface of the gate conductive film 130.

[0098] The first source / drain region 160 may be formed on the first active region AR1. For example, the first source / drain region 160 may be formed in the first active pattern F1 and the second active pattern F2 on both sides (e.g., opposite sides) of the gate conductive film 130. The first source / drain region 160 may be separated from the gate conductive film 130 by the gate spacer 140.

[0099] The second source / drain region 260 may be formed on the second active region AR2. For example, the second source / drain region 260 may be formed in the third active pattern F3 and the fourth active pattern F4 on both sides (e.g., opposite sides) of the gate conductive film 130. The second source / drain region 260 may be separated from the gate conductive film 130 by the gate spacer 140.

[0100] The first and second source / drain regions 160 and 260 may include an epitaxial layer formed in each of the first to fourth active patterns F1 to F4 .

[0101] When the semiconductor device formed in the first active region AR1 is a PFET, the first source / drain region 160 may include p-type impurities or impurities for blocking / preventing diffusion of p-type impurities. For example, the first source / drain region 160 may include at least one of boron (B), carbon (C), indium (In), gallium (Ga), and Al, or a combination thereof.

[0102] When the semiconductor device formed in the second active region AR2 is an NFET, the second source / drain region 260 may include n-type impurities or impurities for blocking / preventing diffusion of n-type impurities. For example, the second source / drain region 260 may include at least one of phosphorus (P), antimony (Sb), arsenic (As), or a combination thereof.

[0103] Although the first source / drain region 160 and the second source / drain region 260 are each formed of a single film, the present disclosure is not limited thereto. For example, the first source / drain region 160 and the second source / drain region 260 may each be formed of a multilayer film containing impurities having different concentrations.

[0104] A plurality of interlayer insulating films 110, 210, 314, and 410 may be formed on the substrate 100. For example, first to seventh interlayer insulating films 110, 210, 314, 410, 510, 610, and 710 sequentially stacked may be formed on the substrate 100.

[0105] The first to seventh interlayer insulating films 110 , 210 , 314 , 410 , 510 , 610 , and 710 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0106] In some embodiments, a liner film 312 may be further formed between the second interlayer insulating film 210 and the third interlayer insulating film 314. The liner film 312 may protect / prevent the second interlayer insulating film 210 from being damaged during the process of forming the connection contacts CM11 to CM17. The liner film 312 may include, for example, but not limited to, at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, aluminum nitride (AlN), or a combination thereof. Although the liner film 312 is shown as a single film, the present disclosure is not limited thereto. Unlike the example shown, the liner film 312 may be formed by stacking multiple insulating materials.

[0107] The first interlayer insulating film 110 and the second interlayer insulating film 210 may be formed on the field insulating film 105, the first source / drain region 160, the second source / drain region 260, the gate spacer 140, and the gate capping pattern 150 (e.g., formed to cover the field insulating film 105, the first source / drain region 160, the second source / drain region 260, the gate spacer 140, and the gate capping pattern 150). For example, the first interlayer insulating film 110 may cover the upper surface of the field insulating film 105, the upper surface of the first source / drain region 160, the upper surface of the second source / drain region 260, and the side surfaces of the gate spacer 140. The second interlayer insulating film 210 may cover the upper surface of the gate capping pattern 150 and the upper surface of the first interlayer insulating film 110.

[0108] The source / drain contacts CA11 to CA16 penetrate the first interlayer insulating film 110 and the second interlayer insulating film 210 and may be connected to the first source / drain region 160 or the second source / drain region 260. For example, the first to third source / drain contacts CA11, CA12, and CA13 may be connected to the first source / drain region 160, and the fourth to sixth source / drain contacts CA14, CA15, and CA16 may be connected to the second source / drain region 260.

[0109] The gate contacts CB11 and CB12 penetrate the gate capping pattern 150 and the second interlayer insulating film 210 and may be connected to the gate conductive film 130. For example, the first gate contact CB11 may be connected to the gate conductive film 130 of the first gate electrode G1, and the second gate contact CB12 may be connected to the gate conductive film 130 of the second gate electrode G2.

[0110] In some embodiments, the upper surfaces of the source / drain contacts CA11 to CA16 and the upper surfaces of the gate contacts CB11 and CB12 may be coplanar. Figures 3 to 6 As shown, upper surfaces of the source / drain contacts CA11 to CA16 and upper surfaces of the gate contacts CB11 and CB12 may be located in the same plane as an upper surface of the second interlayer insulating film 210 .

[0111] Connection contacts CM11 to CM17 penetrate the liner film 312 and the third interlayer insulating film 314 and can be connected to the source / drain contacts CA11 to CA16 or the gate contacts CB11 and CB12. For example, the first connection contact CM11 can contact the upper surface of the first source / drain contact CA11. The second connection contact CM12 can contact the upper surface of the second source / drain contact CA12. The third connection contact CM13 can contact the upper surface of the third source / drain contact CA13. The fourth connection contact CM14 can contact the upper surface of the first gate contact CB11. The fifth connection contact CM15 can contact the upper surface of the second gate contact CB12. The sixth connection contact CM16 can contact the upper surface of the fourth source / drain contact CA14. The seventh connection contact CM17 can contact the upper surface of the sixth source / drain contact CA16.

[0112] The connection contacts CM11 to CM17 may be arranged at the same level as one another. As used herein, the expression "arranged at the same level" means that the connection contacts are formed at the same height relative to the upper surface of the substrate 100. For example, the upper surfaces of the connection contacts CM11 to CM17 may be arranged on the same plane as the upper surface of the third interlayer insulating film 314.

[0113] Each first wiring via VA1 penetrates the fourth interlayer insulating film 410 and may be connected to some of the connection contacts CM11 to CM17. For example, the first wiring via VA1 may be connected to upper surfaces of some of the connection contacts CM11 to CM17.

[0114] The first wiring lines OW1, IW1, IW2, and CW1 may each extend in the first direction X. The first wiring lines OW1, IW1, IW2, and CW1 may be arranged at a higher level than the source / drain contacts CA11 to CA16, the gate contacts CB11 and CB12, and the connection contacts CM11 to CM17. For example, the upper surfaces of the first wiring lines OW1, IW1, IW2, and CW1 may be formed to be higher than the upper surfaces of the source / drain contacts CA11 to CA16, the upper surfaces of the gate contacts CB11 and CB12, and the upper surfaces of the connection contacts CM11 to CM17.

[0115] In some embodiments, the first wiring lines OW1, IW1, IW2, and CW1 are all connected to the upper surface of the first wiring via VA1 and may be connected to some of the connection contacts CM11 to CM17. For example, the first output line OW1 may be connected to the second connection contact CM12. The first input line IW1 may be connected to the fourth connection contact CM14. The second input line IW2 may be connected to the fifth connection contact CM15. The first connection line CW1 may be connected to the seventh connection contact CM17.

[0116] The first power supply line V DD and the second power supply line V SS The first power supply lines V DD and the second power supply line V SS The first power supply line V may be arranged at a higher level than the source / drain contacts CA11 to CA16, the gate contacts CB11 and CB12, and the connection contacts CM11 to CM17. DD The upper surface of the second power supply line V SS The upper surface of may be located on the same plane as upper surfaces of the first wiring lines OW1 , IW1 , IW2 , and CW1 .

[0117] In some embodiments, the first power supply line V DD and the second power supply line V SS is connected to the upper surface of the first wiring via VA1 and may be connected to some other portion of the connection contacts CM11 to CM17. For example, the first power supply line V DD Can be connected to the first connection contact CM11. The second power supply line V SS It may be connected to the sixth connection contact CM16 .

[0118] The second wiring via VB1 penetrates the sixth interlayer insulating film 610 and can be connected to some of the first wiring lines OW1, IW1, IW2, and CW1. For example, the second wiring via VB1 can be connected to the upper surface of some of the first wiring lines WOW1, IW1, IW2, and CW1, respectively.

[0119] The second wiring line DW1 may extend in the second direction Y. The second wiring line DW1 may be arranged at a higher level than the first wiring lines OW1, IW1, IW2, and CW1. For example, the upper surface of the second wiring line DW1 may be formed to be higher than the upper surfaces of the first wiring lines OW1, IW1, IW2, and CW1.

[0120] In some embodiments, the second wiring lines DW1 are connected to the upper surface of the second wiring via VB1 and can be connected to some of the first wiring lines OW1, IW1, IW2, and CW1. For example, the second wiring lines DW1 can be connected to the first output line OW1 and the first connection line CW1.

[0121] The first filling line FW1 may be interposed between the second cell isolation film I1b and the third cell isolation film I1c. The first filling line FW1 may extend in the second direction Y to connect the first connection line CW1 and the second connection line CW2. The first filling line FW1 may be arranged at a lower level than the first wiring lines OW1, IW1, IW2, and CW1. For example, the upper surface of the first filling line FW1 may be formed to be the same as or lower than the upper surfaces of the first wiring lines OW1, IW1, IW2, and CW1.

[0122] In some embodiments, the first filling line FW1 may include a filling contact Fa, a first filling via Fb, and a second filling via Fc.

[0123] The filling contacts Fa extend in the second direction Y and may be connected to the first and second connection lines CW1 and CW2. In some embodiments, the filling contacts Fa may be arranged at the same level as the connection contacts CM11 to CM17. Figure 6 As shown, the upper surface of the filling contact Fa may be located on the same plane as the upper surfaces of the connection contacts CM11 to CM17 .

[0124] For example, the first filling via Fb penetrates the fourth interlayer insulating film 410 and may be connected to the upper surface of the filling contact Fa, and the first connecting wire CW1 may be connected to the upper surface of the first filling via Fb.

[0125] The second filling via Fc may connect the first filling wire FW1 and the second connection wire CW2. For example, the second filling via Fc penetrates the fourth interlayer insulating film 410 and may be connected to the upper surface of the filling contact Fa, and the second connection wire CW2 may be connected to the upper surface of the second filling via Fc.

[0126] In some embodiments, the first filling via Fb and the second filling via Fc may be arranged at the same level as the first wiring via VA1. For example, the upper surface of the first filling via Fb and the upper surface of the second filling via Fc may be located on the same plane as the upper surface of the first wiring via VA1.

[0127] In some embodiments, the source / drain contacts CA11 to CA16 and the gate contacts CB11 and CB12 may each include a first barrier film 220 and a first filling film 222. The first barrier film 220 may extend along the upper surface of the first source / drain region 160, the upper surface of the second source / drain region 260, the side surface of the first interlayer insulating film 110, and the side surface of the second interlayer insulating film 210. The first filling film 222 may be located in a space formed by the first barrier film 220 (e.g., may fill the space).

[0128] In some embodiments, the connection contacts CM11 to CM17 and the filling contact Fa may each include a second barrier film 320 and a second filling film 322. The second barrier film 320 may extend along the upper surfaces of the source / drain contacts CA11 to CA16, the upper surfaces of the gate contacts CB11 and CB12, the side surfaces of the liner film 312, and the side surfaces of the third interlayer insulating film 314. The second filling film 322 may be located in a space formed by the second barrier film 320 (e.g., may fill the space).

[0129] In some embodiments, the first wiring via VA1, the first filling via Fb, and the second filling via Fc may each include a third barrier film 420 and a third filling film 422. The third barrier film 420 may extend along the upper surface of the connection contacts CM11 to CM17 and the side surface of the fourth interlayer insulating film 410. The third filling film 422 may be located in a space formed by the third barrier film 420 (e.g., may fill the space).

[0130] In some embodiments, the first wiring lines OW1, IW1, IW2 and CW1, the first power supply line V DD and the second power supply line V SS Each may include a fourth barrier film 520 and a fourth filling film 522. The fourth barrier film 520 may extend along the upper surface of the first wiring via VA1, the upper surface of the fourth interlayer insulating film 410, and the side surface of the fifth interlayer insulating film 510. The fourth filling film 522 may be located in a space formed by the fourth barrier film 520 (e.g., may fill the space).

[0131] In some embodiments, each of the second wiring vias VB1 may include a fifth barrier film 620 and a fifth filling film 622. The fifth barrier film 620 may extend along the upper surface of the first wiring lines OW1, IW1, IW2, and CW1 and the side surface of the sixth interlayer insulating film 610. The fifth filling film 622 may be located in the space formed by the fifth barrier film 620 (e.g., may fill the space).

[0132] In some embodiments, the second wiring line DW1 may include a sixth barrier film 720 and a sixth filling film 722. The sixth barrier film 720 may extend along the upper surface of the second wiring via VB1, the upper surface of the sixth interlayer insulating film 610, and the side surface of the seventh interlayer insulating film 710. The sixth filling film 722 may be located in a space formed by the sixth barrier film 720 (e.g., may fill the space).

[0133] The first to sixth barrier films 220, 320, 420, 520, 620, and 720 may include a metal or a metal nitride to respectively block / prevent the diffusion of the first to sixth filling films 222, 322, 422, 522, 622, and 722. For example, the first to sixth barrier films 220, 320, 420, 520, 620, and 720 may include, but are not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof.

[0134] The first to sixth filling films 222 , 322 , 422 , 522 , 622 , and 722 may include, but are not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and alloys thereof.

[0135] The first wiring via VA1, the first wiring lines OW1, IW1, IW2 and CW1, the first power supply line V DD , the second power supply line V SS , the second wiring via VB1 and the second wiring line DW1 can be formed by, for example, a single damascene process, but is not limited to being formed by a single damascene process. For example, in some embodiments, the first wiring via VA1, the first wiring lines OW1, IW1, IW2 and CW1, the first power supply line V DD , the second power supply line V SS The second wiring via VB1 and the second wiring line DW1 may be formed by, for example, a dual damascene process or another wiring process.

[0136] Figure 7 and Figure 8 is a cross-sectional view for illustrating a semiconductor device according to some embodiments. Figures 1 to 6 The contents of the description are repeated. For reference, Figure 7 It is along Figure 2 A cross-sectional view taken along line AA of FIG. Figure 8 It is along Figure 2 A cross-sectional view taken along line BB.

[0137] Reference Figure 7 and Figure 8In the semiconductor device according to some embodiments, each of the first to fourth active patterns F1 to F4 includes a plurality of line patterns 114 , 116 , and 118 .

[0138] For example, the first to fourth active patterns F1 to F4 may include first to third line patterns 114, 116, and 118 sequentially stacked on the substrate 100 and spaced apart from each other. For example, the first line pattern 114 may be spaced apart from the substrate 100 in the third direction Z, the second line pattern 116 may be spaced apart from the first line pattern 114 in the third direction Z, and the third line pattern 118 may be spaced apart from the second line pattern 116 in the third direction Z.

[0139] The first to third line patterns 114, 116 and 118 may extend in the first direction X. In addition, the first to third line patterns 114, 116 and 118 may penetrate the first gate electrode G1 and the second gate electrode G2. Figure 8 As shown, the first gate electrode G1 and the second gate electrode G2 may surround outer peripheral surfaces of the first to third line patterns 114 , 116 , and 118 .

[0140] exist Figure 8 , although the cross sections of the first to third line patterns 114, 116, and 118 are each shown as a rectangle, this is merely an example. For example, the cross sections of the first to third line patterns 114, 116, and 118 may each be another polygon or a circle.

[0141] In some embodiments, each of the first to fourth active patterns F1 to F4 may further include a fin pattern 112 protruding from the upper surface of the substrate 100 and extending in the first direction X. For example, a first line pattern 114 may be disposed on the fin pattern 112 .

[0142] Figure 9 is a layout diagram for illustrating a semiconductor device according to some embodiments. Figure 10 It is along Figure 9 For the sake of convenience, the above-mentioned Figures 1 to 8 Repeating portion of the description.

[0143] Reference Figure 9 and Figure 10 , in the semiconductor device according to some embodiments, the first filling line FW1 includes a third filling via Fd.

[0144] The third filling via Fd extends in the second direction Y and may be connected to the first and second connection wirings CW1 and CW2 . For example, the third filling via Fd may be connected to lower surfaces of the first and second connection wirings CW1 and CW2 .

[0145] In some embodiments, the third filling via Fd may be arranged at the same level as the first wiring via VA1. For example, the upper surface of the third filling via Fd may be located on the same plane as the upper surface of the first wiring via VA1. In some embodiments, the third filling via Fd may include a third barrier film 420 and a third filling film 422.

[0146] Figure 11 is a layout diagram for illustrating a semiconductor device according to some embodiments. Figure 12 It is along Figure 11 For the sake of convenience, the above-mentioned Figures 1 to 10 Repeating portion of the description.

[0147] Reference Figure 9 and Figure 10 , in the semiconductor device according to some embodiments, the first filling line FW1 includes a filling wiring line Fe.

[0148] The filling wiring line Fe extends in the second direction Y and may be connected to the first and second connection lines CW1 and CW2 . For example, the filling wiring line Fe may be connected to side surfaces of the first and second connection lines CW1 and CW2 .

[0149] In some embodiments, the filling wiring line Fe can be arranged at the same level as the first wiring lines OW1, IW1, IW2, and CW1. For example, the upper surface of the filling wiring line Fe can be located on the same plane as the upper surfaces of the first wiring lines OW1, IW1, IW2, and CW1. In some embodiments, the filling wiring line Fe can include a fourth barrier film 520 and a fourth filling film 522. In some embodiments, the filling wiring line Fe can be formed integrally with the first connecting line CW1 and the second connecting line CW2.

[0150] In the following, reference will be made to Figures 1 to 13 The function of the first filling line FW1 of the semiconductor device according to some embodiments is described.

[0151] Figure 13 is an example layout diagram for explaining the function of the filling circuit of the semiconductor device according to some embodiments. Figures 1 to 12 Repeating portion of the description.

[0152] Reference Figure 13 , the wiring line (eg, the first connection wire CW1 ) of the first cell region CR1 may be routed to another cell region through the first filling wire FW1 .

[0153] For example, the first connection line CW1 can be connected to the wiring line of another cell region (for example, the second connection line CW2) through the first filling line FW1. As a result, the first cell region CR1 provides an output signal to the other cell region through the first filling line FW1 and the second connection line CW2, or can receive an input signal from the other cell region.

[0154] As the internal structures of semiconductor devices become increasingly complex and highly integrated, the use of high-level wiring for wiring of semiconductor devices is increasing. However, excessive use of high-level wiring leads to power consumption and loss of PnR resources, which causes the performance and yield of semiconductor devices to decline.

[0155] However, semiconductor devices according to some embodiments can use first filler wires FW1 to reduce the use of high-level wiring. As described above, since the first filler wires FW1 can be formed in the first filler region FR1, which is a dummy cell region that fills the empty space between cell regions, no additional space is required for wiring the semiconductor device. In addition, since the first filler wires FW1 can be arranged at a level lower than the first wiring level M1, signals of the first cell region CR1 can be routed without using additional high-level wiring (e.g., second wiring wires DW1 arranged at the second wiring level M2). This can provide a semiconductor device with reduced power consumption and PnR resource loss.

[0156] In the following, reference will be made to Figures 1 to 27 Semiconductor devices according to some embodiments are described.

[0157] Figures 14 to 17 1 and 2 are diagrams illustrating various layouts of semiconductor devices according to some embodiments. Figure 18 is an example layout diagram for explaining the function of the filling circuit of the semiconductor device according to some embodiments. Figures 1 to 13 Repeating portion of the description.

[0158] Reference Figures 14 to 17 , the semiconductor device according to some embodiments further includes a second cell region CR2 .

[0159] The standard cells provided by the cell library may be disposed in the second cell region CR2. Figures 14 to 17In the embodiment, the standard cell to be provided to the second cell region CR2 may be a NAND cell. However, this is merely an example, and needless to say, the standard cell provided in the second cell region CR2 may be various cells, for example, a NOR cell or an XOR cell.

[0160] The first filling region FR1 may be interposed between the first cell region CR1 and the second cell region CR2. For example, the first cell region CR1, the first filling region FR1, and the second cell region CR2 may be sequentially arranged along the first direction X.

[0161] In some embodiments, the second cell region CR2 may be defined by a third cell isolation film I1c and a fourth cell isolation film I1d arranged along the first direction X. For example, the third cell isolation film I1c and the fourth cell isolation film I1d may extend side by side in the second direction Y. The second cell region CR2 may be defined between the third cell isolation film I1c and the fourth cell isolation film Idd. The third cell isolation film I1c may isolate the first fill region FR1 from the second cell region CR2.

[0162] According to some embodiments, the semiconductor device may include a third gate electrode G3, a fourth gate electrode G4, a seventh source / drain contact CA21 to a twelfth source / drain contact CA26, a third gate contact CB21 and a fourth gate contact CB22, an eighth connection contact CM21 to a fifteenth connection contact CM27, a second output line OW2, a third output line OW3, a third input line IW3 and a third wiring line DW2.

[0163] The third gate electrode G3 and the fourth gate electrode G4 may be disposed in the second cell region CR2. For example, the third gate electrode G3 and the fourth gate electrode G4 may be interposed between the third cell isolation film I1c and the fourth cell isolation film I1d.

[0164] The seventh to twelfth source / drain contacts CA21 to CA26 may be arranged on both sides (e.g., opposite sides) of the third gate electrode G3 or the fourth gate electrode G4. The seventh to twelfth source / drain contacts CA21 to CA26 may be connected to the source / drain regions of the first active area AR1 or the second active area AR2. Since the arrangement of the seventh to twelfth source / drain contacts CA21 to CA26 may be similar to that of the first to sixth source / drain contacts CA11 to CA16, a detailed description thereof will not be provided below.

[0165] The third gate contact CB21 and the fourth gate contact CB22 may be arranged to overlap with the third gate electrode G3 or the fourth gate electrode G4. For example, the third gate contact CB21 may be connected to overlap with the third gate electrode G3, and the fourth gate contact CB22 may be connected to overlap with the fourth gate electrode G4. Since the arrangement of the third gate contact CB21 and the fourth gate contact CB22 may be similar to the arrangement of the first gate contact CB11 and the second gate contact CB12, a detailed description thereof will not be provided below.

[0166] The eighth to fourteenth connection contacts CM21 to CM27 may be connected to some of the source / drain contacts of the seventh to twelfth source / drain contacts CA21 to CA26 or some of the gate contacts of the third and fourth gate contacts CB21 and CB22, respectively. Since the arrangement of the eighth to fourteenth connection contacts CM21 to CM27 may be similar to that of the first to seventh connection contacts CM11 to CM17, a detailed description thereof will not be provided below.

[0167] The second output line OW2 may be arranged in the first wiring region I to overlap with the ninth connection contact CM22. In addition, a first wiring via VA1 may be formed to connect the ninth connection contact CM22 and the second output line OW2. Thus, the eighth source / drain contact CA22 may be connected to the second output line OW2.

[0168] The third input line IW3 may be arranged in the second wiring region II to overlap with the eleventh connection contact CM24. Furthermore, a first wiring path VA2 may be formed connecting the eleventh connection contact CM24 and the third input line IW3. Thus, the third gate contact CB21 may be connected to the third input line IW3. The third input line IW3 may function as an input line for providing a first input signal to the second cell region CR2.

[0169] The second connection line CW2 may be arranged in the third wiring region III to overlap with the twelfth connection contact CM25. Furthermore, a first wiring path VA2 may be formed connecting the twelfth connection contact CM25 and the second connection line CW2. Thus, the fourth gate contact CB22 may be connected to the second connection line CW2. The second connection line CW2 may function as an input line for providing a second input signal to the second cell region CR2.

[0170] The third output line OW3 may be arranged in the fourth wiring region IV to overlap with the fourteenth connection contact CM27. Furthermore, a first wiring via VA2 may be formed connecting the fourteenth connection contact CM27 and the third output line OW3. Thus, the twelfth source / drain contact CA26 may be connected to the third output line OW3.

[0171] The third input line IW3, the second connection line CW2, the second output line OW2, and the third output line OW3 can be formed in a BEOL process step. The third input line IW3, the second connection line CW2, the second output line OW2, and the third output line OW3 can be formed at the same routing level. For example, the third input line IW3, the second connection line CW2, the second output line OW2, and the third output line OW3 can be arranged at the first routing level M1.

[0172] The third wiring line DW2 may extend in the second direction Y to overlap with the second output line OW2 and the third output line OW3. Furthermore, a second wiring via VB2 connecting the second output line OW2 and the third wiring line DW2 and a second wiring via VB2 connecting the third output line OW3 and the third wiring line DW2 may be formed. Thus, the eighth source / drain contact CA22 may be connected to the twelfth source / drain contact CA26.

[0173] The third wiring line DW2 may be formed during a BEOL process step. The third wiring line DW2 may be formed at a higher level than the third input line IW3, the second connection line CW2, the second output line OW2, and the third output line OW3. For example, the third wiring line DW2 may be arranged at the second wiring level M2.

[0174] The first filling wire FW1 may connect the first connection wire CW1 and the second connection wire CW2 , thereby enabling the output signal of the first cell region CR1 to be provided as the second input signal of the second cell region CR2 .

[0175] Reference Figure 14 In the semiconductor device according to some embodiments, the first filling line FW1 may include the above Figures 1 to 6 The filling contact Fa, the first filling via Fb, and the second filling via Fc explained in the description of FIG.

[0176] Reference Figure 15 In the semiconductor device according to some embodiments, the first filling line FW1 may include the above Figure 9 and Figure 10 The third filling path Fd described in the description of .

[0177] Reference Figure 16 In the semiconductor device according to some embodiments, the first filling line FW1 may include the above Figure 11 and Figure 12 The filling wiring line Fe is described in the description.

[0178] Reference Figure 17In the semiconductor device according to some embodiments, the second connection wire CW2 may be routed in the second wiring region II.

[0179] For example, the second connection line CW2 may be arranged in the second wiring region II to overlap with the eleventh connection contact CM24. In addition, a first wiring path VA2 may be formed connecting the eleventh connection contact CM24 and the second connection line CW2. Thus, the third gate contact CB21 may be connected to the second connection line CW2.

[0180] In some embodiments, the third input line IW3 may be arranged in the third wiring region III to overlap with the twelfth connection contact CM25. In addition, a first wiring path VA2 may be formed to connect the twelfth connection contact CM25 and the third input line IW3. Thus, the fourth gate contact CB22 may be connected to the third input line IW3.

[0181] In some embodiments, the first filling wire FW1 may extend over the second to fourth wiring regions II to IV in the second direction Y. Thus, the first filling wire FW1 may be connected to the second connection wire CW2 in the second wiring region II.

[0182] Reference Figure 18 , the wiring lines (eg, the first connection wires CW1 ) of the first cell region CR1 may be routed to the second cell region CR2 through the first filling wires FW1 .

[0183] For example, the first connection line CW1 can be connected to the wiring line (e.g., the second connection line CW2) of the second cell region CR2 through the first filling line FW1. Therefore, the first cell region CR1 can provide an output signal to the second cell region CR2 through the first filling line FW1 and the second connection line CW2, or can receive an input signal from the second cell region CR2.

[0184] Figures 19 to 21 The various exemplary layout diagrams are used to illustrate the functions of the filling circuits of the semiconductor device according to some embodiments. Figures 1 to 18 Repeating portion of the description.

[0185] Reference Figure 19 , the semiconductor device according to some embodiments further includes a third cell region CR3 and a second filling region FR2 .

[0186] The standard cells provided by the cell library may be provided in the third cell region CR3. For example, various standard cells such as NAND cells, NOR cells, and XOR cells may be provided in the third cell region CR3. The second fill region FR2 may be a dummy cell region located in an empty space between cell regions where standard cells are provided (e.g., filling the empty space).

[0187] The second filling region FR2 may be interposed between the second cell region CR2 and the third cell region CR3. For example, the first cell region CR1, the first filling region FR1, the second cell region CR2, the second filling region FR2, and the third cell region CR3 may be sequentially arranged along the first direction X.

[0188] In some embodiments, the wiring lines (eg, third connection lines CW3 ) of the second cell region CR2 may be routed to the third cell region CR3 through the second filling lines FW2 .

[0189] For example, a second filling line FW2 extending in the second direction Y and connected to the third connection line CW3 may be formed in the second filling region FR2. The third connection line CW3 may be connected to a wiring line (e.g., a fourth connection line CW4) of the third cell region CR3 through the second filling line FW2. Therefore, the second cell region CR2 may provide an output signal to the third cell region CR3 through the second filling line FW2 and the fourth connection line CW4, or may receive an input signal from the third cell region CR3.

[0190] The second filling line FW2 can be formed at the same level as the first to fourth connecting lines CW1, CW2, CW3, and CW4, or at a lower level than the first to fourth connecting lines CW1, CW2, CW3, and CW4. For example, the second filling line FW2 can be arranged at a level lower than the first wiring level M1. Since the second filling line FW2 can be similar to the first filling line FW1, a detailed description thereof will not be provided below.

[0191] Reference Figure 20 , the semiconductor device according to some embodiments further includes a fourth cell region CR4 , a fifth cell region CR5 , and a third filling region FR3 .

[0192] The fourth cell region CR4 may be arranged together with the first cell region CR1 along the second direction Y. The fifth cell region CR5 may be arranged together with the second cell region CR2 along the second direction Y. Standard cells provided by the cell library may be provided in each of the fourth cell region CR4 and the fifth cell region CR5. As an example, various standard cells such as a NAND cell, a NOR cell, or an XOR cell may be provided in each of the fourth cell region CR4 and the fifth cell region CR5.

[0193] The third filling region FR3 may be between the fourth cell region CR4 and the fifth cell region CR5. For example, the fourth cell region CR4, the third filling region FR3, and the fifth cell region CR5 may be sequentially arranged along the first direction X. The third filling region FR3 may be a dummy cell region located in an empty space between cell regions where standard cells are provided (e.g., filling the empty space).

[0194] In some embodiments, the wiring lines (eg, the first connection wires CW1 ) of the first cell region CR1 may be routed to the fifth cell region CR5 through the first filling wires FW1 .

[0195] For example, the first filling line FW1 may extend over the first filling region FR1 and the third filling region FR3 in the second direction Y. The first connecting line CW1 may be connected to a wiring line (e.g., a fifth connecting line CW5) of the fifth cell region CR5 through the first filling line FW1. Therefore, the first cell region CR1 may provide an output signal to the fifth cell region CR5 through the first filling line FW1 and the fifth connecting line CW5, or may receive an input signal from the fifth cell region CR5.

[0196] Reference Figure 21 , the semiconductor device according to some embodiments further includes a fourth filling region FR4 .

[0197] The fourth filling region FR4 may be arranged along the first direction X1 together with the first filling region FR1. For example, the first cell region CR1, the first filling region FR1, and the fourth filling region FR4 may be arranged sequentially along the first direction X. In addition, the fourth filling region FR4 may be arranged along the second direction Y together with the fifth cell region CR5. The fourth filling region FR4 may be a dummy cell region located in an empty space between cell regions where standard cells are provided (e.g., filling the empty space).

[0198] In some embodiments, the wiring lines (eg, the first connection wires CW1 ) of the first cell region CR1 may be routed to the fifth cell region CR5 through the third filling wires FW3 .

[0199] For example, a third filling line FW3 extending in the second direction Y and connected to the fifth connection line CW5 may be formed in the fourth filling region FR4. Therefore, the first cell region CR1 may provide an output signal to the fifth cell region CR5 through the third filling line FW3 and the fifth connection line CW5, or may receive an input signal from the fifth cell region CR5.

[0200] The third filling line FW3 can be formed at the same level as or lower than the first to fifth connecting lines CW1, CW2, CW3, CW4, and CW5. For example, the third filling line FW3 can be arranged at a level lower than the first wiring level M1. Since the third filling line FW3 can be similar to the first filling line FW1, a detailed description thereof will not be provided below.

[0201] Figure 22 is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments.

[0202] Reference Figure 22 The computer system may include a central processing unit (CPU) 10, a working memory 30, an I / O device 50, and an auxiliary memory 70. Here, the computer system may be provided as a dedicated device for layout design of semiconductor devices according to some embodiments. In some embodiments, the computer system may also include various design and verification simulation programs.

[0203] The CPU 10 can execute software (applications, operating systems, device drivers) to be executed on the computer system. The CPU 10 can execute the operating system to be loaded into the working memory 30. The CPU 10 can execute various application programs to be driven based on the operating system. For example, the CPU 10 can execute the layout design tool 32, the placement and routing tool 34, and / or the optical proximity correction (OPC) tool 36 loaded into the working memory 30.

[0204] An operating system or application program may be loaded into the working memory 30. When the computer system is booted, based on a boot sequence, an operating system image (not shown) stored in the secondary memory 70 may be loaded into the working memory 30. The operating system may support overall input and output operations of the computer system.

[0205] A layout design tool 32 for layout design of a semiconductor device according to some embodiments may be loaded from the auxiliary memory 70 into the working memory 30. Subsequently, a placement and routing tool 34 for placing the designed standard cells, rearranging internal line patterns in the placed standard cells, and routing the placed standard cells may be loaded from the auxiliary memory 70 into the working memory 30. Subsequently, an optical proximity correction (OPC) tool 36 for performing an OPC on the designed layout data may be loaded from the auxiliary memory 70 into the working memory 30.

[0206] The I / O device 50 can control user input and output from the user interface device. For example, the I / O device 50 can be equipped with a keyboard and a monitor to receive information input from the user. The user can use the I / O device 50 to receive information about semiconductor regions and data paths whose operating characteristics need to be adjusted. In addition, the processing progress and processing results of the OPC tool 36 can be displayed through the I / O device 50.

[0207] The auxiliary memory 70 may be provided as a storage medium of the computer system and may store application programs, operating system images, and various data.

[0208] The system interconnector 90 may be a system bus for providing a network within the computer system. The CPU 10, the working memory 30, the I / O device 50, and the auxiliary memory 70 may be electrically connected to each other through the system interconnector 90 and may exchange data with each other.

[0209] Figure 23 is a flowchart for explaining a layout design method for a semiconductor device and a method for manufacturing a semiconductor device according to some embodiments.

[0210] Reference Figure 23 , you can use the above reference Figure 22 The computer system described is used to perform high-level design (high level design) of a semiconductor integrated circuit (S10). High-level design can mean describing the integrated circuit to be designed in a high-level language of a computer language. For example, a high-level language such as C language can be used for high-level design. The circuit designed by the high-level design can be expressed more specifically by register transfer level (RTL) coding or simulation. Subsequently, the code generated by the register transfer level coding is converted into a netlist and can be synthesized into an entire semiconductor component. The synthesized schematic circuit can be verified by a simulation tool, and adjustment processing can be performed based on the verification results.

[0211] Subsequently, a layout design (S20) for implementing a logic-completed semiconductor integrated circuit on a silicon substrate may be performed. For example, the layout design may be performed by referring to a schematic circuit synthesized in a high-level design or a netlist corresponding to the circuit. The layout design may include a wiring process for placing and connecting various standard cells provided from a cell library according to defined design rules.

[0212] Layout is a process used to define the shapes and dimensions of the patterns used to form transistors and metal lines actually formed on a silicon substrate. For example, to actually form an inverter circuit on a silicon substrate, layout patterns such as PFETs, NFETs, P-wells, N-wells, and gate electrodes, as well as the lines to be laid out thereon, are appropriately laid out.

[0213] Subsequently, wiring of the selected and laid-out standard cells may be performed. Specifically, a high-level height line (line pattern) may be laid out on the laid-out standard cells. By performing wiring, the laid-out standard cells may be connected to each other according to design.

[0214] After routing, layout verification can be performed to check whether there are any parts that violate the design rules. The items to be verified may include DRC (Design Rule Check), ERC (Electronic Rule Check), LVS (Layout Verification), etc.

[0215] Subsequently, an optical proximity correction (OPC) process (S30) may be performed. The layout pattern provided by the layout design may be implemented on the silicon substrate using a photolithography process. At this time, optical proximity correction may be a technique for correcting distortion phenomena that may occur in the photolithography process.

[0216] Subsequently, a photomask may be manufactured based on the layout changed by the optical proximity correction (S40).The photomask may be manufactured in such a manner that a layout pattern is drawn using, for example, a chrome film coated on a glass substrate.

[0217] Subsequently, the generated photomask can be used to manufacture a semiconductor element (S50). In the manufacturing process of the semiconductor element using the photomask, various types of exposure and etching processes can be repeated. Through such processes, the shape of the pattern formed during the layout design can be continuously formed on the silicon substrate.

[0218] Figures 24 to 27 The layout diagram for illustrating the layout design method of a semiconductor device according to some embodiments. Figures 1 to 23 Repeating portion of the description.

[0219] Reference Figure 24, the cell regions CR can be arranged according to the defined design rules. Various standard cells provided by the cell library can be arranged in each cell region CR. Since the cell regions CR have various sizes, an empty space ES can be formed between the arranged cell regions CR.

[0220] Then, refer to Figure 25 The filling region FR may be disposed in the empty space ES. The filling region FR may be a dummy cell region located in (eg, filling) the empty space ES between the cell regions CR where standard cells are disposed.

[0221] Reference Figures 26A to 26F , various cell layouts may be provided in the filling region FR according to the layout of the first connection wires CW1 and the second connection wires CW2 .

[0222] For example, the layout of the first connection line CW1 and the second connection line CW2 can be used to provide Figures 26A to 26F The unit layout. Figures 26A to 26F The various cell layouts shown are merely examples, and the present disclosure is not limited thereto. For example, it goes without saying that the shape and layout of the first filling wire FW1 can be further changed according to the layout of the first connection wire CW1 and the second connection wire CW2.

[0223] Reference Figure 27 , various filling lines FW can be laid out in the filling region FR.

[0224] Each filling line FW may be, for example, one of the first filling lines FW1 explained above in the description of Fig. 26. Therefore, a layout design method for a semiconductor device that reduces power consumption and PnR resource loss can be provided.

[0225] While the present invention has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined in the appended claims. It is therefore intended that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description as indicating the scope of the invention.

Claims

1. A semiconductor device comprising a first cell region and a filling region adjacent to each other in a first direction, the semiconductor device comprising: an active pattern extending in the first direction inside the first unit region; a gate electrode extending on the active pattern in a second direction intersecting the first direction; a gate contact located on an upper surface of the gate electrode and electrically connected to the upper surface of the gate electrode; a source / drain contact, the source / drain contact being located on and electrically connected to the source / drain region of the active pattern, the source / drain contact being adjacent to one side of the gate electrode; a connecting line extending in the first direction over the first cell region and the filling region and being located on and electrically connected to one of the gate contact or the source / drain contacts; and a filling line extending in the second direction inside the filling region and being located on and electrically connected to the connecting line, wherein the upper surface of the gate contact and the upper surface of the source / drain contacts are coplanar, and Wherein, the height of the upper surface of the filling line is equal to or lower than the height of the upper surface of the connecting line.

2. The semiconductor device according to claim 1, further comprising: a first connection contact located on the upper surface of the gate contact and electrically connected to the upper surface of the gate contact; a second connection contact located on the upper surface of the source / drain contact and electrically connected to the upper surface of the source / drain contact; and a wiring path located on one of the upper surfaces of the first connecting contact or the second connecting contact and electrically connected to the one of the upper surfaces of the first connecting contact or the second connecting contact, The connection line is located on an upper surface of the wiring via and is electrically connected to the upper surface of the wiring via.

3. The semiconductor device according to claim 2, wherein The filling line includes a filling contact, an upper surface of the filling contact being coplanar with the upper surfaces of the first connecting contact and the second connecting contact.

4. The semiconductor device according to claim 2, wherein The filling circuit includes a filling via, an upper surface of the filling via being coplanar with the upper surface of the routing via.

5. The semiconductor device according to claim 1, wherein The upper surface of the filling line is coplanar with the upper surface of the connecting line.

6. The semiconductor device according to claim 1, further comprising: a wiring path located on the upper surface of the connection line and electrically connected to the upper surface of the connection line; and A wiring line extends in the second direction and is located on an upper surface of the wiring via and electrically connected to the upper surface of the wiring via.

7. The semiconductor device according to claim 1, further comprising: a first cell isolation film extending in the second direction between the first cell region and the filling region; Wherein, the filling area includes a dummy cell area, and The filling line is limited to the dummy cell area.

8. The semiconductor device according to claim 7, further comprising: a second cell isolation film extending in the second direction to define the filling region, The filling region is located between the first cell isolation film and the second cell isolation film, and The first cell isolation film and the second cell isolation film are spaced apart from each other by one grid pitch.

9. The semiconductor device according to claim 1, wherein The active pattern includes a fin pattern protruding from an upper surface of a substrate.

10. The semiconductor device according to claim 1, wherein The active pattern includes a plurality of line patterns spaced apart from each other on a substrate.

11. A semiconductor device comprising a first unit region and a second unit region spaced apart from each other in a first direction, and a filling region located between the first unit region and the second unit region, the semiconductor device comprising: a gate electrode extending in a second direction intersecting with the first direction inside the first cell region; a source / drain contact adjacent to one side of the gate electrode; a first connecting line extending in the first direction over the first cell region and the filling region and being located on and electrically connected to the source / drain contacts; a second gate electrode extending in the second direction inside the second cell region; a gate contact located on an upper surface of the second gate and electrically connected to the upper surface of the second gate; a second connecting line extending in the first direction over the filling region and the second cell region and being located on and electrically connected to the gate contact; and a filling line extending in the second direction inside the filling region to connect the first connecting line and the second connecting line, wherein the first connecting line and the second connecting line are at a first wiring level, and The filling line includes a portion at a level lower than the first wiring level.

12. The semiconductor device according to claim 11, further comprising: a first connection contact located on an upper surface of the source / drain contact and electrically connected to the upper surface of the source / drain contact; a second connecting contact located on the upper surface of the gate contact and electrically connected to the upper surface of the gate contact; a first wiring pathway electrically connecting an upper surface of the first connecting contact and a lower surface of the first connecting line; and A second wiring path electrically connects an upper surface of the second connection contact and a lower surface of the second connection line.

13. The semiconductor device according to claim 12, wherein The filling circuit includes: a filling contact, the filling contact being at the same level as the first connecting contact and the second connecting contact; a first filling via located on a first portion of an upper surface of the filling contact and electrically connecting the filling contact and the lower surface of the first connecting line; and A second filling via is located on a second portion of the upper surface of the filling contact and electrically connects the filling contact and the lower surface of the second connection line.

14. The semiconductor device according to claim 12, wherein The filling line is at the same level as the first and second wiring vias.

15. The semiconductor device according to claim 11, in, The portion of the filling line at the level below the first wiring level is a first portion including a via, and The filling circuit further includes a second portion at the first wiring level, and the second portion includes a wiring circuit.

16. The semiconductor device according to claim 11, further comprising: A wiring line is located on the first connection line and is electrically connected to the first connection line and is at a second wiring level higher than the first wiring level.

17. A semiconductor device, comprising: a first power line and a second power line, wherein the first power line and the second power line extend in parallel in a first direction; a first cell isolation film, a second cell isolation film, and a third cell isolation film, wherein the first cell isolation film, the second cell isolation film, and the third cell isolation film are spaced apart from each other in the first direction and extend in parallel in a second direction intersecting the first direction; a first active pattern extending in the first direction between the first power line and the second power line; a first gate electrode extending in the second direction between the first cell isolation film and the second cell isolation film; a first source / drain contact, the first source / drain contact being located on the first source / drain region of the first active pattern and electrically connected to the first source / drain region of the first active pattern, the first source / drain contact being adjacent to one side of the first gate electrode; a first connection contact located on an upper surface of the first source / drain contact and electrically connected to the upper surface of the first source / drain contact; a first wiring path located on an upper surface of the first connecting contact and electrically connected to the upper surface of the first connecting contact; a first wiring line extending in the first direction and located on an upper surface of the first wiring via and electrically connected to the upper surface of the first wiring via; a second wiring path located on an upper surface of the first wiring line and electrically connected to the upper surface of the first wiring line; a second wiring line extending in the second direction and located on an upper surface of the second wiring via and electrically connected to the upper surface of the second wiring via; and a filling line extending in the second direction between the second cell isolation film and the third cell isolation film and located on the first wiring line and electrically connected to the first wiring line, The height of the upper surface of the filling circuit is equal to or lower than the height of the upper surface of the first wiring circuit.

18. The semiconductor device according to claim 17, further comprising: a second active pattern extending in the first direction between the first power line and the first active pattern; a second gate electrode extending in the second direction between the first cell isolation film and the first gate electrode; and a second source / drain contact, the second source / drain contact being located on the second source / drain region of the second active pattern and electrically connected to the second source / drain region of the second active pattern, the second source / drain contact being adjacent to one side of the second gate electrode, The second source / drain contact is electrically connected to the fill line through the first wiring via, the first wiring line, the second wiring via, and the second wiring line.

19. The semiconductor device according to claim 18, wherein The first active pattern is located in an NFET region, and the second active pattern is located in a PFET region.

20. The semiconductor device according to claim 17, wherein The second cell isolation film and the third cell isolation film are spaced apart from each other by a distance of 60 nanometers or less.

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