Semiconductor device

Abstract

The present disclosure provides semiconductor devices. A semiconductor device includes a substrate having a first region and a second region; gate electrodes stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in the first region, and extending in a second direction perpendicular to the first direction at different lengths in the second region; first separation regions penetrating the gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; second separation regions penetrating the gate electrodes in the second region, extending in the second direction between the first separation regions, and spaced apart from each other in the second direction; and a first vertical structure penetrating the gate electrodes in the second region and closest to the first region, wherein a width of the second separation regions in the third direction is greater than a width of the first vertical structure, a first end point of the second separation regions adjacent to the first region is spaced apart from a center axis of the first vertical structure in the second direction, and is farther from the first region than the center axis of the first vertical structure.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device. BACKGROUND

[0002] Semiconductor devices perform high-capacity data processing with a small volume. Therefore, it is advantageous to increase the integration of such semiconductor devices. In order to improve the integration of semiconductor devices, semiconductor devices having a vertical transistor structure instead of an existing planar transistor structure have been proposed. SUMMARY

[0003] An aspect of the disclosure can provide a semiconductor device having improved integration and / or electrical characteristics.

[0004] According to an aspect of the disclosure, a semiconductor device can include a substrate having a first region and a second region; a plurality of gate electrodes stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in the first region, and including a plurality of pad regions provided by some of the plurality of gate electrodes extending in a second direction perpendicular to the first direction with different lengths in the second region; a plurality of first separation regions penetrating the plurality of gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; a plurality of second separation regions penetrating the plurality of gate electrodes between the plurality of first separation regions, and including a second main separation region extending from the first region in the second direction and a second auxiliary separation region extending from the second region in the second direction; a plurality of channel structures penetrating the plurality of gate electrodes, extending vertically on the substrate, and arranged in the first region; and a plurality of dummy channel structures penetrating the plurality of gate electrodes, extending vertically on the substrate, and arranged in the second region, wherein the plurality of pad regions includes a first pad region provided by an uppermost first gate electrode among the plurality of gate electrodes and a second pad region provided by a second gate electrode below the first gate electrode, the plurality of dummy channel structures includes a pair of first dummy channel structures penetrating the first pad region and arranged adjacent to the first region and a pair of second dummy channel structures arranged adjacent to a first end of the first gate electrode, the plurality of second auxiliary separation regions are arranged between the first pad regions adjacent to each other and have a first edge portion adjacent to the first dummy channel structures and a first end closest to the first region on the first edge portion, a center axis of the first dummy channel structure is spaced apart from a center axis of the second dummy channel structure by a first distance in the second direction, and the first edge portion of the second auxiliary separation region is spaced apart from the center axis of the first dummy channel structure by a second distance smaller than the first distance in the second direction.

[0005] According to an aspect of the disclosure, a semiconductor device can include a substrate having a first region and a second region; a plurality of gate electrodes stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in the first region, and including pad regions provided by some of the plurality of gate electrodes extending different lengths in a second direction perpendicular to the first direction in the second region; first separation regions penetrating the gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; second separation regions penetrating the gate electrodes in the second region and extending in the second direction; and channel structures and dummy channel structures penetrating the gate electrodes, extending vertically on the substrate, and arranged in the first region and the second region, respectively, wherein the pad regions include a first pad region and a second pad region arranged in the second direction from the first region in order, a first edge portion adjacent to the first region of the second separation regions is spaced apart from a center axis of the dummy channel structure penetrating the first pad region and adjacent to the first edge portion by a first distance in the second direction, and the first distance is greater than a maximum width of the dummy channel structure.

[0006] According to another aspect of the disclosure, a semiconductor device can include a substrate having a first region and a second region; gate electrodes stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in the first region, and extending in a second direction perpendicular to the first direction and having different lengths in the second region; first separation regions penetrating the gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; second separation regions penetrating the gate electrodes in the second region, extending in the second direction between the first separation regions, and spaced apart from each other in the second direction; and first vertical structures penetrating the gate electrodes in the second region and closest to the first region, wherein a width of the second separation regions in the third direction is greater than a width of the first vertical structures, a first end point of the second separation regions adjacent to the first region is spaced apart from a center axis of the first vertical structures in the second direction, and is farther from the first region than the center axis of the first vertical structures. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] FIG. 1 is a schematic block diagram of a semiconductor device according to an example embodiment in the present disclosure.

[0009] FIG. 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an example embodiment in the present disclosure.

[0010] FIG. 3A is a schematic plan view of a semiconductor device according to an example embodiment in the present disclosure.

[0011] FIG. 3B is a partial enlarged plan view of a portion "A" in FIG. 3A

[0012] FIG. 4A to FIG. 4F is a cross-sectional view showing an example of a semiconductor device according to an example embodiment in the present disclosure.

[0013] FIG. 4G is a partial enlarged cross-sectional view of a portion "B" in FIG. 4D

[0014] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an example embodiment in the present disclosure.

[0015] FIG. 6A to FIG. 6C is a partial enlarged plan view showing a modification of a semiconductor device according to an example embodiment in the present disclosure.

[0016] FIG. 7A to FIG. 7D is a cross-sectional view showing another modification of a semiconductor device according to an example embodiment in the present disclosure.

[0017] FIG. 8A to FIG. 8D is a cross-sectional view showing an example of a method of forming a semiconductor device according to an example embodiment in the present disclosure. DETAILED DESCRIPTION

[0018] Hereinafter, example embodiments in the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] FIG. 1 is a schematic block diagram of a semiconductor device according to an example embodiment.

[0020] Referring to FIG. 1 , the semiconductor device 10 can include a memory cell array 20 and / or a peripheral circuit 30. The peripheral circuit 30 can include a row decoder 32, a page buffer 34, an input / output (I / O) buffer 35, control logic 36, and / or a voltage generator 37.

[0021] The memory cell array 20 includes a plurality of memory blocks, each of which can include a plurality of memory cells. The plurality of memory cells can be connected to the row decoder 32 through a string select line (SSL), a word line (WL), and / or a ground select line (GSL) and to the page buffer 34 through a bit line (BL). In an example embodiment, a plurality of memory cells arranged in the same row can be connected to the same word line WL, and a plurality of memory cells arranged in the same column can be connected to the same bit line BL. ​​

[0022] The row decoder 32 decodes the input address ADDR to generate and transmit a driving signal of the word line WL. The row decoder 32 can supply a word line voltage generated by the voltage generator 37 to each of the selected word line WL and the unselected word line WL in response to the control of the control logic 36.

[0023] The page buffer 34 can be connected to the memory cell array 20 through the bit line BL to read data stored in the memory cell. The page buffer 34 can temporarily store data to be stored in the memory cell or detect data already stored in the memory cell according to the operation mode. The page buffer 34 can include a column decoder and / or a sense amplifier. The column decoder can selectively activate the bit line BL of the memory cell array 20, and the sense amplifier can detect a voltage of the bit line BL selected by the column decoder to read data stored in the selected memory cell during a read operation.

[0024] The I / O buffer 35 can receive data DATA and transfer the data DATA to the page buffer 34 during a program operation, and output the data DATA received from the page buffer 34 to the outside during a read operation. The I / O buffer 35 can transfer an input address or a command to the control logic 36.

[0025] The control logic 36 can control the operation of the row decoder 32 and / or the page buffer 34. The control logic 36 can receive a control signal and an external voltage transmitted from the outside and operate according to the received control signal. The control logic 36 can control a read, write, and / or erase operation in response to the control signal.

[0026] The voltage generator 37 can generate a voltage required for internal operation, such as a program voltage, a read voltage, an erase voltage, etc., using an external voltage. The voltage generated by the voltage generator 37 can be transferred to the memory cell array 20 through the row decoder 32.

[0027] Any element disclosed above can include or be implemented as: processing circuitry, such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0028] FIG. 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an example embodiment.

[0029] Referring to FIG. 2The memory cell array 20 can include a plurality of memory cell strings S each including memory cells M connected in series to each other and ground select transistors GST and string select transistors SST1 and SST2 connected in series to opposite ends of the memory cells M. The plurality of memory cell strings S can be connected in parallel to each of the bit lines BL0 to BL2. The plurality of memory cell strings S can be commonly connected to a common source line CSL. That is, the plurality of memory cell strings S can be arranged between the plurality of bit lines BL0 to BL2 and the common source line CSL. In some example embodiments, a plurality of common source lines CSL can be arranged two-dimensionally.

[0030] The memory cells M connected in series to each other can be controlled by word lines WL0 to WLn for selecting the memory cells M. Each of the memory cells M can include a data storage element. Gate electrodes of the memory cells M arranged at the same or substantially the same distance from the common source line CSL can be commonly connected to one of the word lines WL0 to WLn so as to be in an equipotential state. Alternatively, even if the gate electrodes of the memory cells M are arranged at the same or substantially the same distance from the common source line CSL, the gate electrodes arranged in different rows or columns can be independently controlled.

[0031] The ground select transistors GST can be controlled by a ground select line GSL and can be connected to the common source line CSL. The string select transistors SST1 and SST2 can be controlled by string select lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3 and can be connected to the bit lines BL0 to BL2. FIG. 2 A structure in which one ground select transistor GST and two string select transistors SST1 and SST2 are connected to a plurality of memory cells M connected in series to each other is illustrated, but each of the string select transistors SST1 and SST2 can be connected or a plurality of ground select transistors GST can be connected. One or more dummy lines DWL or buffer lines can be further arranged between an uppermost word line WLn among the word lines WL0 to WLn and the string select lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3. In some example embodiments, one or more dummy lines DWL can be arranged between a lowermost word line WL0 and the ground select line GSL.

[0032] When signals are applied to the string selection transistors SST1 and SST2 through the string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3, the applied signals are transmitted to the series-connected memory cells M through the bit lines BL0 to BL2, thereby performing data read and write operations. In addition, an erase operation for erasing data written in the memory cells M can be performed by applying a predetermined or optionally desired erase voltage through the substrate. In some example embodiments, the memory cell array 20 can include at least one dummy memory cell string that is electrically separated from the bit lines BL0 to BL2.

[0033] FIG. 3A is a schematic plan view of a semiconductor device according to example embodiments in the present disclosure, FIG. 3B is a partial enlarged plan view of a portion "A" in FIG. 3A FIG. 4A to FIG. 4F are cross-sectional views taken along lines I-I', II-II', III-III', IV-IV', V-V', and VI-VI' of FIG. 3A FIG. 4G is a partial enlarged plan view of a portion "B" in FIG. 4D FIG. 3A The portion "A" in can be a portion including the same pattern as a portion indicated by lines I-I', II-II', III-III', IV-IV', and V-V' of FIG. 3A

[0034] Referring to FIG. 3A to FIG. 4G , a semiconductor device 100 according to example embodiments can include a substrate 101 having a first region R1 and / or a second region R2, a substrate insulating layer 110 disposed in the substrate 101 and at the second region R2, gate electrodes 130 stacked on the substrate 101, a channel structure CH and a dummy channel structure DCH disposed to penetrate the gate electrodes 130, first and second separation regions MS1 and MS2a and MS2b extending through the gate electrodes 130, an upper separation region SS penetrating a portion of the uppermost gate electrode 130, and a lower separation region GS penetrating a portion of the lowermost gate electrode 130. The channel structure CH can include a channel layer 140, a gate dielectric layer 145, a channel insulating layer 150, and / or a channel pad 155. The semiconductor device 100 can further include an interlayer insulating layer 120, a cell region insulating layer 170, and / or a contact plug MC, the interlayer insulating layer 120 being alternately stacked with the gate electrodes 130 on the substrate 101.

[0035] The first region R1 of the substrate 101 can be a region in which the gate electrodes 130 are vertically stacked and the channel structure CH is disposed, and can be a region corresponding to FIG. 1 ​​​​corresponding to the memory cell array 20. The first region R1 can be referred to as a memory cell array region. A second region R2 of the substrate 101 can be a region in which the gate electrodes 130 extend to have different lengths and the dummy channel structures DCH are provided, which can correspond to a region of the memory cell array 20 and the peripheral circuit 30 FIG. 1 The second region R2 can be referred to as a connection region. The second region R2 can be disposed in at least one end of the first region R1 in at least one direction, for example, the X direction.

[0036] The substrate 101 can have an upper surface extending in the X direction and the Y direction. The substrate 101 can include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The substrate 101 can be provided as a bulk wafer or an epitaxial layer.

[0037] The substrate insulating layer 110 can be disposed in the substrate 101 in the second region R2 of the substrate 101. As shown in FIG. 1A, the substrate insulating layer 110 can be disposed between the first separation region MS1 and the second separation regions MS2a and MS2b so as not to overlap the first separation region MS1 and the second separation regions MS2a and MS2b in the Z direction in the second region R2. The substrate insulating layer 110 can extend to a region in which the second separation regions MS2a and MS2b are spaced apart from each other in the X direction. According to an example embodiment, the substrate insulating layer 110 can not extend to a region in which the second separation regions MS2a and MS2b are spaced apart from each other in the X direction. FIG. 4A 、 FIG. 4B and FIG. 5 The substrate insulating layer 110 can be disposed between the first separation region MS1 and the second separation regions MS2a and MS2b so as not to overlap the first separation region MS1 and the second separation regions MS2a and MS2b in the Z direction in the second region R2. The substrate insulating layer 110 can extend to a region in which the second separation regions MS2a and MS2b are spaced apart from each other in the X direction. According to an example embodiment, the substrate insulating layer 110 can not extend to a region in which the second separation regions MS2a and MS2b are spaced apart from each other in the X direction.

[0038] The substrate insulating layer 110 can be formed by, for example, shallow trench isolation (STI). The substrate insulating layer 110 can extend from the upper surface of the substrate 101 into the substrate 101 to a predetermined or optionally desired depth. The substrate insulating layer 110 can be formed of an insulating material and can include, for example, an oxide, a nitride, or a combination thereof. The substrate insulating layer 110 can also be described as an insulating region configuring the substrate 101. In some example embodiments, the substrate 101 can include an insulating region corresponding to the substrate insulating layer 110 and a conductive region based on a semiconductor region.

[0039] The gate electrodes 130 are spaced apart from each other perpendicularly on the first region R1 and can extend from the first region R1 to the second region R2 in different lengths.

[0040] The gate electrodes 130 can include ground selection gate electrodes 130G constituting gates of ground selection transistors GST, memory cell gate electrodes 130M constituting gates of the plurality of memory cells M, and dummy gate electrodes 130D constituting gates of dummy memory cells DM. FIG. 2The string selection gate electrodes 130Sd and 130Su of the gate electrodes of the string selection transistors SST1 and SST2. The number of the memory cell gate electrodes 130M constituting the memory cell M can be determined according to the capacity of the semiconductor device 100. According to some example embodiments, the string selection gate electrodes 130Sd and 130Su and the ground selection gate electrode 130G can each be one or two or more, and can have the same or different structure from the gate electrodes 130 of the memory cell M. Some of the gate electrodes 130 (e.g., the memory cell gate electrodes 130M adjacent to the ground selection gate electrode 130G and the string selection gate electrodes 130Sd and 130Su) can be dummy gate electrodes.

[0041] As shown in FIG. 3A and FIG. 3B The gate electrodes 130 can be arranged to be separated in the Y direction by predetermined or optionally desired units by the first separation regions MS1 extending in the X direction. The gate electrodes 130 between a pair of the first separation regions MS1 can form one memory block, but the range of the memory block is not limited thereto.

[0042] The memory cell gate electrodes 130M can form one layer in one memory block. Each of the memory cell gate electrodes 130M can include eight sub-gate electrodes extending in the X direction between the pair of the first separation regions MS1, and can be connected by gate connection portions (see 130Mc in FIG. 4D to be arranged as a single layer in a region in which the second separation regions MS2a and MS2b are spaced apart from each other in the X direction. The gate connection portion refers to a region in which the gate electrodes 130 are connected horizontally at the same level.

[0043] The string selection gate electrodes 130Sd and 130Su can be completely separated into eight sub-gate electrodes by the first separation regions MS1 and the second separation regions MS2a and MS2b and the upper separation regions SS between the pair of the first separation regions MS1.

[0044] The ground selection gate electrode 130G can be connected by the gate connection portions between some of the second separation regions MS2a and MS2b, but can be separated into four sub-gate electrodes by the second main separation regions MS2a and the lower separation regions GS between the second main separation regions MS2a.

[0045] As shown in FIG. 3A and FIG. 4FAs illustrated, the gate electrodes 130 in the second region R2 of the substrate 101 extend in the X direction at different lengths to form a step, and provide a pad region PAD in which the lower gate electrode 130 is exposed upward. In the present disclosure, the pad region PAD can be used as a term referring to the entire region in which the gate electrodes 130 form a step in the second region R2. A predetermined or optionally desired number of gate electrodes 130 (e.g., one, two, four, or five gate electrodes 130) can form a gate group, and a step structure can be formed in the X direction between the gate groups. For example, as illustrated, FIG. 4F As illustrated, one gate group can include five gate electrodes 130, and a step structure can be formed in the X direction between the gate groups. The gate electrodes 130 constituting one gate group can also be provided to have a step structure from each other in the Y direction.

[0046] In some example embodiments, the pad region PAD can include a first upper pad region UP1, a second upper pad region UP2, and / or a third upper pad region UP3 provided in the X direction from one end of the first region R1 toward the second region R2 in order. The first upper pad region UP1, the second upper pad region UP2, and / or the third upper pad region UP3 can be provided by three gate electrodes 130 stacked in order from the top of the gate electrodes 130. For example, the first upper pad region UP1 can be provided by the uppermost gate electrode 130Su in the second region R2, and the second upper pad region UP2 can be provided by the gate electrode 130Sd provided below the uppermost gate electrode 130Su in the second region R2.

[0047] In some example embodiments, a plurality of first upper pad regions UP1 can be provided and spaced apart from each other in the Y direction. The first upper pad regions UP1 can be separated by the upper separation region SS and the second auxiliary separation region MS2b and can be separated by the first separation region MS1 and the second main separation region MS2a.

[0048] In some example embodiments, the first upper pad region UP1, the second upper pad region UP2, and / or the third upper pad region UP3 can have different first, second, and / or third lengths L1, L2, and / or L3 in the X direction, respectively, but are not limited thereto.

[0049] Each gate electrode 130 can be exposed upward from the pad region PAD and connected to the contact plug MC, so that the gate electrode 130 can be connected to the upper wiring structure. In the pad region PAD, the gate electrode 130 can have a thicker region to be stably connected to the contact plug MC, but is not limited thereto.

[0050] The gate electrode 130 can include a metal such as tungsten (W). According to some example embodiments, the gate electrode 130 can include a polysilicon or a metal silicide material.

[0051] In some example embodiments, the gate electrode 130 can include an inner gate conductive layer and / or a diffusion barrier 133 surrounding the gate conductive layer. The diffusion barrier 133 can include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0052] In some example embodiments, the semiconductor device 100 can further include an erase gate electrode forming an erase transistor, which is disposed above the string select gate electrodes 130Su and 130Sd or below the ground select gate electrode 130G and used in an erase operation utilizing a gate-induced drain leakage (GIDL) phenomenon.

[0053] An interlayer insulating layer 120 can be disposed between the gate electrodes 130. The interlayer insulating layer 120 can be disposed to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 and extend in the X direction, like the gate electrodes 130. The interlayer insulating layer 120 can include an insulating material such as silicon oxide or silicon nitride.

[0054] The channel structures CH can be disposed while being spaced apart from each other in rows and columns on the first region R1. The channel structures CH can be arranged to form a lattice pattern, or can be arranged in a zigzag in one direction. The channel structures CH can extend vertically on the substrate 101. The channel structures CH can have a column shape and / or can have an inclined side surface that narrows toward the substrate 101 according to an aspect ratio. Among the channel structures CH arranged in the first region R1, some of the channel structures CH adjacent to the second region R2 can be dummy channels. Also, the channel structures CH overlapping with the upper separation region SS can be dummy channels. In some example embodiments, the dummy channels can have the same or similar structure as the channel structures CH, but can not perform a substantial function in the semiconductor device 100.

[0055] Referring to FIG. 4D and FIG. 4G A channel layer 140 can be disposed in the channel structures CH. The channel layer 140 in the channel structures CH can be formed in a ring shape surrounding an inner channel insulating layer 150, but according to some example embodiments, the channel layer 140 can have a column shape such as a circular column or a prismatic column without the channel insulating layer 150. The channel layer 140 can be connected to the epitaxial layer 105 at a bottom, and an insulating layer can be further disposed between the channel layer 140 and the epitaxial layer 105. The channel layer 140 can include a semiconductor material such as polysilicon or single-crystal silicon. The semiconductor material can be an undoped material or a material containing p-type or n-type impurities. The channel structures CH disposed in a straight line in the Y direction can be connected to different bit lines BL0 to BL2 according to the arrangement of the upper wiring structure connected to the channel pad 155 (see FIG. 2).FIG. 2 ).

[0056] The channel pad 155 can be disposed on the channel layer 140 in the channel structure CH. The channel pad 155 can be disposed to cover an upper surface of the channel insulating layer 150 and electrically connected to the channel layer 140. The channel pad 155 can include, for example, doped polysilicon.

[0057] The gate dielectric layer 145 can be disposed between the gate electrode 130 and the channel layer 140. The gate dielectric layer 145 can include, in order from the channel layer 140, a tunneling layer 141, a data storage layer 142, and / or a blocking layer 143. The tunneling layer 141 can tunnel electric charges to the data storage layer 142 and can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The data storage layer 142 can be a charge trap layer or a floating gate conductive layer. The blocking layer 143 can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In some example embodiments, at least a portion of the gate dielectric layer 145 can extend in a horizontal direction along the gate electrode 130.

[0058] The epitaxial layer 105 can be disposed on the substrate 101 and at a lower end of the channel structure CH, and can be disposed on a side surface of at least one gate electrode 130. The epitaxial layer 105 can be disposed in a recessed area of the substrate 101. An insulating layer 105S can be disposed between the epitaxial layer 105 and the lowermost ground select gate electrode 130G. An upper surface of the epitaxial layer 105 can be higher than an upper surface of the lowermost gate electrode 130 and lower than a lower surface of the next lowermost gate electrode 130, but is not limited to as shown. In some example embodiments, the epitaxial layer 105 can be omitted, in which case the channel layer 140 can be directly connected to the substrate 101.

[0059] The channel contact plug 157 can be disposed on the channel structure CH. The channel contact plug 157 can be connected to the channel pad 155. The channel contact plug 157 can connect the channel structure CH to the upper wiring structure, and can be connected to each of the bit lines BL0 to BL2 (see FIG. 1A). FIG. 2 The channel contact plug 157 can not be disposed on the dummy channel structure DCH. Alternatively, the channel contact plug 157 can be disposed on the dummy channel structure DCH and can not be connected to the upper wiring structure. The channel contact plug 157 can not be disposed on the dummy channel structure DCH or the channel structure CH overlapping the upper separation area SS.

[0060] The dummy channel structure DCH can be provided in the second region R2, can have the same or similar structure as the channel structure CH, but can not perform a substantial function in the semiconductor device 100. For example, the dummy channel structure DCH can be connected to the substrate 101 through the substrate insulating layer 110. The dummy channel structure DCH can be regularly arranged in rows and columns in the pad region PAD of the gate electrode 130. The dummy channel structure DCH can have a maximum diameter of a second width W2, which is greater than a first width W1 that is a maximum diameter of the channel structure CH.

[0061] When the smallest unit surrounded by the first separation region MS1 and the second separation regions MS2a and MS2b in the pad region PAD is a unit pad region, the dummy channel structure DCH can be disposed at four corners of one unit pad region. However, the length of each unit pad region can be different for each gate electrode 130, and the number and / or spacing of the dummy channel structures DCH arranged in each unit pad region can also be different.

[0062] The dummy channel structure DCH can include a support channel structure DCHS provided outside the lower separation region GS in the Y direction. The support channel structure DCHS can be provided on both sides of the lower separation region GS in the Y direction. The support channel structure DCHS can have a maximum diameter greater than the maximum diameters of the channel structure CH and the dummy channel structure DCH. For example, the support channel structure DCHS can have a maximum diameter of a third width W3, which is greater than the first width W1 that is the maximum diameter of the channel structure CH.

[0063] The support channel structure DCHS can have a shape in which the width in the Y direction is greater than the width in the X direction, compared to the channel structure CH and the dummy channel structure DCH having a circular or approximately circular shape. The support channel structure DCHS can have an elongated, rectangular, or elliptical shape extending in the Y direction.

[0064] The dummy channel structure DCH can be regularly arranged. Since the dummy channel structure DCH is arranged to penetrate the substrate insulating layer 110, the lower end thereof can be positioned to a lower height than the lower end of the channel structure CH. Accordingly, the dummy channel structure DCH can have a greater length than the channel structure CH. In addition, the epitaxial layer 105 in the dummy channel structure DCH can be arranged such that at least a portion of the side surface is surrounded by the substrate insulating layer 110.

[0065] As FIG. 3BAs shown, the dummy channel structure DCH can be disposed adjacent to four corners of a first upper pad area UP1 provided by the uppermost gate electrode 130Su. The dummy channel structure DCH can include a pair of first dummy channel structures DCH1 disposed through the first upper pad area UP1 and adjacent to the first region R1, and a pair of second dummy channel structures DCH2 adjacent to a first end S1 of the uppermost gate electrode 130Su. The first end S1 can also be referred to as one end of the first upper pad area UP1. Center axes of the first dummy channel structures DCH1 can be spaced apart from center axes of the second dummy channel structures DCH2 by a first distance d1 in the X direction. A distance between the pair of first dummy channel structures DCH1 in the Y direction can be less than the first distance d1.

[0066] In the disclosure, the dummy channel structure DCH can be referred to as a vertical structure. For example, the vertical structure can include a first vertical structure disposed closest to the first region R1 in the second region R2 and connected to the first upper pad area UP1. The first vertical structure can refer to the first dummy channel structure DCH1.

[0067] In a second upper pad area UP2 provided by a gate electrode 130Sd disposed under the uppermost gate electrode 130Su, two groups of dummy channel structures DCH forming a pair of first dummy channel structures DCH1 and a pair of second dummy channel structures DCH2 can be arranged parallel to each other in the X direction.

[0068] The first separation region MS1 and the second separation regions MS2a and MS2b can be arranged to extend in the X direction in the first region R1 and the second region R2. The first separation region MS1 and the second separation regions MS2a and MS2b can be arranged parallel to each other. The first separation region MS1 and the second separation regions MS2a and MS2b can be arranged to form a constant pattern in the Y direction, and the second separation regions MS2a and MS2b are aligned with and spaced apart from each other in the X direction. The first separation region MS1 and the second separation regions MS2a and MS2b can be through separation regions connected to the substrate 101 through all of the gate electrodes 130 stacked on the substrate 101. The first separation region MS1 and the second separation regions MS2a and MS2b can be arranged by partially recessing an upper portion of the substrate 101, or can be arranged in contact with an upper surface of the substrate 101 on the substrate 101. As the number of stacks of the gate electrodes 130 increases, the second separation regions MS2a and MS2b can reduce stress applied to the gate electrodes 130.

[0069] The second partition regions MS2a and MS2b may include a second primary partition region MS2a and a second secondary partition region MS2b. The second primary partition region MS2a is spaced apart from the pair of first partition regions MS1 in the Y direction at a predetermined or optionally desired interval. The second secondary partition region MS2b is spaced apart from the first partition region MS1 ​​and the second primary partition region MS2a in the Y direction at a predetermined or optionally desired interval.

[0070] The second main dividing region MS2a can be arranged throughout the first region R1 and the second region R2. The second main dividing region MS2a can be arranged as a whole extending from the first region R1 to a portion of the second region R2 and spaced apart from it in the X direction, and again extending as a whole within the second region R2. Multiple second main dividing regions MS2a can be divided and arranged in a straight line at predetermined or optionally desired intervals. The second auxiliary dividing region MS2b can be provided only in the second region R2. Multiple second auxiliary dividing regions MS2b can be divided and arranged in a straight line at predetermined or optionally desired intervals.

[0071] In the plan view, the second auxiliary partition region MS2b may have a side extending in the X direction. The side extending in the X direction of the second auxiliary partition region MS2b may extend substantially flat in the X direction without any protrusions. The portion of the side extending in a straight line in the second auxiliary partition region MS2b may have a length equal to or greater than the first distance d1. The dummy channel structure DCH may not be arranged in the area where the second auxiliary partition region MS2b is arranged. The second auxiliary partition region MS2b may not overlap with the dummy channel structure DCH. The width of the second auxiliary partition region MS2b in the Y direction may be greater than the maximum width of the dummy channel structure DCH. The second auxiliary partition region MS2b may contact a portion of the upper partition region SS.

[0072] like FIG. 3A to FIG. 4E As shown, the first partition region MS1 ​​and the second partition regions MS2a and MS2b may include a conductive layer 109 and / or a partition insulating layer 107 covering the sides of the conductive layer 109. The conductive layer 109 may be formed of a conductive material, and the partition insulating layer 107 may be formed of an insulating material. The conductive layer 109 may be separated from the gate electrode 130 by the partition insulating layer 107. The first partition region MS1 ​​may include the above-mentioned reference... FIG. 2The described common source line CSL, the second separation region MS2a and MS2b can include a dummy common source line. In some example embodiments, the dummy common source line can be in a floating state, where the dummy common source line is not connected to a device driving the semiconductor device 100 or an electrical signal is not applied to the dummy common source line. The structure of the cross section of the first separation region MS1 in the Y direction can be the same or substantially the same as the structure of the cross section of the second separation region MS2a and MS2b in the Y direction. However, according to some example embodiments, the width of the first separation region MS1 in the Y direction can be greater than the width of the second separation region MS2 in the Y direction.

[0073] The second auxiliary separation region MS2b can have a first edge portion eg1 adjacent to the first dummy channel structure DCH1. The first edge portion eg1 of the second auxiliary separation region MS2b can be spaced apart from the central axis of the first dummy channel structure DCH1 by a second distance d2 in the X direction. A first extension line passing through the first edge portion eg1 of the second auxiliary separation region MS2b and the central axis of the first dummy channel structure DCH1 can form a first angle θ1 (0° < θ1 < 90°) with a second extension line in the X direction. The first edge portion eg1 of the second auxiliary separation region MS2b can be spaced apart from the central axis of the first dummy channel structure DCH1 by a third distance d3, which is a straight line distance.

[0074] In some example embodiments, the second distance d2 can be less than the first distance d1. The second distance d2 can be greater than one third of the first distance d1. The second distance d2 can be greater than the maximum diameter of the dummy channel structure DCH. The second distance d2 can be less than the first length L1 of the first upper pad region UP1 and the second length L2 of the second upper pad region UP2. The second distance d2 can be greater than one twentieth of the second length L2 of the second upper pad region UP2.

[0075] In some example embodiments, the first distance d1 can be in a range from about 400 nm to about 600 nm. The second distance d2 can be in a range from about 150 nm to about 400 nm. The third distance d3 can be in a range from about 200 nm to about 500 nm.

[0076] In some example embodiments, the first angle θ1 can be less than about 40°. The first angle θ1 can decrease as the second distance d2 or the third distance d3 increases.

[0077] The second auxiliary separation area MS2b can have a first end point e1 which is a starting point extending from the second area R2 in the X direction. The first end point e1 can be one end point of the second auxiliary separation area MS2b closest to the first area R1. The first end point e1 can be located on the first edge portion eg1 and can be an end point at which the second auxiliary separation area MS2b contacts the upper separation area SS, but is not limited thereto. The first end point e1 of the second auxiliary separation area MS2b can be spaced apart from the channel structure CH closest to the second auxiliary separation area MS2b by a fourth distance d4 in the X direction. The first end point e1 of the second auxiliary separation area MS2b can be spaced apart from the first end S1 of the uppermost gate electrode 130Su by a fifth distance d5 in the X direction.

[0078] In some example embodiments, the fourth distance d4 can be greater than a distance by which the first dummy channel structure DCH1 is spaced apart from the channel structure CH closest to the first dummy channel structure DCH1 in the X direction. The fifth distance d5 can be less than a distance by which the first dummy channel structure DCH1 is spaced apart from the first end S1 in the X direction.

[0079] In some example embodiments, the fourth distance d4 can be in a range from about 300 nm to about 500 nm. The fifth distance d5 can be in a range from about 200 nm to about 400 nm.

[0080] According to some example embodiments in the present disclosure, the first auxiliary separation area MS2b can be disposed to be spaced apart from the first dummy channel structure DCH1 by a predetermined or optionally desired distance, so that a pattern defect in which the second auxiliary separation area MS2b is bent toward the first dummy channel structure DCH1 or an edge portion eg1 of the second auxiliary separation area MS2b protrudes toward the first dummy channel structure DCH1 can be reduced or minimized. If the pattern defect occurs, in a process of removing the conductive material from the opening OP after forming the gate electrode with the conductive material through the opening OP (see FIG. 8C and FIG. 8D ), the conductive material can remain between the second auxiliary separation area MS2b and the lower gate electrode layer 130 due to the pattern defect. In some example embodiments, since deposition of a residue of the conductive material is reduced or prevented by reducing or minimizing the pattern defect, a semiconductor device having improved electrical characteristics can be provided. Further, when the edge portion of the opposite side of the second auxiliary separation area MS2b or the second main separation area MS2a is disposed to be spaced apart from the dummy channel structure DCH adjacent thereto by a predetermined or optionally desired distance, the same effect of reducing or preventing the pattern defect can be obtained.

[0081] However, when the second auxiliary separation region MS2b is formed deviating from the above-described first to fifth distances d1, d2, d3, d4, and d5 and the first angle θ1, a defect can occur in the pattern of the second auxiliary separation region MS2b. For example, if the second distance d2 is less than about 150 nm, the edge portion of the second auxiliary separation region MS2b can not be spaced apart from the first dummy channel structure DCH1 sufficiently, and in some example embodiments, the second auxiliary separation region MS2b can be bent or protrude toward the first dummy channel structure DCH1. Further, if the second distance d2 is greater than about 400 nm, the edge portion of the second auxiliary separation region MS2b is disposed close to the second dummy channel structure DCH2, and in some example embodiments, the second auxiliary separation region MS2b can be bent or protrude toward the second dummy channel structure DCH2.

[0082] Referring to FIG. 4A and FIG. 4B , FIG. 4A is a cross-sectional view of the first dummy channel structure DCH1 taken along a line I-I' in the Y direction, FIG. 4B is a cross-sectional view taken along a line II-II' passing through the second dummy channel structure DCH2 in the Y direction.

[0083] Since the first edge portion eg1 and the first end point e1 of the second auxiliary separation region MS2b are spaced apart from the central axis of the first dummy channel structure DCH1, the cross-section of the second auxiliary separation region MS2b can be invisible between the dummy channel structures DCH, and the cross-section of the upper separation region SS can be visible between the dummy channel structures DCH. FIG. 4A is illustrated in the cross-sectional view of FIG. 11. As shown in FIG. 11, the second auxiliary separation region MS2b can overlap the second dummy channel structure DCH2 in the Y direction, and thus the cross-section of the second auxiliary separation region can be illustrated between the dummy channel structures DCH. FIG. 4B

[0084] The upper separation region SS can extend in the X direction between the first separation region MS1 and the second main separation region MS2a in the first region R1. The upper separation region SS can be arranged in parallel with the second auxiliary separation region MS2b, and can be in contact with the end point of the second auxiliary separation region MS2b. The upper separation region SS can be disposed to penetrate a portion of the gate electrode 130 including the string selection gate electrodes 130Su and 130Sd among the gate electrodes 130. The string selection gate electrodes 130Su and 130Sd separated by the upper separation region SS can form different string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3 (see FIG. 12). FIG. 2

[0085] ​​The upper separation region SS can include an upper insulating layer 103. As shown in FIG. 4A , FIG. 4C and FIG. 4D The upper insulating layer 103 can penetrate the string selection gate electrodes 130Su and 130Sd and the uppermost memory cell gate electrode 130M to separate the three gate electrodes 130 from each other in the Y direction. However, in example embodiments, the number of gate electrodes 130 separated by the upper insulating layer 103 can be variously modified.

[0086] The lower separation region GS can be provided at the same level as the lowermost ground selection gate electrode 130G. The lower separation region GS can be provided adjacent to the regions in which the second main separation regions MS2a are spaced apart from each other. The ground selection gate electrode 130G can be separated or divided into four layers in the Y direction between the pair of first separation regions MS1 by the lower separation region GS. For example, the lower separation region GS can be arranged to connect the second main separation regions MS2a, including the regions in which the second main separation regions MS2a are spaced apart from each other.

[0087] As shown in FIG. 4E , the lower separation region GS can include a lower insulating layer 160. The lower insulating layer 160 can be formed of, for example, silicon oxide, and can be the same material as the interlayer insulating layer 120.

[0088] Referring to FIG. 4F , the pad region PAD will be described in detail. In FIG. 4F , for the purpose of description, the diffusion barrier 133 forming a part of the gate electrode 130 is omitted, and only the gate electrode 130 is shown.

[0089] The pad region PAD can include: upper pad regions UP1, UP2, UP3, UP4, UP5, and / or UP6, having a stepped structure sequentially lowered in the X direction from the first region R1 toward the second region R2; dummy pad regions DP1, DP2, DP3, and / or DP4, having a stepped structure lowered in each of the X direction and the Y direction; and one or more intermediate pad regions MP and / or lower pad regions LP1, LP2, LP3, LP4, and / or LP5. Contact plugs MC penetrating the cell region insulating layer 170 can be provided on the pad region PAD.

[0090] The gate electrode 130 can include a lower gate group 130_1, an intermediate gate group 130_2, and / or an upper gate group 130_3. The intermediate gate group 130_2 can be provided on the lower gate group 130_1. The upper gate group 130_3 can be provided on the intermediate gate group 130_2.

[0091] The lower gate group 130_1 can include a first lower gate electrode 130_1a, a second lower gate electrode 130_1b, a third lower gate electrode 130_1c, a fourth lower gate electrode 130_1d, and / or a fifth lower gate electrode 130_1e, which are sequentially stacked from the substrate 101. The lower gate group 130_1 can extend different lengths in the X direction in the second area R2 to provide lower pad areas LP1, LP2, LP3, LP4, and / or LP5. For example, the fifth lower gate electrode 130_1e can provide the first lower pad area LP1. As shown in FIG. 1A, the lower gate group 130_1 can have a stepped structure in the X direction, and as shown in FIG. 1B, the lower gate group 130_1 can have a stepped structure in the Y direction. The first lower gate electrode 130_1a can be a ground select gate electrode 130G. FIG. 4F FIG. 3A

[0092] One or more intermediate gate groups 130_2 can be provided. Each of the one or more intermediate gate groups 130_2 can include a first intermediate gate electrode 130_2a, a second intermediate gate electrode 130_2b, a third intermediate gate electrode 130_2c, a fourth intermediate gate electrode 130_2d, and / or a fifth intermediate gate electrode 130_2e, which are sequentially stacked on the lower gate group 130_1. The intermediate gate group 130_2 can extend different lengths in the X direction in the second area R2 to provide intermediate pad areas MP. As shown in FIG. 1A, the intermediate gate group 130_2 can have a stepped structure between the intermediate gate groups 130_2 in the X direction, and as shown in FIG. 1B, each of the intermediate gate electrodes 130_2a, 130_2b, 130_2c, 130_2d, and / or 130_2e forming one intermediate gate group 130_2 can also have a stepped structure in the Y direction. Thus, a portion of the upper surface of each of the intermediate gate electrodes 130_2a, 130_2b, 130_2c, 130_2d, and / or 130_2e forming one intermediate gate group 130_2 can be exposed upward to provide the intermediate pad areas MP. The intermediate gate electrodes 130_2a, 130_2b, 130_2c, 130_2d, and / or 130_2e can be memory cell gate electrodes 130M. FIG. 4F FIG. 3A

[0093] ​​​​The upper gate group 130_3 can include a first upper gate electrode 130_3a, a second upper gate electrode 130_3b, a third upper gate electrode 130_3c, a fourth upper gate electrode 130_3d, a fifth upper gate electrode 130_3e, and / or a sixth upper gate electrode 130_3f, which are sequentially stacked on the uppermost intermediate gate group 130_2. The upper gate group 130_3 can extend different lengths in the X direction in the second region R2 to provide upper pad regions UP1, UP2, UP3, UP4, UP5, and / or UP6. For example, the sixth upper gate electrode 130_3f can provide the first upper pad region UP1. As shown in FIG. 13B, the upper gate group 130_3 can have a stepped structure in the X direction, but with reference to FIG. 13A, the upper gate group 130_3 can not have a stepped structure in the Y direction. The sixth upper gate electrode 130_3f can be a string selection gate electrode 130Su. FIG. 4F FIG. 3A

[0094] Dummy pad regions DP1, DP2, DP3, and / or DP4 can be disposed on the first upper gate electrode 130_3a. The dummy pad regions DP1, DP2, DP3, and / or DP4 can have a stepped structure that is lowered in each of the X direction and the Y direction. For example, the dummy pad regions DP1, DP2, DP3, and / or DP4 can have a stepped structure of at least five steps in each of the X direction and the Y direction.

[0095] A contact plug MC can penetrate a portion of the upper portion of the cell region insulating layer 170 in the second region R2 and can be connected to each uppermost gate electrode 130 among the gate electrodes 130 that form the pad region PAD. The contact plug MC makes the gate electrode 130 partially recessed and can be connected to the gate electrode 130. The contact plug MC can be connected to a wiring at the upper portion. The contact plug MC can electrically connect the gate electrode 130 to a circuit element in the peripheral circuit region. The position, number, and / or shape of the contact plug MC can be variously changed. For example, the contact plug MC can be connected to the gate electrode 130, respectively. The contact plug MC can include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), or the like. The contact plug MC can further include a barrier metal layer.

[0096] FIG. 3B FIG. 4F With reference to FIGS. 13A and 13B, the contact plug MC can include a first upper contact plug MCu1 disposed between the pair of first dummy channel structures DCH1 and the pair of second dummy channel structures DCH2 in the first upper pad region UP1. The first upper contact plug MCu1 can be disposed in a central region of the first upper pad region UP1.

[0097] ​​​​The contact plug MC can comprise, in addition to the first upper contact plug MCu1, a second upper contact plug MCu2 connected to the second upper pad region UP2, a third upper contact plug MCu3 connected to the third upper pad region UP3, a fourth upper contact plug MCu4 connected to the fourth upper pad region UP4, a fifth upper contact plug MCu5 connected to the fifth upper pad region UP5, and / or a sixth upper contact plug MCu6 connected to the sixth upper pad region UP6. The contact plug MC can comprise first to fourth dummy contact plugs MCd1, MCd2, MCd3, and / or MCd4 connected to the first to fourth dummy pad regions DP1, DP2, DP3, and / or DP4, respectively. The contact plug MC can comprise one or more middle contact plugs MCm connected to one or more middle pad regions MP, respectively. The contact plug MC can comprise first to fourth lower contact plugs MC11, MC12, MC13, MC14, and / or MC15 connected to the lower pad regions LP1, LP2, LP3, LP4, and / or LP5, respectively.

[0098] The cell region insulating layer 170 can be provided to cover the stack structure of the substrate 101 and / or the gate electrode 130. In some example embodiments, the cell region insulating layer 170 can comprise a plurality of insulating layers. The cell region insulating layer 170 can comprise an insulating material such as silicon oxide and silicon nitride.

[0099] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to example embodiments in the present disclosure. FIG. 5 is a cross-sectional view taken along FIG. 4B line VII-VII' in . Line VII-VII' is a cutting line that cuts the semiconductor device horizontally at a level between the upper end of the substrate insulating layer and the lower end of the first separation region (see FIG. 4A to FIG. 4E ).

[0100] Referring to FIG. 5 , unlike FIG. 3B , the upper separation region SS, the gate electrode 130, and the contact plug MC are not shown. Further, since it is a cross-sectional view at a level between the upper end of the substrate insulating layer 110 and the lower end of the first separation region MS1, the substrate insulating layer 110 provided in the substrate 101 of the second region R2 is shown.

[0101] Referring to FIG. 4D , since the first separation region MS1 and the second separation regions MS2a and MS2b have widths in the X direction and the Y direction that decrease toward the substrate 101, respectively, the first separation region MS1 and the second separation regions MS2a and MS2b can have relatively small sizes compared to the plan view of FIG. 3B .

[0102] The second auxiliary separation region MS2b can have a first lower edge portion legl that has a greater distance from the center axis of the first dummy channel structure DCH1 than the first edge portion egl. The first lower edge portion legl of the second auxiliary separation region MS2b can be disposed to be spaced apart from the center axis of the first dummy channel structure DCH1 by a second distance ld2 in the X direction. The second distance ld2 can be relatively greater than FIG. 3B the second distance d2 in the X direction. A first extension line passing through the first lower edge portion legl of the second auxiliary separation region MS2b and the center axis of the first dummy channel structure CH can form a second angle Θ2 (0° < Θ2 < 90°) with a second extension line in the X direction. The second angle Θ2 can be smaller than FIG. 3B the first angle Θ1. The first lower edge portion legl of the second auxiliary separation region MS2b can be spaced apart from the center axis of the first dummy channel structure DCH1 by a third distance ld3 (which is a straight line distance). The third distance ld3 can be greater than FIG. 3B the third distance d3.

[0103] The second auxiliary separation region MS2b can have a first lower end point lel that has a greater distance from the first region R1 than the first end point el. The first lower end point lel of the second auxiliary separation region MS2b can be spaced apart from the channel structure CH closest to the second auxiliary separation region MS2b by a fourth distance ld4 in the X direction. The fourth distance ld4 can be greater than FIG. 3B the fourth distance d4.

[0104] A case in which the defect pattern in which the second auxiliary separation region MS2b is bent or protruded toward the first dummy channel structure DCH1 can be a case in which an opening OP (see FIG. 8C ) for forming the second auxiliary separation region MS2b is bent or protruded toward the dummy channel structure (DCH). In some example embodiments, the opening OP can partially recess the substrate insulating layer 110. In a process of forming the gate electrode with a conductive material after forming the opening OP, a residue of the conductive material can be deposited between the second auxiliary separation region MS2b, the lower gate electrode 130, and / or the substrate insulating layer 110 due to the defect pattern to cause a defect. According to some example embodiments in the disclosure, since the second auxiliary separation region MS2b is disposed to be spaced apart from the first dummy channel structure DCH1 by a predetermined or optionally desired distance, the occurrence of the defect pattern can be reduced.

[0105] FIG. 6A to FIG. 6C is a partial enlarged plan view illustrating a variation of a semiconductor device according to some example embodiments in the disclosure.

[0106] Referring to FIG. 6A In the semiconductor device 100a, the first end point e1a and the first edge portion eg1a of the second auxiliary separation region MS2b can be closer to the first end S1 than the first upper contact plug MCu1.

[0107] In relation to FIG. 3B the example embodiment, the distance in the X direction between the first edge portion eg1a and the central axis of the first dummy channel structure DCH1 can be increased. For example, the first edge portion eg1a can be spaced apart from the central axis of the first dummy channel structure DCH1 in the X direction by a second distance d2a. A first extension line passing through the first edge portion eg1a and the central axis of the first dummy channel structure DCH1 can form a first angle θ1d with a second extension line in the X direction, and the first edge portion eg1a and the central axis of the first dummy channel structure DCH1 can be spaced apart from each other by a third distance d3a.

[0108] The first end point e1a can be spaced apart from the channel structure CH closest to the second auxiliary separation region MS2b in the X direction by a fourth distance d4a. The first end point e1a can be spaced apart from the first end S1 of the uppermost gate electrode 130Su in the X direction by a fifth distance d5a.

[0109] In comparison with FIG. 3B the example embodiment, the second to fifth distances d2a, d3a, d4a, and / or d5a can be relatively increased. In comparison with FIG. 3B the example embodiment, the first angle θ1d can be relatively decreased. However, the changeable ranges of the second to fifth distances d2a, d3a, d4a, and / or d5a and the first angle θ1d can not deviate from the descriptions of the distances and angles described above with reference to FIG. 3B the example embodiment.

[0110] Referring to FIG. 6B In the semiconductor device 100b, the second auxiliary separation region MS2b can have a first end point e1 and a second end point e2 located on the opposite side in the X direction. The second end point e2 can be disposed to be spaced apart from the central axis of the dummy channel structure DCH disposed in the third upper pad region UP3 in the X direction, away from the first region R1. The second end point e2 can be spaced apart from the central axis of the dummy channel structure DCH disposed in the third upper pad region UP3 in the X direction by a sixth distance d6. The dummy channel structure DCH can be a dummy channel structure DCH disposed adjacent to the third upper contact plug MCu3.

[0111] The present example embodiment can be understood as an example embodiment of the semiconductor device 100b including the second auxiliary separation regions MS2b spaced apart from each other by a reduced distance in the X direction. Further, although not shown, the end point or edge portion of the second main separation region MS2a can be arranged to be spaced apart from the center axis of the adjacent dummy channel structure DCH by a predetermined or optionally desired distance in the X direction, as with the second auxiliary separation regions MS2b.

[0112] In the present example embodiment, the edge portion or end point at which the second auxiliary separation regions MS2b are spaced apart from each other in the X direction is provided to be spaced apart from the dummy channel structure DCH by a predetermined or optionally desired distance, in addition to the start point at which the second auxiliary separation regions MS2b begin to extend in the second region R2, thereby reducing or minimizing the pattern defect of the second auxiliary separation regions MS2b bending or protruding toward the dummy channel structure DCH.

[0113] Referring to FIG. 6C In the semiconductor device 100c, the pad region PAD can include a first upper pad region UP1, a second upper pad region UP2, a third upper pad region UP3, a fourth upper pad region UP4, and / or a fifth upper pad region UP5 extending the same length in the X direction.

[0114] In some example embodiments, the dummy channel structures DCH adjacent to the four corners can be respectively provided in one unit pad region. Each unit pad region can be connected to the contact plug MC, and the contact plug MC can include first to fifth contact plugs MCu1, MCu2, MCu3, MCu4, and / or MCu5 connected to the first to fifth upper pad regions UP1, UP2, UP3, UP4, and / or UP5, respectively.

[0115] In some example embodiments, the first edge portion eg1 and the first end point e1 of the second auxiliary separation regions MS2b need only be spaced apart from the first dummy channel structure DCH1 by a predetermined or optionally desired distance, and the positions of the dummy channel structures DCH, the contact plug MC, the lower separation region GS, and the gate ends S1, S2, S3, S4, and / or S5 or the length of one unit pad region can be understood as an example of the semiconductor device 100c which can be variously modified.

[0116] FIG. 7A to FIG. 7D is a cross-sectional view showing another modification of a semiconductor device according to some example embodiments of the present disclosure.

[0117] Referring to FIG. 7AThe semiconductor device 100d can include a memory cell region CELL and / or a peripheral circuit region PERI. The memory cell region CELL can be disposed at an upper end of the peripheral circuit region PERI. In some example embodiments, the memory cell region CELL can be disposed at a lower end of the peripheral circuit region PERI.

[0118] As described above with reference to FIG. 3A to FIG. 4C The memory cell region CELL can include the substrate 101, the substrate insulating layer 110, the gate electrode 130, the channel structure CH and / or the dummy channel structure DCH, the first separation region MS1 and the second separation regions MS2a and MS2b and / or the upper separation region SS, as described above with reference to FIG. 3B to FIG. 6C The memory cell region CELL can have a structure according to various example embodiments as described above with reference to

[0119] The peripheral circuit region PERI can include a base substrate 201, circuit elements 220 arranged on the base substrate 201, circuit contact plugs 270 and / or wiring 280.

[0120] The base substrate 201 can have an upper surface extending in the X-direction and the Y-direction. The base substrate 201 can be formed with a separate device isolation layer to define an active region. Source / drain regions 205 including impurities can be arranged in a portion of the active region. The base substrate 201 can include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor or a Group II-VI oxide semiconductor.

[0121] The circuit elements 220 can include planar transistors. Each circuit element 220 can include a circuit gate insulating layer 222, a spacer layer 224 and / or a circuit gate electrode 225. The source / drain regions 205 can be arranged in the base substrate 201 and on both sides of the circuit gate electrode 225.

[0122] A peripheral region insulating layer 290 can be disposed on the base substrate 201 and the circuit elements 220. The circuit contact plugs 270 can be connected to the source / drain regions 205 through the peripheral region insulating layer 290. Electrical signals can be applied to the circuit elements 220 through the circuit contact plugs 270. In a region not shown, the circuit contact plugs 270 can also be connected to the circuit gate electrodes 225. The wiring 280 can be connected to the circuit contact plugs 270 and can be arranged in multiple layers. In a region not shown, the gate electrodes 130 of the memory cell region CELL can be connected to the circuit elements 220 of the peripheral circuit region PERI through separate through regions that penetrate the peripheral circuit region PERI and through vias in the through regions.

[0123] In the semiconductor device 100d, after the peripheral circuit region PERI is first manufactured, the substrate 101 on which the memory cell region CELL is formed can be manufactured. The substrate 101 can have the same size as the base substrate 201, or can be formed to be smaller than the base substrate 201.

[0124] Referring to FIG. 7B , the semiconductor device 100e can further include the first horizontal conductive layer 104 and / or the second horizontal conductive layer 106 disposed on the upper surface of the substrate 101 and between the substrate 101 and the lowermost interlayer insulating layer 120. Further, in the semiconductor device 100e, the structure of the channel structure CHe can be different from that of the example embodiment of FIG. 3A to FIG. 4G , the first separation region MS1c and the second separation region MS2ac can be formed of the separation insulating layer 107, and the substrate insulating layer 110 can not be provided.

[0125] At least some of the first horizontal conductive layer 104 and / or the second horizontal conductive layer 106 can be used as part of a common source line of the semiconductor device 100e, and can also be used as the common source line together with the substrate 101. As shown in the enlarged view of FIG. 7B , the first horizontal conductive layer 104 can be directly connected to the channel layer 140 at the periphery of the channel layer 140. The first horizontal conductive layer 104 and / or the second horizontal conductive layer 106 can include a semiconductor material, such as polysilicon. In some example embodiments, at least the first horizontal conductive layer 104 can be a doped layer, and the second horizontal conductive layer 106 can be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 104. The first horizontal conductive layer 104 can be referred to as a source conductive layer.

[0126] The channel structure CHe can not include the epitaxial layer 105 (see FIG. 4C ), and have a structure in which the channel layer 140 extends to the lower end and is connected to the first horizontal conductive layer 104.

[0127] Referring to FIG. 7C , in the semiconductor device 100f, the stack structure of the gate electrode 130 is formed of the vertically stacked lower stack structure 130A and the upper stack structure 130B, and the channel structure CHf can include the vertically stacked first channel structure CH1 and the second channel structure CH2. When the number of the relatively stacked gate electrodes 130 is large, the structure of the channel structure CHf can be introduced to stably form the channel structure CHf. Further, in the semiconductor device 100f, the first separation region MS1d and the second separation region MS2ad can be formed of the separation insulating layer 107. The insulating layer 125 can be disposed between the lower stack structure 130A and the upper stack structure 130B.

[0128] The channel structure CHf can have a form in which the lower first channel structure CH1 and the upper second channel structure CH2 are connected, and can have a curved portion due to a width difference in the connection region. The channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 can be connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 1550 can be provided only at the upper end of the upper second channel structure CH2. However, in some example embodiments, each of the first channel structure CH1 and the second channel structure CH2 includes a channel pad 155. In some example embodiments, the channel pad 155 of the first channel structure CH1 can be connected to the channel layer 140 of the second channel structure CH2.

[0129] Referring to FIG. 7D , the semiconductor device 100g can further include a string selection channel structure SCH on the channel structure CH, string selection gate structures 180u and 180d arranged to surround a portion of sides of the string selection channel structure SCH, a pad portion 199 on the string selection channel structure SCH, and an upper cell region insulating layer 170u. The string selection channel structure SCH can include a string selection channel layer 190, a string selection channel insulating layer 196 inside the string selection channel layer 190, and / or a string selection channel pad 198 covering an upper surface of the string selection channel insulating layer 196 and connected to the string selection channel layer 190.

[0130] The string selection gate structures 180u and 180d can be provided on the channel structure CH. The string selection gate structures 180u and 180d constituting a string selection line can extend in the X direction and can be spaced apart from each other at regular intervals in the Y direction by a string gate separation region SSS. The string selection gate structures 180u and 180d can also be spaced apart from each other in the Y direction by first and second separation regions MS1 and MS2a and MS2b. The string selection gate structures 180u and 180d are gate electrodes of a string selection transistor and can correspond to FIG. 2 string selection lines SSL0 to SSL2 of FIG. 1. The string gate separation region SSS can be in the form of a line extending in the X direction or a rectangle, but can also be arranged in a zigzag form in one direction. The string selection gate structures 180u and 180d can include a semiconductor material such as polysilicon or single crystal silicon, and the semiconductor material can be an undoped material or a material containing p-type or n-type impurities. The number of string gate electrode layers forming the string selection gate structures 180u and 180d can be 1 or 2 or more, and can have a structure different from that of the gate electrode 130 of the memory cell M.

[0131] In some example embodiments, the string selection gate structures 180u and 180d can include a string selection gate electrode 180d and an erase gate electrode 180u that forms an erase transistor used in an erase operation using a gate-induced drain leakage (GIDL) phenomenon, but are not limited thereto.

[0132] The string selection channel structures SCH can be arranged to be spaced apart from each other while forming rows and columns on the stack structure of the gate electrodes 130, and can be arranged to overlap the channel structures CH. The string selection channel structures SCH can be arranged to form a lattice pattern, or can be arranged in a zigzag form in one direction. The string selection channel structures SCH can have a cylindrical shape, and can have an inclined side surface that narrows toward the substrate 101 according to an aspect ratio. The string selection channel structures SCH can penetrate the string selection gate structures 180u and 180d. The string selection channel layer 190 can be electrically insulated from the string selection gate structures 180u and 180d by the cell region insulating layer 170. The string selection channel structures SCH can have a maximum diameter that is smaller than a maximum diameter of the channel structures CH, but are not limited thereto.

[0133] FIG. 8A to FIG. 8D FIG. 1 is a cross-sectional view illustrating an example of a method for forming a semiconductor device according to some example embodiments of the present disclosure.

[0134] Referring to FIG. 8A In the second region R2, the substrate insulating layer 110 can be formed in the substrate 101.

[0135] A portion of the substrate 101 can be anisotropically etched to form a trench region. The trench region can have a width that decreases downward due to an aspect ratio. Next, the trench region can be filled with an insulating material, and a process of planarizing an upper surface of the substrate 101 can be performed.

[0136] The substrate insulating layer 110 can be formed in the second region R2 of the substrate 101, except for regions in which the first separation regions MS1 and the second separation regions MS2a and MS2b are located. The substrate insulating layer 110 can be formed in the second region R2 of the substrate 101 such that the substrate insulating layer 110 overlaps regions of each of the second separation regions MS2a and MS2b that are spaced apart from each other in the X direction in the Z direction.

[0137] The sacrificial layers 129 and the interlayer insulating layers 120 can be alternately stacked on the substrate 101. Portions of the sacrificial layers 129 and portions of the interlayer insulating layers 120 can be removed such that the sacrificial layers 129 extend different lengths in the X direction.

[0138] The sacrificial layers 129 can be layers that are replaced with the gate electrodes 130 by subsequent processes. The sacrificial layers 129 can be formed of a material that is etchable with selectivity with respect to the interlayer insulating layers 120. For example, the interlayer insulating layers 120 can be formed of at least one of silicon oxide and silicon nitride, and the sacrificial layers 129 can be formed of a material different from the interlayer insulating layers 120 selected from among silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the thicknesses of the interlayer insulating layers 120 can not be uniform. For example, the lowermost interlayer insulating layer 120 can be formed relatively thin, and the uppermost interlayer insulating layer 120 can be formed relatively thick. The thicknesses and the number of the interlayer insulating layers 120 and the sacrificial layers 129 can be variously changed from those shown.

[0139] In the second region R2, the photolithography process and the etching process can be repeatedly performed on the sacrificial layers 129 so that the upper sacrificial layers 129 are extended shorter than the lower sacrificial layers 129. Accordingly, the sacrificial layers 129 can have a stepped shape. According to some example embodiments, the material forming the sacrificial layers 129 can be further deposited in a region in which the sacrificial layers 129 are elongated longer than the upper sacrificial layers 129 and are exposed, so that the sacrificial layers 129 can be formed to have a relatively thick thickness at the end portion.

[0140] In the process of forming the sacrificial layers 129 and the interlayer insulating layers 120, after the lowermost sacrificial layer 129 is formed, a patterning process and a deposition process of an insulating material can be performed to form a lower separation region GS including a lower insulating layer 160 (see FIG. 2B). FIG. 4E ) The lower insulating layer 160 can be formed of a material having etching selectivity with respect to the sacrificial layers 129.

[0141] Referring to FIG. 8B The upper separation region SS can be formed, the cell region insulating layer 170 covering the stack structure of the sacrificial layers 129 and the interlayer insulating layers 120 can be formed, and the channel structure CH and the dummy channel structure DCH penetrating the stack structure of the sacrificial layers 129 and the interlayer insulating layers 120 can be formed.

[0142] After the sacrificial layers 129 and the interlayer insulating layers 120 are alternately stacked, a region in which the upper separation region SS is to be formed can be exposed using a separate mask layer, and a predetermined or optionally desired number of sacrificial layers 129 and interlayer insulating layers 120 can be removed from the uppermost portion. The upper separation region SS can extend below with respect to a region in which the string selection gate electrodes 130Su and 130Sd are formed, as FIG. 4CThe upper insulating layer 103 can be formed of a material having etch selectivity with respect to the sacrificial layer 129, and can be formed of, for example, the same material as the interlayer insulating layer 120.

[0143] The cell region insulating layer 170 can be formed to cover a portion of the upper surface of the substrate 101, the upper surface of the uppermost sacrificial layer 129 in the first region R1, and the upper surface of the sacrificial layer 129 forming a stepped shape in the second region R2.

[0144] The holes for forming the channel structure CH and / or the dummy channel structure DCH can be formed by anisotropically etching the sacrificial layer 129 and the interlayer insulating layer 120. Due to the height of the stack structure, the sidewalls of the holes for forming the channel structure CH and the dummy channel structure DCH can not be perpendicular to the upper surface of the substrate 101. The channel structure CH can be formed in the first region R1 of the substrate 101, and the dummy channel structure DCH can be formed in the second region R2. The dummy channel structure DCH can be formed to pass through at least a portion of the substrate insulating layer 110. In some example embodiments, the channel structure CH and the dummy channel structure DCH can be formed to be proximate to a portion of the substrate 101. However, according to some example embodiments, the dummy channel structure DCH can not pass completely through the substrate insulating layer 110, but only extend into the substrate insulating layer 110 so as not to be in contact with the substrate 101.

[0145] In the channel structure CH and the dummy channel structure DCH, the epitaxial layer 105, at least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and / or the channel pad 155 can be formed. Except for the dummy channel structure DCH, the dummy channel structure can also be formed in this process together with the channel structure CH when the dummy channel structure is further arranged together with the channel structure CH in the first region R1.

[0146] The epitaxial layer 105 can be formed using selective epitaxial growth (SEG). The epitaxial layer 105 can be formed of a single layer or multiple layers. The epitaxial layer 105 can include polysilicon, monocrystalline silicon, polygermanium, or monocrystalline germanium doped with impurities or not doped with impurities. In the dummy channel structure DCH, the epitaxial layer 105 can be formed such that its upper end is located in the substrate insulating layer 110 and at least a portion of its side surface is surrounded by the substrate insulating layer 110. Thus, in the dummy channel structure DCH, the epitaxial layer 105 is positioned to be spaced apart from the sacrificial layer 129.

[0147] The gate dielectric layer 145 can be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this process, all or some of the gate dielectric layer 145 can be formed, and a portion extending vertically along the channel structure CH and the dummy channel structure DCH to the substrate 101 can be formed in this process. The channel layer 140 can be formed on the gate dielectric layer 145 in the channel structure CH and the dummy channel structure DCH. The channel insulating layer 150 is formed to fill the channel structure CH and the dummy channel structure DCH and can be an insulating material. However, according to some example embodiments, a portion between the channel layers 140 can be filled with a conductive material instead of the channel insulating layer 150. The channel pad 155 can be formed of a conductive material, such as polysilicon.

[0148] Referring to FIG. 8C , an opening OP is formed through the stack structure of the sacrificial layer 129 and the interlayer insulating layer 120, and the sacrificial layer 129 can be removed through the opening OP.

[0149] The opening OP can be formed by forming a mask layer using a photolithography process and anisotropically etching the stack structure. Before the opening OP is formed, the cell region insulating layer 170 can be additionally formed on the channel structure CH and the dummy channel structure DCH to protect the lower structure. The opening OP can be formed in a trench shape at positions corresponding to the first separation region MS1 and the second separation regions MS2a and MS2b. Accordingly, the opening OP can be formed to extend in the X direction, some of the opening OPs can extend along the entire first region R1 and the second region R2, and other of the opening OPs can extend only in the second region R2. In this process, the substrate 101 can be exposed at a lower portion of the opening OP.

[0150] The sacrificial layer 129 can be selectively removed with respect to the interlayer insulating layer 120 using, for example, a wet etch. Accordingly, a plurality of side openings can be formed between the interlayer insulating layer 120, and some sidewalls of the gate dielectric layer 145 of the channel structure CH and side surfaces of the interlayer insulating layer 120 can be exposed through the side openings. In this operation, after the sacrificial layer 129 is removed, the stack structure of the interlayer insulating layer 120 can have lower stability, but the stack structure can be more stably supported by regions where the openings OP are spaced apart from each other and the dummy channel structure DCH.

[0151] Referring to FIG. 8D , the gate electrode 130 can be formed by filling the regions from which the sacrificial layer 129 is removed with a conductive material. Before the gate electrode 130 is formed, the diffusion barrier 133 can be formed in the regions from which the sacrificial layer 129 is removed.

[0152] The gate electrodes 130 can include a metal, polysilicon, or a metal silicide material. The openings OP can provide a transport path for the material forming the gate electrodes 130. The gate electrodes 130 can be connected to each other instead of being spaced apart from each other to form gate connection portions between the openings OP spaced apart from and aligned with each other in the X direction. After the gate electrodes 130 are formed, the material forming the gate electrodes 130 deposited in the openings OP can be removed by an additional process.

[0153] Next, reference will be made to FIG. 3B and FIG. 4A The separation insulating layer 107 and the conductive layer 109 can be formed in the openings OP.

[0154] The separation insulating layer 107 can include an insulating material, and the conductive layer 109 can further include a conductive material. Accordingly, the first separation region MS1 and the second separation regions MS2a and MS2b can be formed, and the first separation region MS1 and the second separation regions MS2a and MS2b can be formed in the same process operation to have the same structure as each other.

[0155] Thereafter, an upper wiring structure such as a channel contact plug 157 and a bit line can be further formed on the channel structure CH.

[0156] As described above, according to some example embodiments in the disclosure, by arranging the separation regions to be spaced apart from the dummy channel structure by a predetermined or optionally desired distance, defects of the pattern in which the separation regions are bent or protruded toward the dummy channel structure can be reduced or minimized. Accordingly, defects due to deposition of conductive residues near the gate electrode adjacent to the lower portion of the separation region can be reduced or prevented.

[0157] Although example embodiments have been shown and described above, it will be obvious to those skilled in the art that modifications and changes can be made without departing from the scope of the present disclosure as defined by the appended claims.

[0158] This application claims the benefit of priority of Korean Patent Application No. 10-2020-0039034, filed on March 31, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a substrate having a first region and a second region; a plurality of gate electrodes stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in the first region, and including a plurality of pad regions provided by some of the plurality of gate electrodes extending in a second direction perpendicular to the first direction at different lengths in the second region; a plurality of first separation regions penetrating the plurality of gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; a plurality of second separation regions penetrating the plurality of gate electrodes between the plurality of first separation regions, and including a second main separation region extending from the first region into the second region in the second direction and a second auxiliary separation region extending from the second region in the second direction and spaced apart from the second main separation region in the third direction; a plurality of channel structures penetrating the plurality of gate electrodes, extending vertically on the substrate, and arranged in the first region; and a plurality of dummy channel structures penetrating the plurality of gate electrodes, extending vertically on the substrate, and arranged in the second region, wherein the plurality of pad regions includes a first pad region provided by an uppermost first gate electrode among the plurality of gate electrodes and a second pad region provided by a second gate electrode below the first gate electrode, the plurality of dummy channel structures includes a pair of first dummy channel structures penetrating the first pad region and arranged adjacent to the first region and a pair of second dummy channel structures arranged adjacent to a first end of the first gate electrode, the second auxiliary separation region is arranged between the first pad regions adjacent to each other and has a first edge portion adjacent to the first dummy channel structure and a first end point on the first edge portion closest to the first region, a center axis of the first dummy channel structure is spaced apart from a center axis of the second dummy channel structure in the second direction by a first distance, the first edge portion of the second auxiliary separation region is spaced apart from the center axis of the first dummy channel structure in the second direction by a second distance smaller than the first distance, and a first channel structure closest to the second region among the plurality of channel structures is spaced apart from the first dummy channel structure in the second direction by a distance smaller than a distance by which the first channel structure is spaced apart from the first end point of the second auxiliary separation region in the second direction.

2. The semiconductor device according to claim 1, wherein the second distance is greater than one third of the first distance.

3. The semiconductor device according to claim 2, wherein the second pad region has a first length in the second direction, and the second distance is smaller than the first length.

4. The semiconductor device according to claim 1, wherein ​ A distance between the first end point of the second auxiliary separation region and the first end is smaller than a distance between the center axis of the first dummy channel structure and the first end.

5. The semiconductor device according to claim 1, wherein The second distance is 150 nm to 400 nm.

6. The semiconductor device according to claim 1, wherein A minimum distance between the first edge portion of the second auxiliary separation region and the center axis of the first dummy channel structure is 200 nm to 500 nm.

7. The semiconductor device according to claim 1, further comprising: an upper separation region penetrating between the plurality of first separation regions and including at least one gate electrode of the first gate electrode, and being in contact with the first end point of the second auxiliary separation region.

8. The semiconductor device according to claim 1, further comprising: a substrate insulating layer in the substrate between the first separation region and the second separation region in the second region, wherein the substrate insulating layer does not overlap with the plurality of first separation regions and the plurality of second separation regions in the first direction.

9. The semiconductor device according to claim 8, wherein the second auxiliary separation region has a first lower end point farther from the first region than the first end point on a horizontal plane between a lower end and an upper end of the substrate insulating layer, and the first lower end point of the second auxiliary separation region is spaced apart from the center axis of the first dummy channel structure in the second direction by a third distance greater than the second distance.

10. The semiconductor device according to claim 1, wherein each of the plurality of first separation regions and each of the plurality of second separation regions includes a conductive layer including a conductive material and a separation insulating layer covering a side surface of the conductive layer, and a structure of a cross section of the plurality of first separation regions in the third direction is identical to a structure of a cross section of the second auxiliary separation region in the third direction.

11. The semiconductor device according to claim 1, wherein the second auxiliary separation region has a portion in which a side surface is in the second direction from a plan view, and the portion of the second auxiliary separation region extends the first distance or more.

12. The semiconductor device according to claim 1, wherein the plurality of pad regions include a lower pad region, one intermediate pad region or a plurality of intermediate pad regions on the lower pad region, and a dummy pad region and an upper pad region on the one intermediate pad region or the plurality of intermediate pad regions, the one intermediate pad region or the plurality of intermediate pad regions have a stepped structure that is lowered in the second direction and lowered in the third direction, and the dummy pad region has a stepped structure of at least five steps in each of the second direction and the third direction.

13. The semiconductor device according to claim 1, further comprising: a first contact plug connected to the first pad region in the second region and between the pair of first dummy trench structures and the pair of second dummy trench structures, and the first end point of the second auxiliary separation region is closer to the first end than the first contact plug.

14. The semiconductor device of claim 1, wherein the pad region further includes a third pad region provided by a third gate electrode under the second gate electrode including the second pad region, the plurality of dummy trench structures further includes a third dummy trench structure on the third pad region, the second auxiliary separation region has a second end point located opposite the first end point in the second direction, and the second end point of the second auxiliary separation region is spaced apart from a center axis of the third dummy trench structure in the second direction.

15. A semiconductor device, comprising: a substrate having a first region and a second region; a plurality of gate electrodes stacked in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other in the first region, and including pad regions provided by different lengths of some of the plurality of gate electrodes extending in a second direction perpendicular to the first direction in the second region; a first separation region penetrating the gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; a second separation region penetrating the gate electrodes and extending in the second direction, the second separation region including a second main separation region extending from the first region into the second region in the second direction and a second auxiliary separation region extending from the second region in the second direction and spaced apart from the second main separation region in the third direction; and trench structures and dummy trench structures penetrating the gate electrodes, extending perpendicularly on the substrate, and arranged in the first region and the second region, respectively, wherein the pad region includes a first pad region and a second pad region arranged in the second direction from the first region in order, a first edge portion of the second auxiliary separation region adjacent to the first region is spaced apart from a center axis of the dummy trench structure penetrating the first pad region and adjacent to the first edge portion by a first distance in the second direction, the first distance is greater than a maximum width of the dummy trench structure, and a first trench structure closest to the second region among the trench structures is spaced apart from a first dummy trench structure closest to the first region among the dummy trench structures by a distance in the second direction that is smaller than a distance by which the first trench structure is spaced apart from the first edge portion of the second auxiliary separation region in the second direction.

16. The semiconductor device of claim 15, wherein the dummy trench structures penetrating the first pad region are spaced apart from each other by a second distance in the second direction, and the second distance is greater than the maximum width of the dummy trench structure. The first distance is greater than one third of the second distance.

17. The semiconductor device according to claim 15, wherein the dummy trench structure includes the first dummy trench structure adjacent to the first region and a second dummy trench structure adjacent to one end of the first pad region, a first extension line passing through the first edge portion in the second direction and a second extension line passing through a center axis of the first dummy trench structure and the first edge portion form a first angle, and the first angle is less than 40°.

18. The semiconductor device according to claim 15, wherein the second separation region has a width decreasing toward an upper surface of the substrate in the second direction and the third direction, and a distance between the first edge portion of the second separation region and the center axis of the dummy trench structure increases toward the substrate.

19. The semiconductor device according to claim 15, wherein a structure of a cross section of the first separation region in the third direction is identical to a structure of a cross section of the second separation region in the third direction.

20. A semiconductor device comprising: a substrate having a first region and a second region; gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending and having different lengths in a second direction perpendicular to the first direction in the second region; first separation regions penetrating the gate electrodes in the first region and the second region, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction; second separation regions penetrating the gate electrodes, extending in the second direction between the first separation regions and spaced apart from each other in the second direction, the second separation regions including a second main separation region extending in the second direction from the first region into the second region and a second auxiliary separation region extending in the second direction from the second region and spaced apart from the second main separation region in the third direction; a trench structure penetrating the gate electrodes in the first region; and a first vertical structure penetrating the gate electrodes in the second region and closest to the first region, wherein a width of the second separation region in the third direction is greater than a width of the first vertical structure, a first end point of the second auxiliary separation region adjacent to the first region is spaced apart from a center axis of the first vertical structure in the second direction and farther from the first region than the center axis of the first vertical structure, and a first trench structure closest to the second region among the trench structures is spaced apart from the first vertical structure in the second direction by a distance smaller than a distance by which the first trench structure is spaced apart from the first end point of the second auxiliary separation region in the second direction. ​

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