Semiconductor device

Abstract

A semiconductor device includes a substrate having a first conductivity type, a high voltage well having a second conductivity type formed in the substrate, a source well formed in the substrate on a side of the high voltage well, a drain well formed in the high voltage well, an isolation layer formed over the high voltage well between the source well and the drain well, a gate layer formed over the substrate and extending continuously from over an edge portion of the source well to over an edge portion of the isolation layer, a source region formed in the source well alongside the gate layer, a drain region formed in the drain well, and at least one floating conductor layer formed over the isolation layer. A distance between the floating conductor layer and the drain region is less than a distance between the floating conductor layer and the source region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a floating conductor layer. Background Technology

[0002] Ultra-high voltage (ultra-HV) semiconductor devices are widely used in display components, portable devices, and other diverse applications. The goals of ultra-high voltage semiconductor devices include high breakdown voltage, low specific on-resistance (Ron), and high reliability at both room temperature and high temperature environments.

[0003] However, with the expanding applications of ultra-high voltage semiconductor devices, the search for higher breakdown voltages has become a current research focus. Summary of the Invention

[0004] The present invention provides a semiconductor device having a floating conductor layer, which can increase the breakdown voltage by more than 500V by reducing the characteristic on-resistance (Ron).

[0005] The semiconductor device of the present invention includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type, a source well having a first conductivity type, a drain well having a second conductivity type, an isolation layer, a gate layer, a source region, a drain region, and at least one floating conductor layer. The high-voltage well is formed in the substrate, the source well is formed in the substrate on one side of the high-voltage well, the drain well is formed in the high-voltage well, the isolation layer is formed above the high-voltage well between the source well and the drain well, the gate layer is formed above the substrate and extends continuously from above the edge portion of the source well to above the edge portion of the isolation layer, the source region is formed in the source well next to the gate layer, and the floating conductor layer is formed above the isolation layer. The distance between the floating conductor layer and the drain region is less than the distance between the floating conductor layer and the source region.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0008] Figure 2 yes Figure 1 A cross-sectional schematic diagram of a semiconductor device along line segment II-II′.

[0009] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0010] Figure 4 yes Figure 2 The electric field distribution diagram beneath the isolation layer of a semiconductor device.

[0011] Figure 5 This is a breakdown voltage curve of Experimental Example 1 and Comparative Example 1 as a function of the dose ratio of the N-type high-voltage trap.

[0012] Figure 6 This is a breakdown voltage curve of Experimental Example 2 and Comparative Example 2 as the dose ratio of the P-type top region changes.

[0013] Figure 7 The Ron curves are for Experiment 1 and Experiment 2, and for N-type high-voltage traps and P-type top regions without floating conductor layers, where the doses are standard values.

[0014] [Symbol Explanation]

[0015] 10: Semiconductor devices

[0016] 100: Substrate

[0017] 102: High-pressure trap

[0018] 104: Source trap

[0019] 104a, 108a: Edge portion

[0020] 106: Drain trap

[0021] 108: Isolation layer

[0022] 110: Gate layer

[0023] 112: Source Region

[0024] 114: Drain region

[0025] 116, 300a, 300b: Floating conductor layer

[0026] 118: First doped region

[0027] 120: Second doped region

[0028] 122: Field Oxide Layer

[0029] 124: Drift Zone

[0030] 126: Top Zone

[0031] 128: Gradient Region

[0032] 400: Rise Zone

[0033] s1, s2: Distance

[0034] t1, t2: thickness

[0035] w1, w2, w3: Width Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0037] The following provides many different implementations or embodiments for carrying out various features of the invention. Moreover, these embodiments are merely illustrative and are not intended to limit the scope and application of the invention. Furthermore, for clarity, the relative dimensions (e.g., length, thickness, spacing, etc.) and relative positions of various regions or structural elements may be reduced or enlarged. Additionally, similar or identical element symbols are used in the various drawings to represent similar or identical elements or features.

[0038] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 yes Figure 1 A cross-sectional schematic diagram of a semiconductor device along line segment II-II′.

[0039] Please refer to Figure 1 and Figure 2The semiconductor device 10 of this embodiment includes a substrate 100 having a first conductivity type, a high-voltage well 102 having a second conductivity type, a source well 104 having a first conductivity type, a drain well 106 having a second conductivity type, an isolation layer 108, a gate layer 110, a source region 112, a drain region 114, and at least one floating conductor layer 116. In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type. In another embodiment, the first conductivity type is N-type and the second conductivity type is P-type. The substrate 100 is a semiconductor substrate, for example, formed of bulk silicon, an epitaxial layer, or silicon-on-insulator (SOI) material. In this embodiment, the semiconductor device 10 can be a laterally diffused metal-oxide-semiconductor field-effect transistor (MOSFET) device, and can be applied to mix-mode circuit design or simulation circuit design, such as LED lighting, energy-saving lamps, ballasts, motor drivers, etc. A high-voltage well 102 is formed in the substrate 100, a source well 104 is formed in the substrate 100 on one side of the high-voltage well 102, and a drain well 106 is formed in the high-voltage well 102. In one embodiment, the source well 104 and the high-voltage well 102 are adjacent to each other. The aforementioned source region 112 is formed in the source well 104 next to the gate layer 110, and the source region 104 includes a first heavily doped region 118 of a first conductivity type and a second heavily doped region 120 of a second conductivity type, the second heavily doped region 120 being formed between the first heavily doped region 118 and the gate layer 110.

[0040] The isolation layer 108 is formed above the high-voltage well 102 between the source well 104 and the drain well 106. An isolation structure such as a field oxide (FOX) layer 122 is provided outside the active region or oxide-defined (OD) region. These isolation structures and the isolation layer 108 can be fabricated in the same thermal oxidation step. However, the invention is not limited to this; the isolation structure can also be replaced with a localized silicon oxide (LOCOS) layer or a shallow channel isolation (STI) structure. In one embodiment, the isolation layer 108 partially overlaps with the drain well 106 and is separated from the source well 104.

[0041] The gate layer 110 is formed above the substrate 100 and extends continuously from above the edge portion 104a of the source well 104 to above the edge portion 108a of the isolation layer 108. A gate oxide layer (not shown) is generally disposed between the gate layer 110 and the substrate 100, and spacer walls (not shown) may be formed on the sidewalls of the gate layer 110. The material of the gate layer 110 may be polysilicon or other suitable conductive materials.

[0042] The floating conductor layer 116 is formed above the isolation layer 108, and the distance s1 between the floating conductor layer 116 and the drain region 114 is smaller than the distance s2 between the floating conductor layer 116 and the source region 112; that is, the floating conductor layer 116 is closer to the drain region 114 and farther from the source well 104. Because the electrically floating conductor layer 116 is provided above the isolation layer 108, when an ultra-high voltage (e.g., above 500V) is applied to the drain region 114, the electric field distribution below the isolation layer 108 will be as follows: Figure 4 As shown, by maintaining a small, fixed electric field in the source region 112 through the presence of the floating conductor layer 116, voltage spikes can be avoided and Ron can be reduced, thus further increasing the breakdown voltage. In contrast, the electric field distribution without the floating conductor layer will show a significant spike region 400. In one embodiment, the distance s1 between the floating conductor layer 116 and the drain region 114 can be maintained at more than 1 μm, more than 4 μm in one embodiment, and more than 8 μm in another embodiment. Combined with a floating conductor layer 116 with a width w1 of approximately 4 μm, the breakdown voltage can reach more than 500V. In one embodiment, the width w1 of the floating conductor layer 116 is the width w2 of the isolation layer 108 (see...). Figure 1 The thickness t1 of the floating conductor layer 116 is 0.2 to 0.3 times, for example, 0.22 to 0.3 times, of the thickness t2 of the isolation layer 108. The material of the floating conductor layer 116 includes polysilicon or metal (e.g., aluminum); if it is polysilicon, the floating conductor layer 116 can be formed simultaneously with the gate layer 110, thus avoiding additional steps. However, the invention is not limited thereto.

[0043] exist Figure 2 In this embodiment, the semiconductor device 10 may further include a drift region 124 formed in the high-voltage well 102 below the isolation layer 108. In this embodiment, the drift region 124 includes a top region 126 having a first conductivity type and a grade region 128 having a second conductivity type, the grade region 128 being formed between the isolation layer 108 and the top region 126. In one embodiment, the grade region 128 may extend beyond the isolation layer 108 and be connected to the gate layer 110. Furthermore, the drift region 124 may be located directly below the floating conductor layer 116 or partially overlap with the floating conductor layer 116.

[0044] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention, wherein the component symbols of the previous embodiment are used to represent the same or similar components, and the description of the same components can be referred to the relevant content of the previous embodiment, and will not be repeated here.

[0045] exist Figure 3In this configuration, two floating conductor layers 300a and 300b are formed above the isolation layer 108. The distance s1 between the floating conductor layer 300b and the drain region 114 is smaller than the distance s2 between the floating conductor layer 300a and the source region 112, and the distance s1 can be maintained above 1 μm, for example, above 8 μm. In other words, if the floating conductor layers 300a and 300b are considered as a single unit, even though they are not coupled to each other, they are generally closer to the drain region 114 and farther from the source-well 104. Although Figure 3 The two floating conductor layers 300a and 300b shown are not limited to this invention. The number of floating conductor layers can also be greater than two, such as three, four, etc. The width w3 of the floating conductor layers 300a and 300b can be 0.025 to 0.37 times the width w2 of the isolation layer 108.

[0046] Several experiments are listed below to more specifically verify the technical effects of the semiconductor device of the present invention. However, without departing from the scope of protection of the present invention, the materials used, quantities, size ratios, parameters, and measurement methods, etc., can be appropriately changed. Therefore, the present invention should not be interpreted as limiting based on the experiments described below.

[0047] <Experimental Example 1>

[0048] Production Figure 2 The semiconductor device shown has a standard dose (STD) of 3.5E12 / cm for the N-type high-voltage well (102). 2 The standard dose (STD) for the P-type top region (126) is 8E12 / cm². 2 The distance (s1) between the floating conductor layer and the drain region was fixed at 8 μm. Then, the widths of the floating conductor layer in the polysilicon were 4 μm, 6 μm, and 8 μm, and the breakdown voltage (BVD) was measured under varying dose ratios of the N-type high-voltage sink. The results are shown in... Figure 5 .

[0049] <Experimental Example 2>

[0050] Production Figure 2 The semiconductor device shown has a polysilicon floating conductor layer with a thickness of approximately The thickness of the silicon oxide insulating layer is approximately The standard dose (STD) for an N-type high-pressure trap (102) is 3.5E12 / cm². 2 The standard dose (STD) for the P-type top region (126) is 8E12 / cm². 2The distance (s1) between the floating conductor layer and the drain region was fixed at 8 μm. Then, the widths of the floating conductor layer in the polycrystalline silicon were 4 μm, 6 μm, and 8 μm, and the breakdown voltage was measured under varying dose ratios in the P-type top region. The results are shown in... Figure 6 .

[0051] <Comparative Example 1>

[0052] Production Figure 2 The semiconductor device shown is identical to that in Experimental Example 1, but without the floating conductor layer. The breakdown voltage was measured under varying dose ratios of the N-type high-voltage sink, and the results are shown in [the table / image / etc.]. Figure 5 .

[0053] <Comparative Example 2>

[0054] Production Figure 2 The semiconductor device shown is identical to that in Experimental Example 2, but without a floating conductor layer. The breakdown voltage was measured under varying dose ratios in the P-type top region. The results are shown in... Figure 6 .

[0055] from Figure 5 It can be seen that the breakdown voltage of Experimental Example 1 with the floating conductor layer increases with the increase of the dose of the N-type high-voltage trap, indicating that the charge of n is greater than the charge of p (Qn>Qp), which can increase the breakdown voltage; from Figure 6 It can be seen that the breakdown voltage of Experimental Example 2 with the floating conductor layer increases with the decrease of the dose in the P-type top region, which also indicates that Qn>Qp can increase the breakdown voltage. In contrast, Comparative Examples 1 and 2 without the floating conductor layer did not show the above trend.

[0056] <Ron Analysis>

[0057] The Ron values ​​obtained in Experiments 1-2 (floating conductor layer width 4 μm) for N-type high-voltage traps with breakdown voltages exceeding 500 V (+7%) and P-type top region (-9%) are recorded together with the Ron values ​​obtained in the N-type high-voltage traps and P-type top regions without floating conductor layers, where both doses are standard values. Figure 7 .from Figure 7 The Ron measured three times shows that, with a floating conductor layer, a standard dose of +7% for the N-type high-voltage sink or -9% for the P-type top region can improve Ron by more than 5%. Therefore, it is inferred that simultaneously adjusting the dose of the N-type high-voltage sink and the dose of the P-type top region can further reduce Ron.

[0058] In summary, the present invention provides a floating conductor layer above the isolation layer, so that when ultra-high voltage (such as above 500V) is applied to the drain region, the electric field distribution can be maintained at a fixed level due to the presence of the floating conductor layer, and then increase towards the source region. Therefore, it can avoid voltage surges and reduce Ron, thereby increasing the breakdown voltage, which is beneficial for the application of ultra-high voltage components.

[0059] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A semiconductor device comprising: a substrate having a first conductivity type; a high voltage well having a second conductivity type and formed in the substrate; a source well having the first conductivity type and formed in the substrate on a side of the high voltage well, the source well and the high voltage well being adjacent to each other; a drain well having the second conductivity type and formed in the high voltage well; an isolation layer formed over the high voltage well between the source well and the drain well; a gate layer formed over the substrate and continuously extending from over an edge portion of the source well to over an edge portion of the isolation layer; a source region formed in the source well beside the gate layer; a drain region formed in the drain well; and at least one floating conductor layer formed over the isolation layer, and a distance between the floating conductor layer and the drain region is smaller than a distance between the floating conductor layer and the source region; a drift region formed in the high voltage well under the isolation layer, the drift region having a top region of the first conductivity type and a gradient region of the second conductivity type formed between the isolation layer and the top region, the gradient region extending out of the isolation layer and being in contact with the gate layer.

2. The semiconductor device according to claim 1, wherein the at least one floating conductor layer includes two or more floating conductor layers.

3. The semiconductor device according to claim 1, wherein the distance between the floating conductor layer and the drain region is 1 μm or more.

4. The semiconductor device according to claim 1, wherein a width of the at least one floating conductor layer is 0.025 to 0.8 times a width of the isolation layer.

5. The semiconductor device according to claim 1, wherein a thickness of the at least one floating conductor layer is 0.22 to 0.3 times a thickness of the isolation layer.

6. The semiconductor device according to claim 1, wherein a material of the floating conductor layer includes polysilicon or metal.

7. The semiconductor device according to claim 1, wherein the drift region is located directly below the floating conductor layer.

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