A switching power supply low current detection circuit and a switching power supply low current control method

Abstract

The present invention relates to the technical field of switching power supplies, and specifically to a switching power supply low-current detection circuit and a switching power supply low-current control method, comprising a display screen; a filter capacitor COUT, the filter capacitor COUT is connected to the two ends of the switching power supply; a voltage sampling circuit, the voltage sampling circuit is connected to the two ends of the filter capacitor COUT and is used to collect voltage signals; a first comparator COMP1, one input end of the first comparator COMP1 is connected to the FB signal end of the voltage sampling circuit, and the other two input ends of the first comparator COMP1 are respectively connected to corresponding reference voltage REFH and REFL ends; a pulse conversion circuit, the pulse conversion circuit is connected to the output end of the first comparator COMP1, and the pulse conversion circuit is used to convert a PULSE pulse signal output by the first comparator COMP1 into a RAMP voltage signal.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a switching power supply low-current detection circuit and a switching power supply low-current control method. Background Art

[0002] In battery-powered switching power supply applications such as mobile power supplies and Bluetooth headset charging boxes, due to the limited battery capacity, it is necessary to shut down the switching power supply system after the output load current decreases to a certain value to reduce system power consumption and extend the standby time of such products.

[0003] There are generally two ways in the existing technology to detect whether the load current of the switching power supply is lower than the set critical value. The first way is to directly connect a precision power resistor in series in the load path and directly detect the voltage on the power resistor. This method has several disadvantages. First, the precision power resistor is expensive, which increases the system cost. Second, the power resistor will have a large power loss, which reduces the system efficiency. Third, under low current conditions, the voltage drop of the power resistor is very small, and a high-precision comparator is required to detect the voltage of the resistor, which increases the design difficulty and cost of the detection circuit. The second way is to judge by detecting the rate at which the output voltage drops during the off period TOFF of the switching power supply in burst mode, that is, Where ΔV is the peak-to-peak value of the output voltage ripple in light load mode, COUT is the output filter capacitor of the switching power supply, and TOFF is the duration of the shutdown cycle. The disadvantage of this method is that the current critical value is proportional to the capacitance of the capacitor COUT. When different COUT capacitance values ​​need to be selected according to the characteristics of the solution in different application solutions, the current critical value has to change with the change of COUT capacitance. Summary of the invention

[0004] The purpose of the present invention is to provide a switching power supply low current detection circuit and a switching power supply low current control method to solve the problem that the current critical value is proportional to the capacitance value of the capacitor COUT. When different COUT capacitance values ​​need to be selected according to the characteristics of the scheme in different application schemes, the current critical value has to change with the change of COUT capacitance value.

[0005] To achieve the above-mentioned purpose, the present invention is widely used in technical solutions for small current detection, and in particular provides the following technical solutions: a small current detection circuit for a switching power supply, comprising:

[0006] A filter capacitor COUT, wherein the filter capacitor COUT is connected to two ends of the switching power supply;

[0007] A voltage sampling circuit, wherein the voltage sampling circuit is connected to both ends of the filter capacitor COUT and is used to collect a voltage signal;

[0008] A first comparator COMP1, wherein one input terminal of the first comparator COMP1 is connected to the FB signal terminal of the voltage sampling circuit, and the other two input terminals of the first comparator COMP1 are respectively connected to corresponding reference voltage REFH and REFL terminals;

[0009] A pulse conversion circuit, the pulse conversion circuit is connected to the output end of the first comparator COMP1, and the pulse conversion circuit is used to convert the PULSE pulse signal output by the first comparator COMP1 into a RAMP voltage signal;

[0010] A second comparator COMP2, wherein one output terminal of the second comparator COMP2 is connected to one output terminal of the pulse conversion circuit, and the other output terminal of the second comparator COMP2 is connected to another reference voltage REF3;

[0011] A delay circuit is connected to the output terminal of the second comparator COMP2 and is used to output a low current signal.

[0012] Preferably, the voltage sampling circuit includes a circuit composed of resistors R1 and R2 or a sampling circuit composed of an integrated circuit.

[0013] Preferably, the pulse conversion circuit includes a pulse conversion circuit composed of a current source I1, a current source I2, a PMOS transistor MP1, an NMOS transistor MN1, and a capacitor C1.

[0014] Preferably, one end of the current source I2 is connected to the external power supply VDD, the other end of the current source I2 is connected to the source of the PMOS transistor MP1, the drain of the PMOS transistor MP1 is connected to the source of the NMOS transistor MN1, and is respectively connected to one end of the capacitor C1 and an input end of the second comparator COMP2; the drain of the NMOS transistor MN1 is respectively connected to the other end of the capacitor C1 and is grounded via the current source I1, and the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 are both connected to the output end of the first comparator COMP1.

[0015] Preferably, the current magnitude ratio of the current source I1 and the current source I2 is set to adjust the required small current detection critical value.

[0016] The control method of the small current according to the above circuit comprises the following steps:

[0017] Step S1: adjusting the critical value of the required small current detection by setting the ratio of the current source I1 and the current source I2;

[0018] Step S2: When the output load current of the switching power supply is small, the switching power supply operates in a burst mode, and the working cycle of the switching power supply is a normal switching cycle TON and an off cycle TOFF;

[0019] During the TON stage, the current source I1 discharges the capacitor C1, causing the RAMP voltage to decrease by:

[0020] During the TOFF stage, the current source I2 charges the capacitor C1, causing the RAMP voltage to increase by:

[0021] Step S3: In the small-load current stage, according to different magnitudes of the load current, the small current is set for the first small-current stage and the second small-current stage.

[0022] Step S4: In the first small-current stage, when the switching power supply TON > TOFF, that is, K = TON / TOFF > 1, according to the calculation formulas of ΔV1 and ΔV2, the decrease value ΔV1 of the RAMP voltage in each period is greater than the increase value ΔV2 of the RAMP voltage. Therefore, the RAMP voltage is always lower than the reference voltage REF3, and the second comparator COMP2 outputs a low level, so the switching power supply continues to operate in the current state.

[0023] Step S5: In the second small-current stage, when the switching power supply TON < TOFF, that is, K = TON / TOFF < 1, according to the above calculation formulas of ΔV1 and ΔV2, the decrease value ΔV1 of the RAMP voltage in each period is less than the increase value ΔV2 of the RAMP voltage. Therefore, the RAMP voltage gradually increases. When the RAMP voltage is greater than the reference voltage REF3, the second comparator COMP2 outputs a high level, so the small-current signal output is valid, and the switching power supply is controlled to shut down.

[0024] Preferably, in step S3, the load current in the first small-current stage is greater than the critical value of current detection, and the load current in the second small-current stage is less than the critical value of current detection, then the currents of the current source I1 and the current source I2 are equal.

[0025] Conversely, when the load current in the first small-current stage is less than the critical value of current detection and the load current in the second small-current stage is greater than the critical value of current detection, the currents of the current source I1 and the current source I2 are not equal.

[0026] Preferably, in the said step S4, the second comparator COMP2 outputs a low level, which is filtered by the delay circuit to eliminate the influence of short-term load current changes. After being delayed by the delay circuit, the low-current signal also outputs low, that is, the low-current signal is invalid.

[0027] Preferably, in the said step S5, the second comparator COMP2 outputs a high level. After being delayed by the delay circuit, the low-current signal outputs high, that is, the low-current signal is valid.

[0028] Compared with the prior art, the beneficial effects of the present invention are:

[0029] The present invention converts the output voltage waveform of the switching power supply into a PULSE pulse signal with a ratio of K=TON / TOFF, and then determines whether the output current of the switching power supply is lower than a set critical value by determining the value of the K value; the method does not require a traditional precision power detection resistor and a high-precision comparator, and the detection current critical value is also independent of the capacitance value of the output filter capacitor of the switching power supply, and the working state of the switching power supply can also be controlled by a small current control method. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The schematic diagram of the switching power supply low current detection circuit of the present invention is as follows:

[0031] Figure 2 It is a schematic flow chart of the small current control method of the present invention;

[0032] Figure 3 It is a schematic diagram of the low current stage 1 and the low current stage 2 of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] See also Figure 1-Figure 3 , an embodiment provided by the present invention:

[0035] A switching power supply low current detection circuit, a switching power supply output filter capacitor COUT 1, a low current detection unit 2;

[0036] A voltage sampling circuit 201, which is connected to both ends of the filter capacitor COUT and is used to collect voltage signals;

[0037] A first comparator COMP1 202, wherein one input terminal of the first comparator COMP1 202 is connected to the FB signal terminal of the voltage sampling circuit 201, and the other two input terminals of the first comparator COMP1 202 are respectively connected to corresponding reference voltage REFH and REFL terminals;

[0038] A pulse conversion circuit 203, wherein the pulse conversion circuit 203 is connected to the output terminal of the first comparator COMP1 202, and the pulse conversion circuit 203 is used to convert the PULSE pulse signal output by the first comparator COMP1 202 into a RAMP voltage signal;

[0039] A second comparator COMP2 204, wherein one output terminal of the second comparator COMP2 204 is connected to one output terminal of the pulse conversion circuit 203, and another output terminal of the second comparator COMP2 204 is connected to another reference voltage REF3;

[0040] The delay circuit 205 is connected to the output terminal of the second comparator COMP2 204 and is used to output a low current signal.

[0041] The voltage sampling circuit 201 includes a sampling circuit formed by a resistor R1 and a resistor R2 or an integrated circuit.

[0042] The pulse conversion circuit 203 includes a current source I1, a current source I2, a PMOS transistor MP1, an NMOS transistor MN1, and a capacitor C1.

[0043] One end of the current source I2 is connected to the external power supply VDD, and the other end of the current source I2 is connected to the source of the PMOS transistor MP1. The drain of the PMOS transistor MP1 is connected to the source of the NMOS transistor MN1, and is respectively connected to one end of the capacitor C1 and an input end of the second comparator COMP2 204; the drain of the NMOS transistor MN1 is respectively connected to the other end of the capacitor C1 and is grounded through the current source I1, and the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 are both connected to the output end of the first comparator COMP1 202.

[0044] The current magnitude ratio of the current source I1 and the current source I2 is set to adjust the required small current detection threshold.

[0045] Here, the current source I1 is equal to the current source I2 for example. Figure 1 and Figure 3 When the switching power supply outputs a large load current, the output voltage VOUT is a DC voltage without a low-frequency triangle wave. The FB voltage detected by the sampling circuit is always lower than the input reference voltages REFH and REFL of the first comparator COMP1 202, PULSE is always at a high level, the NMOS transistor MN1 is turned on, the PMOS transistor MP1 is turned off, the current source I1 discharges the positive electrode RAMP of the capacitor C1 through MN1, RAMP is always at a low level, the second comparator COMP2 204 outputs a low level, the output low current signal of the delay circuit 205 is also always at a low level, the low current signal is invalid, and the system is always in a working state.

[0046] refer to Figure 2 , Figure 3 A switching power supply low current control method shown includes the following steps:

[0047] Step S1; Adjust the critical value of the required small current detection by setting the ratio of current source I1 and current source I2.

[0048] Step S2; When the load current output by the switching power supply is small, the switching power supply operates in the burst mode, and the working cycle of the switching power supply is the normal on-time TON and off-time TOFF.

[0049] During the TON stage, the current source I1 discharges the capacitor C1, and the decrease value of the RAMP voltage is:

[0050] During the TOFF stage, the current source I2 charges the capacitor C1, and the increase value of the RAMP voltage is:

[0051] Step S3; In the small load current stage, according to different magnitudes of the load current, set the small current for the first small current stage and the second small current stage.

[0052] Step S4; In the first small current stage, when the on-time TON of the switching power supply is greater than the off-time TOFF, that is, K = TON / TOFF > 1, according to the calculation formulas of ΔV1 and ΔV2, the decrease value of the RAMP voltage ΔV1 per cycle is greater than the increase value of the RAMP voltage ΔV2. Therefore, the RAMP voltage is always lower than the reference voltage REF3, and the second comparator COMP2 204 outputs a low level, then the switching power supply continues to operate in the current state.

[0053] Step S5; In the second small current stage, when the on-time TON of the switching power supply is less than the off-time TOFF, that is, K = TON / TOFF < 1, according to the above calculation formulas of ΔV1 and ΔV2, the decrease value of the RAMP voltage ΔV1 per cycle is less than the increase value of the RAMP voltage ΔV2. Therefore, the RAMP voltage gradually increases. When the RAMP voltage is greater than the reference voltage REF3, the second comparator COMP2 204 outputs a high level, then the small current signal output is valid, and the switching power supply is controlled to shut down.

[0054] In step S3, the load current in the first small current stage is greater than the critical value of the current detection, and the load current in the second small current stage is less than the critical value of the current detection, then the currents of current source I1 and current source I2 are equal.

[0055] On the contrary, when the load current in the first small current stage is less than the critical value of the current detection and the load current in the second small current stage is greater than the critical value of the current detection, then the currents of current source I1 and current source I2 are not equal.

[0056] In step S4, the second comparator COMP2 204 outputs a low level, and the delay circuit 205 filters the influence of short-term load current changes. After the delay circuit 205 delays, the low current signal is also output as low, that is, the low current signal is invalid.

[0057] In step S5, the second comparator COMP2 204 outputs a high level, and after being delayed by the delay circuit 205, the low current signal output is high, that is, the low current signal is valid.

[0058] refer to Figure 3 Specifically, when the output load current of the switching power supply is small, the switching power supply operates in burst mode. The working cycle of the switching power supply is divided into a normal switching cycle TON and a shutdown cycle TOFF. The output voltage VOUT is a triangular wave. After the sampling circuit samples the VOUT voltage and divides it by resistors R1 and R2, the FB voltage is also a triangular wave.

[0059] In the TON period, the switching power supply performs normal switching action. Since the load current is very small, the output voltage VOUT gradually increases, and the sampling voltage FB also increases accordingly. When the FB voltage is higher than the input reference voltage REFH of the first comparator COMP1 202, the switching power supply switches from the TON period to the TOFF period, PULSE becomes a low level, the NMOS transistor MN1 is turned off, the PMOS transistor MP1 is turned on, the current source I2 passes, and the PMOS transistor MP1 charges the positive electrode RAMP of the capacitor C1, and the RAMP voltage gradually increases;

[0060] At the same time, during the TOFF period, the switching power supply stops switching, and the output voltage VOUT is maintained by the capacitor COUT. The VOUT voltage gradually decreases, and the sampling voltage FB also decreases accordingly.

[0061] When the FB voltage is lower than the input reference voltage REFL of the first comparator COMP1 202, the switching power supply switches from the TOFF cycle to the TON cycle, PULSE becomes high level, the NMOS transistor MN1 is turned on, the PMOS transistor MP1 is turned off, and the current source I1 discharges to the positive electrode RAMP of the capacitor C1 through MN1.

[0062] In the TON phase, I1 discharges capacitor C1, causing the RAMP voltage to decrease by:

[0063] During the TOFF phase, I2 charges capacitor C1, causing the RAMP voltage to increase by:

[0064] In the small-load current stage, according to different magnitudes of the load current, the ratio of TON to TOFF is different. The smaller the current, the smaller TON and the larger TOFF. To better illustrate the detection principle of the present invention, the small-load current stage is divided into two stages for illustration herein;

[0065] The load current in the first small-current stage is greater than the current detection critical value, and the load current in the second small-current stage is less than the current detection critical value. Since it is set herein that the current of current source I1 is equal to the current of current source I2,

[0066] In the first small-current stage; TON > TOFF, that is, K = TON / TOFF > 1. From the above calculation formulas of ΔV1 and ΔV2, it can be known that the decrease value ΔV1 of the RAMP voltage in each period is greater than the increase value ΔV2 of the RAMP voltage. Therefore, the RAMP voltage is always lower than the reference voltage REF3, and the second comparator COMP2 204 outputs a low level. To filter out the influence of short-time load current changes, a delay circuit 205 is added here. After being delayed by the delay circuit 205, the low-current signal also outputs low, that is, the low-current signal is invalid, and the switching power supply continues to work in the current state.

[0067] In the first small-current stage, TON < TOFF, that is, K = TON / TOFF < 1. From the above calculation formulas of ΔV1 and ΔV2, it can be known that the decrease value ΔV1 of the RAMP voltage in each period is less than the increase value ΔV2 of the RAMP voltage. Therefore, the RAMP voltage gradually increases. When the RAMP voltage is greater than the reference voltage REF3, the second comparator COMP2 204 outputs a high level. After being delayed by the delay circuit 205, the low-current signal outputs high, that is, the low-current signal is valid, and this signal controls the switching power supply system to shut down.

[0068] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A switching power supply low current detection circuit, characterized in that: include: A filter capacitor COUT, wherein the filter capacitor COUT is connected to two ends of the switching power supply; A voltage sampling circuit, wherein the voltage sampling circuit is connected to both ends of the filter capacitor COUT and is used to collect a voltage signal; A first comparator COMP1, wherein one input terminal of the first comparator COMP1 is connected to the FB signal terminal of the voltage sampling circuit, and the other two input terminals of the first comparator COMP1 are respectively connected to corresponding reference voltage REFH and REFL terminals; A pulse conversion circuit, the pulse conversion circuit is connected to the output end of the first comparator COMP1, and the pulse conversion circuit is used to convert the PULSE pulse signal output by the first comparator COMP1 into a RAMP voltage signal; A second comparator COMP2, wherein one output terminal of the second comparator COMP2 is connected to one output terminal of the pulse conversion circuit, and the other output terminal of the second comparator COMP2 is connected to another reference voltage REF3; A delay circuit is connected to the output terminal of the second comparator COMP2 and is used to output a low current signal.

2. A switching power supply low current detection circuit according to claim 1, characterized in that: The voltage sampling circuit includes a circuit composed of resistors R1 and R2 or a sampling circuit composed of an integrated circuit.

3. A switching power supply low current detection circuit according to claim 1, characterized in that: The pulse conversion circuit includes a current source I1, a current source I2, a PMOS transistor MP1, an NMOS transistor MN1, and a capacitor C1.

4. A switching power supply low current detection circuit according to claim 3, characterized in that: One end of the current source I2 is connected to the external power supply VDD, and the other end of the current source I2 is connected to the source of the PMOS transistor MP1, the drain of the PMOS transistor MP1 is connected to the source of the NMOS transistor MN1, and is respectively connected to one end of the capacitor C1 and an input end of the second comparator COMP2; the drain of the NMOS transistor MN1 is respectively connected to the other end of the capacitor C1 and is grounded through the current source I1, and the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 are both connected to the output end of the first comparator COMP1.

5. A switching power supply low current detection circuit according to claim 4, characterized in that: The current magnitude ratio of the current source I1 and the current source I2 is set to adjust the required small current detection threshold.

6. The switching power supply low current control method of the switching power supply low current detection circuit according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step S1: adjusting the critical value of the required small current detection by setting the ratio of the current source I1 and the current source I2; Step S2: When the output load current of the switching power supply is small, the switching power supply operates in a burst mode, and the working cycle of the switching power supply is a normal switching cycle TON and an off cycle TOFF; In the TON stage, the current source I1 discharges the capacitor C1 so that the RAMP voltage decreases to: ×TON; In the TOFF phase, the current source I2 charges the capacitor C1 so that the RAMP voltage increases by: ×TOFF; Step S3: In the load low current stage, according to different load current sizes, the low current is set to the low current stage 1 and the low current stage 2; Step S4: In the low current stage 1, when the switching power supply TON>TOFF, that is, K=TON / TOFF>1, and From the calculation formula 2, we can know that the RAMP voltage decreases by Greater than RAMP voltage increase value , so the RAMP voltage is always lower than the reference voltage REF3, the second comparator COMP2 outputs a low level, and the switching power supply continues to work in the current state; Step S5; In the second stage of small current, when the on-time TON of the switching power supply is less than the off-time TOFF, that is, K = TON / TOFF < 1, according to the calculation formulae above and in Formula 2, it can be known that the decrease value of the RAMP voltage in each period is less than the increase value of the RAMP voltage Therefore, the RAMP voltage gradually increases. When the RAMP voltage is greater than the reference voltage REF3, the second comparator COMP2 outputs a high level, then the small current signal output is valid, and the switching power supply is controlled to shut down.

7. A switching power supply low current control method according to claim 6, characterized in that: In step S3 , the load current in the low current stage 1 is greater than the critical value of the current detection, and the load current in the low current stage 2 is less than the critical value of the current detection, and the currents of the current source I1 and the current source I2 are equal.

8. A switching power supply low current control method according to claim 6, characterized in that: In step S4, the second comparator COMP2 outputs a low level, and the delay circuit filters the influence of short-term load current changes. After the delay circuit delays, the low current signal is also output as low, that is, the low current signal is invalid.

9. A switching power supply low current control method according to claim 6, characterized in that: In the step S5, the second comparator COMP2 outputs a high level, and after being delayed by the delay circuit, the low current signal output is high, that is, the low current signal is valid.

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