A data management system and data management method

Abstract

This application provides a data management system and method. The data management system includes a central processing unit (CPU) controller, a network chip, and external memory. The network chip includes a statistical counting module connected to the external memory. The CPU controller, connected to the network chip, is used to send management commands to the network chip. The statistical counting module in the network chip is used to perform management operations on relevant data of a counter in the external memory based on the management commands. This achieves data management of the network chip without requiring the participation of the CPU core within the network chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a data management system and data management method. Background Technology

[0002] As an indispensable functional module for the normal operation of a chip, the statistical counter provides an important debugging tool for monitoring the chip's operational status. Within the chip, statistical counters can be used to statistically count information such as packet quantity, packet traffic, Quality of Service (QoS), and the status of various functional modules. During chip operation, the statistical counter module monitors various types of counters, and a dedicated module is typically responsible for updating and collecting statistical counter information. Generally, the data collected by the counters is stored in the chip's external memory or the statistical counter module's internal storage area (SRAM). Pre-defined one-to-one mapping rules between counter addresses and memory (DDR / SRAM) and strict hardware design logic ensure accurate access to specific counters. During chip operation, various counter data are continuously refreshed, and each counter requires a "read -> modify -> write" step during update. Furthermore, if specific state-related counter data is needed, data can be loaded from the memory associated with the corresponding counter address through resource scheduling and then sent back to the CPU core for processing. As the chip business expands and the need to ensure chip operation more efficiently increases, the demand for statistical counters is growing. As a result, the number and categories of statistical counter entries that chips need to monitor will become increasingly large.

[0003] Due to the limitations of chip resources (high implementation cost and limited processing performance), monitoring a large number of statistical count entries may impose additional overhead on the main business of the CPU core and lead to excessive consumption of internal chip space. Furthermore, obtaining statistical data for a specific business state requires the CPU core to initiate a command, load the statistical data from the memory corresponding to the specified counter during command execution, and then transmit it back to the chip's CPU core for processing. This results in the chip's business operations and state monitoring competing for the same hardware and software resources. Simultaneously, this reduces the access speed of statistical data, hindering the chip's real-time monitoring of operational status data.

[0004] Therefore, how to efficiently and conveniently use debugging methods to monitor the statistical data of network chips in real time is one of the technical issues worth considering. Summary of the Invention

[0005] In view of this, this application provides a data management system and a data management method for efficiently managing the statistical data of network chips.

[0006] Specifically, this application is implemented through the following technical solution:

[0007] According to a first aspect of this application, a data management system is provided, comprising: a central processing unit (CPU) controller, a network chip, and an external memory, wherein the network chip includes a statistical counting module connected to the external memory, wherein:

[0008] The CPU controller is connected to the network chip and is used to send control commands to the network chip;

[0009] The statistical counting module in the network chip is used to perform control operations on the relevant data of the counter in the external memory based on the control instructions.

[0010] According to a second aspect of this application, a data management method is provided, applied in a central processing unit (CPU) controller, wherein the CPU controller is connected to a network chip, the network chip includes a statistical counting module, the statistical counting module being externally connected to an external memory, and the method includes:

[0011] A control command is sent to the network chip so that the statistical counting module in the network chip performs control operations on the relevant data of the counter in the external memory based on the control command.

[0012] According to a third aspect of this application, a data management method is provided, applied in a network chip, the network chip being connected to a central processing unit (CPU) controller, the network chip including a statistical counting module, the statistical counting module being externally connected to an external memory, the method comprising:

[0013] Receive control commands sent by the CPU controller;

[0014] The statistical counting module performs control operations on the relevant data of the counter in the external memory based on the control instructions.

[0015] The beneficial effects of the embodiments of this application are as follows:

[0016] When the CPU controller needs to manage data in the network chip, it sends management commands to the network chip. Upon receiving the commands, the network chip forwards them to the statistics and counting module. This module then accesses external memory based on the received commands and performs management operations on the relevant counter data recorded in the external memory. In this way, the CPU core within the network chip can manage the statistical data without intervention, thus ensuring uninterrupted business operations of the CPU core and achieving efficient management of statistical data within the network chip. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a data management and control system provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the interaction flow of a data management method provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of another data management system provided in an embodiment of this application;

[0020] Figure 4a This is a flowchart illustrating another data management method provided in an embodiment of this application;

[0021] Figure 4b This is a schematic diagram of a signal flow mode provided in an embodiment of this application;

[0022] Figure 5a This is a flowchart illustrating another data management method provided in an embodiment of this application;

[0023] Figure 5b This is a schematic diagram of another signal flow mode provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of the structure of a network chip provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of the structure of a statistical counting module provided in an embodiment of this application. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0027] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the corresponding listed items.

[0028] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0029] The data management system provided in this application will be described in detail below.

[0030] See Figure 1 , Figure 1 This is a schematic diagram of a data management system provided in this application. The data management system includes a CPU controller, a network chip, and an external memory. The network chip includes a statistical counting module connected to the external memory. The network chip also includes at least one CPU core, wherein: Figure 1 Each network chip can include n+1 CPU cores. CPU core 0 runs the main program, while CPU cores 1 through n run application programs APP1 through APPn respectively, providing various service functions. A schematic diagram of the interaction between the CPU controller and the network chip can be found in [reference needed]. Figure 2 As shown:

[0031] S201, the CPU controller sends control commands to the network chip.

[0032] In this step, the CPU controller is connected to the network chip. When it is necessary to manage the statistical data in the network chip, it generates management instructions and then sends the management instructions to the network chip.

[0033] It should be noted that this embodiment does not limit the number of network chips connected to the CPU controller. That is, the CPU controller can be connected to at least one network chip. However, the execution process of the CPU controller managing the statistical data of each network chip is the same. For the convenience of the following description, we will only use the CPU controller managing the statistical data of one network chip as an example.

[0034] Specifically, the main function of the CPU controller is to handle various transactions on the control and management plane of the network chip. These transactions can involve all aspects of the chip's operating status (reflected by statistical data). This management approach helps each CPU core in the network chip to run its services more independently, while the CPU controller provides a more convenient means to monitor the network chip's real-time status. Furthermore, as the manager of the control plane, the CPU controller can simultaneously monitor the status of multiple network chips and communicate with them.

[0035] Optionally, the CPU controller can, but is not limited to, connect to each network chip via the Peripheral Component Interconnect (PCI) standard. Specifically, the CPU controller includes multiple PCI interfaces, and the CPU controller can connect to one network chip through each PCI, thereby enabling the CPU controller to simultaneously connect multiple network chips and manage the statistical data of multiple network chips at the same time.

[0036] Optionally, when the CPU controller needs to manage a specified network chip, it can first log in to the network chip. After successful login, the CPU controller can display the management view of the network chip, which includes various management options for managing the network chip. Then, the user can trigger a management command for a certain management option, thus generating a management command. The CPU controller can then send the management command to the network chip.

[0037] Optionally, users can also pre-configure management requirements for network chips in the CPU controller. Different management requirements correspond to different management instructions. The CPU controller can send pre-configured management instructions to each network chip as needed to monitor the operating status of the network chip and manage its data.

[0038] S202. The network chip uses its internal statistical counting module to perform control operations on the relevant data of the counter in the external memory based on the control instructions.

[0039] In this step, after receiving the control command, the network chip sends it to the statistics and counting module. The statistics and counting module can then access the external memory based on the received control command and perform control operations on the relevant counter data recorded in the external memory. In this way, the CPU core in the network chip can control the statistical data without intervention, thus not interfering with the CPU core's business services. In other words, efficient control of the statistical data in the network chip is achieved.

[0040] Optionally, the aforementioned control commands can be, but are not limited to, read commands, modify commands, search commands, and write commands, etc. That is, different types of control commands contain different opcodes; specifically, read, modify, search, and write each correspond to different opcodes. For example, if the opcode for read is written in a control command, then that control command is a read command, and so on. These will not be described in detail here. Based on different control commands, the statistics and counting module in the network chip can perform different control operations, such as reading statistical data, modifying statistical data, writing statistical data, or searching statistical data, etc.

[0041] In one possible embodiment, the network chip further includes a cache module, and the CPU controller is connected to the cache module via a communication channel, as shown in the reference. Figure 3 The data management system shown.

[0042] Based on this, when the CPU controller sends control instructions to the network chip, it can implement step S201 according to the following process: When the CPU controller needs to control the relevant data of the counter in the network chip, it sends the control instructions to the communication channel to convert them into control messages and send them to the cache module in the network chip. The control messages include the control instructions.

[0043] Based on this, after receiving the control message, the aforementioned cache module sends the control instructions parsed from the control message to the statistics and counting module. In this way, the statistics and counting module can receive the control instructions sent by the CPU controller.

[0044] Specifically, the CPU controller accesses and manages the statistical data stored in external memory for tracking the network chip's operating status using a bypass method, which is not only simple but also convenient and fast. In this embodiment, the CPU controller bypasses the network chip's CPU core and directly sends the control command through the communication channel between the CPU controller and the cache module. The cache module then forwards the control command to the statistical counting module to achieve control over the statistical data of the network chip's operating status, that is, control over the data of the corresponding counters stored in external memory. (Refer to...) Figure 3 The signal flow pattern of the data control method shown Figure 3 In this example, path1 represents the data flow process.

[0045] To further explain, the communication channel between the CPU controller and the cache module is a PCI channel. The CPU controller can send control commands to the PCI channel via the PCI interface. The PCI channel is equipped with a PCI message construction module, which captures the control commands and encapsulates them into control messages. These control messages include the control commands, and the PCI message construction module then sends them to the cache module in the network chip. Specifically, after receiving a control command, the PCI message construction module automatically constructs a message based on the command type and fills it according to the message format, such as filling in address information, counter identifiers, and other related content. The address information can be understood as the address information of the next hop, and the counter identifier can be understood as the counter identifier of the counter to be accessed. Furthermore, if the control command is a write command, the control command also includes the data to be written, and the filled control message in this case also includes the data to be written.

[0046] Based on this, after receiving the control message, the caching module parses the control instruction from the message and forwards it to the statistics and counting module. The statistics and counting module can then perform control operations on the relevant data of the counter indicated by the control instruction in the external memory. This efficiently enables the control of statistical data used to monitor the operating status of the network chip.

[0047] Optionally, the aforementioned control instruction includes a target counter identifier; based on this, the statistical counting module can cache the module to execute step S202 in the following manner: after receiving the control instruction, the statistical counting module parses the target counter identifier from the control instruction; and performs control operations based on the data recorded in the storage space corresponding to the target counter identifier in the external memory.

[0048] Specifically, the statistics and counting module can find the storage address corresponding to the counter identifier recorded in the control instruction according to the established address mapping rules. This storage address is recorded as the storage address of the data recorded by the counter corresponding to the counter identifier in the external memory. Then, based on the determined storage address, it accesses the external memory and performs control operations on the data recorded in the storage space corresponding to the counter identifier in the external memory. In this way, the CPU controller supervises the statistical data in a bypass manner without the participation of the CPU core in the network chip, which greatly improves the operating efficiency of the network chip. Moreover, this bypass method can achieve a high level of efficiency in accessing and processing statistical data.

[0049] In another possible embodiment, the CPU controller further includes a cache, and based on this, the CPU controller can also... Figure 4a The process shown executes a data control method, including the following steps:

[0050] S401, the CPU controller caches control instructions into its own cache.

[0051] S402, the CPU core in the network chip accesses the cache in the CPU controller; after reading the control instruction, it sends the control instruction to the statistical counting module in the network chip.

[0052] In steps S401 and S402, a portion of the CPU controller's memory, i.e., its cache, can be used to cache management instructions or returned statistical data. That is, when the CPU controller needs to monitor statistical data in the network chip, it first writes the management instructions into its own cache. This allows for the scheduling of core CPUs; that is, CPU cores that meet certain conditions can be pre-specified, and then those CPU cores access the CPU controller's cache. It should be noted that the aforementioned CPU cores that meet the conditions can be CPU cores with high processing power or low workload, depending on the actual situation. Furthermore, at least one CPU core that meets the conditions can be selected. When multiple CPU cores that meet the conditions are selected, they can be allowed to access the CPU controller's cache in a round-robin fashion, thus avoiding putting processing pressure on these CPU cores.

[0053] Furthermore, once the selected CPU core in the network chip reads the control instructions from the CPU controller's cache, it can send the control instructions to the statistics and counting module via, but not limited to, the SOC internal bus. In this way, the statistics and counting module can perform control operations based on the control instructions. Specifically, the selected CPU core can reserve several threads in advance. These threads are dedicated to reading control instructions from the CPU controller's cache and subsequently writing control results. These threads will not affect the CPU core's processing load; and when reading control instructions is not required, these threads can also be used to handle related CPU core tasks.

[0054] Optionally, the network chip provided in this embodiment may further include a cache module. For the signal flow pattern of the implemented data management method, please refer to [reference needed]. Figure 4b As shown, Figure 4b In this example, path2 represents the data flow process. Based on this, when the selected CPU core reads the control instruction from the aforementioned cache, it will send the control instruction to... Figure 4b The cache module shown in the figure then forwards the control instructions to the statistics and counting module, which then performs the corresponding control operation based on the control instructions.

[0055] Optionally, the control instruction in this embodiment includes a target counter identifier; then the statistical counting module can perform step S202 according to the following process: parse the target counter identifier from the control instruction; and perform control operations based on the data recorded in the storage space corresponding to the target counter identifier in the external memory.

[0056] Specifically, the statistics and counting module can find the storage address corresponding to the counter identifier recorded in the control instruction according to the established address mapping rules. This storage address is recorded as the storage address of the data recorded by the counter corresponding to the counter identifier in the external memory. Then, based on the determined storage address, the module can access the external memory and perform control operations on the data recorded in the storage space corresponding to the counter identifier in the external memory.

[0057] It should be noted that the CPU core can also send control commands to the statistics and counting module in the form of messages.

[0058] S403. If the statistics and counting module performs a control operation and there is a control result, it will send the control result to the CPU core in the network chip.

[0059] In this step, after the statistics and counting module performs the control operation, it may obtain the control result. When the control result exists, it will be returned to the CPU core in the network chip along the original path.

[0060] S404: The CPU core in the network chip writes the control results into the cache of the CPU controller.

[0061] In this step, the CPU core writes the control results (e.g., returned data) to the CPU controller's cache via the connection between the network chip and the CPU controller.

[0062] S405, the CPU controller reads the control results from its own cache.

[0063] In this step, the CPU controller can read the control results from its own cache. Thus, the external CPU controller can be used to monitor the statistical data in real time using the above method.

[0064] It should be noted that steps S403 to S405 are only executed when the statistics and counting module needs to return the control result to the CPU controller. For example, when the control instruction is a read instruction, the statistics and counting module needs to return the read data (control result) to the CPU core in the network chip. Then, the CPU core writes the read data into the CPU controller's cache. In this way, the CPU controller can read the data returned by the statistics and counting module from its own cache. This also realizes the CPU controller's control over the network chip's statistical data. Moreover, since this application only selects CPU cores that meet the conditions to forward the control instruction, it does not require the participation of all CPU cores in the network chip, thus not affecting the CPU core's own business processing.

[0065] In another possible embodiment, this embodiment can also be implemented according to Figure 5a The method shown implements data governance methods, including the following steps:

[0066] When the CPU core in the S501 network chip needs to operate the counter during service processing, it sends a data operation instruction to the statistics and counting module. This data operation instruction includes the target counter identifier.

[0067] S502, after receiving a data operation instruction, the statistical counting module in the network chip performs the corresponding operation on the data in the storage space corresponding to the target counter identifier in the external memory.

[0068] In steps S501-S502, the CPU core in the network chip may need to retrieve statistical data from the network chip. Based on this, when the CPU needs to operate the counter during service processing, it can generate a data operation instruction and then send the data operation instruction to the statistical counting module. In this way, the statistical counting module can execute the operation corresponding to the data operation instruction according to step S502.

[0069] It should be noted that the CPU core can also send data operation instructions to the statistics and counting module in the form of messages.

[0070] Optionally, the network chip in this embodiment further includes a cache module, which is connected between the CPU core and the statistics and counting module; that is, the cache module is connected to both the CPU core and the statistics and counting module. For the signal flow pattern of the implemented data management method, please refer to [reference needed]. Figure 5b , Figure 5b In this example, path3 represents the data flow process. Based on this, the CPU core sends data manipulation instructions to... Figure 5b The data is processed by the cache module, which then forwards the data operation instructions to the statistics and counting module so that the statistics and counting module can perform the corresponding operations.

[0071] It should be noted that the data operation instructions in this embodiment may include, but are not limited to, read, modify, and write instructions. It is worth noting that when the data operation instruction is a read instruction, the statistics and counting module will perform the corresponding read operation on the data in the storage space corresponding to the target counter identifier in the external memory. The data will then be read, and the statistics module will send the read data to the CPU core via the cache module. This achieves the CPU core's control over the statistics data when needed.

[0072] It should be noted that the three data management methods provided in this application can coexist in practical applications; that is, they can be enabled simultaneously, or they can be enabled at different times, or only one or two data management methods can be configured, depending on the actual situation. This increases the flexibility of data management for network chips.

[0073] Optionally, based on any of the above embodiments, when the network chip includes a cache module, and the cache module is located between the CPU core and the statistics counting module in the network chip, refer to Figure 3 , Figure 4b or Figure 5b This refers to any data management method within the data management system shown. Based on this, a first clock synchronization module and a second clock synchronization module are configured between the aforementioned cache module and the statistics counting module, as referenced. Figure 6 As shown, where:

[0074] After receiving the control command or data operation command sent by the cache module, the first clock synchronization module will perform clock domain conversion on the control command or data operation command and send the converted control command or data operation command to the statistics counting module.

[0075] In addition, the second clock synchronization module receives the control results sent by the statistical counting module; performs clock domain conversion on the control results; and sends the converted control results to the cache module.

[0076] Specifically, the key components in the entire data path are the cache module and external storage, which directly interact with the statistics and counting module. The cache module performs preliminary classification of received control messages, control commands, data operation instructions, or control results and sends them to the corresponding interfaces. Upon receiving control messages, operation instructions, data operation instructions, or control results, the statistics and counting module parses and processes them, requiring access to the external storage mapped to it during this process. The statistics and counting module primarily initializes statistical data, updates counter data, periodically scans and updates statistical data, collects statistical information through message queues, and enables dynamic, cyclical, and automatic allocation between counters and network data streams. The implementation of statistical functions relies on the transmission, parsing, and response to commands.

[0077] Based on this, taking the receipt of a control command by the cache module as an example, when the cache module receives a control command, it will identify and process the command. If it finds that the control command is destined for the statistics and counting module, the cache module will cache the control command in the first clock synchronization module. The first clock synchronization module will convert the clock domain of the control command to synchronize it with its own clock domain, facilitating subsequent identification and processing by the statistics and counting module. Then, the converted control command is sent to the statistics and counting module. After receiving the control command, the statistics and counting module will parse it to extract the opcode and target counter identifier. Then, based on the target counter identifier and opcode, it will execute the control operation indicated by the opcode on the data corresponding to the target counter identifier recorded in the external memory, such as reading, writing, or modifying data.

[0078] Furthermore, after the statistics and counting module obtains data by executing control operations based on control instructions, it encapsulates the data into data packets as control results and returns them to the second clock synchronization module. The second clock synchronization module performs clock domain conversion on the control results to convert them into a clock domain that matches the cache module, facilitating processing by the cache module. Then, the converted control results are sent to the cache module, which feeds back the control results to the CPU controller. This achieves the execution of control operations from external memory and the return of control results, thus realizing the control of statistical data from the network chip.

[0079] When the first clock synchronization module receives a control message, it performs clock domain conversion on the control message after receiving it from the cache module, and sends the converted control message to the statistics and counting module. When the statistics and counting module obtains a control result based on the control message, the second clock synchronization module receives the control result from the statistics and counting module, performs clock domain conversion on the control result, and sends the converted control result to the cache module.

[0080] It should be noted that the processing of control messages and data operation commands also refers to the processing of control commands, and will not be described in detail here. Furthermore, the first clock synchronization module and the second clock synchronization module in this embodiment may be, but are not limited to, first-in-first-out (FIFO) modules.

[0081] Furthermore, a statistical memory adaptation module and a message queue module are also provided between the statistical counting module and the external storage; please refer to [the relevant documentation]. Figure 6 As shown, when the control command is a read, modify, or write command, the statistics module sends the command to the statistics memory adaptation module. The statistics memory adaptation module can then read, modify, or write the counter data recorded in the external memory based on the command. However, during the operation, some state changes may occur, generating data reflecting these changes. This data is first temporarily stored in the message queue module, and then the statistics memory adaptation module reads it from the message queue module and writes it to the external memory, thus writing the data to the storage space corresponding to the counter identifier in the external memory. This facilitates access by the software program and more conveniently realizes message interaction between hardware and software.

[0082] Furthermore, when the memory adaptation module reads data from external storage and this data needs to be sent back, the statistical memory adaptation module can send the read data to the statistical counting module. This read data is the control result. The statistical counting module then sends the read data to the second clock synchronization module, which in turn sends the clock-domain converted data to the cache module. Finally, the cache module returns the received data to the CPU controller or CPU core.

[0083] Optionally, based on any of the above embodiments, the statistical counting module in this embodiment includes a scheduling unit, a command cache unit, and an execution unit. The scheduling unit communicates with the command cache unit, and the command cache unit is connected to the execution unit. (Refer to...) Figure 7 As shown, where:

[0084] The aforementioned scheduling unit is used to send a cache request to the aforementioned command cache unit after receiving the aforementioned control instruction, so as to cache the aforementioned control instruction in the command cache unit;

[0085] The aforementioned command caching unit is used to insert the aforementioned control instructions into the connection table corresponding to the counter indicated by the control instructions. In practical applications, the scheduling unit continuously parses out control instructions and then sends them to the command caching unit, thereby the command caching unit continuously inserts the received control instructions into the corresponding connection table.

[0086] The aforementioned execution unit is configured to read control commands from the aforementioned command cache unit, parse counter identifiers from the read control commands, and execute the operations indicated by the aforementioned control commands on the data in the storage space corresponding to the aforementioned counter identifiers in the aforementioned external memory.

[0087] Specifically, when information (control commands, control messages, data operation commands) arrives at the statistics and counting module, the scheduling unit first receives this information. Then, the scheduling unit classifies the received information to determine whether it is sent to external memory or returned to the CPU controller or CPU core, in order to execute different operations. For example, it determines the target of the control command. Once the target is determined, the control command is sent to the corresponding interface and the corresponding operation is executed (such as retrieving the data corresponding to the target counter identifier from external memory). For ease of description, a control command is used as an example. When a control command arrives at the scheduling unit, the scheduling unit confirms that the control command is to operate on external memory, and then parses the opcode from the control command to identify the type of control command. In addition, the scheduling unit sends a cache request to the command cache unit. After receiving the response from the command cache unit, the scheduling unit writes the control command into the connection table corresponding to the counter (counter identifier) ​​indicated by the control command, maintained by the command cache unit.

[0088] Then, the execution unit in this embodiment reads the control instructions from the command cache unit according to the set rules, and then parses the target counter identifier and opcode from the control instructions. Since the external memory stores the statistical data of each counter used to monitor the operating status of the network chip, the execution unit can determine the target storage address corresponding to the target counter identifier based on the mapping relationship between the counter identifier and the storage address, and then execute the control operation indicated by the opcode on the data in the storage space corresponding to the target storage address in the external memory.

[0089] Furthermore, after the execution unit performs a control operation on a control instruction, it will notify the scheduling unit to instruct the scheduling unit to delete the control instruction.

[0090] Furthermore, after the execution unit performs a control operation in response to the control command, if there is a control result, the execution unit can send the control result to the cache module.

[0091] Optionally, the control instructions recorded in the connection table provided in this embodiment are written in chronological order; in addition, the statistics counting module also includes a high-speed cache, with which the scheduling unit can communicate. Please also refer to... Figure 7 As shown, the control command in this embodiment includes a target counter identifier, wherein:

[0092] The scheduling unit is also used to send the cache address of the control command to the cache, wherein the cache address is the free address that the command cache unit sends to the scheduling unit after writing the previous control command;

[0093] The aforementioned cache is used to cache the received cache address and the control instructions sent by the command cache unit; it can also cache the data generated by the execution unit after executing the control instructions.

[0094] The aforementioned execution unit is further configured to read control commands from the aforementioned command cache unit and parse the target counter identifier from the read control commands; query the aforementioned cache for the existence of data corresponding to the target counter identifier based on the target counter identifier; if it exists, perform the operation indicated by the aforementioned control commands on the data corresponding to the target counter identifier in the aforementioned cache.

[0095] Specifically, the command cache unit maintains a connection table. Control commands are written into this table in the order they are received. After a control command is written to the connection table corresponding to the counter indicated by that command, the command cache unit sends the connection table to a free address following the control command. Simultaneously, the command cache unit informs the scheduling unit of the connection table's free status, i.e., whether it is free. Therefore, the aforementioned cache address is the free address in the connection table, i.e., the free address after the command cache unit writes the control command. When the scheduling unit receives the cache address and the connection table's free status, if it confirms that the connection table is free, it writes the control command to the aforementioned free cache address and sends that cache address to the cache; if the connection table is not free, it can temporarily postpone writing control commands to the command cache unit.

[0096] In this way, after receiving the above cache address, the cache will store the cache address. In addition, the cache can also store the initial data read from external memory, and can also cache the data generated by the execution unit executing control instructions, etc., depending on the actual situation.

[0097] Based on this, the aforementioned execution unit can also perform control operations according to the following process: After reading the control instruction from the command cache unit, it extracts the target counter identifier from the control instruction, and then uses the target counter identifier to query whether the data corresponding to the target counter identifier exists in the cache. If it exists, it extracts the data from the cache, and then performs the control operation indicated by the control instruction on the data. If the data corresponding to the target counter identifier does not exist in the cache, it performs the operation indicated by the control instruction on the data of the counter corresponding to the target counter identifier recorded in the external memory.

[0098] It should be noted that the command cache unit can maintain a connection table for each counter, or multiple counters can correspond to one connection table, depending on the actual situation. However, the control instructions stored in each connection table are written in chronological order.

[0099] In one possible embodiment, the statistical counting module in this embodiment also includes an internal storage area, please also refer to... Figure 7 As shown, where:

[0100] The internal storage area is used to store data related to the counter.

[0101] In practical applications, counter data is typically stored in external memory. However, it's also possible to customize the storage method by storing a portion of the counters used to monitor the network chip's operating status in internal memory, and then storing the remaining counter data in external memory. This way, when the statistical counting module parses the target counter identifier, if it locates the corresponding counter's data in internal memory based on the target counter identifier, it performs a control operation on the data corresponding to the target counter in the internal memory. If the network chip needs the counter's data, the statistical counting module will send the data generated from the control operation to the network chip. (Please refer to [reference needed]). Figure 7 As shown. When the data of the counter corresponding to the target counter is located based on the target counter identifier and stored in the external memory, a control operation is performed on the data corresponding to the target counter stored in the external memory. At this time, if the network chip needs the relevant data of the counter, the statistics and counting module will send the data generated by the control operation to the network chip. Please also refer to... Figure 7 As shown.

[0102] It should be noted that this application does not limit the number of counters stored in the internal storage area; the specific number can be determined based on the actual situation. For example, in a real-world scenario, if the number of counters used to detect the operating status of the network chip is relatively small, then all counter data can be stored in the internal storage area.

[0103] It should be noted that the internal storage area in this embodiment may be, but is not limited to, static random access memory (SRAM), etc.

[0104] Optionally, the statistical counting module in this application also includes a transmit (TX) interface and a receive (RX) interface for communicating with external memory; please also refer to... Figure 7 As shown. Based on this, the execution unit can write data to external memory via the TX interface, or read statistical data recorded in external memory via the RX interface; in addition, the cache can also read statistical data recorded in external memory via the RX interface.

[0105] It should be noted that the cache module in any of the above embodiments of this application may be, but is not limited to, a level 2 cache module. Furthermore, the external memory in any of the embodiments of this application may be, but is not limited to, DDR-type memory.

[0106] Based on the same inventive concept, this embodiment also provides a data management method applied in a CPU controller. The CPU controller is connected to a network chip, which includes a statistical counting module connected to external memory. Based on this, the CPU controller can perform the following process data management method: send management instructions to the network chip, so that the statistical counting module in the network chip performs management operations on the relevant data of the counter in the external memory based on the aforementioned management instructions.

[0107] By implementing the above data management method, when the CPU controller needs to manage the data detected by the network chip using the counter by the statistical counting module, it can send a management command to the network chip. Upon receiving the management command, the network chip forwards it to the statistical counting module. In this way, the statistical counting module can access external memory based on the received management command and then perform management operations on the relevant counter data recorded in the external memory. Thus, the CPU core in the network chip can manage the statistical data without intervention, ensuring that the CPU core's business services are not disrupted. This achieves efficient management of the statistical data in the network chip.

[0108] Optionally, when the CPU controller sends control instructions to the network chip, it may perform the following process: when it is necessary to control the relevant data of the counter in the network chip, the control instructions are sent to the communication channel to be converted into control messages and sent to the cache module in the network chip, and the control messages include the control instructions.

[0109] Specifically, the implementation of the above process can be referred to the relevant description of the CPU controller in the data management system, which will not be elaborated here.

[0110] Optionally, in this embodiment, the CPU controller includes a cache area. Based on this, the data management method provided in this embodiment further includes: the CPU controller caches management instructions in its own cache area; and reads management results from its own cache area, wherein the management results are obtained by the kernel in the network chip reading the management instructions from the aforementioned cache area and forwarding them to the statistics and counting module, and then the statistics and counting module executing the management instructions.

[0111] Specifically, the implementation of the above process can be referred to the relevant description of the CPU controller in the data management system, which will not be elaborated here.

[0112] Based on the same inventive concept, this embodiment also provides a data management method applied in a network chip. The network chip is connected to a CPU controller and includes a statistical counting module connected to an external memory. When the data management method is executed in the network chip, it can be implemented according to the following process: receiving management instructions sent by the CPU controller; the statistical counting module performing management operations on the relevant data of the counter in the external memory based on the management instructions.

[0113] By implementing the above data management method, when the CPU controller needs to manage the data detected by the counter in the network chip by the statistical counting module, it can send a management command to the network chip. Upon receiving the management command, the network chip forwards it to the statistical counting module. In this way, the statistical counting module can access external memory based on the received management command and then perform management operations on the relevant counter data recorded in the external memory. Thus, the CPU core in the network chip can manage the statistical data without intervention, ensuring that the CPU core's business services are not disrupted. This achieves efficient management of the statistical data in the network chip.

[0114] Optionally, the network chip further includes a cache module, and the CPU controller is connected to the cache module via a communication channel. Based on this, the control instructions sent by the CPU controller can be received according to the following process: the cache module receives a control message, wherein the control message is obtained by the CPU controller converting the control instructions after sending it to the communication channel; the control instructions parsed from the control message are sent to the statistics and counting module.

[0115] Specifically, the implementation of the above process can be referred to the relevant descriptions of the above process in the cache module and the statistical counting module of the network chip in the data management and control system, which will not be elaborated here.

[0116] Optionally, the control instruction in this embodiment includes a target counter identifier. Based on this, the statistical counting module can perform control operations on the relevant data of the counter in the external memory according to the control instruction, as follows: after receiving the control message, the control instruction is parsed from the control message; the target counter identifier is parsed from the control instruction; and the control operation is performed based on the data recorded in the storage space corresponding to the target counter identifier in the external memory.

[0117] Specifically, the implementation of the above process can be referred to the relevant description of the above process in the statistical counting module of the network chip in the data management system, which will not be elaborated here.

[0118] Optionally, the network chip in this embodiment further includes at least one CPU core, and the CPU controller in this embodiment further includes a cache. Based on this, the data management method provided in this embodiment further includes: the CPU core in the network chip accessing the cache in the CPU controller; after reading the management instruction, sending the management instruction to the statistics and counting module; and when the statistics and counting module performs the management operation and there is a management result, sending the management result to the CPU core in the network chip; and the CPU core writing the management result into the cache of the CPU controller.

[0119] Specifically, the implementation of the above process can be referred to the relevant descriptions of the above process in the CPU core and statistical counting module of the network chip in the data management and control system, which will not be elaborated here.

[0120] Furthermore, control operations can be performed based on control instructions in the following manner: the statistical counting module parses the target counter identifier from the control instructions; and the control operations are performed based on the data recorded in the storage space corresponding to the target counter identifier in the external memory.

[0121] Specifically, the implementation of the above process can be referred to the relevant description of the above process in the statistical counting module of the network chip in the data management system, which will not be elaborated here.

[0122] Optionally, the network chip in this embodiment further includes at least one CPU core. Based on this, the data management method provided in this embodiment further includes: when it is necessary to operate the counter during the service processing, the CPU core in the network chip sends a data operation instruction to the statistical counting module, the data operation instruction including a target counter identifier; after receiving the data operation instruction, the statistical counting module performs corresponding operations on the data in the storage space corresponding to the target counter identifier in the external memory.

[0123] Specifically, the implementation of the above process can be referred to the relevant descriptions of the above process in the CPU core and statistical counting module of the network chip in the data management and control system, which will not be elaborated here.

[0124] Optionally, the network chip in this embodiment further includes a cache module, which is located between the CPU core and the statistical counting module in the network chip. A first clock synchronization module and a second clock synchronization module are configured between the cache module and the statistical counting module. Based on this, control commands or data operation commands can be sent to the statistical counting module in the following manner: the first clock synchronization module receives the control commands or data operation commands sent by the cache module, performs clock domain conversion processing on the control commands or data operation commands, and sends the converted control commands or data operation commands to the statistical counting module.

[0125] Based on this, the control message can be sent to the statistics and counting module in the following way: after receiving the control message sent by the above-mentioned cache module, the control message is converted to a clock domain; and the converted control message is sent to the above-mentioned statistics and counting module.

[0126] Based on this, when the statistical counting module generates a control result by performing corresponding operations based on control instructions, control messages, and data operation instructions, the data control method provided in this embodiment further includes: the second clock synchronization module receiving the control result sent by the statistical counting module; performing clock domain conversion processing on the control result; and sending the converted control result to the cache module.

[0127] Specifically, the implementation of the above process can be referred to the relevant descriptions of the above process in the first clock synchronization module and the second clock synchronization module in the network chip of the data management and control system, which will not be elaborated here.

[0128] Optionally, the statistical counting module provided in this embodiment further includes a scheduling unit, a command cache unit, and an execution unit. The scheduling unit communicates with the command cache unit, and the command cache unit is connected to the execution unit. Based on this, the data management method can also be executed according to the following process: the scheduling unit receives a management instruction and sends a cache request to the command cache unit to cache the management instruction in the command cache unit; after receiving the management instruction, the command cache unit inserts the management instruction into the connection table corresponding to the counter indicated by the management instruction; the execution unit reads the management instruction from the command cache unit and parses the counter identifier from the read management instruction; and performs the operation indicated by the management instruction on the data in the storage space corresponding to the counter identifier in the external memory.

[0129] Specifically, the implementation of the above process can be referred to the relevant descriptions of the above process in the various units of the network chip in the data management system, which will not be elaborated here.

[0130] Optionally, the control instructions recorded in the connection table in this embodiment are written in chronological order; the above-mentioned statistical counting module also includes a high-speed cache, and the control instructions include a target counter identifier. Based on this, the data control method provided in this embodiment further includes: a scheduling unit sending the cache address of the control instructions to the cache, wherein the cache address is the free address sent by the command cache unit after writing the previous control instruction to the scheduling unit; the cache receiving the cache address and pre-reading initial data from external memory; the execution unit reading the control instructions from the command cache unit and parsing the target counter identifier from the read control instructions; querying the cache for the existence of data corresponding to the target counter identifier based on the target counter identifier; if it exists, the data corresponding to the target counter identifier in the cache performs the operation indicated by the control instructions.

[0131] In addition, the cache can also store initial data read from external memory, and can also cache data generated by the execution unit when executing control instructions, etc., depending on the actual situation.

[0132] Specifically, the implementation of the above process can be referred to the relevant descriptions of the above process in the various units of the network chip in the data management system, which will not be elaborated here.

[0133] By implementing the data management system and method provided in any embodiment of this application, the operating efficiency and forwarding performance of network chips can be greatly improved. Furthermore, when a network chip is running multiple service programs, all CPU cores can be used to carry the services without processing the status monitoring data in the service process. Status statistics during service operation are quickly and conveniently monitored and managed by the CPU controller through a bypass method. Therefore, by separating status monitoring from services, the network chip can carry more services, and the CPU controller can simultaneously manage multiple network chips. In addition, a large amount of statistical data used to monitor the operating status of the network chip in this application is transmitted back to the CPU controller and does not require management by the network chip itself, thereby reducing the design complexity and workload of the network chip and improving the memory utilization rate of the network chip in processing services.

[0134] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0135] The specific implementation process of the functions and roles of each unit / module in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0136] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units / modules described as separate components may or may not be physically separate. The components shown as units / modules may or may not be physical units / modules, that is, they may be located in one place or distributed across multiple network units / modules. Some or all of the units / modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0137] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A data management and control system, characterized in that, include: The system comprises a central processing unit (CPU) controller, a network chip, and external memory. The network chip includes a statistical counting module connected to the external memory. The CPU controller is connected to the network chip and is used to send control commands to the network chip; The statistical counting module in the network chip is used to perform control operations on the relevant data of the counter in the external memory based on the control instructions. The statistical counting module includes a scheduling unit, a command cache unit, and an execution unit. The scheduling unit communicates with the command cache unit, and the command cache unit is connected to the execution unit. The scheduling unit is configured to send a cache request to the command cache unit after receiving the control instruction, so as to cache the control instruction in the command cache unit; The command cache unit is used to insert the control instruction into the connection table corresponding to the counter indicated by the control instruction; the command cache unit maintains a connection table, which includes control instructions written in chronological order; The execution unit is configured to read control commands from the command cache unit, parse counter identifiers from the read control commands, and execute the operations indicated by the control commands on the data in the storage space corresponding to the counter identifier in the external memory.

2. The system according to claim 1, characterized in that, The network chip also includes a cache module, and the CPU controller is connected to the cache module via a communication channel; The CPU controller is specifically used to send the control instruction to the communication channel when it is necessary to control the relevant data of the counter in the network chip, so as to convert it into a control message and send it to the cache module in the network chip. The control message includes the control instruction. The caching module is used to send the control instructions parsed from the control message to the statistics and counting module after receiving the control message.

3. The system according to claim 2, characterized in that, The control command includes the target counter identifier; The statistical counting module is specifically used to parse the target counter identifier from the control instruction after receiving the control instruction; and to perform control operations based on the data recorded in the storage space corresponding to the target counter identifier in the external memory.

4. The system according to claim 1, characterized in that, The CPU controller includes a cache, and the network chip includes at least one CPU core. The CPU controller is used to cache control instructions into its own cache area; The CPU core in the network chip is used to access the cache in the CPU controller; after reading the control instruction, it sends the control instruction to the statistics and counting module. The statistical counting module is also used to send the control result to the CPU core in the network chip if the control operation results in a control result. The CPU core in the network chip is also used to write the control results into the cache of the CPU controller; The CPU controller is also used to read the control results from its own cache.

5. The system according to claim 4, characterized in that, The control command includes the target counter identifier; The statistical counting module is specifically used to parse the target counter identifier from the control command; and to perform control operations based on the data recorded in the storage space corresponding to the target counter identifier in the external memory.

6. The system according to claim 1, characterized in that, The network chip also includes at least one CPU core, wherein: The CPU core in the network chip is also used to send data operation instructions to the statistical counting module when the counter needs to be operated during the service processing. The data operation instructions include the target counter identifier. The statistical counting module is used to perform corresponding operations on the data in the storage space corresponding to the target counter identifier in the external memory after receiving the data operation instruction.

7. The system according to claim 1, 4, or 6, characterized in that, The network chip further includes a cache module, which is located between the CPU core and the statistics counting module in the network chip. A first clock synchronization module and a second clock synchronization module are configured between the cache module and the statistics counting module, wherein: The first clock synchronization module is used to perform clock domain conversion processing on the control instruction or data operation instruction sent by the cache module after receiving the control instruction or data operation instruction; and send the converted control instruction or data operation instruction to the statistics counting module. The second clock synchronization module is used to receive the control result sent by the statistics counting module; perform clock domain conversion processing on the control result; and send the converted control result to the cache module.

8. The system according to claim 2, characterized in that, A first clock synchronization module and a second clock synchronization module are configured between the cache module and the statistics counting module, wherein: The first clock synchronization module is used to perform clock domain conversion processing on the control message after receiving the control message sent by the cache module; and send the converted control message to the statistics counting module. The second clock synchronization module is used to receive the control result sent by the statistics counting module; perform clock domain conversion processing on the control result; and send the converted control result to the cache module.

9. The system according to claim 1, characterized in that, The statistical counting module also includes a high-speed cache; the control command includes a target counter identifier. The scheduling unit is also used to send the cache address of the control command to the cache, wherein the cache address is the free address that the command cache unit sends to the scheduling unit after writing the previous control command; The cache is used to cache the received cache address; The execution unit is further configured to read control commands from the command cache unit and parse the target counter identifier from the read control commands; query the cache for data corresponding to the target counter identifier based on the target counter identifier; if it exists, execute the operation indicated by the control command on the data corresponding to the counter identifier in the cache.

10. The system according to claim 1, characterized in that, The statistical counting module also includes an internal storage area; The internal storage area is used to store the control results generated after the execution unit performs the corresponding operation based on the control instruction.

11. A data management and control method, characterized in that, The method, applied in a central processing unit (CPU) controller, wherein the CPU controller is connected to a network chip, the network chip includes a statistical counting module connected to external memory, and the method includes: A control command is sent to the network chip so that the statistical counting module in the network chip performs control operations on the relevant data of the counter in the external memory based on the control command; The statistical counting module includes a scheduling unit, a command cache unit, and an execution unit. The scheduling unit communicates with the command cache unit, and the command cache unit is connected to the execution unit. After receiving the control instruction, the scheduling unit sends a cache request to the command cache unit to cache the control instruction in the command cache unit; The command cache unit inserts the control instruction into the connection table corresponding to the counter indicated by the control instruction; the command cache unit maintains a connection table, which includes control instructions written in chronological order; The execution unit reads control commands from the command cache unit and parses the counter identifier from the read control commands; and executes the operation indicated by the control commands on the data in the storage space corresponding to the counter identifier in the external memory.

12. A data management and control method, characterized in that, The method is applied in a network chip, which is connected to a central processing unit (CPU) controller. The network chip includes a statistical counting module connected to external memory. Receive control commands sent by the CPU controller; The statistical counting module performs control operations on the relevant data of the counter in the external memory based on the control instructions. The statistical counting module includes a scheduling unit, a command cache unit, and an execution unit. The scheduling unit communicates with the command cache unit, and the command cache unit is connected to the execution unit. After receiving the control instruction, the scheduling unit sends a cache request to the command cache unit to cache the control instruction in the command cache unit; The command cache unit inserts the control instruction into the connection table corresponding to the counter indicated by the control instruction; the command cache unit maintains a connection table, which includes control instructions written in chronological order; The execution unit reads control commands from the command cache unit and parses the counter identifier from the read control commands; and executes the operation indicated by the control commands on the data in the storage space corresponding to the counter identifier in the external memory.

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