Method and device for optimizing circuit design

Abstract

The present invention provides a method and apparatus for optimizing circuit design. The method and apparatus take into account the influence of drain-source degradation current under at least two effects on the delay of actual circuit clock signals. According to the method and apparatus for optimizing circuit design of the present invention, it is possible to verify the deficiencies in the circuit design without having to conduct multiple tape-out trials, thereby reducing costs. In addition, it is possible to verify whether the redundancy in the circuit design is sufficient without having to conduct multiple tape-out trials, and only simulation is required, thereby shortening the design cycle.

Description

Technical Field

[0001] The present invention relates to a method and device for optimizing circuit design, and more specifically, to a method and device for optimizing circuit design while taking into account negative bias temperature instability (NBTI) or hot carrier injection (HCI) effects. Background Art

[0002] As the integration of integrated circuits continues to increase, more and more devices are integrated on a unit area of ​​the chip, which requires a faster clock speed. In order to meet this demand, it is necessary to reduce the geometric size of the device and apply new materials and new technologies, but such improvements will have a great impact on the delay of the circuit and the life of the device. In the prior art, most of the research focuses on a single PMOS device or a single NMOS device, and studies their NBTI or HCI effects separately. However, in actual application circuits, the devices are not in a single working state. Most of the time, NBTI and HCI degradation occur together. If only a single NBTI degradation or HCI degradation result is considered, it is inaccurate for the actual circuit. Therefore, the overall reliability of the device should be studied more comprehensively, and it should be extended to the performance improvement of the entire circuit.

[0003] In the prior art, Korean patent KR102087441B1 entitled "A hierarchical digital circuit reliability verification method" provides a hierarchical digital circuit reliability verification method, including: in the BSIM3v3 model, a calculation formula for the threshold voltage drift △Vth of the MOSFET transistor affected by the HCI, NBTI and TDDB effects is used to form a new BSIM3v3 model that can evaluate the performance change of the MOSFET transistor; then the SPICE simulator is used to call the new BSIM3v3 model to simulate a circuit containing only one MOSFET transistor, thereby generating a degraded MOSFET transistor model file; based on the degraded MOSFET transistor model file, a degraded digital cell library is extracted through a cell library characterization tool; finally, the digital circuit is analyzed based on the degraded digital cell library to achieve the prediction of large-scale digital circuit performance degradation.

[0004] Most of the current research has two problems: First, only the reliability of a single device is considered. For example, in PMOS devices, only the NBTI effect is considered, and the coupling effect of the HCI effect is not considered. Second, the conclusion is simply derived from the formula theory without combining it with the actual circuit. It is very likely that the life span will be overestimated, resulting in inaccurate models in the later stage and affecting the tape-out. For example, through a simple linear addition algorithm, the threshold voltage change of NBTI and the threshold voltage change of HCI are added together to calculate the life span of the entire product. The algorithm lacks experimental proof and accuracy.

[0005] Therefore, it is urgent to solve the above technical problems in the prior art. Summary of the invention

[0006] The present invention provides a method and apparatus for optimizing circuit design by comprehensively considering the two effects of NBTI and HCI. Compared with a single NBTI model or a single HCI model, the method and apparatus for optimizing circuit design of the present invention are more accurate. Through the method and apparatus for optimizing circuit design of the present invention, the performance loss of the device level and circuit level during the aging stage can be accurately simulated. In addition, by combining the reliability calculation model with HSPICE (EDA design tool) simulation, the reliability verification of the device level is combined with the reliability simulation of the circuit level, and the performance loss caused by aging can be considered in the early stage of design, so as to design the circuit more accurately and avoid too many or too few design schemes.

[0007] According to a first aspect of the present invention, a method for optimizing circuit design is provided, the method at least comprising: taking into account the influence of drain-source degeneration current under at least two effects on the delay of a clock signal of an actual circuit.

[0008] A preferred embodiment of the method for optimizing circuit design according to the present invention comprises:

[0009] Calculate the first drain-source degradation current I under the first effect ds1 ;

[0010] Calculate the second drain-source degradation current I under the second effect ds2 ;

[0011] Calculate the total drain-source degradation current I total , by the first drain-source degradation current I ds1 and the second drain-source degradation current I ds2 The total drain-source degradation current I is calculated according to the following formula: total :

[0012] I total =A×(I ds1 +I ds2) / exp(I ds1 +I ds2 )

[0013] The value of A ranges from 0 to 1;

[0014] The total drain-source degradation current I total Perform simulation.

[0015] According to a preferred embodiment of the method for optimizing circuit design of the present invention, the A value is 0.37.

[0016] According to a preferred embodiment of the method for optimizing circuit design of the present invention,

[0017] The first drain-source degradation current I ds1 is the drain-source degradation current under the negative bias instability NBTI effect; and

[0018] The second drain-source degradation current I ds2 It is the drain-source degradation current under the hot carrier injection HCI effect.

[0019] According to a preferred embodiment of the method for optimizing circuit design of the present invention, the first drain-source degradation current I ds1 It is obtained by the following formula:

[0020]

[0021] Among them, C ox is the oxide capacitance per unit area, C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; V g is the applied voltage of the transistor; W is the channel width; V ds is the drain-source voltage; R ds is the drain-source resistance; L is the channel length; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift;

[0022] in,

[0023]

[0024]

[0025] Among them, ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; μ 0 is the intrinsic mobility; θ is the proportionality constant associated with the transistor.

[0026] According to a preferred embodiment of the method for optimizing circuit design of the present invention, the second drain-source degradation current I ds2 It is obtained by the following formula:

[0027]

[0028] Where W is the channel width; L is the channel length; V g is the applied voltage of the transistor; V ds is the drain-source voltage; the oxide capacitance per unit area C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift;

[0029] in,

[0030]

[0031]

[0032] Among them, I ds is the drain-source current; ψ it is the critical energy required for electrons to form an interface state; λ is the mean free path of electrons; t is the working time; μ 0 is the intrinsic mobility; β is the oxide layer material related factor; ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; C, n, k are process-related factors.

[0033] According to a second aspect of the present invention, there is provided a device for optimizing circuit design, the device comprising at least:

[0034] A device for taking into account the influence of drain-source degeneration current under at least two effects on the delay of a clock signal in an actual circuit.

[0035] A preferred embodiment of the device for optimizing circuit design according to the present invention comprises:

[0036] Used to calculate the first drain-source degradation current I under the first effect ds1 Devices;

[0037] Used to calculate the second drain-source degradation current I under the second effect ds2 Devices;

[0038] Used to calculate the total drain-source degradation current I total The device is degraded by the first drain-source current I ds1 and the second drain-source degradation current I ds2 The total drain-source degradation current I is calculated according to the following formula: total :

[0039] I total =A×(I ds1 +I ds2 ) / exp(I ds1 +I ds2 )

[0040] The value of A ranges from 0 to 1;

[0041] For the total drain-source degradation current I total The device for performing the simulation.

[0042] According to a preferred embodiment of the apparatus for optimizing circuit design of the present invention, the A value is 0.37.

[0043] According to a preferred embodiment of the device for optimizing circuit design of the present invention,

[0044] The first drain-source degradation current I ds1 is the drain-source degradation current under the negative bias instability NBTI effect; and

[0045] The second drain-source degradation current I ds2 It is the drain-source degradation current under the hot carrier injection HCI effect.

[0046] According to a preferred embodiment of the device for optimizing circuit design of the present invention, for calculating the first drain-source degradation current I under the first effect ds1 The first drain-source degradation current I is obtained by the following formula ds1 :

[0047]

[0048] Among them, C ox is the oxide capacitance per unit area, C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; V g is the applied voltage of the transistor; W is the channel width; V ds is the drain-source voltage; R ds is the drain-source resistance; L is the channel length; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift;

[0049] in,

[0050]

[0051]

[0052] Among them, ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; μ 0 is the intrinsic mobility; θ is the proportionality constant associated with the transistor.

[0053] According to a preferred embodiment of the device for optimizing circuit design of the present invention, for calculating the second drain-source degradation current I under the second effect ds2 The second drain-source degradation current I is obtained by the following formula ds2 :

[0054]

[0055] Where W is the channel width; L is the channel length; V g is the applied voltage of the transistor; V ds is the drain-source voltage; the oxide capacitance per unit area C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; the threshold voltage V th =V th0 +△Vth , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift;

[0056] in,

[0057]

[0058]

[0059] Among them, I ds is the drain-source current; ψ it is the critical energy required for electrons to form an interface state; λ is the mean free path of electrons; t is the working time; μ 0 is the intrinsic mobility; β is the oxide layer material related factor; ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; C, n, k are process-related factors.

[0060] According to a third aspect of the present invention, a machine-readable medium is provided, on which machine-executable instructions are stored. When the machine-executable instructions are executed by a machine, the machine-executable instructions execute any one of the methods described in the first aspect above.

[0061] According to the method and device for optimizing circuit design of the present invention, the deficiencies in the circuit design can be verified without multiple tape-out trials, thereby reducing costs. In addition, it is possible to verify whether the redundancy in the circuit design is sufficient without multiple tape-out trials, and only simulation is required, thereby shortening the design cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 The overall flow chart of the conventional circuit design in the prior art is shown.

[0063] Figure 2 An overall flow chart of the circuit design according to the present invention is shown. DETAILED DESCRIPTION

[0064] The embodiments of the present invention will be described in further detail below.

[0065] Figure 1A flow chart of a conventional circuit design of the prior art is shown. In step 101, simulation is performed while setting a very large redundancy to ensure reliability. In step 102, tape-out trial production is performed. In step 103, aging tests are performed for life attenuation, circuit performance drift, etc. In step 104, it is determined whether the attenuation is within the redundancy range. If the attenuation is within the redundancy range, then in step 105, there is no need to modify the circuit design, the product is good, and can be delivered to the customer. If the attenuation is not within the redundancy range, then in step 106, it is necessary to add drift data and perform the simulation in step 102 again.

[0066] like Figure 1 As can be seen in the figure, in the prior art, aging tests are required to discover deficiencies in circuit design. As the circuit ages, the delay of the clock signal in the DRAM will also increase significantly, which will affect the circuit performance. However, if the circuit needs to be improved through trial production every time, the cost will increase significantly.

[0067] The inventors of the present invention realize that by predicting or considering the performance loss caused by aging in the early stage of design, the circuit can be designed more accurately, which will greatly reduce costs and shorten the design cycle. Predicting or considering the performance loss caused by aging in the early stage of design is achieved by accurately simulating the performance loss of the device level and circuit level during the aging stage, combined with the fitting model obtained by the present invention for simulation.

[0068] Figure 2 The overall flow chart of the circuit design according to the present invention is shown. In step 201, simulation is performed while calculating the drift vector. At this time, a very large redundancy is not required, and a small amount of redundancy is sufficient. In step 202, tape-out trial production is performed. In step 203, aging tests are performed for life attenuation, circuit performance drift, etc. In step 204, since the drift vector has been considered in the simulation stage at the beginning of the design, the product can be directly delivered to the customer if it is good.

[0069] In step 201 of the present invention, the calculation of the drift vector takes into account the influence of the drain-source degeneration current under at least two effects on the actual circuit clock signal delay. Preferably, the two effects are the NBTI effect and the HCI effect.

[0070] The first drain-source degradation current I under the NBTI effect can be calculated according to the formula known in the prior art: ds1 ,For example

[0071]

[0072] Among them, C ox is the oxide capacitance per unit area, C ox =q / (E ox×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; V g is the applied voltage of the transistor; W is the channel width; V ds is the drain-source voltage; R ds is the drain-source resistance; L is the channel length; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift;

[0073] in,

[0074]

[0075]

[0076] Among them, ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; μ 0 is the intrinsic mobility; θ is the proportionality constant associated with the transistor.

[0077] The second drain-source degradation current I under the HCI effect can be calculated according to the formula known in the prior art: ds2 ,For example

[0078]

[0079] Where W is the channel width; L is the channel length; V g is the applied voltage of the transistor; V ds is the drain-source voltage; the oxide capacitance per unit area C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μeff is the mobility drift;

[0080] in,

[0081]

[0082]

[0083] Among them, I ds is the drain-source current; ψ it is the critical energy required for electrons to form an interface state; λ is the mean free path of electrons; t is the working time; μ 0 is the intrinsic mobility; β is the oxide layer material related factor; ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; C, n, k are process-related factors.

[0084] Through fitting modeling, the total drain-source degradation current I is obtained. total The first drain-source degradation current I under NBTI effect ds1 and the second drain-source degradation current I under the HCI effect ds2 The relationship between them is:

[0085] I total =A×(I ds1 +I ds2 ) / exp(I ds1 +I ds2 )

[0086] The value of A ranges from 0 to 1, preferably 0.37.

[0087] Then, the total drain-source degradation current I total Instead of simulating the original drain-source current, the signal delay can be fed back. The clock part is improved in the design circuit, reducing the unnecessary tape-out requirements in the later stage.

[0088] Since the total drain-source degradation current I total The influence of NBTI and HCI effects is taken into account at the same time, the drift vector is considered in the early stage of design, and the circuit design is optimized.

[0089] The present invention further relates to a program product including a machine-readable medium for executing machine-executable instructions or data structures or storing the instructions or data structures thereon. Such a machine-readable medium can be any available medium, which can be accessed by a general-purpose or special-purpose computer or other machine with a processor. For example, such a machine-readable medium can include RAM, ROM, EPROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium, which can be used to execute or store the required program code in the form of machine-executable instructions or data structures, and can be accessed by a general-purpose or special-purpose computer or other machine with a processor. When information is transmitted or provided to a machine on a network or another communication connection (hard-wired, wireless, or a combination of hard-wired or wireless), the machine appropriately regards the connection as a machine-readable medium. Therefore, any such connection is appropriately referred to as a machine-readable medium. The above combination is also included in the scope of a machine-readable medium. Machine-executable instructions include instructions and data that, for example, enable a general-purpose computer, a special-purpose computer or a special-purpose processing machine to perform certain functions or a group of functions.

[0090] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims.It should be understood that the scope of the invention is defined by the claims.

Claims

1. A method for optimizing circuit design, characterized in that: The method at least includes: taking into account the influence of the drain-source degradation current under at least two effects on the delay of the actual circuit clock signal; Wherein, the method further comprises: Calculate the first drain-source degradation current I under the first effect ds1 ; Calculate the second drain-source degradation current I under the second effect ds2 ; Calculate the total drain-source degradation current I total , by the first drain-source degradation current I ds1 and the second drain-source degradation current I ds2 The total drain-source degradation current I is calculated according to the following formula: total : I total =A×(I ds1 +I ds2 ) / exp(I ds1 +I ds2 ) The value of A ranges from 0 to 1; The total drain-source degradation current I total Conduct simulation; Wherein the first drain-source degradation current I ds1 is the drain-source degradation current under the negative bias instability NBTI effect; and The second drain-source degradation current I ds2 is the drain-source degradation current under the hot carrier injection HCI effect; Wherein the first drain-source degradation current I ds1 It is obtained by the following formula: Among them, C ox is the oxide capacitance per unit area, C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; V g is the applied voltage of the transistor; W is the channel width; V ds is the drain-source voltage; R ds is the drain-source resistance; L is the channel length; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift; in, Among them, ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; μ0 is the intrinsic mobility; θ is the proportionality constant associated with the transistor; The second drain-source degradation current I ds2 It is obtained by the following formula: Where W is the channel width; L is the channel length; V g is the applied voltage of the transistor; V ds is the drain-source voltage; the oxide capacitance per unit area C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift; in, Among them, I ds is the drain-source current; ψ it is the critical energy required for electrons to form interface states; λ is the mean free path of electrons; t is the working time; μ0 is the intrinsic mobility; β is the oxide layer material related factor; ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; C, n, k are process-related factors.

2. The method according to claim 1, characterized in that The A value is 0.

37.

3. A device for optimizing circuit design, characterized in that: The device at least comprises: Means for taking into account the influence of drain-source degradation current under at least two effects on the delay of a clock signal in an actual circuit; Wherein, the device further comprises: Used to calculate the first drain-source degradation current I under the first effect ds1 Devices; Used to calculate the second drain-source degradation current I under the second effect ds2 Devices; Used to calculate the total drain-source degradation current I total The device is degraded by the first drain-source current I ds1 and the second drain-source degradation current I ds2 The total drain-source degradation current I is calculated according to the following formula: total : I total =A×(I ds1 +I ds2 ) / exp(I ds1 +I ds2 ) The value of A ranges from 0 to 1; For the total drain-source degradation current I total a device for performing simulation; The first drain-source degradation current I ds1 is the drain-source degradation current under the negative bias instability NBTI effect; and The second drain-source degradation current I ds2 is the drain-source degradation current under the hot carrier injection HCI effect; It is used to calculate the first drain-source degradation current I under the first effect ds1 The first drain-source degradation current I is obtained by the following formula ds1 : Among them, C ox is the oxide capacitance per unit area, C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; V g is the applied voltage of the transistor; W is the channel width; V ds is the drain-source voltage; R ds is the drain-source resistance; L is the channel length; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift; in, Among them, ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; μ0 is the intrinsic mobility; θ is the proportionality constant associated with the transistor; The second drain-source degradation current I is used to calculate the second effect. ds2 The second drain-source degradation current I is obtained by the following formula ds2 : Where W is the channel width; L is the channel length; V g is the applied voltage of the transistor; V ds is the drain-source voltage; the oxide capacitance per unit area C ox =q / (E ox ×d), where d is the distance between the capacitor plates, q is the charge on the electron, and E ox is the gate oxide electric field; the threshold voltage V th =V th0 +△V th , where V th0 is the initial threshold voltage, △V th is the threshold voltage drift; mobility μ eff =μ eff0 +△μ eff , where μ eff0 is the initial mobility, △μ eff is the mobility drift; in, Among them, I ds is the drain-source current; ψ it is the critical energy required for electrons to form interface states; λ is the mean free path of electrons; t is the working time; μ0 is the intrinsic mobility; β is the oxide layer material related factor; ΔN it is the increased interface trap concentration; ΔN ox is the increased oxide trap concentration; C, n, k are process-related factors.

4. The device according to claim 3, characterized in that The A value is 0.

37.

5. A machine-readable medium, characterized in that The machine-readable medium stores machine-executable instructions. When the machine-executable instructions are executed by a machine, the machine-executable instructions execute the method according to claim 1 or 2.

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