Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device comprises a gate layer, a low-doped semiconductor layer, a crystalline ferroelectric layer, and a source terminal and a drain terminal. The crystalline ferroelectric layer is arranged between the gate layer and the low-doped semiconductor layer. The source terminal and the drain terminal are arranged on the low-doped semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor manufacturing technology involves the integration of hundreds of process steps to manufacture semiconductor devices and electronic components with increasingly complex three-dimensional geometries. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a gate layer; a low-doped semiconductor layer; a crystalline ferroelectric layer arranged between the gate layer and the low-doped semiconductor layer; and a source terminal and a drain terminal arranged on the low-doped semiconductor layer.

[0004] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor material layer; a gate layer, arranged above the semiconductor material layer; a ferroelectric layer, arranged between the gate layer and the semiconductor material layer; an interface layer, arranged between the ferroelectric layer and the semiconductor material layer; and a source and a drain, arranged on the semiconductor material layer, wherein the interface layer comprises at least one of the materials of the semiconductor material layer and the materials of the ferroelectric layer.

[0005] According to another aspect of an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a semiconductor layer and forming a dielectric layer; performing a pressurization treatment to transform the semiconductor layer into a low-doped semiconductor layer, and transforming the dielectric layer into a crystalline ferroelectric layer; forming a gate layer; forming an insulating layer over the gate layer, the crystalline ferroelectric layer and the low-doped semiconductor layer; forming a contact opening in the insulating layer to expose a portion of the low-doped semiconductor layer; and forming a source terminal and a drain terminal on the low-doped semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 6 are schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 7 and Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0009] Fig. 9is a schematic cross-sectional view showing a portion of a structure thereof and a semiconductor device according to some embodiments of the present disclosure.

[0010] Figures 10 to 15 are schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0011] Fig.16 and Fig.17 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0012] Fig.18 and Fig.19 is a schematic perspective view showing a semiconductor device according to some embodiments of the present disclosure.

[0013] Fig. 20 and Fig.21 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0016] In addition, for the convenience of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar or different elements or features shown in the drawings, and may be used interchangeably according to the order of existence or context of the description.

[0017] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed herein are merely illustrative and relate to integrated structures that include more than one type of semiconductor device, and are not intended to limit the scope of the present disclosure. The embodiments of the present disclosure describe exemplary manufacturing processes for integrated structures formed by one or more semiconductor devices (such as transistors) and the integrated structures manufactured thereby. Some embodiments of the present disclosure relate to structures including semiconductor transistors and other semiconductor devices. The substrate and / or wafer may include one or more types of integrated circuits or electronic components therein. The semiconductor device may be formed on a bulk semiconductor substrate or a silicon / germanium on insulator substrate. The embodiments are intended to provide further explanation, but are not intended to limit the scope of the present disclosure.

[0018] Figures 1 to 6 Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figures 1 to 6 A schematic cross-sectional view of a device region DR of an integrated structure is shown. Fig. 9 is a schematic cross-sectional view showing a portion of a structure and a semiconductor device therein according to some embodiments of the present disclosure.

[0019] refer to Figure 1 In some embodiments, a substrate 100 having one or more connection structures 102 therein is provided. Figure 1 As shown, in some embodiments, a connection structure 102 (only one is shown) is formed in the substrate 100 within the device region DR. It should be understood that the number of the connection structure 102 may be more than one, and the number or configuration of the connection structure 102 should not be limited by the exemplary embodiments or drawings of the present disclosure. Figures 1 to 6 , only a portion of the device region DR of the substrate 100 is shown for illustration purposes. In some embodiments, the substrate 100 further includes one or more active components such as transistors, diodes, optoelectronic devices, and / or one or more passive components such as capacitors, inductors, and resistors. Fig. 9 , the integrated structure 90 includes a substrate 900 and a semiconductor device 960 formed on the substrate 900. In some embodiments, the substrate 900 and the semiconductor device 960 are formed on the substrate 900. Figure 1 The substrate 100 is basically similar.

[0020] Reference Figure 1 and Fig. 9In some embodiments, substrate 100 or substrate 900 includes a semiconductor substrate. In one embodiment, substrate 100 or 900 includes a crystalline silicon substrate or a doped semiconductor substrate (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate). In some embodiments, substrate 100 or 900 includes one or more doped regions or various types of doped regions, depending on design requirements. In some embodiments, the doped region is doped with p-type and / or n-type dopants. For example, the p-type dopant is boron or BF2, and the n-type dopant is phosphorus or arsenic. The doped region can be configured for an n-type metal oxide semiconductor (MOS) transistor or a p-type MOS (PMOS) transistor. In some alternative embodiments, substrate 100 or 900 includes a semiconductor substrate made of other suitable elemental semiconductors, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide.

[0021] In some embodiments, Fig. 9 As shown, substrate 900 includes transistors such as NMOS 902 and PMOS 904 formed in semiconductor substrate 901. In one embodiment, NMOS 902 and / or PMOS 904 are formed after a complementary MOS (CMOS) process. Fig. 9 As shown, in some embodiments, more than one isolation structure 906 is formed in the semiconductor substrate 901. In some embodiments, the isolation structure 906 is a trench isolation structure. In other embodiments, the isolation structure 906 includes a local oxidation of silicon (LOCOS) structure. In some embodiments, the insulator material of the isolation structure 906 includes silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, or low-k dielectric material. In one embodiment, the insulator material can be formed by CVD such as high-density plasma chemical vapor deposition (HDP-CVD) and sub-atmospheric pressure CVD (SACVD), or can be formed by spin coating. In some embodiments, transistors such as NMOS 902 and PMOS 904 and the isolation structure 906 are formed in the substrate 900 during the front-end (FEOL) process.

[0022] In some embodiments, the substrate 900 includes a metallization structure 908 embedded in an insulating layer 910. Fig. 9As shown, the insulating layer 910 and the metallization structure 908 are located above the transistor formed in the semiconductor substrate 901. In some embodiments, the insulating layer 910 includes one or more dielectric layers. In some embodiments, the material of the insulating layer 910 includes silicon oxide, spin-on dielectric material, low-k dielectric material or a combination thereof. The formation of the insulating layer 910 includes, for example, performing one or more processes by chemical vapor deposition (CVD) or by spin coating. In some embodiments, the metallization structure 908 includes interconnect structures, such as metal lines, vias and contact plugs. In some embodiments, the material of the metallization structure 908 includes aluminum (Al), aluminum alloy, copper (Cu), copper alloy, tungsten (W) or a combination thereof. In an exemplary embodiment, transistors such as NMOS 902 and PMOS 904 are electrically connected to the metallization structure 908, and some transistors are further electrically interconnected by the metallization structure 908. The metallization structure 908 shown herein is for illustrative purposes only. The metallization structure 908 may include other configurations and may include one or more vias and / or damascene structures.

[0023] Back to Figure 1 In some embodiments, the connection structure 102 embedded in the substrate 100 may be part of a metallization structure in the substrate 100 for electrical connection and interconnection, and the metallization structure in the substrate 100 is similar to Fig. 9 The metallization structure 908 shown in FIG. In one embodiment, the connection structure 102 includes a conductive via. Here, the connection structure 102 may be optional and is representatively shown for the purpose of electrical connection. Figure 1 In the embodiment, the gate material layer 110 is blanket formed over the substrate 100 covering the connection structure. In an embodiment, the gate material layer 110 is in direct contact with the connection structure 102. In some embodiments, the gate material layer 110 includes one or more metal material layers. In some embodiments, the formation of the gate material layer 110 includes one or more deposition processes selected from chemical vapor deposition (CVD) (e.g., plasma enhanced CVD (PECVD) and laser assisted CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g., sputtering and electron beam evaporation). In some embodiments, the formation of the gate material layer 110 includes an electroplating process. In some embodiments, the gate material layer 110 is formed to have a thickness of about 5nm to about 100nm. In some embodiments, the gate material layer 110 is formed to have a thickness of about 1nm to about 50nm. In some embodiments, the material of the gate material layer 110 includes aluminum (Al), titanium (Ti), tungsten (W), tantalum (Ta), nitrides thereof, combinations thereof and / or alloys thereof. For example, the gate material layer 110 may include one or more stacks of TiN, TaN, W / TiN, TiN / TiAl / TiN, or TiN / TiAl / TaN.

[0024] exist Figure 1 In some embodiments, the gate dielectric material layer 120 is integrally formed above the gate material layer 110. In some embodiments, the gate dielectric material layer 120 includes a ferroelectric material. In some embodiments, the material of the gate dielectric material layer 120 includes an amorphous ferroelectric material and / or a polycrystalline ferroelectric material. In some embodiments, the gate dielectric material layer 120 includes an amorphous ferroelectric material and a crystalline ferroelectric material. In some embodiments, the gate dielectric material layer 120 includes one or more selected from hafnium zirconium oxide (or hafnium oxide doped with zirconium) or hafnium oxide doped with silicon, aluminum, lanthanum (La) and / or gadolinium (Gd). In one embodiment, the material of the gate dielectric material layer 120 includes hafnium zirconium oxide, denoted as Hf (x) Zr (1-x) O2, where x is in the range of 0.1 to 0.9 (0.1≤x≤0.9). In one embodiment, the material of the gate dielectric material layer 120 includes silicon-doped hafnium oxide (HfSiO), aluminum-doped hafnium oxide (HfAlO), lanthanum-doped hafnium oxide (HfLaO) and / or gadolinium-doped hafnium oxide (HfGdO). In some embodiments, the formation of the gate dielectric material layer 120 includes one or more deposition processes selected from CVD (e.g., PECVD and laser-assisted CVD), ALD, and PVD (e.g., sputtering and electron beam evaporation). For example, the gate dielectric material layer 120 can be formed by depositing a hafnium zirconium oxide layer by ALD. In some embodiments, the gate dielectric material layer 120 is formed to have a thickness of about 3 nm to about 20 nm.

[0025] In some embodiments, after forming the gate dielectric material layer 120, a semiconductor material layer 130 is formed over the gate dielectric material layer 120 to form a stack structure 10. In some embodiments, the material of the semiconductor material layer 130 includes a metal oxide material. In some embodiments, the formation of the semiconductor material layer 130 includes one or more deposition processes selected from the following: CVD (e.g., PECVD and laser-assisted CVD), ALD and PVD (e.g., sputtering, pulsed laser deposition (PLD)) and electron beam evaporation). For example, the formation of the semiconductor material layer 130 includes a CVD process or an ALD process. In an embodiment, the semiconductor material layer 130 is formed to have a thickness of about 1 nm to about 30 nm. In some embodiments, the material of the semiconductor material layer 130 includes indium gallium zinc oxide (IGZO). In some embodiments, the material of the semiconductor material layer 130 includes a conductive oxide semiconductor material, such as gallium oxide (e.g., Ga2O3), indium oxide (e.g., In2O3), zinc oxide (ZnO), titanium oxide (e.g., TiO2), aluminum oxide (e.g., Al2O3), or a combination thereof.

[0026] Reference Figure 1 and Figure 2 In some embodiments, a patterning process is performed on the stack structure 10 of the gate material layer 110, the gate dielectric material layer 120, and the semiconductor material layer 130, so that the stack structure 10 is patterned to form a stack structure 12, and the stack structure 12 has a gate layer 111, a gate dielectric layer 121, and a semiconductor layer 131 sequentially stacked from bottom to top. In some embodiments, the stack structure 10 of the gate material layer 110, the gate dielectric material layer 120, and the semiconductor material layer 130 is patterned into the stack structure 12 in a continuous patterning process. In some embodiments, the gate material layer 110, the gate dielectric material layer 120, and the semiconductor material layer 130 are sequentially patterned by multiple patterning processes. Figure 2 As shown, in an exemplary embodiment, the patterned stack structure 12 is disposed on the connection structure 102 , thereby exposing the substrate 100 . Figure 2 The sidewalls of the stack structure 12 can be shown as being vertically aligned or coplanar, and the stack structure 12 can be patterned into substantially the same pattern design or configuration. However, it should be understood that the various layers of the stack structure 12 may have different patterns or configurations depending on the product design. In some embodiments, the patterning and formation of the stack structure 12 includes performing a photolithography process and an anisotropic etching process. In some embodiments, a photoresist pattern (not shown) can be used as an etching mask to remove portions of the stack structure 10 that are not covered by the photoresist pattern during the etching process, and then the photoresist pattern is removed by a stripping process.

[0027] exist Figure 3In the embodiment, the semiconductor layer 131 and the gate dielectric layer 121 of the stack structure 12 are subjected to a pressure treatment PT so that the semiconductor layer 131 and the gate dielectric layer 121 are respectively transformed into a low-doped semiconductor layer 131P and a crystalline ferroelectric layer 121P, and an interface layer 140 is provided between the low-doped semiconductor layer 131P and the crystalline ferroelectric layer 121P. In some embodiments, the pressure treatment PT includes performing a high pressure annealing (HPA) treatment in an ambient atmosphere of oxygen (O2). In an embodiment, the HPA treatment is performed in an annealing chamber at a pressure of at least higher than 1 atm in a temperature range of about 300 degrees Celsius to about 450 degrees Celsius, in an environment of 100% O2, for a treatment time of about 1 minute to 5 hours. In an embodiment, the HPA treatment is performed in an annealing chamber at a higher pressure (higher than 1 atm) and a treatment time of less than one hour. In one embodiment, the HPA treatment is performed in a temperature range of about 300 degrees Celsius to about 450 degrees Celsius, which is relatively lower than the crystallization annealing temperature. It should be understood that the exposed substrate 100 may remain unchanged or protected during processing even if not clearly shown in the drawings or described in context. In some embodiments, the gate layer 111 remains unchanged during the pressurization process PT because the material of the gate layer 111 is quite stable.

[0028] In some embodiments, the amorphous ferroelectric material in the gate dielectric layer 121 is transformed and becomes polycrystalline to form a crystalline ferroelectric layer 121P by the high pressure and lower annealing temperature used in the HPA process. That is, the HPA process crystallizes the amorphous ferroelectric material of the gate dielectric layer 121, and the gate dielectric layer 121 is tuned to a crystalline ferroelectric layer 121P. In an embodiment, more than 50% or 60% of the ferroelectric phase exists in the material of the crystalline ferroelectric layer 121P. In an embodiment, more than 70% or 80% of the ferroelectric phase exists in the material of the crystalline ferroelectric layer 121P. In an embodiment, more than 90% of the ferroelectric phase exists in the material of the crystalline ferroelectric layer 121P. For example, by the pressure treatment PT, the amorphous hafnium zirconium oxide material in the gate dielectric layer 121 is transformed and crystallized, wherein at least 50% of the ferroelectric phase (e.g., orthorhombic phase) exists. Due to the presence of the ferroelectric phase in the material, a crystalline ferroelectric layer 121P with good ferroelectric properties and crystallinity is formed. In some embodiments, for example, in the case where the ferroelectric phase includes HfO2, the ferroelectric phase is an orthorhombic phase. Some parameters such as the material selection of the metal gate may affect the ferroelectric response of the ferroelectric material, because the crystal structure and strain introduced by the gate layer 111 will affect the crystallinity of the crystalline ferroelectric layer 121P. Since a ferroelectric phase is formed in the crystalline ferroelectric layer 121P, a ferroelectric response is achieved for the crystalline ferroelectric layer 121P. The selection of the material of the gate layer 111 is not strictly limited and is separated from the ferroelectric phase of the ferroelectric layer. In some embodiments, the semiconductor material of the semiconductor layer 131 is solidified by the annealing and oxygen environment used in the HPA process, and the oxygen vacancies of the semiconductor layer 131 are stabilized and reduced, so that the doping level of the semiconductor layer 131 is reduced. The semiconductor layer 131 is reduced (compared to the untreated semiconductor layer 131), and a low-doped semiconductor layer 131P is formed. That is, there are fewer oxygen vacancies in the low-doped semiconductor layer 131P. In one embodiment, the low-doped semiconductor layer 131P has a lower electron doping level (for example, having a 1E17cm -3 To 1E19cm -3 The low temperature annealing is compatible with the back-end process of the production line and is also beneficial to the semiconductor layer 131 due to its low tolerance to high temperature. By using the HPA process with a lower annealing temperature, the formed semiconductor layer 131 has good quality and a satisfactory doping level.

[0029] refer to Figure 3In some embodiments, after performing the pressure treatment PT, an interface layer 140 is formed between the crystalline ferroelectric layer 121P and the low-doped semiconductor layer 131P. In an embodiment, the interface layer 140 is formed to have a thickness of about 0.1 nm to about 2 nm. The interface layer 140 is formed of the same or similar elements from the upper and lower layers by the interaction between the gate dielectric layer 121 and the semiconductor layer 131 during the pressure treatment PT. In some embodiments, the formed interface layer 140 includes elements or components mainly from the gate dielectric layer 121. In some embodiments, the formed interface layer 140 includes elements or components mainly from the semiconductor layer 131. In some embodiments, the formed interface layer 140 includes materials or elements or components from the gate dielectric layer 121 and the semiconductor layer 131 whose stoichiometric ratios change under different reaction conditions. In some embodiments, the formed interface layer 140 includes a composition gradient region, and the composition may gradually change from one layer to another. In some embodiments, the material of the interface layer 140 includes hafnium oxide, aluminum oxide, or a combination thereof. In some embodiments, the interface layer 140 may be formed between the crystalline ferroelectric layer 121P and the low-doped semiconductor layer 131P without a distinct interface therebetween. For example, the interface layer 140 may be formed due to thermodynamic equilibrium and element diffusion. The formation of the interface layer 140 may help prevent the formation of a non-ferroelectric phase in the crystalline ferroelectric layer 121P and may enhance the ferroelectric properties of the crystalline ferroelectric layer 121P.

[0030] In some alternative embodiments, by adjusting the conditions of the pressure treatment PT, no interface layer is formed between the crystalline ferroelectric layer 121P and the low-doped semiconductor layer 131P under appropriate reaction conditions.

[0031] Reference Figure 4 , an interlayer dielectric (ILD) layer 150 having a contact opening 155 is formed over the substrate 100. In some embodiments, the material of the ILD layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, or one or more low-k dielectric materials. Examples of low-k dielectric materials include silicate glass, such as fluorosilicate glass (FSG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG), Hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene) or a combination thereof. It should be understood that the ILD layer 150 may include one or more dielectric materials or one or more dielectric layers. In some embodiments, the ILD layer 150 is formed to a suitable thickness by CVD (e.g., flowable CVD (FCVD), PECVD, high density plasma CVD (HDPCVD), sub-atmospheric pressure CVD (SACVD) and low pressure CVD (LPCVD)), spin coating or other suitable methods. For example, the ILD layer 150 can be formed by PECVD to cover the exposed substrate 100 and the stack structure 12, and the stack structure 12 has a gate layer 111, a crystalline ferroelectric layer 121P, a low-doped semiconductor layer 131P and an interface layer 140. The contact opening 155 is formed in the ILD layer 150, exposing the low-doped semiconductor layer 131P. For example, the formation of the contact opening 155 may include forming a patterned mask layer (not shown) over the ILD layer 150, and anisotropically etching the ILD layer 150 using the patterned mask layer as a mask to form the contact opening 155 exposing the top surface 131Pt. Figure 4 As shown, the contact opening 155 is shown as having substantially vertical sidewalls. It is understood that the contact opening can be formed with sloped sidewalls if feasible.

[0032] Afterwards, in Figure 5 , a contact terminal 160 is formed in the contact opening 155 and is in direct contact with the low-doped semiconductor layer 131P. In some embodiments, a barrier layer 162 is deposited over the contact opening 155 and conformally covers the sidewalls of the contact opening 155 and covers the top surface 131Pt of the low-doped semiconductor layer 131P. In some embodiments, a seed layer 164 is formed over the contact opening 155 and on the barrier layer 162. In some embodiments, the barrier layer 162 is formed before forming the seed layer 164 to prevent the material of the seed layer from outwardly diffusing. After the seed layer 164 is formed to cover the sidewalls and the bottom of the contact opening 155, a metal contact 166 is then formed on the seed layer 164 within the contact opening 155 and fills the contact opening 155. Referring to Figure 5 , the contact terminal 160 is directly formed on the low-doped semiconductor layer 131P.

[0033] In some embodiments, a barrier material (not shown) and a seed material (not shown) are sequentially formed over the contact opening 155 and conformally cover the exposed low-doped semiconductor layer 131P and the sidewalls of the contact opening 155, and then a metal material (not shown) is filled into the contact opening 155 and on the seed material to form a metal contact 166. The barrier material, the seed material, and the metal material may include, for example, one or more materials selected from tungsten (W), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, and nitrides thereof. In some embodiments, the barrier material is formed by CVD or PVD. In some embodiments, the seed material is formed by CVD or PVD. In some embodiments, the metal material is formed by CVD or PVD. In alternative embodiments, the formation of the metal material may include performing a plating process (such as electrochemical plating (ECP)). In some embodiments, the barrier material includes titanium nitride (TiN) formed by a metal organic CVD (MOCVD) process, the seed material includes tungsten formed by CVD, and the metal material includes tungsten formed by a CVD process (particularly a tungsten CVD process). For example, the metal contact 166 includes a tungsten contact, and the barrier layer 162 includes a titanium nitride barrier layer.

[0034] In some embodiments, the additional barrier material, the additional seed material, and the additional metal material may be removed by performing a planarization process, an etching process, or other suitable process. In some embodiments, the planarization process may include performing a chemical mechanical polishing (CMP) process. In some embodiments, the barrier layer 162, the seed layer 164, and the metal contact 166 constitute the contact terminal 160. Figure 5 As shown, the top surface 150t of the ILD layer 150 is substantially flush and level with the top surface 160t of the contact terminal 160. In some embodiments, the contact terminal 160 serves as a source terminal and a drain terminal of the transistor. Figure 5 , a transistor structure 50 is obtained. The transistor structure 50 includes a stack structure 12, the stack structure 12 having a gate layer 111, a crystalline ferroelectric layer 121P, an interface layer 140, and a low-doped semiconductor layer 131P sequentially stacked from bottom to top, and a contact terminal 160 is located on the stack structure 12. The low-doped semiconductor layer 131 is used as a channel layer of the transistor structure 50. In some embodiments, the transistor structure 50 is a bottom-gate transistor structure or a back-gate transistor structure.

[0035] A ferroelectric field effect transistor (FE-FET) is a transistor comprising a ferroelectric material sandwiched between the gate and source-drain conductive regions of the device. In some embodiments, transistor structure 50 comprises a ferroelectric field effect transistor (FE-FET), and crystalline ferroelectric layer 121P serves as a gate insulator or gate dielectric layer of the transistor structure.

[0036] Reference Figure 6 In some embodiments, an interconnect structure 170 is formed on the ILD layer 150 and above the contact terminal 160, and a semiconductor device structure 60 is formed. In one embodiment, the interconnect structure 170 is in direct contact with the contact terminal 160 and is electrically connected to the contact terminal 160 of the transistor structure 50, so that the transistor structure 50 is further electrically connected to other components or devices. In some embodiments, the interconnect structure 170 includes a first metal line 172 formed on a first liner layer 174 and a first metal via 176 surrounded by a second liner layer 178. In some embodiments, a first liner material (not shown) is directly formed on the ILD layer 150 and on the top surface 160t of the contact terminal 160, a first metal layer (not shown) is formed on the first liner material, and then the first liner material and the first metal layer are patterned into a first metal line 172 and a first liner layer 174 is formed using photolithography and etching techniques. The first liner material can be formed by, for example, PVD (such as sputtering) or CVD. In some embodiments, the first liner material includes, for example, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, combinations thereof, or other suitable materials. In some embodiments, the first liner layer 174 can prevent the material of the first metal line 172 from diffusing outward and / or improve the adhesion of the first metal line 172. In some embodiments, the first metal layer can be formed by performing a plating process, such as electrochemical plating (ECP) or chemical plating, a PVD process, or a CVD process. In some embodiments, the first metal layer includes, for example, copper, copper-aluminum alloy, tantalum, titanium, tungsten, alloys thereof, or other suitable metal materials.

[0037] In some embodiments, Figure 6 As shown, the first metal line 172 is in direct contact with and electrically connected to the contact terminal 160. For example, the first metal line 172 may include copper or a copper alloy and may be formed by performing a PVD process and a CVD process. In one embodiment, the thickness of the first metal line 172 may be adjusted according to design requirements. Figure 6 As shown, in some embodiments, another ILD layer 180 is formed over the ILD layer 150 and the first metal line 172. The material and formation method of the ILD layer 180 may be similar to the material and formation method of the ILD layer 150, and will be described in detail. For simplicity, it is omitted later. A via opening V is formed in the ILD layer 180 to partially expose the first metal line 172 below. One or more methods for forming the via opening V are similar to the method for forming the contact opening 155. Figure 6 , a via V having sloped sidewalls is shown. It should be understood that the via opening may be formed with substantially vertical sidewalls, if feasible.

[0038] In some embodiments, Figure 6 In the embodiment of the present invention, a second liner layer 178 is formed in the through hole V covering the sidewall and bottom of the through hole V, and then a first metal via 176 is formed on the second liner layer 178 and in the through hole V. Then, a second liner material (not shown) is formed over the through hole V and conformally covers the exposed surface of the through hole V, and then a second metal layer (not shown) is formed on the ILD layer 180 and filled into the opening V. The formation method and material of the second liner layer 178 are similar to those of the first liner layer 174. The formation method and material of the first metal via 176 are similar to those of the first metal line 172. For simplicity, a detailed description thereof will be skipped here. However, it should be understood that the material of the first metal line 172 may be different from that of the first metal via 176, and the material of the first liner layer 174 may be different from that of the second liner layer 178.

[0039] Figure 6 The number and configuration of the metal lines and / or metal vias of the interconnect structure 170 shown are for illustration only, and in some alternative embodiments, more than two metal lines or metal vias may be formed according to actual design requirements. In addition, a multi-layer interconnect structure may be formed for electrical connection and interconnection.

[0040] The semiconductor device structure 60 illustrates an integrated circuit or a portion of an integrated circuit. In some embodiments, the semiconductor device structure 60 includes active devices such as oxide semiconductor thin film transistors, high voltage transistors, and / or other suitable components. In some embodiments, the semiconductor device structure 60 also includes passive components such as resistors, capacitors, inductors, and / or fuses. In some embodiments, the semiconductor device structure 60 may be configured to include a plurality of semiconductor components. Figures 1 to 6 Additional steps are provided before, during, and after the processing steps shown, and some of the steps described above may be replaced or eliminated for other embodiments of the method.

[0041] In the illustrated embodiment, the described methods and structures can be formed compatible with current semiconductor manufacturing processes. In an exemplary embodiment, the described methods and structures are formed in a back-end-of-line (BEOL) process. In some embodiments, the described methods and structures can be formed in an intermediate process.

[0042] In the above-mentioned embodiment, the gate dielectric layer and the semiconductor layer are processed and transformed into a crystalline ferroelectric layer and a low-doped semiconductor layer, respectively, by a pressurization treatment. By a single pressurization treatment (including an HPA treatment in an oxygen environment), the amorphous ferroelectric layer becomes a crystalline ferroelectric layer having good ferroelectric properties and realizing a ferroelectric response. At the same time, by performing a single pressurization treatment, the semiconductor channel layer has better stability, the oxygen vacancies and the doping level of the semiconductor channel layer are adjusted to the desired level, and the threshold voltage of the ferroelectric transistor is appropriately set. By adjusting the parameters and / or conditions of the pressurization treatment, the characteristics of the crystalline ferroelectric layer and the low-doped semiconductor layer can be fine-tuned, and the performance of the semiconductor device can be improved. Instead of multiple treatments, only one pressurization treatment is performed for the manufacture of the transistor structure, which leads to increased output and production yield.

[0043] In some embodiments, the interface layer formed between the low-doped semiconductor layer and the crystalline ferroelectric layer regulates interface characteristics between the low-doped semiconductor layer and the crystalline ferroelectric layer and enhances ferroelectric characteristics of the crystalline ferroelectric layer.

[0044] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 7 The exemplary structure shown in FIG. Figures 1 to 6 The process steps described in the embodiments are used for manufacturing, but it should be understood that any other compatible process steps or methods can be utilized, and understandable modifications or adjustments can be made to form the exemplary structures of the present disclosure. Figure 7 In some embodiments, the semiconductor device structure 70 includes a stack structure of a gate layer 710, a crystalline ferroelectric layer 720, an interface layer 740, and a low-doped semiconductor layer 730 sequentially stacked from bottom to top. In some embodiments, the semiconductor device structure 70 includes a source terminal 760A and a drain terminal 760B located on the low-doped semiconductor layer 730. In some embodiments, the source terminal 760A and the drain terminal 760B are separated from each other by an intermediate layer of a dielectric (ILD) layer 750 located therebetween. In some embodiments, the source terminal 760A includes a barrier layer 762A, and the drain terminal 760B also includes a barrier layer 762B. In some embodiments, the low-doped semiconductor layer 730 is in direct contact with the source terminal 760A and the drain terminal 760B. Figure 7 In the embodiment, the interface layer 740 is sandwiched between the low-doped semiconductor layer 730 and the crystalline ferroelectric layer 720. Suitable materials for the various layers or elements are described in the previous embodiments and will not be repeated here.

[0045] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 8 The exemplary structure shown in FIG. 1 can be used in the same manner as previously described. Figures 1 to 6 However, in some embodiments, by adjusting the parameters and conditions of the pressure treatment, no clear interface layer is formed. Figure 8 The structure shown is similar to but different from Figure 7 The structure shown in the figure has the following main structural differences: Figure 8 The interface layer in the semiconductor device structure 80 is shown. Figure 8 In some embodiments, the semiconductor device structure 80 includes a stack structure of a gate layer 810, a crystalline ferroelectric layer 820, and a low-doped semiconductor layer 830 sequentially stacked from bottom to top. In some embodiments, the structure 80 includes a source terminal 860A and a drain terminal 860B located on the low-doped semiconductor layer 830. In some embodiments, the source terminal 860A and the drain terminal 860B are in contact with the low-doped semiconductor layer and are separated from each other by an interlayer dielectric (ILD) layer 850. In some embodiments, the ILD layer 850 located between the source and drain terminals 860A, 860B is in direct contact with the low-doped semiconductor layer 830. Figure 8 , source terminal 860A includes blocking layer 862A, and drain terminal 860B also includes blocking layer 862B.

[0046] Figures 10 to 15 are schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0047] Reference Fig.10 In some embodiments, a substrate 300 is provided. Figures 10 to 16 , only a portion of the substrate 300 is shown for illustration purposes. In some embodiments, the substrate 300 is similar to the substrates 100, 900 in the previous embodiments, and the substrate 300 may include one or more active components, such as transistors, diodes, optoelectronic devices, and / or one or more passive components, such as capacitors, inductors, and resistors. Fig.10As shown, a semiconductor layer 330 and an isolation structure 305 are formed over the substrate 300. In some embodiments, the semiconductor layer 330 is formed by forming a semiconductor material layer (not shown) over the substrate 300 and patterning the semiconductor material layer into a semiconductor layer 330, and defining the active area AR by a patterning process. Thereafter, an isolation structure 305 is formed in the non-active area NAR surrounding the active area AR for isolation. In an embodiment, the thickness of the formed semiconductor layer 330 is about 1 nm to about 5 nm. In some embodiments, the material of the semiconductor material layer includes indium gallium zinc oxide (IGZO). In some embodiments, the material of the semiconductor material layer includes a conductive oxide semiconductor material, such as gallium oxide (e.g., Ga2O3), indium oxide (e.g., In2O3), zinc oxide (ZnO), titanium oxide (e.g., TiO2), aluminum oxide (e.g., Al2O3), or a combination thereof. In some embodiments, the formation of the semiconductor material layer includes one or more deposition processes selected from CVD, ALD, and PVD. In an embodiment, the semiconductor layer 330 is made of IGZO formed by PVD. Referring to Fig.10 In some embodiments, more than one isolation structure 305 is formed on the substrate 300. In some embodiments, the isolation structure 305 is a trench isolation structure, and the insulator material of the isolation structure 305 includes silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, or low-k dielectric material.

[0048] Reference Fig.10 , a gate dielectric material layer 320 is formed over the semiconductor layer 330 and the isolation structure 305. In some embodiments, the gate dielectric material layer 320 includes a ferroelectric material. In some embodiments, the material of the gate dielectric material layer 320 includes an amorphous ferroelectric material. In some embodiments, the material of the gate dielectric material layer 320 includes an amorphous ferroelectric material and a crystalline ferroelectric material. In some embodiments, the gate dielectric material layer 320 includes one or more selected from hafnium zirconium oxide (or hafnium oxide doped with zirconium) or hafnium oxide doped with silicon, aluminum, lanthanum (La) and / or gadolinium (Gd). In one embodiment, the material of the gate dielectric material layer 320 includes hafnium zirconium oxide, denoted as Hf (x) Zr (1-x)O2, where x is in the range of 0.1 to 0.9 (0.1≤x≤0.9). In an embodiment, the material of the gate dielectric material layer 320 includes silicon-doped hafnium oxide (HfSiO), aluminum-doped hafnium oxide (HfAlO), lanthanum-doped hafnium oxide (HfLaO) and / or gadolinium-doped hafnium oxide (HfGdO). In some embodiments, the formation of the gate dielectric material layer 320 includes one or more deposition processes selected from CVD (e.g., PECVD and laser-assisted CVD), ALD and PVD (e.g., sputtering and electron beam evaporation). For example, the gate dielectric material layer 320 can be formed by depositing a hafnium zirconium oxide layer by ALD. In some embodiments, the gate dielectric material layer 120 is formed to have a thickness of about 3 nm to about 20 nm.

[0049] Reference Fig.11 , a pressure treatment PT is performed on the semiconductor layer 330 and the gate dielectric material layer 320, thereby converting the semiconductor layer 330 and the gate dielectric material layer 320 into a low-doped semiconductor layer 331 and a crystallized ferroelectric material layer 321, respectively, and an interface layer 340 is formed between the low-doped semiconductor layer 331 and the crystallized ferroelectric material layer 321. Since the semiconductor layer 330 is located in the active region AR, the interface layer 340 is mainly located in the active region AR. In some embodiments, the pressure treatment PT includes performing a high pressure annealing (HPA) treatment in an ambient atmosphere of oxygen (O2). In an embodiment, the HPA treatment is performed in an annealing chamber with a pressure of at least higher than 1atm in a temperature range of about 300 degrees Celsius to about 450 degrees Celsius, in an environment of 100% O2, and for a treatment time of about 1 minute to 5 hours. In an embodiment, the HPA treatment is performed in the annealing chamber at a higher pressure (higher than 1atm) and a treatment time of less than one hour. In one embodiment, the HPA process is performed at a temperature ranging from about 300 degrees Celsius to about 450 degrees Celsius, which is relatively lower than the crystallization annealing temperature. It should be understood that during the pressure process PT, the substrate 300 and the isolation structure 305 may remain unchanged.

[0050] In some embodiments, the interface layer 340 is formed between the crystalline ferroelectric material layer 321 and the low-doped semiconductor layer 331. In one embodiment, the thickness of the interface layer 340 is formed to be about 0.1 nm to about 2 nanometers. In some embodiments, under different reaction conditions, the formed interface layer 340 includes some elements or components of stoichiometric ratio changes from one or both of the gate dielectric material layer 320 and the semiconductor layer 330. In some embodiments, the formed interface layer 340 includes a composition gradient region, and the composition can gradually change from one layer to another. In some embodiments, the material of the interface layer 340 includes hafnium oxide, aluminum oxide, or a combination thereof. In some embodiments, the interface layer 340 can be formed between the crystalline ferroelectric material layer 321 and the low-doped semiconductor layer 331 without a clear interface therebetween. For example, the formation of the interface layer 340 can help prevent the formation of a non-ferroelectric phase in the crystalline ferroelectric material layer 321 and enhance the ferroelectric properties of the crystalline ferroelectric material layer 321.

[0051] Reference Fig.12 , a patterning process is performed to define the layers stacked on the low-doped semiconductor layer 331 to form a gate layer 310 and a crystalline ferroelectric layer 321P. After the pressure treatment PT, a gate material layer (not shown) is formed on the crystalline ferroelectric material layer 321, and then patterned into the gate layer 310. During the patterning process, not only the crystalline ferroelectric material layer 321 is patterned into the gate. In the crystalline ferroelectric layer 321P, the interface layer 340 below the crystalline ferroelectric material layer 321 is also patterned into an interface layer 340P. In some embodiments, the gate layer 310, the crystalline ferroelectric layer 321P and the interface layer 340P are sequentially stacked on the low-doped semiconductor layer 331. In some embodiments, the patterning process includes photolithography and etching processes. In some embodiments, the material of the gate layer 310 includes aluminum (Al), titanium (Ti), tungsten (W), tantalum (Ta), nitrides thereof, combinations thereof and / or alloys thereof. For example, the gate layer 310 may include one or more stacks of TiN, TaN, W / TiN, TiN / TiAl / TiN or TiN / TiAl / TaN. In some embodiments, the formation of the gate material layer includes one or more deposition processes selected from CVD, ALD and PVD.

[0052] Reference Fig.12 In an exemplary embodiment, the stack structure 31 of the gate layer 310, the crystalline ferroelectric layer 321P, and the interface layer 340P disposed on the low-doped semiconductor layer 331 may be referred to as a gate structure. In some embodiments, the stack structure 31 partially covers the low-doped semiconductor layer 331 below, thereby exposing a portion of the low-doped semiconductor layer 331.

[0053] In some embodiments, Fig.12As shown, the stack structure 31 of the gate layer 310 , the crystalline ferroelectric layer 321P and the interface layer 340P is located in the active region AR. Fig.12 The sidewalls of the stack structure 31 of the gate layer 310, the crystalline ferroelectric layer 321P, and the interface layer 340P are shown to be vertically aligned or coplanar, and the low-doped semiconductor layer 331 may have a pattern different from the pattern of the stack structure 31 of the gate layer 310, the crystalline ferroelectric layer 321P, and the interface layer 340P. However, it should be understood that the various layers of the stack structure may have different patterns or configurations depending on the product design.

[0054] exist Fig.13 In the embodiment, an ILD layer 350 is formed, and contact openings 355, 356 above the substrate 300 cover the stack structure 31 of the gate layer 310, the crystalline ferroelectric layer 321P and the interface layer 340P, the exposed low-doped semiconductor layer 331 and the isolation structure 305. The material and formation method of the ILD layer 350 are similar to those of the ILD layer described in the above paragraphs, and for simplicity, the details will be omitted here.

[0055] Reference Fig.13 , contact openings 355 and 356 are formed in the ILD layer 350 to expose portions of the low-doped semiconductor layer 331 and the gate layer 310, respectively. In some embodiments, the contact opening 355 exposes a portion of the top surface 331t of the semiconductor layer 331. In some embodiments, one or more contact openings 356 expose the gate layer 310. Fig.13 , contact openings 355 and 356 are shown as having substantially vertical sidewalls. It will be appreciated that, if feasible, the contact holes may be formed with inclined sidewalls. The number or size of the contact openings is not limited to the number or size shown in the drawings.

[0056] Afterwards, in Fig.14In some embodiments, the contact terminal 360 is formed in the contact opening 355 and in the contact opening 356. In some embodiments, the contact terminal 360 formed in the contact opening 355 is directly located on the low-doped semiconductor layer 331, respectively. In some embodiments, the contact terminal 360 is directly formed on the top surface 331t of the low-doped semiconductor layer 331, and the bottom surface 360b of the contact terminal 360 is in direct contact with the top surface 331t of the low-doped semiconductor layer 331 in the contact opening 355. In some embodiments, the barrier layer 362 is deposited above the contact openings 355 and 356 and conformally covers the sidewalls and bottom of the contact openings 355 and 356. Similar materials and formation methods for forming the contact terminal 160 can be used to form the contact terminal 360, and the contact terminal 360 can be formed with a seed layer and / or an adhesion layer, but for simplicity, the details are skipped here. In some embodiments, the contact terminal 360 formed in the contact opening 356 is directly connected to the gate layer 310.

[0057] Reference Fig.14 In some embodiments, a transistor structure 30 is obtained, and the contact terminals 360 are used as source and drain terminals of the transistor. Fig.14 In the embodiment, the transistor structure 30 includes a stacked structure 31 of a low-doped semiconductor layer 331, a gate layer 310, a crystalline ferroelectric layer 321P and an interface layer 340P, and a contact terminal 360 located on the semiconductor layer 331. The low-doped semiconductor layer 331 is used as a channel layer, and the interface layer 340P located between the crystalline ferroelectric layer 321P and the low-doped semiconductor layer 331 helps to enhance the ferroelectric properties of the crystalline ferroelectric layer 321P. In some embodiments, the transistor structure 30 is a top-gate transistor structure or a front-gate transistor structure.

[0058] Reference Fig.15 In some embodiments, an interconnect structure 370 and another ILD layer 380 are formed on the ILD layer 350, and a semiconductor device structure 40 is formed. In some embodiments, the interconnect structure 370 is formed on and in direct contact with the contact terminal 360, and is electrically connected to the contact terminal 360 of the transistor structure 30, so that the transistor structure 30 is further electrically connected to other components or devices. In some embodiments, the interconnect structure 370 includes a metal line 372 and a metal via 376 connected to the metal line 372. Similar materials and formation methods used to form the interconnect structure 170 can be used to form the interconnect structure 370, and the interconnect structure 370 can be formed with a liner layer, a seed layer and / or a barrier layer / adhesion layer, and a multi-layer interconnect structure can be formed for electrical connection and interconnection.

[0059] Although the steps of the method are illustrated and described as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted in a limiting sense. In addition, not all of the processes or steps shown are necessary to implement one or more embodiments of the present disclosure.

[0060] Fig.16 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure. Fig.16 In some embodiments, the semiconductor device structure 42 includes a gate structure 1600 of a gate layer 1610 sequentially stacked on a low-doped semiconductor layer 1630 (from top to bottom), a crystalline ferroelectric layer 1620, and an interface layer 1640. In some embodiments, the semiconductor device structure 42 includes a source terminal 1660A and a drain terminal 1660B directly located on the low-doped semiconductor layer 1630. In some embodiments, the source terminal 1660A and the drain terminal 1660B are located at two opposite sides of the semiconductor device structure and are separated from the gate structure 1600 by an interlayer dielectric (ILD) layer 1650 located therebetween. In some embodiments, the source terminal 1660A and the drain terminal 1660B may further include a seed layer and / or an adhesion / barrier layer. In some embodiments, the interface layer 1640 contacts and abuts the crystalline ferroelectric layer 1620 and the low-doped semiconductor layer 1630. In some embodiments, the ILD layer 1650 sandwiched between the source terminal 1660A and the drain terminal 1660B is directly located on the low-doped semiconductor layer 1630. Fig.16 In the embodiment, the bottom surface 1640 b of the interface layer 1640 is in contact with the top surface 1630 t of the low-doped semiconductor layer 1630 .

[0061] Fig.17 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Fig.17 The structure shown is similar to but different from Fig.16 The main structural difference of the structure shown is that there is no interface layer in the semiconductor device structure 44, such as Fig.17 See Fig.17 In some embodiments, the semiconductor device structure 44 includes a gate structure 1700 of a gate layer 1710 stacked on a low-doped semiconductor layer 1730 and a crystalline ferroelectric layer 1720. In some embodiments, the structure 44 includes a source terminal 1760A and a drain terminal 1760B directly located on the low-doped semiconductor layer 1730. In some embodiments, the source terminal 1760A and the drain terminal 1760B are physically separated from (but electrically connected to) the underlying low-doped semiconductor layer 1730. The gate structure 1700 is then covered by an ILD layer 1750, and the crystalline ferroelectric layer 1720 is in direct contact with the semiconductor layer 1730.

[0062] Fig.18 and Fig.19 is a schematic perspective view showing a semiconductor device according to some embodiments of the present disclosure. Fig.18 The structure is shown before the source and drain terminals are formed. Fig.19 The structure is shown after forming the source and drain terminals. Fig. 20 and Fig.21 According to some embodiments of the present disclosure, Fig.19 Schematic cross-sectional views of a semiconductor device taken along lines AA′ and BB′.

[0063] Reference Fig.18 In some embodiments, the semiconductor device structure 46 includes a low-doped semiconductor layer 1930, a crystalline ferroelectric layer 1920 located on and surrounding the low-doped semiconductor layer 1930, and an interface layer 1940 located between the low-doped semiconductor layer 1930 and the crystalline ferroelectric layer 1920. Fig.18 , Fig.19 , Fig. 20 and Fig.21 , it can be seen that the interface layer 1940 occupies the interface between the low-doped semiconductor layer 1930 and the crystalline ferroelectric layer 1920, and extends not only on the top surface 1930t of the low-doped semiconductor layer 1930 but also on two opposite side surfaces 1930s. In some embodiments, the inverted U-shaped gate layer 1910, the inverted U-shaped crystalline ferroelectric layer 1920, and the inverted U-shaped interface layer 1940 surround the low-doped semiconductor layer 1930, and the interface layer 1940 physically contacts the top surface 1930t and the two opposite side surfaces 1930s of the low-doped semiconductor layer 1930. That is, the interface layer 1940 covers at least three sides of the low-doped semiconductor layer 1930 and is surrounded by the crystalline ferroelectric layer 1920 and the gate layer 1910. See FIG. Fig.19 , Fig. 20 and Fig.21 The gate structure 1900 of the gate layer 1910, the crystalline ferroelectric layer 1920 and the interface layer 1940 is disposed on the top side and two opposite sides of the low-doped semiconductor layer 1930 and surrounds them. Fig.19 and Fig.21In some embodiments, the gate structure 1900 may have an inverted U-shape wrapped around the semiconductor layer 1930. In some embodiments, the semiconductor device structure 46 includes a source terminal 1960 and a drain terminal 1960 directly located on the low-doped semiconductor layer 1930, and the source terminal 1960 and the drain terminal 1960 may respectively have an inverted U-shape wrapped around the low-doped semiconductor layer 1930. In some embodiments, the source terminal 1960 and the drain terminal 1960 are located at two opposite sides of the gate structure 1900 and are separated from the gate structure 1900 by an interlayer dielectric (ILD) layer (not shown) located therebetween. Fig.19 , Fig. 20 and Fig.21 In the example, the ILD layer is not shown for simplicity. In some embodiments, the source terminal and the drain terminal 1960 may further include a seed layer and / or an adhesion / barrier layer. In some embodiments, the semiconductor device structure 46 includes a dual-gate transistor structure.

[0064] In an exemplary embodiment, forming an interface layer between a channel layer (eg, a low-doped semiconductor layer) and a crystalline ferroelectric layer enhances the ferroelectric properties of the ferroelectric layer. Overall, the performance of the semiconductor device is enhanced.

[0065] In some embodiments of the present disclosure, a semiconductor device is described. The semiconductor device includes a gate layer, a low-doped semiconductor layer, a crystalline ferroelectric layer, and a source terminal and a drain terminal. The crystalline ferroelectric layer is disposed between the gate layer and the low-doped semiconductor layer. The source terminal and the drain terminal are disposed on the low-doped semiconductor layer.

[0066] The semiconductor device further includes an interface layer between the crystalline ferroelectric layer and the low-doped semiconductor layer.

[0067] In the above semiconductor device, the interface layer includes a first material of the low-doped semiconductor layer and a second material of the crystalline ferroelectric layer.

[0068] In the above semiconductor device, the first material of the low-doped semiconductor layer includes indium gallium zinc oxide IGZO, gallium oxide, indium oxide, zinc oxide, titanium oxide, aluminum oxide or a combination thereof, and the second material of the crystalline ferroelectric layer includes hafnium zirconium oxide or doped hafnium oxide.

[0069] In the above semiconductor device, the gate layer is located at a first side of the low-doped semiconductor layer, and the source terminal and the drain terminal are located at a second side opposite to the first side of the low-doped semiconductor layer.

[0070] In the above semiconductor device, the gate layer and the source and drain terminals are located on the same side of the low-doped semiconductor layer, and the source and drain terminals are located at two opposite sides of the gate layer.

[0071] In the above semiconductor device, the source terminal and the drain terminal are located at two opposite sides of the gate stack of the gate layer and the crystalline ferroelectric layer, and three sides of the low-doped semiconductor layer are covered by the gate stack and the source terminal and the drain terminal.

[0072] In the above semiconductor device, the crystalline ferroelectric layer is polycrystalline.

[0073] In some embodiments of the present disclosure, a semiconductor device is described. The semiconductor device includes a semiconductor material layer, a gate layer, a ferroelectric layer, an interface layer, and a source electrode and a drain electrode. The gate layer is arranged above the semiconductor material layer. The ferroelectric layer is arranged between the gate layer and the semiconductor material layer. The interface layer is arranged between the ferroelectric layer and the semiconductor material layer. The source electrode and the drain electrode are arranged on the semiconductor material layer. The interface layer includes at least one of the material of the semiconductor material layer and the material of the ferroelectric layer.

[0074] In the above semiconductor device, the material of the interface layer includes hafnium oxide, aluminum oxide or a combination thereof.

[0075] In the above semiconductor device, the ferroelectric layer and the gate layer surround the semiconductor material layer, and the ferroelectric layer is connected to the semiconductor material layer through an interface extending on three sides of the semiconductor material layer.

[0076] In the above semiconductor device, the gate layer and the source and drain electrodes are located on the same side of the semiconductor material layer.

[0077] In the above semiconductor device, the source electrode and the drain electrode are located at one side of the semiconductor material layer, and the one side of the semiconductor material layer is opposite to the other side of the semiconductor material layer where the gate layer is located.

[0078] In some embodiments of the present disclosure, a method for forming a semiconductor device is described. A semiconductor layer is formed and a dielectric layer is formed. A pressurization process is performed to transform the semiconductor layer into a low-doped semiconductor layer and the dielectric layer into a crystalline ferroelectric layer. A gate layer is formed. An insulating layer is formed over the gate layer, the crystalline ferroelectric layer, and the low-doped semiconductor layer. A contact opening is formed in the insulating layer, the contact opening exposing a portion of the low-doped semiconductor layer. A source terminal and a drain terminal are formed on the low-doped semiconductor layer.

[0079] In the above method, the gate layer is formed before forming the semiconductor layer and forming the dielectric layer, and the semiconductor layer and the dielectric layer are sequentially formed on the gate layer.

[0080] In the above method, the gate layer, the dielectric layer, and the semiconductor layer are patterned before the pressure treatment is performed.

[0081] In the above method, after the pressure treatment is performed, a gate layer is formed on the crystalline ferroelectric layer, and the gate layer and the crystalline ferroelectric layer are patterned to form a gate structure.

[0082] In the above method, performing the pressure treatment includes performing a high pressure annealing (HPA) treatment in an ambient atmosphere of oxygen.

[0083] In the above method, the HPA treatment is performed at a pressure at least above 1 atm and at a temperature ranging from about 300 degrees Celsius to about 450 degrees Celsius.

[0084] In the above method, performing the pressure treatment includes forming an interface layer between the low-doped semiconductor layer and the crystalline ferroelectric layer.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: Gate layer; A low-doped semiconductor layer; a crystalline ferroelectric layer, disposed between the gate layer and the low-doped semiconductor layer; as well as A source terminal and a drain terminal are arranged on the low-doped semiconductor layer, The semiconductor device further comprises an interface layer between the crystalline ferroelectric layer and the low-doped semiconductor layer, The interface layer is formed by pressurizing the semiconductor layer and the dielectric layer located on the gate layer, wherein the pressurizing treatment transforms the semiconductor layer into the low-doped semiconductor layer so that the low-doped semiconductor layer has an electron doping value in the range of 1E17cm-3 to 1E19cm-3, and transforms the dielectric layer into the crystalline ferroelectric layer. 2 . The semiconductor device according to claim 1 , wherein the interface layer has a thickness of 0.1 nm to 2 nm.

3. The semiconductor device according to claim 2, wherein: The interface layer includes a first material of the low-doped semiconductor layer and a second material of the crystalline ferroelectric layer.

4. The semiconductor device according to claim 3, wherein: The first material of the low-doped semiconductor layer includes indium gallium zinc oxide (IGZO), gallium oxide, indium oxide, zinc oxide, titanium oxide, aluminum oxide, or a combination thereof, and the second material of the crystalline ferroelectric layer includes hafnium zirconium oxide or doped hafnium oxide.

5. The semiconductor device according to claim 1, wherein The gate layer is located at a first side of the low-doped semiconductor layer, and the source terminal and the drain terminal are located at a second side of the low-doped semiconductor layer opposite to the first side.

6. The semiconductor device according to claim 1, wherein The gate layer and the source and drain terminals are located at a same side of the low-doped semiconductor layer, and the source and drain terminals are located at two opposite sides of the gate layer.

7. The semiconductor device according to claim 1, wherein The source terminal and the drain terminal are located at two opposite sides of a gate stack of the gate layer and the crystalline ferroelectric layer, and three sides of the low-doped semiconductor layer are covered by the gate stack and the source terminal and the drain terminal.

8. The semiconductor device according to claim 1, wherein The crystalline ferroelectric layer is polycrystalline.

9. A semiconductor device comprising: Semiconductor layer; A gate layer, disposed above the semiconductor layer; A ferroelectric layer, disposed between the gate layer and the semiconductor layer; An interface layer, disposed between the ferroelectric layer and the semiconductor layer; as well as A source electrode and a drain electrode are arranged on the semiconductor layer, Wherein, the interface layer comprises at least one of the material of the semiconductor layer and the material of the ferroelectric layer, Wherein, the interface layer is formed by pressurizing the semiconductor material layer and the ferroelectric material layer located on the gate layer, and the pressurizing treatment transforms the semiconductor material layer into the semiconductor layer so that the semiconductor layer has an electron doping value in the range of 1E17cm-3 to 1E19cm-3, and transforms the ferroelectric material layer into the ferroelectric layer so that the ferroelectric layer is a crystalline ferroelectric layer.

10. The semiconductor device according to claim 9, wherein The material of the interface layer includes hafnium oxide, aluminum oxide or a combination thereof.

11. The semiconductor device according to claim 9, wherein: The crystalline ferroelectric layer and the gate layer surround the semiconductor layer, and the crystalline ferroelectric layer is connected to the semiconductor layer through an interface extending on three sides of the semiconductor layer.

12. The semiconductor device according to claim 9, wherein The gate layer and the source and drain electrodes are located on a same side of the semiconductor layer.

13. The semiconductor device according to claim 9, wherein: The source electrode and the drain electrode are located at one side of the semiconductor layer, the one side of the semiconductor layer being opposite to the other side of the semiconductor layer where the gate layer is located.

14. A method for manufacturing a semiconductor device, comprising: forming a semiconductor layer and forming a dielectric layer; performing a pressure treatment to transform the semiconductor layer into a low-doped semiconductor layer and transform the dielectric layer into a crystalline ferroelectric layer; forming a gate layer; forming an insulating layer over the gate layer, the crystalline ferroelectric layer, and the low-doped semiconductor layer; forming a contact opening in the insulating layer to expose a portion of the low-doped semiconductor layer; as well as A source terminal and a drain terminal are formed on the low-doped semiconductor layer.

15. The method according to claim 14, wherein: The gate layer is formed before forming the semiconductor layer and forming the dielectric layer, and the semiconductor layer and the dielectric layer are sequentially formed on the gate layer.

16. The method according to claim 15, wherein: Before performing the pressurization process, the gate layer, the dielectric layer, and the semiconductor layer are patterned.

17. The method according to claim 14, wherein: After the pressure treatment is performed, the gate layer is formed on the crystalline ferroelectric layer, and the gate layer and the crystalline ferroelectric layer are patterned to form a gate structure.

18. The method according to claim 14, wherein: Performing the pressurization process includes performing a high pressure annealing process in an oxygen ambient atmosphere.

19. The method according to claim 18, wherein: The high pressure annealing treatment is performed at a pressure at least higher than 1 atm and at a temperature ranging from 300 degrees Celsius to 450 degrees Celsius.

20. The method according to claim 18, wherein: Performing the pressure treatment includes forming an interface layer between the low-doped semiconductor layer and the crystalline ferroelectric layer.

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