Film stacks for lithography applications

Abstract

Provided herein are methods for forming a film stack including a hard mask layer and etching the hard mask layer to form features in the film stack. The methods described herein facilitate profile and size control of features through an appropriate profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hard mask layer includes the following steps: forming a hard mask layer on a substrate, wherein the hard mask layer includes a metal-containing material, the metal-containing material including a metal element having an atomic number greater than 28; supplying an etching gas mixture to the substrate; and etching the hard mask layer exposed by a photoresist layer.

Description

Technical Field

[0001] Embodiments herein generally relate to film stacks and etching processes for etching such film stacks with high selectivity and good profile control for EUV lithography exposure and patterning processes. Background Art

[0002] Reliably producing submicron and smaller features is one of the key requirements for very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as circuit technology continues to miniaturize, the size and spacing of circuit features (such as interconnects) places additional demands on processing capabilities. The multi-layer interconnects at the heart of this technology require accurate imaging and placement of high aspect ratio features (such as vias and other interconnects). Reliable formation of these interconnects is critical to further increasing device and interconnect density. In addition, it is desirable to form submicron sized features and interconnects with reduced waste of intermediate materials (such as resists and hard mask materials).

[0003] As feature sizes get smaller, the demand for higher aspect ratios steadily increases to 20:1 and even higher, with the aspect ratio being defined as the ratio between the depth of a feature and the width of the feature. Developing film stacks and etch processes that can reliably form features with such high aspect ratios presents significant challenges. However, improper control or low resolution of the photolithography exposure and development processes may result in poor critical dimensions of the photoresist layer used to transfer features in the film stack, resulting in unacceptable line width roughness (LWR). Large line width roughness (LWR) and undesirable wobble profiles of the photoresist layer caused by the photolithography exposure and development processes may result in incorrect feature transfer to the film stack, ultimately leading to device failure and yield loss.

[0004] In addition, during the etching of such a film stack, the redeposition or accumulation of byproducts or other materials generated during the etching process may accumulate on the top and / or sidewalls of the etched features, thereby undesirably blocking the opening of the features being formed in the material layer. Different materials selected for the film stack may cause different amounts or profiles of byproducts to be redeposited in the film stack. In addition, because the opening of the etched feature is narrowed and / or sealed by the cumulative redeposition of the material, the reactive etchant is prevented from reaching the lower surface of the feature, thereby limiting the available depth-to-width ratio. In addition, because the accumulation of redeposited materials or byproducts may be randomly and / or irregularly attached to the top surface and / or sidewalls of the etched feature, the irregular profiles and growth of the redeposited materials generated may change the flow path of the reactive etchant, thereby causing the curved or twisted profiles of the features formed in the material layer. Inaccurate profiles or structural dimensions may cause the device structure to collapse, ultimately leading to device failure and reducing product yield. Poor etching selectivity for materials included in the film stack may undesirably lead to inaccurate profile control, thereby ultimately leading to device failure.

[0005] Therefore, there is a need in the art for suitable film stacks and etching methods for etching features having desired profiles and small dimensions in such film stacks. Summary of the invention

[0006] Methods of forming and etching a film stack to form high aspect ratio features in the film stack are provided. The methods described herein facilitate the profile and size control of features having a high aspect ratio through appropriate sidewall and bottom management schemes and selecting desired materials for the film stack. In one or more embodiments, a method for etching a hard mask layer includes the steps of: forming a hard mask layer on a substrate, wherein the hard mask layer includes a metal-containing material, the metal-containing material including a metal element having an atomic number greater than 28; supplying an etching gas mixture to the substrate; and etching the hard mask layer exposed by a photoresist layer.

[0007] In other embodiments, a method for etching a hard mask layer includes the following steps: forming a passivation layer on a surface of a photoresist layer disposed on the hard mask layer, wherein the hard mask layer contains at least one of tin oxide, silicon tin oxide, tantalum oxide, indium tin oxide, and indium gallium zinc oxide; and etching the hard mask layer exposed by the photoresist layer, wherein the hard mask layer is etched by a gas mixture having a chlorine-containing gas or a bromine-containing gas.

[0008] In some embodiments, a method for etching a hard mask layer includes the steps of etching the hard mask layer exposed by a photoresist layer, wherein the hard mask layer is etched by a gas mixture having a chlorine-containing gas or a bromine-containing gas, wherein the hard mask layer includes at least two layers having different absorption coefficients. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order that the above-recited features of the embodiments herein may be obtained and understood in detail, a more particular description of the disclosure briefly summarized above may be had by reference to the examples shown in the accompanying drawings.

[0010] Figure 1 Depicted is a processing chamber that may be used to form a dielectric layer according to one or more embodiments.

[0011] Figure 2 A flow chart for performing a spacer layer patterning process according to one or more implementations is depicted.

[0012] Figure 3A-3D Depicted is a method for utilizing a Figure 2 The process depicted in FIG. 1 shows a film stack at various stages during an etch process used to etch a dielectric layer in a substrate.

[0013] Figure 4A-4B Depicted are various embodiments of a film stack formed on a substrate, the film stack may have a Figure 2 The features in which the depicted process is formed.

[0014] Figure 5 Depicted is a flow chart of another method for performing a spacer layer patterning process in accordance with one or more implementations.

[0015] Figure 6A-6D Depicted is a method for utilizing a Figure 5 0048] FIGURE 2 is an exemplary schematic diagram of another film stack at various stages during an etch process to etch a dielectric layer in a substrate as depicted in the process depicted in FIGURE 2.

[0016] To facilitate understanding of the embodiments, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0017] It is to be noted, however, that the appended drawings illustrate only illustrative examples and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. DETAILED DESCRIPTION

[0018] Embodiments of the present application include methods for forming a film stack and etching processes for etching such a film stack to form features having a desired aspect ratio and profile in the film stack. The film stack includes a hard mask layer having a metal-containing material in the film stack. The hard mask layer can be a single layer or multiple layers having selected film properties to assist in etching resistance and enhance photolithography exposure performance as required. In one or more embodiments, the hard mask layer is a metal-containing material having a desired absorption coefficient, or a mixture having different absorption coefficient values, so as to assist in exposure and development accuracy during the photolithography exposure process. An etching process having a desired chemical property is also selected to pattern the film stack, in particular to etch the hard mask layer.

[0019] Figure 1 is a cross-sectional view of one example of a processing chamber 100 suitable for performing a patterning process to etch a film stack having a hard mask layer made of a metal-containing material. Suitable processing chambers that may be suitable for use with the teachings disclosed herein include, for example, the EMBODIMENTS® process chambers available from Applied Materials, Inc. of Santa Clara, California. or Processing Chamber. Although the illustrated processing chamber 100 includes a number of features that enable excellent etching performance, it is contemplated that other processing chambers may be adapted to benefit from one or more of the inventive features disclosed herein.

[0020] The processing chamber 100 includes a chamber body 102 and a lid 104 enclosing an interior space 106. The chamber body 102 is typically made of aluminum, stainless steel, or other suitable materials. The chamber body 102 typically includes a sidewall 108 and a bottom 110. A substrate support pedestal access port (not shown) is typically defined in the sidewall 108 and selectively sealed by a slit valve to facilitate entry and exit of the substrate 103 from the processing chamber 100. An exhaust port 126 is defined in the chamber body 102 and couples the interior space 106 to a pump system 128. The pump system 128 typically includes one or more pumps and throttle valves to evacuate and regulate the pressure of the interior space 106 of the processing chamber 100. In one or more embodiments, the pump system 128 maintains the pressure within the interior space 106 at an operating pressure typically between about 10 mTorr and about 500 Torr.

[0021] The lid 104 is sealingly supported on the sidewall 108 of the chamber body 102. The lid 104 can be opened to allow access to the interior volume 106 of the processing chamber 100. The lid 104 includes a window 142 that facilitates optical process monitoring. In one embodiment, the window 142 is formed of quartz or other suitable material that can transmit signals utilized by the optical monitoring system 140 mounted outside the processing chamber 100.

[0022] The optical monitoring system 140 is positioned to observe at least one of the interior volume 106 of the chamber body 102 and / or the substrate 103 positioned on the substrate support pedestal assembly 148 through the window 142. In one or more embodiments, the optical monitoring system 140 is coupled to the lid 104 and facilitates integrated deposition processing using optical metrology to provide information that enables process adjustments to compensate for incoming substrate pattern feature inconsistencies (such as thickness and the like), provide process status monitoring (such as plasma monitoring, temperature monitoring, and the like) as needed. One optical monitoring system that may benefit from the present invention is available from Applied Materials, Inc. of Santa Clara, California. Full spectrum interferometry metrology module.

[0023] The gas panel 158 is coupled to the processing chamber 100 to provide processing and / or cleaning gases to the interior volume 106. Figure 1 In the depicted example, inlet ports 132', 132" are provided in the lid 104 to allow gas to be delivered from the gas panel 158 to the interior space 106 of the processing chamber 100. In one embodiment, the gas panel 158 is adapted to provide a fluorinated process gas through the inlet ports 132', 132" and into the interior space 106 of the processing chamber 100. In one embodiment, the process gas provided from the gas panel 158 includes at least a fluorinated gas, a chlorine gas and a carbon-containing gas, an oxygen gas, a nitrogen-containing gas, and a chlorine-containing gas. Examples of fluorinated gases and carbon-containing gases include CHF3, CH2F2, and CF4. Other fluorinated gases may include one or more of C2F, C4F6, C3F8, and C5F8, and the like. Examples of oxygen-containing gases include O2, CO2, CO, N2O, NO2, O3, H2O, and the like. Examples of nitrogen-containing gases include N2, NH3, N2O, NO2, and the like. Examples of chlorine-containing gases include HCl, Cl2, CCl4, CHCl3, CH2Cl2, CH3Cl and the like. Suitable examples of carbon-containing gases include methane (CH4), ethane (C2H6), ethylene (C2H4) and the like.

[0024] The showerhead assembly 130 is coupled to the interior surface 114 of the lid 104. The showerhead assembly 130 includes a plurality of holes that allow gas to flow from the inlet ports 132', 132" through the showerhead assembly 130 into the interior space 106 of the processing chamber 100 and spread over the entire surface of the substrate 103 to be processed in the processing chamber 100 in a predetermined distribution pattern.

[0025] The remote plasma source 177 may optionally be coupled to the gas panel 158 to facilitate separation of the gas mixture from the remote plasma prior to entering the interior space 106 for processing. The RF source power 143 is coupled to the showerhead assembly 130 through the matching network 141. The RF source power 143 is typically capable of producing up to about 3000 W at a tunable frequency in the range from about 50 kHz to about 200 MHz.

[0026] The showerhead assembly 130 also includes an area that is transmissive to optical metrology signals. The optically transmissive area or passage 138 is adapted to allow the optical monitoring system 140 to view the interior space 106 and / or the substrate 103 located on the substrate support base assembly 148. The passage 138 may be a material, hole, or a plurality of holes formed or disposed in the showerhead assembly 130 that is substantially transmissive to the wavelength of energy generated by the optical monitoring system 140 and reflected back to the optical monitoring system 140. In one or more embodiments, the passage 138 includes a window 142 to prevent gas from leaking through the passage 138. The window 142 may be a sapphire plate, a quartz plate, or other suitable material. The window 142 may alternatively be disposed in the cover 104.

[0027] In one embodiment, the showerhead assembly 130 is configured with multiple zones that allow for separate control of the gases flowing into the interior volume 106 of the processing chamber 100. Figure 1 In the example shown, the showerhead assembly 130 has an inner region 134 and an outer region 136 that are respectively coupled to the gas panel 158 through separate inlet ports 132 ′, 132 ″.

[0028] The substrate support pedestal assembly 148 is disposed in the interior space 106 of the processing chamber 100 below the gas distribution (showerhead) assembly 130. The substrate support pedestal assembly 148 holds the substrate 103 during processing. The substrate support pedestal assembly 148 typically includes a plurality of lift pins (not shown) disposed therethrough that are configured to lift the substrate 103 from the substrate support pedestal assembly 148 and facilitate exchanging the substrate 103 by a robot (not shown) in a conventional manner. The liner 118 may tightly surround the perimeter of the substrate support pedestal assembly 148.

[0029] In one embodiment, the substrate support pedestal assembly 148 includes a mounting plate 162, a base 164, and an electrostatic chuck 166. The mounting plate 162 is coupled to the bottom 110 of the chamber body 102 and includes passages for routing facilities (such as fluids, power lines, sensor leads, etc.) to the base 164 and the electrostatic chuck 166. The electrostatic chuck 166 includes at least one clamping electrode 180 for holding the substrate 103 below the showerhead assembly 130. The electrostatic chuck 166 is driven by a clamping power source 182 to generate an electrostatic force that holds the substrate 103 to a clamping surface, as is well known. Alternatively, the substrate 103 may be held to the substrate support pedestal assembly 148 by clamping, vacuum, or gravity.

[0030] At least one of the substrate 164 or the electrostatic chuck 166 may include at least one optional embedded heater 176, at least one optional embedded isolator 174, and a plurality of conduits 168, 170 to control the lateral temperature profile of the substrate support pedestal assembly 148. The conduits 168, 170 are fluidly coupled to a fluid source 172 that circulates a temperature regulating fluid therethrough. The heater 176 is regulated by a power source 178. The conduits 168, 170 and heater 176 are utilized to control the temperature of the substrate 164, thereby heating and / or cooling the electrostatic chuck 166, and ultimately controlling the temperature profile of the substrate 103 disposed thereon. A plurality of temperature sensors 190, 192 may be used to monitor the temperature of the electrostatic chuck 166 and the substrate 164. The electrostatic chuck 166 may further include a plurality of gas channels (not shown), such as grooves, formed in the substrate support pedestal support surface of the electrostatic chuck 166 and fluidly coupled to a source of a heat transfer (or backside) gas, such as He. In operation, a backside gas is provided into the gas channel at a controlled pressure to enhance heat transfer between the electrostatic chuck 166 and the substrate 103 .

[0031] In one embodiment, the substrate support pedestal assembly 148 is configured as a cathode and includes an electrode 180 that is coupled to a plurality of RF power bias sources 184, 186. The RF bias power sources 184, 186 are coupled between the electrode 180 disposed in the substrate support pedestal assembly 148 and another electrode, such as the showerhead assembly 130 or a ceiling (lid 104) of the chamber body 102. The RF bias power ignites and sustains a plasma discharge formed from a gas disposed in a processing region of the chamber body 102.

[0032] exist Figure 1In the depicted example, dual RF bias power sources 184, 186 are coupled to an electrode 180 disposed in a substrate support pedestal assembly 148 through a matching circuit 188. The signals generated by the RF bias power sources 184, 186 are delivered to the substrate support pedestal assembly 148 through a single feed through the matching circuit 188 to ionize a gas mixture provided in the plasma processing chamber 100, thereby providing the ion energy required for performing deposition or other plasma enhanced processes. The RF bias power sources 184, 186 are typically capable of generating RF signals having a frequency from about 50 kHz to about 200 MHz and a power between about 0 Watts and about 8000 Watts, such as about 1 Watt and about 5000 Watts. An additional bias power source 189 may be coupled to the electrode 180 to control the characteristics of the plasma.

[0033] During operation, substrate 103 is disposed on substrate support pedestal assembly 148 in plasma processing chamber 100. Processing gas and / or gas mixture is introduced into chamber body 102 from gas panel 158 through showerhead assembly 130. Vacuum pump system 128 maintains pressure inside chamber body 102 while removing deposition byproducts.

[0034] A controller 150 is coupled to the processing chamber 100 to control the operation of the processing chamber 100. The controller 150 includes a central processing unit (CPU) 152, a memory 154, and support circuits 156 to control the processing sequence and regulate the gas flow from the gas panel 158. The CPU 152 can be any form of general-purpose computer processor that can be used in an industrial environment. The software routines can be stored in the memory 154 (such as a random access memory, a read-only memory, a floppy disk or a hard disk drive, or other forms of digital storage). The support circuits 156 are coupled to the CPU 152 in a conventional manner and can include caches, clock circuits, input / output systems, power supplies, and the like. Bidirectional communication between the controller 150 and the various components of the processing chamber 100 is handled by a number of signal cables.

[0035] Figure 2 A flow chart of a method 200 for etching a film stack 302 having a hard mask layer 310 formed of a metal-containing material is shown. Figure 3A-3D is a cross-sectional view of a portion of a substrate 300 corresponding to various stages of method 200. Method 200 may be used as needed to form features having desired critical dimensions and profiles, such as contact structures, gate structures, NAND structures, or interconnect structures for logic or memory devices. Alternatively, method 200 may be advantageously utilized to etch other types of structures.

[0036] In one or more examples, the film stack 302 has a photoresist layer 312 disposed thereon. The photoresist layer 312 may be a positive photoresist and / or a negative photoresist capable of chemical amplification reaction. The photoresist layer 312 is a polymer organic material suitable for EUV lithography processing. In one or more examples, the photoresist layer 312 includes at least one metal element selected from at least one of Sn, Ta, In, Ga, Zr, Zn, any alloy thereof, and any combination thereof. The metal element included in the photoresist layer 312 may change the light absorption efficiency during the lithography exposure process as needed.

[0037] The photoresist layer 312 is disposed on the hard mask layer 310, and the hard mask layer 310 is further disposed on the bottom anti-reflective coating (BARC) layer 308. Figure 4A As shown, an optional organic layer 370 may be formed between the photoresist layer 312 and the bottom anti-reflective coating layer 308 as desired. The optional organic layer 370 includes an organic material or a mixture of organic or inorganic materials. In embodiments where the optional organic layer 370 is an organic material, the organic material may be a cross-linkable polymer material that may be applied to the substrate 300 by a spin coating process and then thermally cured so that the photoresist layer 312 may be applied thereon. In embodiments where the optional organic layer 370 is a mixture of organic or inorganic materials, the optional organic layer 370 may be a dielectric material formed by any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin coating, spray coating, or the like.

[0038] The optional organic layer 370 acts as a planarization layer, an anti-reflective coating, and / or a photoacid direction controller, and can provide etch resistance and line edge roughness control when transferring the pattern into the underlying hard mask layer 310 and the layers below the hard mask layer 310. During the transfer of the resist process, the anti-patterning function from the optional organic layer 370 can be used with the underlying hard mask layer 310. In one or more examples, the optional organic layer 370 does not interact with the photoresist layer 312 and does not interfacially mix and / or diffuse or cross-contaminate with the photoresist layer 312.

[0039] BARC layer 308 is disposed on dielectric multilayer 305 on substrate 300. A target layer (not shown) may be formed between dielectric multilayer 305 and substrate 300 as desired. Photoresist layer 312 defines opening 314 that exposes surface 316 of hard mask layer 310 for etching.

[0040] The substrate 300 may be any one of a semiconductor substrate, a silicon wafer, a glass substrate, and the like. The substrate 300 may be a crystalline silicon substrate (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire. The substrate 300 may have various sizes, such as 200 mm, 300 mm, 450 mm or other diameters, and may be a rectangular or square panel. Unless otherwise specified, the examples described herein are performed on substrates having a 200 mm diameter, a 300 mm diameter or a 450 mm diameter.

[0041] The hard mask layer 310 formed in the film stack 302 is selected to be a metal-containing material. The hard mask layer 310 may include a single layer or multiple layers. Figure 3A In the depicted example, the hard mask layer 310 is a single layer comprising or formed of a metal-containing material (such as a metal dielectric layer) containing a metal element having an atomic number greater than 28 (such as 29-32, 37-51, and 55-83). The metal-containing material may include one or more metal elements selected from tin (Sn), tantalum (Ta), indium (In), gallium (Ga), zinc (Zn), zirconium (Zr), aluminum (Al), or a combination thereof. Suitable examples of metal-containing materials for the hard mask layer 310 may be or include tin oxide (SnO), tin silicon oxide (SnSiO), tantalum oxide (TaO), indium tin oxide (InSnO), indium gallium zinc oxide (IGZO), one or more alloys thereof, one or more dopants thereof, or any combination thereof.

[0042] The metal-containing material selected for the hard mask layer 310 may affect the reflection and / or absorption efficiency of EUV light during the photolithography exposure process. Therefore, by appropriately selecting the material for the hard mask layer 310, the performance of the photolithography exposure process, such as high photolithography resolution, defect reduction, photoresist layer profile control, energy dose reduction, and / or line edge roughness reduction, may be enhanced. In one or more instances, the metal-containing material selected for the hard mask layer 310 may have a relatively high absorption coefficient under EUV light having a wavelength of about 13.5 nm. It is believed that the higher density (or higher concentration value) of the metal element in the metal-containing material for the hard mask layer 310 provides a film property with a higher absorptivity. In addition, dopants of silicon and / or oxygen elements in the metal-containing material for the hard mask layer 310 also help reduce agglomeration during the photolithography exposure process, thereby reducing the possibility of defect generation. Therefore, by appropriately selecting the ratio between the metal element and the oxygen and / or silicon elements in the metal-containing material for the hard mask layer 310, a desired amount of secondary electrons in the metal-containing material for the hard mask layer 310 can be obtained. For example, it is believed that a relatively low oxygen concentration and / or silicon in the metal-containing layer can improve the generation of secondary electrons, which can enhance high absorption. Therefore, the ratio of the metal element to the silicon or oxygen element (metal:Si / O) can be controlled between about 80:1 / 19 and about 90:1 / 9 to provide the desired absorption during the photolithography exposure process. It should be noted that a lower oxygen and / or silicon concentration in the metal-containing material (e.g., a higher metal element concentration in the metal-containing material) provides higher film conductivity and lower film resistivity, thereby also increasing the metal density, which provides higher absorption efficiency. In one or more instances, the thickness of the metal-containing layer for the hard mask layer 310 is about About Between, such as about About Between, for example, About between.

[0043] In one or more examples, selecting a metal element having a relatively large atomic number (e.g., an atomic number greater than 28) in the metal-containing material for the hard mask layer 310 may also provide a relatively high absorption efficiency during the photolithography exposure process. The metal-containing material for the hard mask layer 310 may have an absorption efficiency greater than 1×10 5 (cm 2 / mol) of EUV light absorption cross section.

[0044] In embodiments where the hard mask layer 310 is a single layer, the metal-containing material selected to form the hard mask layer 310 may include a metal element having an atomic number greater than 28 (and in some examples greater than 35). In one or more examples, the metal element may have an atomic number selected from 29-32, 37-51, and 55-83. Exemplary metal elements may be tin (Sn), tantalum (Ta), indium (In), gallium (Ga), zirconium (Zr), zinc (Zn), or any combination thereof.

[0045] In embodiments where the hard mask layer 310 includes one or more layers (such as a dual layer or multiple layers), Figure 4B As shown, the hard mask layer 310 may have a plurality of layers, such as a first layer 310A, a second layer 310B, and a third layer 310C formed of different metal-containing materials. The selection of materials for the first layer 310A, the second layer 310B, and the third layer 310C is based on different absorption coefficients of the metal-containing materials. For example, the first layer 310A, the second layer 310B, and the third layer 310C may each have different high to low, low to high, or alternating high and low absorption coefficients sequentially formed in the hard mask layer 310 to enhance the reflection of EUV light during the photolithography exposure process. In one or more examples, by selecting different types of metal elements in the metal-containing layers for the first layer 310A, the second layer 310B, and the third layer 310C, the first layer 310A, the second layer 310B, and the third layer 310C may have high and low alternating absorption coefficients. For example, the metal element selected for at least one of the first layer 310A, the second layer 310B, and the third layer 310C may have an atomic number greater than 28, such as greater than 35, and at least one of the first layer 310A, the second layer 310B, and the third layer 310C is less than 28. The metal element selected to form the second layer 310B of the hard mask layer 310 may have an atomic number smaller (or larger) than nearby neighboring metal elements formed in the first layer 310A and the third layer 310C. For example, the hard mask layer 310 may include a first layer 310A including a first metal element, a second layer 310B including a second metal element, and a third layer 310C including a third metal element. In some examples, the second metal element in the second layer 310B has an atomic number different from (e.g., greater than or less than) the first metal element in the first layer 310A and / or the third metal element in the third layer 310C.

[0046] In an embodiment in which a double-layer structure is used for the hard mask layer 310, such a double-layer structure may have a first portion (e.g., an upper portion or layer) and a second portion (e.g., a lower portion or layer), the first portion containing a metal element having an atomic number greater than 28 (such as 29-32, 37-51, and 55-83), and the second portion containing an element having an atomic number less than 28 (such as 3-8, 11-16, and 19-27). In addition, instead of forming the hard mask layer 310 as a plurality of layers or more than one layer, the hard mask layer 310 may be formed to have a gradient having different ratios of the metal element to the silicon and / or oxygen element formed in the hard mask layer 310 as required to provide different absorption coefficients along the bulk film body of the hard mask layer 310. For example, the metal element concentration of the hard mask layer 310 may gradually increase or decrease as the thickness of the hard mask layer 310 formed on the substrate 300 increases as required. Alternatively, each layer of the double-layer structure or the plurality of layers of the hard mask layer 310 may also be a gradient layer. For example, in the double-layer structure of the hard mask layer 310, as desired, the upper portion of the hard mask layer 310 may have a low resistivity and a relatively high metal element concentration or even a pure metal layer (e.g., such as a metal Sn layer as an example) while the lower portion of the hard mask layer 310 has a high concentration of silicon and / or oxygen.

[0047] although Figure 4B The embodiment depicted in FIG. 1 only shows the multi-layer as three layers, but it should be noted that the hard mask layer 310 may have as many multi-layers as desired.

[0048] The hard mask layer 310 can be formed by any suitable deposition technique as desired. In one or more examples, the hard mask layer 310 is formed by CVD, ALD, PVD, spin coating, spray coating, or other suitable deposition processes.

[0049] In examples where the hard mask layer 310 is formed by a CVD or PVD process, a carrier gas and / or an inert gas having a relatively high atomic weight (such as Xe or Kr) may be used during the plasma deposition process of the hard mask layer 310. The substrate temperature during the formation of the hard mask layer 310 may be controlled between -50 degrees Celsius and about 250 degrees Celsius. It is believed that relatively low substrate temperature control (e.g., less than 250 degrees Celsius) while forming the hard mask layer 310 may help form the hard mask layer 310 at a relatively slow deposition rate, thereby allowing the film surface to have a relatively smooth surface.

[0050] Furthermore, as discussed above, after forming the hard mask layer 310 on the BARC layer 308, an optional organic layer 370 may be optionally formed on the hard mask layer 310, such as Figure 4AAs shown. In embodiments where the optional organic layer 370 is present, the optional organic layer 370 can help further process the surface of the hard mask layer 310 to provide a relatively strong surface structure as desired. Alternatively, the surface of the hard mask layer 310 can be processed immediately after the hard mask layer 310 is formed. It should be noted that the optional organic layer 370 can be a carbon-based material or a polymer material, which is formed from a silicon- or carbon-containing precursor (such as trimethylsilane (TMS)), CH4 or other carbon- and hydrogen-containing gases as desired.

[0051] Below the hard mask layer 310, the BARC layer 308 is disposed on the dielectric multilayer 305. The BARC layer 308 and the hard mask layer 310 can be used in combination as an etching mask to etch features in the BARC layer 308 for patterning the underlying dielectric multilayer 305 with a desired aspect ratio and profile. The features described herein may include trenches, vias, openings, and the like. In one or more embodiments, the BARC layer 308 may be a material that may be or include silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, doped amorphous carbon, carbon-containing materials, and any combination thereof. In some exemplary embodiments described herein, the BARC layer 308 is an amorphous carbon layer. An example of an amorphous carbon layer may be Advanced Patterning Film available from Applied Materials, Inc. TM (APF).

[0052] The dielectric multilayer 305 can be in the form of a single layer or multiple layers as required. Figure 3A-3D In the depicted example, the dielectric multilayer 305 includes a metal dielectric layer 304 disposed between a first dielectric layer 306 and a second dielectric layer 303. The first dielectric layer 306 and the second dielectric layer 303 may be a silicon-containing material selected from SiON, SiN, SiO2, Si, or a composite layer including SiON or SiN or SiO2 or any suitable material as desired. The metal dielectric layer 304 may be at least one of TaN, TiN, TaON, TaO, TiON, TiO or the like as desired. The target material (not shown) disposed between the dielectric multilayer 305 and the substrate 300 may be a dielectric material. Suitable exemplary materials for the dielectric layer include undoped silicon glass (USG), such as silicon oxide or TEOS, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), high-k materials, low dielectric constant insulating materials (e.g., dielectric constants less than about 4.0), and combinations thereof. Examples of low dielectric constant insulating materials include silicate glass, fluorosilicate glass (FSG), and carbon-doped silicon oxide (SiOC), silicon carbide (SiC), and nitrogen-containing silicon carbide (SiCN), and the like.

[0053] In one or more embodiments described herein, the target layer is an undoped silicon glass (USG) layer. The first dielectric layer 306 and the second dielectric layer 303 are silicon oxide and silicon nitride, respectively. The BARC layer 308 is an amorphous carbon layer. The hard mask layer 310 is a SnO or SnSiO layer.

[0054] The method 200 begins at operation 202 by transferring or providing a substrate 300 to an etch processing chamber such as Figure 1 1. The process chamber 100 is depicted.

[0055] At operation 204, an etching process is performed to etch the hard mask layer 310, such as Figure 3B As shown, the hard mask layer 310 is etched by a selected gas mixture supplied to the processing chamber 100 until the surface 324 of the underlying BARC layer 308 is exposed. During etching, a selected gas mixture is supplied to the processing chamber 100 to etch the hard mask layer 310 to form features 318 in the hard mask layer 310. Since the size of the opening 314 defined by the photoresist layer 312 is kept small (e.g., less than 100 nm), the gas mixture and the processing parameters used to etch the hard mask layer 310 need to be carefully selected so as to etch the hard mask layer 310 with good profile control without damaging the underlying BARC layer 308.

[0056] In one or more examples, the etching process is performed by supplying the etching gas mixture into the processing chamber while maintaining the temperature of the substrate support pedestal assembly 148 between room temperature (eg, about 23 degrees Celsius) and up to about 150 degrees Celsius.

[0057] In some examples, the etching gas mixture includes at least one halogen-containing gas. The halogen-containing gas may include a fluorine-containing gas, a chlorine-containing gas, or a bromide-containing gas. Suitable examples of halogen-containing gases include SF6, SiCl4, Si2Cl6, NF3, HBr, Br2, CHF3, CH2F2, CF4, C2F, C4F6, C3F8, HCl, C4F8, Cl2, HF, CCl4, CHCl3, CH2Cl2, and CH3Cl. In some examples, silicon-containing gases may also be supplied in the etching gas mixture. Suitable examples of silicon-containing gases include SiCl4, Si2Cl6, SiH4, Si2H6, and the like. In addition, in particular, examples of chlorine-containing gases include HCl, Cl2, CCl4, CHCl3, CH2Cl2, CH3Cl, SiCl4, Si2Cl6, and the like, and examples of bromine-containing gases include HBr, Br2, and the like. A reactive gas (such as an oxygen-containing gas or a nitrogen-containing gas, for example, O2, N2, N2O, NO2, O3, H2O, or the like) may also be supplied in the etching gas mixture as desired.

[0058] In one or more embodiments, the halogen-containing gas used to etch the hard mask layer includes a chlorine-containing gas or a bromide-containing gas. When the etching gas mixture is supplied to the processing chamber, an inert gas may be optionally supplied to the etching gas mixture to assist in profile control as needed. Examples of inert gases supplied in the gas mixture include Ar, He, Ne, Kr, Xe, or the like.

[0059] In one specific example, the etching gas mixture used to etch the hard mask layer 310, such as a metal-containing material (eg, Sn / SnO / SnSiO layer), includes HBr, Cl2, Ar, He, or a combination thereof.

[0060] During etching, the chamber pressure of the etching gas mixture is also adjusted. In one or more embodiments, the processing pressure in the plasma processing chamber is adjusted between about 2mTorr and about 100mTorr, for example, at about 3mTorr to 20Torr, such as about 6mTorr. An RF source or bias power may be applied as needed to maintain a plasma formed by a continuous mode or a pulsed mode in the presence of an etching gas mixture. For example, an RF source power having a frequency of about 13.56MHz may be applied to an inductively coupled antenna source at an energy level between about 200 watts and about 1000 watts (such as about 500 watts) to maintain the plasma inside the etching chamber. In addition, an RF bias power having a frequency between about 2MHz and about 13.56MHz may be applied that is less than 500 watts (such as between about 0 watts and about 450 watts, such as about 150 watts).

[0061] In one or more examples, during etching at operation 204, the RF bias power and the RF source power may be pulsed in the processing chamber 100. The RF bias power and the RF source power may be pulsed into the processing chamber synchronously or asynchronously. In some examples, the RF bias power and the RF source power are pulsed into the processing chamber asynchronously. For example, the RF source power may be pulsed into the processing chamber before pulsing the RF bias power. For example, the RF bias power may be in a pulse mode with a time delay with or relative to the RF source power. In one or more examples, the RF source power and the RF bias power are pulsed between about 5% and about 75% of each duty cycle. For example, each duty cycle between each time unit is between about 0.1 milliseconds (ms) and about 10 (ms).

[0062] In one example of the etching gas mixture supplied at operation 204, O2 gas may be supplied into the chamber at a flow rate between about 0 sccm and about 50 sccm. A halogen-containing gas such as HBr may be supplied at a flow rate between about 25 sccm and about 250 sccm, such as about 100 sccm.

[0063] At operation 206, after etching the hard mask layer 310, a surface 324 of the BARC layer 308 is exposed, and a second etching process is further performed to remove a portion of the BARC layer 308 from the exposed surface 324, such as Figure 3C As shown, until the surface 322 of the dielectric multilayer 305 is exposed. The etching gas mixture may be the same as the etching gas mixture supplied at operation 204. Alternatively, the etching gas mixture used to etch the BARC layer 308 may be different from the etching gas mixture used to etch the hard mask layer 310 at operation 204. In one or more examples, the etching gas mixture used to etch the BARC layer 308 may include a chlorine-containing gas, such as HCl or Cl2 gas.

[0064] After forming the features 328 in the BARC layer 308, a descum or stripping process may be performed to remove the remaining photoresist layer 312 (if any) from the substrate, such as Figure 3D It should be noted that further etching processes or patterning processes may be performed as needed to continue transferring features 328 into dielectric multilayer 305 and / or a target layer (not shown) thereon.

[0065] Figure 5 Another example of a flow chart of a method 500 for etching a film stack having a hard mask layer 310 formed of a metal-containing material, such as the film stack 302 discussed above, is shown. Figure 6A-6D 5 is a cross-sectional view of a portion of substrate 300 corresponding to various stages of method 500. Similarly, as discussed above, film stack 302 has photoresist layer 312 disposed thereon. Hard mask layer 310 is disposed on BARC layer 308, wherein dielectric multilayer 305 is formed on substrate 300. Similarly, optional organic layer 370 (eg, Figure 4A ) or multiple layers of hard mask layer 310 (as shown Figure 4B can also be used Figure 5 The method 500 is depicted for etching.

[0066] The method 500 begins at operation 502 by transferring or providing the substrate 300 to a processing chamber, such as a deposition chamber or an etching chamber, as desired.

[0067] At operation 504, before etching the hard mask layer 310, a deposition gas mixture is supplied to form a passivation layer 320 on the photoresist layer 312, such as Figure 6BAs shown. The deposition gas mixture may be supplied in the PVD chamber, or supplied in situ in the etching chamber, so that the passivation layer 320 may be selectively formed on the photoresist layer 312 in a controlled manner, primarily on the surface 325 of the photoresist layer 312. The deposition gas mixture is supplied at a desired angle relative to the substrate surface, so that the passivation layer 320 is primarily formed on the surface 325 of the photoresist layer 312, and not on the sidewalls of the photoresist layer 312 or other exposed portions of the hard mask layer 310. In this manner, the size of the opening 314 defined by the photoresist layer 312 remains unchanged, so as to facilitate the transfer of the features / openings to the hard mask layer 310 without changing the size / geometry.

[0068] In one or more embodiments, the deposition gas mixture includes a silicon-containing gas, an oxygen-containing gas, a carbon-containing gas, or a combination thereof. In one or more examples, the deposition gas mixture includes SiH4 and / or CH4 gas.

[0069] At operation 506, an etching process is then performed to etch the hard mask layer 310, such as Figure 6C 308 is exposed. It should be noted that the etching process can be performed continuously as needed until the feature / opening 318 is further transferred to the dielectric multilayer 305 or the target layer (not shown). During the etching, a selected gas mixture is supplied to the processing chamber 100 to etch the hard mask layer 310 to form features 318 in the hard mask layer 310. The etching gas mixture selected to etch the hard mask layer 310 can be similar to or the same as the etching gas mixture at operation 204 described above.

[0070] After forming the features / openings 318 in the hard mask layer 310, a descum or stripping process may be performed to remove the remaining passivation layer 320 (if any) from the substrate 300, as shown in FIG6D. It should be noted that further etching processes or patterning processes may be performed as needed to continue transferring features to the dielectric multilayer 305 and / or target layers thereon (not shown).

[0071] Therefore, by utilizing a hard mask layer having a metal-containing material having a desired absorption coefficient or a mixture of different absorption coefficient values, photolithography exposure accuracy (such as high resolution), low energy dose, good photoresist profile control, and low line edge roughness can be enhanced.

[0072] Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure may be designed without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims. All documents described herein are incorporated herein by reference, including any priority documents and / or test procedures, as long as they do not contradict this article. It is obvious from the general description and specific embodiments above that, although the form of the present disclosure has been illustrated and described, various modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not intended to be limited thereby. Likewise, with respect to U.S. law, the term "include" is considered synonymous with the term "include". Likewise, whenever a composition, element, or element group is preceded by the conjunction "include", it should be understood that we also consider the same composition or element group with the conjunction "substantially consisting of", "consisting of", "selected from the group consisting of" or "is" before the description of the composition, element, or multiple elements, and vice versa.

[0073] Certain embodiments and features have been described using a set of numerical upper limits and a set of numerical lower limits. It should be understood that, unless otherwise indicated, ranges including combinations of any two values ​​are contemplated, such as any lower value combined with any higher value, any two lower values ​​combined, and / or any two higher values ​​combined. Some lower limits, upper limits, and ranges appear in one or more of the accompanying claims.

Claims

1. A method for etching a hard mask layer, comprising the following steps: forming a hard mask layer on a substrate, wherein the hard mask layer comprises a metal-containing material, the metal-containing material comprises a metal element having an atomic number greater than 28, wherein the hard mask layer is disposed on a bottom anti-reflective coating, the bottom anti-reflective coating is disposed on a dielectric multilayer, and wherein the bottom anti-reflective coating is an amorphous carbon layer, and the dielectric multilayer comprises at least a silicon-containing dielectric layer and a metal dielectric layer; Supplying an etching gas mixture to the substrate further comprises the following steps: supplying a deposition gas mixture to the substrate; and forming a passivation layer on a top surface of a photoresist layer disposed on the hard mask layer; and etching the hard mask layer exposed by the photoresist layer, wherein the etching step further comprises the following steps: pulsing RF power while etching the hard mask layer.

2. The method of claim 1, wherein the metal element is selected from the group consisting of tin, tantalum, indium, gallium, zirconium, zinc, and any combination thereof.

3. The method of claim 1, wherein the metal-containing material comprises tin oxide, silicon tin oxide, tantalum oxide, indium tin oxide, indium gallium zinc oxide, or any combination thereof. The method of claim 1 , wherein the hard mask layer comprises multiple layers. 5 . The method of claim 4 , wherein an upper portion of the hard mask layer has a higher concentration of the metal element than a lower portion of the hard mask layer. The method of claim 4 , wherein the hard mask layer comprises at least two layers having different absorption coefficients. 7 . The method of claim 6 , wherein the hard mask layer comprises a first layer and a second layer, the first layer comprising an element having an atomic number greater than 28, and the second layer comprising an element having an atomic number less than 28.

8. The method of claim 4, wherein the hard mask layer comprises a first layer including a first metal element, a second layer including a second metal element, and a third layer including a third metal element, and wherein the second metal element has an atomic number greater than or less than that of the first metal element or the third metal element.

9. The method of claim 1, wherein the hard mask layer is a gradient layer having different metal element concentrations across the hard mask layer.

10. The method of claim 1, wherein the photoresist layer comprises at least one metal element selected from the group consisting of tin, tantalum, indium, gallium, zirconium, zinc, and any combination thereof.

11. The method of claim 1, wherein the step of forming the hard mask layer further comprises the step of forming a plasma containing xenon or krypton while forming the hard mask layer.

12. The method of claim 1, wherein the step of supplying the etching gas mixture further comprises the step of supplying a chlorine-containing gas or a bromine-containing gas to etch the hard mask layer.

13. A method for etching a hard mask layer, comprising the steps of: forming a hard mask layer on a substrate, wherein the hard mask layer comprises a metal-containing material, the metal-containing material comprises a metal element having an atomic number greater than 28, wherein the metal-containing material further comprises silicon and oxygen, and wherein the metal-containing material comprises 80 atomic percent to 90 atomic percent of the metal element; wherein the hard mask layer is disposed on a bottom anti-reflective coating, the bottom anti-reflective coating is disposed on a dielectric multilayer, and wherein the bottom anti-reflective coating is an amorphous carbon layer, and the dielectric multilayer comprises at least a silicon-containing dielectric layer and a metal dielectric layer; forming a passivation layer on a surface of a photoresist layer disposed on the hard mask layer, wherein the hard mask layer comprises tin oxide, silicon tin oxide, indium tin oxide, indium gallium zinc oxide, or any combination thereof; and Supplying an etching gas mixture to the substrate further comprises the following steps: supplying a deposition gas mixture to the substrate; and forming a passivation layer on a top surface of the photoresist layer disposed on the hard mask layer; and etching the hard mask layer exposed by the photoresist layer, wherein the hard mask layer is etched by a gas mixture containing a chlorine-containing gas or a bromine-containing gas.

14. The method of claim 13, wherein the hard mask layer comprises at least two layers having different absorption coefficients. 15 . The method of claim 13 , wherein an upper portion of the hard mask layer has a higher concentration of the metal element than a lower portion of the hard mask layer.

16. A method for etching a hard mask layer, comprising the steps of: forming a hard mask layer on a substrate, wherein the hard mask layer comprises a metal-containing material, the metal-containing material comprises a metal element having an atomic number greater than 28, wherein the hard mask layer is disposed on a bottom anti-reflective coating, the bottom anti-reflective coating is disposed on a dielectric multilayer, and wherein the bottom anti-reflective coating is an amorphous carbon layer, and the dielectric multilayer comprises at least a silicon-containing dielectric layer and a metal dielectric layer; Supplying an etching gas mixture to the substrate further comprises the following steps: supplying a deposition gas mixture to the substrate; and forming a passivation layer on a top surface of a photoresist layer disposed on the hard mask layer; and etching the hard mask layer exposed by the photoresist layer, wherein the hard mask layer is etched by a gas mixture comprising a chlorine-containing gas or a bromine-containing gas, wherein the etching step further comprises the following steps: pulsing RF power while etching the hard mask layer, and wherein the hard mask layer comprises at least two layers having different absorption coefficients.

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