Power saving power architecture for integrated circuits

Abstract

An integrated circuit includes: a first plurality of circuits receiving a first internal power supply voltage; a first voltage regulator receiving an external power supply voltage and providing the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode; a second voltage regulator receiving the external power supply voltage and providing the first internal power supply voltage at a second rated power lower than the first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode; and a controller controlling the transition of the integrated circuit between the active mode and the low power mode. In the active mode, the controller activates all of the first plurality of circuits, but in the low power mode, the controller activates only a subset of the first plurality of circuits while keeping the remaining circuits inactive.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuits, and more particularly, to internal power architectures for integrated circuits such as microcontrollers (MCUs). Background Art

[0002] Microcontroller (MCU) is an integrated circuit that combines the main components of a computer system (i.e., central processing unit (CPU), memory and input / output (I / O) peripheral circuits) on a single integrated circuit chip. Modern MCUs are useful in a variety of consumer products (such as mobile phones, household appliances, automotive parts, etc.) due to their low cost. Typical MCUs combine different types of circuits with different power requirements on a single chip. For example, digital circuits implemented using complementary metal oxide semiconductor (CMOS) transistors only require a low-voltage power supply for normal operation. Other circuits (such as analog circuits and circuits docked with external circuit systems) require a higher power supply voltage for operation. In addition, these MCUs often operate with battery voltages, and the MCU generates internal voltages to power different types of circuits. At the same time, it is necessary to save power and the MCU provides various low-power modes to assist power saving. There is a contradiction between supporting different types of internal circuits and maintaining low-power operation because the power saving circuit itself consumes a large amount of chip power. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An MCU known in the prior art is shown in block diagram form;

[0004] Figure 2 An MCU with a power saving energy management circuit according to an embodiment is shown in block diagram form;

[0005] Figure 3 Shown by Figure 2 State diagram of the various power states supported by the MCU;

[0006] Figure 4 The partial block diagram and partial schematic diagram form shows Figure 2 The power saving power architecture of the MCU; and

[0007] Figure 5 shows a timing diagram that shows the activation Figure 4 The sequence of various circuits of the MCU.

[0008] The use of the same reference numerals in different figures indicates similar or identical items. Unless otherwise specified, the word "coupled" and its associated verb forms include direct and indirect electrical connections by means known in the art, and unless otherwise specified, any description of a direct connection also implies an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0009] In one form, an integrated circuit includes a first plurality of circuits, a first voltage regulator, a second voltage regulator, and a controller, the first plurality of circuits receiving a first internal power supply voltage. When the integrated circuit is in an active mode, the first voltage regulator receives an external power supply voltage and provides the first internal power supply voltage at a first rated power in response to the external power supply voltage. When the integrated circuit is in a low power mode, the second voltage regulator receives the external power supply voltage and provides the first internal power supply voltage at a second rated power lower than the first rated power in response to the external power supply voltage. The controller controls the transition of the integrated circuit between the active mode and the low power mode. In the active mode, the controller activates all of the first plurality of circuits, and in the low power mode, the controller activates a subset of the first plurality of circuits while keeping the remaining circuits of the first plurality of circuits inactive.

[0010] In another form, a microcontroller includes a central processing unit (CPU) core coupled to a low voltage power bus, a memory coupled to the low voltage power bus and coupled to the CPU core, a plurality of peripheral circuits coupled to the high voltage power bus and coupled to the CPU core; and a power saving energy management circuit. The power saving energy management circuit receives an external power supply voltage and provides a digital power supply voltage to the low voltage power bus and a high power supply voltage to the high voltage power bus. The energy management circuit includes a first regulator, a second regulator, and a controller. When the microcontroller is in an active mode, the first regulator receives the external power supply voltage and provides the digital power supply voltage to the low voltage power bus at a first rated power in response to the external power supply voltage. When the microcontroller is in a low power mode, the second regulator receives the external power supply voltage and provides the digital power supply voltage at a second rated power lower than the first rated power in response to the external power supply voltage. The controller controls the transition of the microcontroller between the active mode and the low power mode. In the active mode, the controller activates the CPU core and the memory, and in the low power mode, the controller puts the CPU core and the memory in a low power state.

[0011] In yet another form, a method of operating an integrated circuit includes: generating a first internal supply voltage having a first nominal voltage on a first supply voltage rail using a first voltage regulator in an active mode, and activating each of a first plurality of circuits coupled to the first supply voltage rail. In a low power mode, the method includes generating the first internal supply voltage having the first nominal voltage on the first supply voltage rail using a second voltage regulator, wherein the second voltage regulator has a lower power rating than the first voltage regulator, and activating a subset of the first plurality of circuits while keeping the remaining circuits of the first plurality of circuits inactive.

[0012] Figure 1 The MCU 100 known in the prior art is illustrated in block diagram form. The MCU 100 includes a set of integrated circuit terminals 110, a low dropout (LDO) voltage regulator 120, an LDO regulator 130, a set of digital circuit blocks 140, a universal serial bus (USB) physical layer interface circuit (PHY) 150, and a set of input / output circuits 160.

[0013] Integrated circuit terminals 110 include a terminal 111 for receiving an external regulation voltage marked as "VREGIN", a terminal 112 for receiving a power supply voltage marked as "VDD", a terminal 113 for receiving a ground voltage marked as "GND" (the ground voltage referenced by VREGIN and VDD), a terminal 114 for conducting a positive USB data signal marked as "D+", a terminal 115 for conducting a negative USB data signal marked as "D-", a terminal 116 for receiving an input / output power supply marked as "VIO", and a group of terminals 117 used as digital and / or analog I / O port pins.

[0014] The LDO voltage regulator 120 has an input connected to the terminal 111, an output for providing an internal supply voltage of 3.3 volts, and a reference terminal connected to ground. VREGIN is an external regulated supply voltage having a nominal value of 5 volts. The LDO voltage regulator 120 is adapted to convert VREGIN into an internal regulated voltage having a value of 3.3 volts in this example.

[0015] The LDO voltage regulator 130 has an input connected to terminal 112 and connected to the output of the LDO voltage regulator 120, an output for providing a 1.8 volt internal power supply voltage, and a reference terminal connected to terminal 113, which provides a ground for the MCU 100. In one mode, the LDO voltage regulator is active and outputs a 3.3 volt internal power supply, which the LDO voltage regulator 130 uses to generate a 1.8 volt internal power supply. In an alternative mode, the LDO voltage regulator 120 is disabled and the external voltage regulator provides a 3.3 volt voltage to terminal 112.

[0016] The digital circuit block 140 includes a set of exemplary digital circuits useful in an MCU, which includes a central processing unit core 141, a random access memory 142, a flash memory 143, an oscillator block 144, and a peripheral logic block 145. The MCU 100 is implemented using low-power complementary metal oxide semiconductor (CMOS) transistors, and the digital circuit block 140 operates on a relatively low power supply voltage of 1.8 volts.

[0017] The USB PHY 150 has bidirectional terminals connected to the terminals 114 and 115, and is powered by an internal 3.3 volt power supply. The input / output circuit 160 includes a set of digital I / O circuits 161 and a set of analog multiplexers 162. Each of these circuit groups is connected to a corresponding terminal in the terminal 117, and both are powered by the 3.3 internal power supply voltage in one mode and by the terminal 116 in another mode.

[0018] MCU 100 uses LDO voltage regulator 120 and LDO regulator 130 to provide internal 3.3 volt and 1.8 volt supply voltages, respectively. Typically, LDO is easy to implement using, for example, a single high power series transistor with a simple feedback loop, using a comparator and a voltage reference to control the conductivity of the pass transistor to regulate the output to the desired voltage. Despite the simple structure, however, LDO regulators are relatively inefficient at lighter loads.

[0019] In order to generate a stable internal power supply, conventional MCUs require large load capacitors for each on-chip power supply. However, these large load capacitors have caused problems. First, they make the MCU have high current consumption, because the voltage regulator with large load capacitors must generate a large bias current to stabilize itself. Second, if they are integrated on the chip, the circuit area and chip cost will be increased. If the MCU cannot support large currents, then for stability, the voltage regulator must further increase the capacitance of the load capacitor so that it becomes the dominant pole, which requires a larger capacitor and causes a further increase in the die area and cost of the chip. Third, if it is impossible to integrate a load capacitor with sufficient size on the chip, then the chip will need a large external capacitor and require an integrated circuit terminal to connect the off-chip capacitor, which increases the chip area and cost. Therefore, the use of large load capacitors makes it difficult to provide a low-cost, low-power MCU.

[0020] Figure 2 The MCU 200 with a power saving energy management circuit according to an embodiment is illustrated in block diagram form. The MCU 200 is an integrated circuit MCU, which generally includes a CPU system 210, a clock unit 220, a power saving energy management circuit 230, a peripheral bus 240, a group of serial interfaces and I / O ports 250, a group of timers and counters 260, and a group of analog interfaces 270.

[0021] The CPU system 210 includes a CPU bus 212 that interconnects a CPU core 211, a bus bridge 213, a flash memory 214, a random access memory (RAM) 215, a debug circuit 216, and a direct memory access controller (DMAC) 217. The CPU system 210 includes a CPU bus 212 that is separated from a peripheral bus 240 to isolate transactions initiated by the CPU core 211 to local devices and memories without affecting the traffic on the peripheral bus 240. The bus bridge 213 is a circuit that allows cross-bus transmission between the CPU bus 212 and the peripheral bus 240. The CPU system 210 provides a flash memory 214 that is used for non-volatile storage of program code that can be boot-loaded from an external source and parameters that need to be saved when the MCU 200 is powered off. The RAM 215 provides a working memory for use by the CPU core 211. The debug circuit 216 provides a program tracing capability with access to registers on the CPU core 211 for software debugging. DMAC 217 provides a programmable direct memory access channel to offload CPU core 211 from routine data movement tasks between peripheral devices and memory.

[0022] MCU 200 includes a set of peripheral devices that make it suitable for various general embedded applications. Peripheral bus 240 interconnects bus bridge 213, clock unit 220, power saving energy management circuit 230, serial interface and I / O port 250, timer and counter 260, and analog interface 270. The serial interface in serial interface and I / O port 250 operates according to various synchronous and asynchronous character-oriented protocols and serial protocols. The I / O port in serial interface and I / O port 250 is a group of general input / output circuits, which have terminals that can be programmed for specific functions or remain available for software for general operation. Timer and counter 260 provides various programmable timing and event counting functions useful for embedded control, and includes watchdog timer and real-time clock. Analog interface 270 includes various analog interface circuits, such as analog comparator and analog-to-digital converter (ADC) for accurate analog input signal measurement.

[0023] Typically, the MCU 200 integrates a CPU system 210 and several peripherals for a wide variety of application environments, and the MCU 200 is suitable for very low power operations. The MCU 200 includes a clock unit 220 that provides the MCU 200 with various clocks and clock functions for supporting its low power mode. For example, the clock unit 220 may include a high frequency oscillator, and a lower precision fully integrated resistor-capacitor (RC) oscillator and an extremely low speed RC oscillator that allow standby and keep-alive operations.

[0024] MCU 200 also includes a power saving energy management circuit 230 that implements a power architecture that provides several programmable functions to support very low power operation in low power mode. Power saving energy management circuit 230 is bidirectionally connected to peripheral bus 240 and has a function for receiving a signal labeled “V DDX ” external supply voltage input terminal, and has a pin labeled “V DDH ”, a relatively high supply voltage for flash memory 214 marked as “V DDH_闪存 ” and the relatively high supply voltage marked “V DDD In this exemplary embodiment, these voltages have the nominal values ​​shown in Table 1:

[0025] name describe Nominal voltage <![CDATA[V DDX ]]> External power supply voltage 5V <![CDATA[V DDH_闪存 ]]> Internal high voltage for flash memory 3V <![CDATA[V DDH ]]> Internal high voltage for analog interface and I / O circuits 2.4V <![CDATA[V DDD ]]> Internal supply voltage for digital CMOS and oscillators 1.2V

[0026] V DDX Is the input voltage for all on-chip voltage regulators, as well as I / O signals. V DDHIt is the voltage used to power analog circuits and circuits that implement external I / O functions. DDH_闪存 is the voltage supplied to the flash memory 214 to allow the flash memory 214 to generate further voltages to program and erase the floating gate memory cells. V DDD It is a relatively low voltage supplied to digital CMOS circuits such as the CPU core 211.

[0027] The power saving energy management unit 230 also provides other functions in addition to voltage generation. For example, it can also include a brown-out detector and a low-power power-on reset circuit, and the brown-out detector is designed to force the MCU 200 to enter reset when the power consumption is too high. It implements a state machine to control the entry and exit of various low-power modes. Specifically, the power saving energy management circuit 230 provides an internal architecture with multiple voltage regulators for supported power supply voltages, but these voltage regulators operate efficiently in different load ranges created by different power saving modes. The further details of the power saving architecture will now be described.

[0028] Figure 3 Shown by Figure 2 300 of various power states supported by the MCU 200. The state diagram 300 includes four power states or modes, including an active mode 310, an idle mode 320, a sleep mode 330, and a shutdown mode 340. When power is supplied to the MCU 200 at initial power-up, the MCU 200 enters the active mode 310 when a power-on reset signal labeled "POR" is active to indicate that the power supply voltage has risen to a suitable voltage for operation, and a signal labeled "ALL_OK" is activated to indicate that all internal voltage regulators are active and have reached their nominal levels. The active mode 310 is a normal operating state in which all circuits are powered on and enabled and the CPU core 211 begins operation by fetching and executing instructions. The available low power states, namely, the idle mode 320, the sleep mode 330, and the shutdown mode 340, are entered only from the active mode 310.

[0029] When a control signal marked as "IDLE" is activated (e.g., by software setting the corresponding idle bit in the memory-mapped power control register), the MCU 200 enters the idle mode 320. In other embodiments, the idle signal can be set in different ways, such as according to the activity detector not detecting any activity for a certain period of time, in response to an external control signal, etc. In the idle mode 320, the clock is removed from the CPU and certain peripherals, but all circuits continue to be powered. Because the MCU 200 is implemented with CMOS circuit implementation, the CMOS circuit does not lose its state when the clock signal is removed. All power supplies remain fully powered, allowing relatively fast wake-up times, but the MCU 200 still consumes leakage power, power consumed by selected peripherals to remain active to report wake-up events, and power consumed by voltage regulators. If the all_on signal is true, the MCU 200 can return to the active mode 310 in response to the activation of an enabled interrupt or the activation of a reset terminal (i.e., a hot reset).

[0030] When a control signal labeled "SNOOZE" is activated (e.g., by software setting a corresponding snooze bit in a memory-mapped power control register), the MCU 200 enters the snooze mode 330. In other embodiments, the snooze signal may be set in different ways, such as based on the activity detector not detecting any activity for a certain period of time, in response to an external control signal, etc. In the snooze mode 330, the clock is removed from the CPU, from certain peripherals, and from the high-power voltage regulator, but as will be explained below, the low-power voltage regulator continues to power all voltage domains so that the components do not lose their state. If the all_on signal is true, the MCU 200 may return to the active mode 310 in response to a wake-up event (an enabled interrupt, a signal from a watchdog timer, etc.), activation of a reset terminal (i.e., a warm reset), or a hard reset (cycling an external power pin).

[0031] When the control signal labeled "SHUTDOWN" is activated (e.g., by setting the corresponding shutdown bit in the memory-mapped power control register by software), MCU 200 enters shutdown mode 340. In other embodiments, the shutdown signal can be set in different ways, such as based on the activity detector not detecting any activity for a certain period of time, in response to an external control signal, etc. In shutdown mode 340, the external power supply voltage V DDXPowered external I / O pins maintain their states, but clocks and internal power are removed from all circuits (including all voltage regulators). If the all_on signal is true, the MCU 200 can return to active mode 310 only in response to a reset indicated by activation of the reset terminal (i.e., warm reset) or a hard reset (cycling external power pins).

[0032] Table II summarizes the various power modes supported by MCU 200:

[0033] Table II

[0034]

[0035] Although certain low power modes and their corresponding behaviors are described, in other embodiments, the MCU 200 may also support modes other than Figure 3 1 and Table II. For example, in these additional low-power modes, different combinations of peripherals can remain active or can be disabled. In addition, the behavior of these peripherals in these various low-power modes and the specific interrupts or wake-up events that are allowed to cause the MCU 200 to exit the idle and / or sleep modes can be software programmable.

[0036] Figure 4 The MCU 400 is shown in partial block diagram and partial schematic form, showing Figure 2 The power saving architecture of the MCU 200 is shown in FIG. MCU 400 generally includes a set of voltage regulators 410 , a set of high voltage peripherals 430 , a set of digital circuits 440 , a flash memory 450 , a control register 460 , and a power management controller 470 .

[0037] The voltage regulator 410 is part of the power saving energy management circuit 230 and includes a low power bias circuit 411, a high power bias circuit 412, regulators 413 and 414, a capacitor 415, regulators 416 and 417, a capacitor 418, a power monitor 420, and capacitors 421, 422, and 423. The low power bias circuit 411 is a circuit having a circuit for receiving V DDX The power supply terminals are marked “V BG_LP The high power bias circuit 412 is a circuit having a power supply terminal and a bias signal labeled “V BG_HP " is a high power bias circuit at the output end of the bias signal. The regulator 413 is a high voltage high power regulator, which has a high voltage high power regulator for receiving V DDX Power supply terminal for receiving V BG_HP The reference input terminal is used to provide V DDHThe first output terminal is used to provide V through the replica path DDH_闪存 The second output terminal of the DDH_LP The third output terminal of the high power bias circuit 412 is connected to the input terminal of the voltage of ". The regulator 414 is a high voltage low power regulator, which has a voltage for receiving V DDX Power supply terminal for receiving V BG_LP 414, a first output terminal connected to the second output terminal of the voltage regulator 413, and a second output terminal connected to the power supply input terminal of the high power bias circuit 412. Capacitor 415 has a first terminal connected to the second output terminal of the voltage regulator 414 and a second terminal connected to ground. Regulator 416 is a low voltage high power regulator having a first terminal for receiving V DDX Power supply terminal for receiving V BG_HP The reference input terminal and the V DDD The output terminal of the voltage regulator 417 is a low voltage low power voltage regulator having a voltage regulator for receiving V DDX Power supply terminal for receiving V BG_LP The power monitor 420 has a first terminal connected to the second output terminal of the voltage regulator 417 and a second terminal connected to the ground. DDX The power input terminal is used to receive V DDH_LP The first input terminal is used to receive V BG_LP The second input terminal is used to receive V BG_HP The third input terminal is used to receive V DDD_LP The fourth input terminal is used to receive V DDH_LP The fifth input terminal is used to receive V DDD The sixth input terminal is used to receive V DDH The capacitor 421 has a seventh input terminal for receiving V DDH_闪存 The capacitor 422 has a first terminal for receiving V DDH The capacitor 423 has a first terminal for receiving V DDD of a first terminal and a second terminal connected to ground.

[0038] The high voltage peripherals 430 include a digital-to-analog converter 431, a set of I / O buffers 432, a successive approximation register (SAR) 433, and an analog comparator 434 (all of which are connected to high voltage (e.g., 5 volt) I / O), and include a watchdog timer 435, a high frequency oscillator 436, a low frequency oscillator 437, and a fast start (FS) oscillator 438 for communicating with internal digital peripherals at a supply voltage of 1.2 volts. Each of the high voltage peripherals 430 has a DAC for receiving V DDH The power terminal and the ground terminal connected to the ground.

[0039] The digital circuit 440 includes an SRAM 441 and a digital block 442. The digital block 442 represents a digital circuit other than the SRAM 441, such as Figure 2 The CPU core 211, bus bridge 213, debug circuit 216, and DMAC 217 of the MCU 200. Each circuit or each group of circuits in the digital block 440 has a function for receiving V DDH The power terminal and the ground terminal connected to the ground.

[0040] Flash memory 450 has a function for receiving V DDH_闪存 A first power supply voltage terminal for receiving V DDD The flash memory 450 uses a second power supply voltage terminal and a ground terminal connected to the ground. HHD_闪存 (or from V DDH_闪存 The READ, WRITE and ERASE cycles are performed internally but are communicated to the CPU core 211 via the CPU bus 212 (where the signals are referenced to V DDD ), and therefore use two supply voltages.

[0041] The control register 460 has three bits (or bit fields) to indicate a request to enter a low power mode, including a sleep bit 461 , an idle bit 462 , and a shutdown bit 463 .

[0042] The power management controller 470 has a first input terminal for receiving a signal marked as "reset", a second input terminal for receiving a wake-up event signal marked as "wake-up_event", a third input terminal for receiving an all_on signal, an input terminal connected to the output terminal of the control register 460, and has an output terminal for providing a signal directly or indirectly indicating whether the integrated circuit 400 is in an active mode, a sleep mode, an idle mode or a shutdown mode, and includes an output terminal marked as "POR" (power-on reset).

[0043] In operation, the power management controller 470 determines the operating mode of the MCU 400, where the operating mode can be requested by software setting a bit or bit field in the control register 460 corresponding to the desired mode. The power management controller 470 then enters the appropriate mode when all preconditions have been met, such as the power monitor 420 indicating that all supply voltages have been enabled via the all_on signal. The power management controller 470 also observes the POR, reset, and wakeup event signals to determine when to make a power state transition. The supported power modes are shown previously in Table II above.

[0044] MCU 400 has a power architecture that achieves both low cost and low power consumption. In order to achieve these two goals at the same time, MCU 400 does not adopt the above-mentioned known large capacitor method, but achieves these two goals separately.

[0045] MCU 400 achieves low cost by partitioning its component circuits according to function, noise, voltage and current requirements. Flash memory 450 generates high levels of noise and uses high voltage and high current. Therefore, flash memory 450 receives a stronger power supply (i.e., a power supply with a higher power rating) and uses a relatively large on-chip capacitor (i.e., capacitor 421 with a value of 150 picofarads (pF)). The analog circuits including DAC 431, SAR 433 and analog comparator 434 generate less noise and use relatively small current, but require a power supply that produces a stable low-noise voltage. Therefore, the analog circuit receives a lower power supply voltage V with a smaller rated power consumption. DDH and a smaller on-chip capacitor (i.e., capacitor 422 having a value of 75 pF). The high power bias circuit 412 and the power monitor 420 generate very little noise and use very low current, but require a power supply that produces a stable, low noise voltage to provide a stable reference voltage and an accurate all_on signal. Therefore, the high power bias circuit 412 and the power monitor 420 receive a lower supply voltage V DDH_LP and a very small on-chip capacitor 415 (i.e., capacitor 415 having a value of 10 pF). SRAM 441 and digital block 442 generate a lot of noise and use a lot of current, but because they are digital CMOS circuits, they can operate at relatively low voltages. Therefore, SRAM 441 and digital block 442 receive the lowest supply voltage, V DDD , but using the largest capacitor, namely on-chip capacitor 423 with a value of 700 pF.

[0046] Partitioning the MCU 400 into these functional groups allows the overall on-chip capacitance to be reduced for a given die area and current consumption / power consumption by using large capacitors only for the most needed voltage domains. In addition, partitioning the MCU 400 into these functional groups isolates the noise generated in one partition (or voltage domain) from the noise generated in other partitions.

[0047] MCU 400 achieves low power by providing a set of high power regulators and bias reference circuits and another set (or "copy" set) of low power regulators and bias reference circuits. The high power regulators include regulators 413 and 416, and the high power reference circuit is high power bias circuit 412. These circuits provide fast settling, highly accurate internal power supply and reference voltage. Regulators 413 and 416 support relatively large current loads, for example, for V DDH_闪存 Supports up to 12 mA for V DDH Supports up to 6 mA for V DDD Supports up to 10 mA. The low power regulators include regulators 414 and 417, and the low power bias circuit includes low power bias circuit 411. Regulators 414 and 417 support internal power supplies with moderate accuracy and settling time, but consume much less bias current than their higher rated counterparts. Regulators 414 and 417 support smaller current loads for V DDH_闪存 Supports current loads up to 20μA for V DDH Supports current loads up to 100μA for V DDD It supports current loads up to 1mA, but only requires about 6.5μA of bias current.

[0048] Different combinations of high-power and low-power regulators and bias reference circuits can be used to support different power modes. Each supply voltage rail uses both a primary branch and a replica branch to alternate between a regulator with a higher power rating and a regulator with a lower power rating. Figure 4 The replica branch is shown as a dashed line. The regulator providing the replica branch is an open loop circuit that is unconditionally stable for any load capacitor and allows switching between regulators corresponding to different power modes. The main branches and their corresponding replica branches for different supply voltage rails are shown in Table III:

[0049] Power Rails Main power supply Main voltage Copy power supply Replica voltage <![CDATA[V DDH_闪存 ]]> Voltage regulator 413 3V Voltage regulator 414 2.1V <![CDATA[V DDH ]]> Voltage regulator 413 2.4V Voltage regulator 414 2.1V <![CDATA[V DDD ]]> Voltage regulator 416 1.2V Voltage regulator 417 1.2V

[0050] Consistent with the selected power state, voltage regulator 410 provides various supply voltages to the internal circuits of MCU 400 using an alternating voltage regulator as specifically outlined in Table IV:

[0051] power supply Active Mode Idle Mode Sleep Mode Shutdown Mode <![CDATA[V DD_闪存 ]]> 413(main) 414 (copy) 414 (copy) All power off <![CDATA[V DDH ]]> 413(main) 413(main) 414 (copy) All power off <![CDATA[V DDH_LP ]]> 414(main) 414(main) 414(main) All power off <![CDATA[V DDD ]]> 416(main) 416(main) 417 (copy) All power off

[0052] In addition, the states of the voltage regulators of the MCU 400 in various power modes are shown in the following Table V:

[0053] Table V

[0054]

[0055] In a specific example, the total bias current of all voltage regulators is 600 microamperes (μA) in active mode, 200 μA in idle mode, 6.5 μA in sleep mode, and 0.3 μA in shutdown mode. When MCU 400 switches from active mode to idle mode, power management controller 470 disconnects regulator 413 and power consumption is reduced to 200 μA. When MCU 400 switches from active mode to sleep mode, power management controller 470 disconnects high power bias circuit 412, high power regulator 413, and high power regulator 416, and power consumption is reduced to 6.5 μA. When MCU 400 switches from active mode to idle mode, power management controller 470 disconnects all regulators and bias circuits and power consumption is reduced to 0.3 μA.

[0056] Digital Circuit 440 at V DDD domain and receive V DDD As its power supply voltage. Portions of SRAM 441 and digital block 442 remain powered during sleep mode while the gate turns off power to other portions. For example, regulator 417 continues to provide power supply voltage V DDD , so that the memory core maintains its state when MCU 400 is in sleep mode, but SRAM 441 performs power gating on the access circuit system. Therefore, SRAM 441 only consumes leakage power in its core, and does not consume power in the power gating circuit. Similarly, parts of digital circuit 440 are power gated, while other parts are powered by the low voltage power supply.

[0057] When in the idle mode 320, the sleep mode 330, and the shutdown mode 340, the flash memory 450 stops receiving V from the voltage regulator 413. DDH_闪存 , but in idle and sleep modes a replica path is used to continue to supply V from voltage regulator 414 DDH_闪存 However, in these modes, MCU 400 does not allow read, write, and erase access to flash memory 450 because any circuits that can access them (including CPU core 211) are disabled. Since it is non-volatile, flash memory 450 retains its contents when power is removed. Flash memory 450 continues to receive V in idle and sleep modes using regulator 417. DDD .

[0058] By using a separate voltage regulator tailored for the lower rated power in idle and / or sleep mode, MCU 400 saves a large amount of bias current that would be required by a higher rated power voltage regulator used in active mode. Therefore, MCU 400 provides low power consumption in low power mode, saves battery life, while maintaining a compact integrated circuit size and keeping the cost low. Similarly, by separating the voltage regulator based on the type of circuit powered by it, the MCU eliminates the need for external capacitors sufficient for most or all of the internal circuits, thereby saving the cost of external capacitors and additional MCU terminals. The design of the regulator can also be changed according to its needs. For example, in one embodiment, regulator 413 can be implemented as an LDO regulator to provide better efficiency under large loads, while regulator 414 can be implemented as a regulated charge pump, which provides better efficiency under lighter loads.

[0059] The power monitor 420 determines whether all power circuits are operating so that the MCU 400 can enter the active mode 310. The power monitor 420 has a function for receiving a low power bias voltage V BG_LP and high power bias voltage V BG_HP Both input terminals have a power supply voltage V DDX , V DDH_LP 、V DDD_LP 、V DDH and V DDD The input terminal of each.

[0060] The power management controller 470 powers up each regulator in the following order. The low power bias circuit 411 receives the external power supply voltage V DDX , and at V DDX When the voltage rises to a sufficient level, it provides a bias voltage V BG_LP . V BG_LP is a reference voltage that is equal to or based on the bandgap voltage. The bandgap of silicon is 1.2 volts, so if V BG_LP is equal to the bandgap voltage, then V DDX must rise above 1.2 volts to allow the bandgap voltage generation circuit to operate. Once V BG_LP At their proper levels, regulators 414 and 417 can provide their respective output voltages at proper levels. The second output terminal of the high voltage low power regulator generates V DDH_LP , the V DDH_LP is provided on a separate signal line to the high power bias circuit 412. Once the regulator 414 begins operating and provides V at its appropriate level DDH_LP, high power bias circuit 412 can begin to operate. In addition, once high power bias circuit 412 begins to operate, it biases regulators 413 and 416, and regulators 413 and 416 begin to increase their respective output voltages by charging capacitors 422 and 423, respectively. When these voltages reach their nominal levels, power monitor 420 activates signal all_on, and power management controller 470 switches MCU 400 to active mode and asserts the ACTIVE signal.

[0061] Figure 5 A timing diagram 500 is shown, which shows the activation Figure 4 In the timing diagram 500, the horizontal axis represents the time in use, and the vertical axis represents the external power supply voltage V DDX The timing diagram 500 shows a waveform 510, which represents the value of the external power supply voltage V DDX The external supply voltage V rises from zero voltage to a value of 5.5 volts (at the high end of its allowed range). DDX The timing diagram 500 also shows four points in time of interest, labeled “t0”, “t1”, “t2”, and “t3”.

[0062] The sequence for powering up the MCU 400 can be summarized as follows. The power supply voltage V DDX starts in the power-off state at 0 volts and at the supply voltage V DDX The voltage regulator 410 ramps up before time t0 when it reaches 0.6 volts. Before time t1, all circuits in the voltage regulator 410 are disabled.

[0063] At time t1, V DDX 4. When the output of low power bias circuit 411 exceeds the threshold voltage of the 3 volt P-channel MOS transistor plus the drain-to-source voltage of the 3 volt N-channel MOS transistor, power monitor 420 enables the charge pump function of regulators 414 and 417 to allow them to generate a voltage greater than V using their replica branches. DDX When the power monitor 420 detects that V DDH_LP >1.5V and V DDD_LP>0.9 volts, the power monitor 420 enables the high power bias circuit 412. When the power monitor 420 detects that the output of the high power bias circuit 412 is greater than 1 volt, the power monitor 420 turns on the voltage regulator 413 and the low voltage high power regulator 416. Finally, when the power monitor 420 detects that V DDH >1.57V and V DDD >1V, the power monitor 420 starts to detect V DDX Level.

[0064] At time t2, the power monitor 420 detects that V DDX has reached 1.8 volts. Power monitor 420 activates all_on, and power management controller 470 places MCU 400 in active mode, in which all circuitry is operating. Power monitor 420 programs the voltage regulator to the more accurate, calibrated settings stored by MCU 400, allowing voltage regulator 410 to provide highly accurate internal voltages. It then turns V DDX The threshold is lowered to 1.71 volts (which is the level at which the chip will enter shutdown mode) thus providing an increased V DDX The power monitor 420 allows read operations to the flash memory 214 until the power monitor 420 detects that V DDH_闪存 ≥2.4V, at which point the power monitor 420 enables the flash memory 214 for write and erase operations as well as read operations.

[0065] MCU 400 changes from active mode 310 to sleep mode 330 as shown below. When sleep=1, the sleep controller inside power management controller 470 activates low power regulators 414 and 417 and the power regulators for V DDH 、V DDH_闪存 , and V DDD The replica path of , and during this time, both high power regulators 413 and 416 and low power regulators 414 and 417 are activated. When regulator 416 is disabled, the sleep controller controls regulator 417 to V DDD The voltage regulator 410 is reduced to 1.1 volts to remove any momentary glitches. After a certain period of time, the sleep controller disables the high power regulator 413 and the high power regulator 416 and the high power bias circuit 412. The current consumption of the voltage regulator 410 is reduced from 600 μA to about 6.5 μA, where the output voltage is less accurate, and the MCU 400 is then in sleep mode.

[0066] MCU 400 changes from sleep mode 330 back to active mode 310 as shown below. When active=1, regulators 413 and 414 are reactivated. Power management controller 470 controls regulator 417 to increase VDDD The voltage regulator 410 increases to 1.2 volts and activates the high power bias circuit 412 and the regulators 413 and 415. After another certain period of time, both the regulators 414 and 417 and the replica path are disabled. The current consumption of the voltage regulator 410 increases from 6.5 μA to about 600 μA, and the outputs of the regulators 413 and 416 are highly accurate again. The MCU 400 is then in active mode.

[0067] According to one aspect of the disclosed embodiment, MCU 400 includes a set of circuits that define voltage domains, such as V DDH The voltage domain receives V DDH As a high voltage peripheral device 430 for its power supply voltage. To generate V DDH , the power saving energy management circuit 230 uses the voltage regulator 413 or the voltage regulator 414. For example, when the MCU 400 is in the active mode, the power management controller 470 uses the V generated by the high power high voltage regulator 413. DDH , because high power high voltage regulator 413 is efficient at high power levels and has a higher power rating than regulator 414. However, when MCU 400 is in sleep mode, some of high voltage peripherals 430 are disabled, and power saving energy management circuit 230 uses high voltage low power regulator 414 to generate V DDH In sleep mode, power management controller 470 disables regulator 413. Regulator 414 has a lower power rating than regulator 413 and although it cannot generate V at a regulated voltage at high power levels, it can also generate V at a regulated voltage. DDH , but it generates the supply voltage V at relatively low power levels DDH In other aspects, it is more efficient than the regulator 413.

[0068] Similarly, to generate V DDD , the power saving energy management circuit 230 uses the voltage regulator 416 or the voltage regulator 417. For example, when the MCU 400 is in the active mode, the power management controller 470 uses the V generated by the high power low voltage regulator 416. DDD , because high power low voltage regulator 416 is efficient at high power levels and has a higher power rating than regulator 417. However, when MCU 400 is in sleep mode, certain digital circuits in digital circuit 440 are disabled, and power saving energy management circuit 230 uses low voltage low power regulator 417 to generate V DDD In sleep mode, power management controller 470 disables regulator 416. Regulator 417 has a lower power rating than regulator 416 and although it cannot generate V at a regulated voltage at high power levels, it can also generate V at a regulated voltage. DDD, but it generates the supply voltage V at relatively low power levels DDD More efficient than regulator 416 in this regard.

[0069] The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. For example, various low-power modes have been described, but in other embodiments, the MCU may support other low-power modes that keep a different set of internal circuits activated while powering down other circuits. In different embodiments, the conditions for entering and exiting various modes may also vary. In addition, although the current consumption is described for specific examples, these values ​​are only approximate, and different integrated circuits and MCUs will have different current levels.

[0070] Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. An integrated circuit, comprising: a first plurality of circuits coupled to a first supply voltage rail and receiving a first internal supply voltage on the first supply voltage rail; a first voltage regulator that receives an external power supply voltage and provides the first internal power supply voltage to the first power supply voltage rail at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode; a second voltage regulator receiving the external power supply voltage for providing the first internal power supply voltage to the first power supply voltage rail at a second rated power lower than the first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode; as well as a controller for controlling a transition of the integrated circuit between the active mode and the low power mode, wherein in the active mode the controller activates all of the first plurality of circuits, and in the low power mode the controller activates a subset of the first plurality of circuits while keeping the remaining circuits of the first plurality of circuits inactive.

2. The integrated circuit according to claim 1, wherein: The first regulator comprises a low dropout regulator; and The second voltage regulator comprises a regulated charge pump which uses a corresponding replica branch to provide the first internal supply voltage.

3. The integrated circuit of claim 1 , comprising: a second plurality of circuits receiving a second internal supply voltage, wherein the second internal supply voltage is lower than the first internal supply voltage; a third voltage regulator that receives the external power supply voltage in the active mode and provides the second internal power supply voltage at a third rated power in response to the external power supply voltage; as well as A fourth voltage regulator receives the external power supply voltage and provides the second internal power supply voltage at a fourth rated power lower than the third rated power in the low power mode.

4. The integrated circuit according to claim 3, wherein: The third regulator comprises a low dropout regulator; and The fourth voltage regulator comprises a regulated charge pump which uses a corresponding replica branch to provide the second internal supply voltage.

5. The integrated circuit according to claim 3, wherein: In the active mode, the controller activates each of the second plurality of circuits by providing a corresponding clock signal to each of the second plurality of circuits, and in the low power mode, the controller keeps the remaining circuits of the first plurality of circuits inactive by stopping providing the corresponding clock signals to the circuits of the first plurality of circuits.

6. The integrated circuit according to claim 3, characterized in that The integrated circuit is a microcontroller, and wherein: The first plurality of circuits includes analog interface circuits; and The second plurality of circuits includes a central processing unit core, a memory, and a bus bridge having a first port coupled to the central processing unit core and a second port coupled to the memory.

7. The integrated circuit of claim 1, wherein: In response to detecting an idle event, the controller further controls a transition of the integrated circuit between the active mode and the idle mode, wherein in the idle mode, the controller places the central processing unit core into a sleep mode and continues to power all of the first plurality of circuits using the first regulator.

8. A microcontroller comprising: a central processing unit core coupled to a low voltage power bus; a memory coupled to the low voltage power bus and to the central processing unit core; a plurality of peripheral circuits coupled to a high voltage power bus and to the central processing unit core; as well as An energy management circuit, the energy management circuit is used to receive an external power supply voltage and provide a digital power supply voltage to the low voltage power bus and provide a high power supply voltage to the high voltage power bus, wherein the energy management circuit comprises: a first voltage regulator that receives the external power supply voltage and provides the digital power supply voltage to the low voltage power bus at a first rated power in response to the external power supply voltage when the microcontroller is in an active mode; a second voltage regulator that receives the external power supply voltage and provides the digital power supply voltage at a second rated power lower than the first rated power in response to the external power supply voltage when the microcontroller is in a low power mode; and A controller for controlling the transition of the microcontroller between the active mode and the low power mode, wherein in the active mode, the controller activates the central processing unit core and the memory, and in the low power mode, the controller places the central processing unit core and the memory in a low power state.

9. The microcontroller according to claim 8, characterized in that The controller places the CPU core and the memory in the low power mode by disabling clocking to the CPU core and the memory while continuing to provide the digital power supply voltage to the CPU core and the memory using the second voltage regulator.

10. The microcontroller according to claim 8, characterized in that The energy management circuit further comprises: a third voltage regulator that receives the external power supply voltage and provides a high power supply voltage to the high voltage power bus at a third rated power in response to the external power supply voltage when the microcontroller is in the active mode; and a fourth voltage regulator, when the microcontroller is in the low power mode, the fourth voltage regulator receiving the external power supply voltage and providing the high power supply voltage at a fourth rated power lower than the third rated power in response to the external power supply voltage, Wherein, in the active mode, the controller activates all of the plurality of peripheral circuits, and in the low power mode, the controller activates a subset of the plurality of peripheral circuits while keeping the remaining peripheral circuits of the plurality of peripheral circuits inactive.

11. The microcontroller according to claim 10, characterized in that The controller transitions from the low power mode to the active mode in response to an input received by one of the remaining peripheral circuits among the plurality of peripheral circuits in the low power mode.

12. The microcontroller according to claim 11, characterized in that: The controller further includes a power monitor that activates a control signal when the outputs of the first regulator, the second regulator, the third regulator, and the fourth regulator are within an acceptable range; and Further in response to the control signal, the controller transitions from the low power mode to the active mode.

13. The microcontroller according to claim 10, wherein: The third regulator comprises a low dropout regulator; and The fourth voltage regulator comprises a regulated charge pump which provides the high supply voltage using a corresponding replica branch.

14. The microcontroller according to claim 10, wherein: In response to detecting an idle event, the controller further controls the microcontroller to switch between the active mode and the idle mode, wherein in the idle mode, the controller places the central processing unit core in a sleep mode, continues to power all of the multiple peripheral circuits using the first regulator, and continues to power the central processing unit core and the memory using the second regulator.

15. The microcontroller according to claim 8, characterized in that The controller transitions from the active mode to the low power mode in response to setting a low power bit in a control register.

16. The microcontroller according to claim 8, wherein: The microcontroller further includes a flash non-volatile memory coupled to the central processing unit core, to the low voltage power bus, and to a flash power supply voltage rail; and The first voltage regulator further provides a flash supply voltage to the flash supply voltage rail in response to the external supply voltage when the microcontroller is in the active mode.

17. A method for operating an integrated circuit, comprising: In active mode: generating a first internal supply voltage having a first nominal voltage on a first supply voltage rail using a first voltage regulator; and activating each of a first plurality of circuits, wherein each of the first plurality of circuits is coupled to the first power supply voltage rail, and In low power mode: generating the first internal supply voltage having the first nominal voltage on the first supply voltage rail using a second voltage regulator, wherein the second voltage regulator has a lower power rating than the first voltage regulator; and A subset of the first plurality of circuits is activated while remaining circuits of the first plurality of circuits are kept inactive.

18. The method of claim 17, further comprising: In the active mode: generating a second internal supply voltage having a second nominal voltage on the second supply voltage rail using a third voltage regulator; and activating each of a second plurality of circuits coupled to the second power supply voltage rail, and in the low power mode: generating the second internal supply voltage having the second nominal voltage on the second supply voltage rail using a fourth voltage regulator, wherein the fourth voltage regulator has a lower power rating than the third voltage regulator; and A subset of the second plurality of circuits is activated while remaining circuits of the second plurality of circuits are kept inactive.

19. The method of claim 17, wherein: said activating each of said first plurality of circuits comprises providing a respective clock signal to each of said first plurality of circuits; The activating the subset of the first plurality of circuits comprises providing a respective clock signal to each of the subset of the first plurality of circuits; and The maintaining the remaining ones of the first plurality of circuits inactive includes removing clock signals from the remaining ones of the first plurality of circuits.

20. The method of claim 17, further comprising: In the active mode: generating a second internal supply voltage having a second nominal voltage lower than the first nominal voltage on a second supply voltage rail using a third voltage regulator; and activating each of a second plurality of circuits coupled to the first supply voltage rail, and in the low power mode: generating the second internal supply voltage having the second nominal voltage on the second supply voltage rail using a fourth voltage regulator, wherein the fourth voltage regulator has a lower power rating than the third voltage regulator; and A subset of the second plurality of circuits is activated while remaining circuits in the second plurality of circuits are kept inactive.

21. A method for operating an integrated circuit, comprising: activating the low power bias circuit, the first high voltage regulator, and the first low voltage regulator when the external power supply voltage rises above a first level; generating a low power reference voltage using the low power bias circuit; generating a first internal supply voltage on a first supply voltage rail using the first high voltage regulator in response to the low power reference voltage and the external supply voltage; activating a subset of a first plurality of circuits coupled to the first supply voltage rail while maintaining remaining circuits of the first plurality of circuits inactive; generating a second internal supply voltage on a second supply voltage rail using the first low voltage regulator in response to the low power reference voltage and the external supply voltage, the second internal supply voltage being lower than the first internal supply voltage; as well as A subset of a second plurality of circuits coupled to the second supply voltage rail is activated while remaining circuits of the second plurality of circuits are kept inactive.

22. The method of claim 21, further comprising: When the external power supply voltage rises to a second level greater than the first level, activating a high power bias circuit, a second high voltage regulator, and a second low voltage regulator; generating a high power reference voltage using the high power bias circuit in response to the first internal supply voltage; generating the first internal supply voltage on the first supply voltage rail using the second high voltage regulator in response to the high power reference voltage and the external supply voltage; activating the remaining circuits of the first plurality of circuits; generating the second internal power supply voltage using the second low voltage regulator in response to the high power reference voltage and the external power supply voltage, the second low voltage regulator having a higher power rating than the first low voltage regulator; as well as The remaining circuits in the second plurality of circuits are activated.

23. The method of claim 22, further comprising: detecting a low power event, and in response to detecting the low power event performing the following operations: disabling the remaining circuits of the first plurality of circuits; disabling the remaining circuits of the second plurality of circuits; enabling the first high voltage regulator; enabling the first low voltage regulator; disabling the second high voltage regulator; disabling the second low voltage regulator; as well as Enter low power mode.

24. The method of claim 23, wherein: Detecting the low power event includes detecting activation of a low power bit in a control register.

25. The method of claim 23, further comprising: Detecting a wake-up event, and in response to detecting the wake-up event, performing the following operations: enabling the second high voltage regulator; enabling the second low voltage regulator; disabling the first high voltage regulator; disabling the first low voltage regulator; enabling the remaining circuits of the first plurality of circuits; enabling the remaining circuits in the second plurality of circuits; and Enter active mode.

26. The method of claim 25, wherein: Detecting the wake-up event includes: Activation of a signal is detected by the subset of the first plurality of circuits.

27. The method of claim 22, further comprising: Detecting an idle event, and in response to detecting the idle event, performing the following operations: putting the central processing unit core into sleep mode; continuing to power all of the first plurality of circuits using the first high voltage regulator; continuing to power all of the second plurality of circuits using the first low voltage regulator; and Enter idle mode.

28. The method of claim 27, further comprising, in response to detecting the idle event but before entering the idle mode, performing the following operations: enabling a third high voltage regulator having a replica branch to a flash memory supply voltage rail coupled to the flash memory; and A fourth high voltage regulator coupled to the flash memory supply voltage rail is disabled.

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