Readout circuit

Abstract

The present disclosure provides a readout circuit including a first switch circuit, a first amplifier circuit, and a first current-to-voltage circuit. The first switch circuit receives a first current signal. The first amplifier circuit is coupled to the first switch circuit via the first circuit node. The first amplifier circuit outputs a first readout current according to a first voltage at the first circuit node. The first current-to-voltage circuit is coupled to the first amplifier circuit and converts the first readout current into a first readout voltage, wherein the second current-to-voltage circuit outputs the first readout voltage via a second circuit node between the first current-to-voltage circuit and the first amplifier circuit.

Description

Technical Field

[0001] The present disclosure relates to an electronic device having a readout circuit. Background Art

[0002] The readout circuit generally made on the array substrate of the electronic device mostly provides the sensing results of multiple sensing units on the array substrate of the electronic device in the form of current to the back-end or external processing circuit for processing. The back-end or external processing circuit is, for example, a driving component (IC) or an external circuit connected to the array substrate, and the back-end or external circuit then converts the sensing results in the form of current into sensing results in the form of voltage. However, the readout current output by the readout circuit on the array substrate of the general electronic device is easily affected by the leakage current of the transistor in the readout circuit. Therefore, when the readout current is sent to the back-end or external processing circuit for processing, it may cause the sensing result to easily carry higher noise. In view of this, several embodiments of the solution will be proposed below. Summary of the invention

[0003] The present disclosure provides an electronic device having a readout circuit suitable for reading out a sensing result of a sensing unit of the electronic device.

[0004] According to an embodiment of the present disclosure, a readout circuit includes a first switch circuit, a first amplifier circuit, and a first current-to-voltage circuit. The first switch circuit receives a first current signal. The first amplifier circuit is coupled to the first switch circuit via the first circuit node. The first amplifier circuit outputs a first readout current according to a first voltage at the first circuit node. The first current-to-voltage circuit is coupled to the first amplifier circuit and converts the first readout current into a first readout voltage, wherein the second current-to-voltage circuit outputs the first readout voltage via a second circuit node between the first current-to-voltage circuit and the first amplifier circuit.

[0005] Based on the above, the readout circuit disclosed in the present invention can first store the current signal provided by the sensing unit into the capacitor through the switch circuit, and provide the amplifier circuit with a first voltage according to the current signal, and then the amplifier circuit can read the corresponding readout current according to the first voltage. In addition, the readout circuit disclosed in the present invention also converts the readout current into a readout voltage for output.

[0006] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the understanding of the readers and for the simplicity of the drawings, the various drawings in the present disclosure only depict a portion of the display device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the drawings are only for illustration and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0008] Figure 1 is a block diagram of a readout circuit according to an embodiment of the present disclosure;

[0009] Figure 2A A circuit diagram of a readout circuit according to a first embodiment of the present disclosure;

[0010] Figure 2B For the purpose of disclosure Figure 2A Operation timing diagram of the readout circuit of the embodiment;

[0011] Figure 2C For the purpose of disclosure Figure 2A A circuit diagram of a current-to-voltage circuit of an embodiment;

[0012] Figure 2D For the purpose of disclosure Figure 2A A circuit diagram of another current-to-voltage circuit of an embodiment;

[0013] Figure 3A is a circuit diagram of a readout circuit according to a second embodiment of the present disclosure;

[0014] Figure 3B For the purpose of disclosure Figure 3A Operation timing diagram of the readout circuit of the embodiment;

[0015] Figure 4A is a circuit diagram of a readout circuit according to a third embodiment of the present disclosure;

[0016] Figure 4B For the purpose of disclosure Figure 4A Operation timing diagram of the readout circuit of the embodiment;

[0017] Figure 4C For the purpose of disclosure Figure 4A Another operation timing diagram of the readout circuit of the embodiment;

[0018] Figure 4D For the purpose of disclosure Figure 4A Another operation timing diagram of the readout circuit of the embodiment;

[0019] Figure 5 A schematic top view of an electronic device according to an embodiment of the present disclosure;

[0020] Fig. 6A is a circuit diagram of a readout circuit according to a fourth embodiment of the present disclosure;

[0021] Figure 6B For the purpose of disclosure Fig. 6A Operation timing diagram of the readout circuit of the embodiment;

[0022] Figure 6C For the purpose of disclosure Fig. 6A A circuit diagram of a differential amplifier according to an embodiment;

[0023] Figure 7 FIG. 4 is a top view of an electronic device according to another embodiment of the present disclosure.

[0024] Description of Figure Numbers

[0025] 100, 200, 300, 400, 530_1 to 530_N, 600, 730_1 to 730_N: readout circuit;

[0026] 100P, 200P, 300P, 400P, 600P, P(1,1)~P(N,M), P(1,0)'~P(N,M)': sensing unit;

[0027] 101, 102, 201, 202, 301, 302, 401, 402, 601, 602, 603, 604: circuit nodes;

[0028] 110, 210, 310, 410, 610, 650: switch circuit;

[0029] 120, 220, 320, 420, 620, 660: capacitance;

[0030] 130, 230, 330, 430, 630, 670: amplifier circuit;

[0031] 140, 240, 240', 240", 340, 440, 640, 680: current-to-voltage circuits;

[0032] 500, 700: electronic devices;

[0033] 510, 710: array substrate;

[0034] 520, 720: column driver;

[0035] 530, 730: row driver;

[0036] 690: Differential amplifier circuit;

[0037] 691: Amplifier;

[0038] Is, In: current signal;

[0039] Iout, Iout1, Iout2: read current;

[0040] Vs, Vn: voltage;

[0041] VA, VB: constant voltage;

[0042] VSS: ground voltage;

[0043] Vout, Vout1, Vout2, Vout3: read current;

[0044] Mrst, Mrc, Mrc1, Mrc2: reset transistor;

[0045] Mro, Mro1, Mro2, Mamp, Mamp1, Mamp2: switching transistors;

[0046] Mres, Mres1, Mres2: load transistors;

[0047] RO, RO_1, RO_2: switching signal;

[0048] RO_RST, RO_RST_C, RO_RST_C_1, RO_RST_C_2: reset signal;

[0049] Res, R1, R2, R3, R4: resistance;

[0050] P21, P22, P23, P31, P32, P33, P41, P42, P43, P41’, P42’, P43’, P41”, P42”, P43”, P44”, P61, P62, P63, P64, P65, P66: period;

[0051] C_0~C_M: column signal lines;

[0052] D_1~D_N: row signal lines. DETAILED DESCRIPTION

[0053] Certain words are used throughout this disclosure and in the appended claims to refer to specific components. Those skilled in the art will appreciate that display device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "including" and "comprising" are open-ended words and should therefore be interpreted as "including but not limited to..."

[0054] In some embodiments of the present disclosure, the terms such as "connection" and "interconnection" related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. And the terms related to bonding and connection may also include the situation that both structures are movable, or both structures are fixed. In addition, the term "coupling" includes any direct and indirect electrical connection means. Although terms such as "first", "second", "third", etc. can be used to describe or name different components, these components are not limited to these terms. These terms are only used to distinguish one component from other components in the specification, and have nothing to do with the manufacturing order of these components. The same terms may not be used in the claims, and may be replaced by "first", "second", "third", etc. according to the order of the components declared in the claims. Accordingly, in the following description, the first component may be the second component in the claims.

[0055] It should be noted that the following embodiments may replace, reorganize, or mix the technical features in several different embodiments to implement other embodiments without departing from the spirit of the present disclosure.

[0056] Figure 1 FIG. 1 is a block diagram of a readout circuit according to an embodiment of the present disclosure. Figure 1 The readout circuit 100 includes a switch circuit 110, a capacitor 120, an amplifier circuit 130, and a current-to-voltage circuit 140. The readout circuit 100 is used to read out the sensing result of the sensing unit 100P. The sensing unit 100P may be, for example, one or more sensing units in an electronic device, and the sensing unit 100P may be, for example, an active pixel sensor (APS) or a passive pixel sensor (PPS). The readout circuit 100 of the present embodiment may be disposed in a peripheral area adjacent to the display area. It is noteworthy that in the embodiments disclosed herein, the sensing unit 100P and the readout circuit 100 are arranged on the same substrate (for example, on an array substrate). For example, at least one layer in the sensing unit 100P (for example, a conductive layer or an insulating layer) may be the same layer as at least one layer in the readout circuit 100. The same layer means that it can be formed by the same manufacturing process, or at least one layer of the sensing unit 100P and at least one layer in the readout circuit 100 may be formed by the same manufacturing process (for example, a lithography process or an etching process).

[0057] The substrate may be a hard substrate or a flexible substrate. The material of the substrate may include, for example, metal, plastic, glass, quartz, sapphire, ceramic, carbon fiber, other suitable substrate materials, or a combination of the foregoing, but the present disclosure is not limited thereto. In some embodiments, the electronic device may further include a plurality of light-emitting units, and the sensing unit 100P and the light-emitting unit may be disposed on the same or different substrates. For example, the light-emitting unit may include any type of display medium or light-emitting component (element), such as an organic light-emitting diode (OLED), a micro light-emitting diode (micro-LED), a sub-millimeter light-emitting diode (mini-LED), a quantum dot light-emitting diode (QLED), a nanowire light-emitting diode (nano wire LED) or a bar type light-emitting diode (bar type LED), but is not limited thereto. The electronic device may be an electronic device having an under-screen biometric characterization recognition function, such as a mobile phone, a tablet computer, etc. Furthermore, the sensing unit 100P may be used for a fingerprint sensor, an iris sensor, a retina sensor, a facial sensor, a vein sensor, a movement sensor, a gesture sensor, a proximity sensor or other suitable sensors, but the present disclosure is not limited thereto.

[0058] In the present embodiment, the switch circuit 110 is coupled between the sensing unit 100P and the capacitor 120. The first end of the capacitor 120 is coupled to the switch circuit 110 through the circuit node 101. The second end of the capacitor 120 is coupled to the constant voltage VA, and the range of the constant voltage VA is, for example, between 0 and 5V, but is not limited thereto. In some embodiments, the constant voltage VA can be a ground voltage, and in other embodiments, the constant voltage VA can be connected to a power supply device, but the present disclosure is not limited thereto. The amplifier circuit 130 is coupled between the circuit nodes 101 and 102. The current-to-voltage circuit 140 is coupled between the amplifier circuit 130 and the ground voltage VSS, and is coupled to the amplifier circuit 130 through the circuit node 102.

[0059] In the present embodiment, when the sensing unit 100P performs sensing, the sensing unit 100P may generate a current signal Is, and the switch circuit 110 may selectively provide the current signal Is to the capacitor 120, so that the capacitor 120 may store the current signal Is provided by the sensing unit 100P. In this regard, since the amount of electricity stored in the capacitor 120 corresponds to the current signal Is provided by the storage sensing unit 100P, the capacitor 120 may provide a corresponding voltage Vs at the circuit node 101, so that the amplifier circuit 130 may obtain a corresponding read current Iout according to the voltage Vs of the circuit node 101. Then, the current-to-voltage circuit 140 may receive the read current Iout through the circuit node 102, and convert the read current Iout into a read voltage Vout. The current-to-voltage circuit 140 may output the read voltage Vout through the circuit node 102. Therefore, since the readout circuit 100 and the sensing unit 100 of this embodiment can be set on the same substrate, and the readout circuit 100 can provide a readout signal in the form of a voltage to the back-end signal processing circuit, the readout circuit 100 of this embodiment can read the sensing unit 100P with lower or no noise sensing results.

[0060] Figure 2A FIG. 1 is a circuit diagram of a readout circuit according to a first embodiment of the present disclosure. Figure 2B For the purpose of disclosure Figure 2A Operation timing diagram of the readout circuit of the embodiment. Figure 2A as well as Figure 2B, the readout circuit 200 includes a switch circuit 210, a capacitor 220, an amplifier circuit 230 and a current-to-voltage circuit 240. The readout circuit 200 is used to read out the sensing result of the sensing unit 200P. The sensing unit 200P may be, for example, one or more sensing pixels in an electronic device. In the present embodiment, the switch circuit 210 includes a switch transistor Mro and a reset transistor Mrst. The first end of the switch transistor Mro is coupled to the sensing unit 200P. The second end of the switch transistor Mro is coupled to the circuit node 201. The control end of the switch transistor Mro receives the switching signal RO. The first end of the reset transistor Mrst is coupled to the first end of the switch transistor Mro. The second end of the reset transistor Mrst is coupled to the constant voltage VA. The control end of the reset transistor Mrst receives the reset signal RO_RST. The capacitor 202 is coupled to the second end of the switch transistor Mro through the circuit node 201. The amplifier circuit 230 includes a switch transistor Mamp. The control terminal of the switch transistor Mamp is coupled to the circuit node 201, the first terminal of the switch transistor Mamp is coupled to the constant voltage VB, and the second terminal of the switch transistor Mamp is coupled to the current-to-voltage circuit 240. In the present embodiment, the switch transistor Mro, the reset transistor Mrst, and the switch transistor Mamp may be low temperature polysilicon thin film transistors (LTPS TFT) or metal-oxide-semiconductor field-effect transistors (MOSFET), but the present disclosure is not limited thereto.

[0061] In this embodiment, the readout circuit 200 is reset first, and then the sensing result of the sensing unit 200P is read out. Figure 2BIn the timing, during period P21, the readout circuit 200 turns on the switch transistor Mro and the reset transistor Mrst simultaneously by switching the signal RO and the reset signal RO_RST, so that the potential of the circuit node 201 and the entire signal transmission path from the capacitor 220 to the sensing unit 200P can be reset to a constant voltage VA. In other embodiments, the potential of the circuit node 201 and the entire signal transmission path from the capacitor 220 to the sensing unit 200P can be close to the constant voltage VA. During period P22, the readout circuit 200 turns on the switch transistor Mro by switching the signal RO, and turns off the reset transistor Mrst by the reset signal RO_RST, so that the capacitor 220 stores the current signal Is provided by the sensing unit 200P, that is, the switch transistor Mro can control the current signal Is of the sensing unit 200P to the capacitor 220. During period P23, the readout circuit 200 turns off the switch transistor Mro and the reset transistor Mrst through the switching signal RO and the reset signal RO_RST, so that the circuit node 201 can have a voltage Vs corresponding to the amount of electricity stored in the capacitor 220 to turn on the switch transistor Mamp. In this regard, the switch transistor Mamp can provide a corresponding readout current Iout to the current-to-voltage circuit 240 through the constant voltage VB according to the voltage Vs of the circuit node 201. Then, the current-to-voltage circuit 240 can convert the readout current Iout into a readout voltage Vout, and then output the readout voltage Vout through the circuit node 202. Therefore, since the readout circuit 200 and the sensing unit 200P of this embodiment can be arranged on the same substrate, and the readout circuit 200 can provide a readout signal in the form of a voltage to the back-end signal processing circuit, the readout circuit 200 of this embodiment can read a lower or noise-free sensing result of the sensing unit 200P.

[0062] In one embodiment, Figure 2A The current-to-voltage circuit 240 may have, for example, Figure 2C The circuit architecture of the current-to-voltage circuit 240'. Figure 2C For the purpose of disclosure Figure 2A A circuit diagram of a current-to-voltage circuit according to an embodiment of the present invention. Figure 2C , Figure 2A The current-to-voltage circuit 240 may be, for example, Figure 2CThe current-to-voltage circuit 240' may include a resistor Res, and the resistor Res may be, for example, greater than or equal to 1M ohm and less than or equal to 10M ohm, but the present disclosure is not limited thereto. The first end of the resistor Res is coupled to the circuit node 202. The second end of the resistor Res is coupled to the ground voltage VSS. Therefore, when the switch transistor Mamp provides a corresponding read current Iout to the resistor Res via the constant voltage VB according to the voltage Vs of the circuit node 201, the read current Iout flows through the resistor Res, and the resistor Res generates a cross-voltage according to the read current Iout, so that the circuit node 202 generates a corresponding read voltage Vout.

[0063] In another embodiment, Figure 2A The current-to-voltage circuit 240 may have, for example, Figure 2D The circuit architecture of the current-to-voltage circuit 240 is shown. Figure 2D For the purpose of disclosure Figure 2A A circuit diagram of another current-to-voltage circuit of an embodiment. Figure 2D , the current-to-voltage circuit 240" includes a load transistor Mres, and the load transistor Mres can be, for example, a diode-connected load transistor. In some embodiments, the current-to-voltage circuit 240" can simultaneously include at least one load transistor Mres and at least one resistor Res, but the present disclosure is not limited to this. The first end of the load transistor Mres is coupled to the control end of the load transistor Mres. The first end of the load transistor Mres is coupled to the ground voltage VSS. The load transistor Mres can be equivalent to a load or a resistor. Therefore, when the switching transistor Mamp provides a corresponding read current Iout to the load transistor Mres via a constant voltage VB according to the voltage Vs of the circuit node 201, the read current Iout flows through the load transistor Mres, and the load transistor Mres generates a cross-voltage according to the read current Iout, so that the circuit node 202 generates a corresponding read voltage Vout.

[0064] Figure 3A FIG. 4 is a circuit diagram of a readout circuit according to a second embodiment of the present disclosure. Figure 3B For the purpose of disclosure Figure 3A Operation timing diagram of the readout circuit of the embodiment. Figure 3A as well as Figure 3B, the readout circuit 300 includes a switch circuit 310, a capacitor 320, an amplifier circuit 330, a current-to-voltage circuit 340 and a reset transistor Mrc. The readout circuit 300 is used to read out the sensing result of the sensing unit 300P. The sensing unit 300P may be, for example, one or more sensing pixels in an electronic device. In the present embodiment, the switch circuit 310 includes a switch transistor Mro. The first end of the switch transistor Mro is coupled to the sensing unit 200P. The second end of the switch transistor Mro is coupled to the circuit node 301. The control end of the switch transistor Mro receives the switching signal RO. The first end of the reset transistor Mrc is coupled to the first end of the capacitor 320. The second end of the reset transistor Mrc is coupled to the second end of the capacitor 320 and the constant voltage VA. The control end of the reset transistor Mrc receives the reset signal RO_RST_C. The capacitor 320 is coupled to the second end of the switch transistor Mro through the circuit node 301. The amplifier circuit 330 includes a switch transistor Mamp. The control end of the switch transistor Mamp is coupled to the circuit node 301, the first end of the switch transistor Mamp is coupled to the constant voltage VB, and the second end of the switch transistor Mamp is coupled to the current-to-voltage circuit 340. In this embodiment, the switch transistor Mro, the reset transistor Mrc, and the switch transistor Mamp may be low-temperature polysilicon thin-film transistors or metal oxide semiconductor field-effect transistors, but the disclosure is not limited thereto. In addition, the current-to-voltage circuit 340 of this embodiment may also have, for example, the above-mentioned Figure 2C The current-to-voltage circuit 240' or Figure 2D The circuit structure of the current-to-voltage circuit 240" will not be described in detail here.

[0065] In this embodiment, the readout circuit 300 will first perform a reset operation, and then read out the sensing result of the sensing unit 300P. Figure 3BIn the timing of period P31, the readout circuit 300 turns on the switch transistor Mro and the reset transistor Mrc simultaneously by switching the signal RO and the reset signal RO_RST_C, so that the potential of the circuit node 301 and the entire signal transmission path from the capacitor 320 to the sensing unit 300P can be reset to a constant voltage VA. In other embodiments, the potential of the circuit node 301 and the entire signal transmission path from the capacitor 320 to the sensing unit 300P can approach a constant voltage VA. During period P32, the readout circuit 300 turns on the switch transistor Mro by switching the signal RO, and the reset signal RO_RST_C turns off the reset transistor Mrc, so that the capacitor 320 stores the current signal Is provided by the sensing unit 300P. During period P33, the readout circuit 300 turns off the switch transistor Mro and the reset transistor Mrc by switching the signal RO and the reset signal RO_RST_C, so that the circuit node 301 can have a charge corresponding to the amount of electricity stored in the capacitor 320 to turn on the switch transistor Mamp. In this regard, the switch transistor Mamp can provide a corresponding read current Iout to the current-to-voltage circuit 340 via a constant voltage VB according to the voltage Vs of the circuit node 301. Then, the current-to-voltage circuit 340 can convert the read current Iout into a read voltage Vout, and then output the read voltage Vout through the circuit node 302. Therefore, since the read circuit 300 and the sensing unit 300P of the present embodiment can be disposed on the same substrate, and the read circuit 300 can provide a read signal in the form of a voltage to the back-end signal processing circuit, the read circuit 300 of the present embodiment can read a lower or noise-free sensing result of the sensing unit 300P.

[0066] Figure 4A FIG. 4 is a circuit diagram of a readout circuit according to a third embodiment of the present disclosure. Figure 4B For the purpose of disclosure Figure 4A Operation timing diagram of the readout circuit of the embodiment. Figure 4A as well as Figure 4B, the readout circuit 400 includes a switch circuit 410, a capacitor 420, an amplifier circuit 430, a current-to-voltage circuit 440, and a reset transistor Mrc. The readout circuit 400 is used to read out the sensing result of the sensing unit 400P. The sensing unit 400P may be, for example, one or more sensing pixels in an electronic device. In the present embodiment, the switch circuit 410 includes a switch transistor Mrc and a reset transistor Mrst. The first end of the switch transistor Mrc is coupled to the sensing unit 400P. The second end of the switch transistor Mrc is coupled to the circuit node 401. The control end of the switch transistor Mrc receives the switching signal RO. The first end of the reset transistor Mrst is coupled to the first end of the switch transistor Mrc. The second end of the reset transistor Mrst is coupled to the constant voltage VA. The control end of the reset transistor Mrst receives the reset signal RO_RST. The first end of the reset transistor Mrc is coupled to the first end of the capacitor 420. The second end of the reset transistor Mrc is coupled to the second end of the capacitor 420 and the constant voltage VA. The control end of the reset transistor Mrc receives the reset signal RO_RST_C. The capacitor 420 is coupled to the second end of the switch transistor Mro through the circuit node 401. The amplifier circuit 430 includes a switch transistor Mamp. The control end of the switch transistor Mamp is coupled to the circuit node 401, the first end of the switch transistor Mamp is coupled to the constant voltage VB, and the second end of the switch transistor Mamp is coupled to the current-to-voltage circuit 440. In the present embodiment, the switch transistor Mro, the reset transistor Mrc, and the switch transistor Mamp may be a low-temperature polysilicon thin-film transistor or a metal oxide semiconductor field effect transistor, but the present disclosure is not limited thereto. Furthermore, the current-to-voltage circuit 440 of the present embodiment may also have, for example, the above-mentioned Figure 2C The current-to-voltage circuit 240' or Figure 2D The circuit structure of the current-to-voltage circuit 240" will not be described in detail here.

[0067] In this embodiment, the readout circuit 400 will first perform a reset operation and then read out the sensing result of the sensing unit 400P. Figure 4BIn the timing, during period P41, the readout circuit 400 turns on the switch transistor Mro, the reset transistor Mrst and the reset transistor Mrc simultaneously by switching the signal RO, the reset signal RO_RST and the reset signal RO_RST_C, so that the potential of the circuit node 401 and the entire signal transmission path from the capacitor 420 to the sensing unit 400P can be reset to a constant voltage VA. During period P42, the readout circuit 400 turns on the switch transistor Mro by switching the signal RO, and the reset signals RO_RST and RO_RST_C turn off the reset transistor Mrst and the reset transistor Mrc, so that the capacitor 420 stores the current signal Is provided by the sensing unit 400P, wherein the time length of period P42 can be greater than twice the time length of period P41. During period P43, the readout circuit 400 turns off the switch transistor Mro, the reset transistor Mrst and the reset transistor Mrc through the switching signal RO, the reset signal RO_RST and the reset signal RO_RST_C, so that the circuit node 401 can have the amount of electricity corresponding to the amount of electricity stored in the capacitor 420, so as to turn on the switch transistor Mamp. In this regard, the switch transistor Mamp can provide the corresponding readout current Iout to the current-to-voltage circuit 440 via the constant voltage VB according to the voltage Vs of the circuit node 401. Then, the current-to-voltage circuit 440 can convert the readout current Iout into a readout voltage Vout, and then output the readout voltage Vout through the circuit node 402. Therefore, the readout circuit 400 of this embodiment can reduce the power consumption of providing a given voltage VA, and can provide a readout signal 400P in the form of a voltage to the back-end signal processing circuit, so as to obtain a lower or noise-free sensing result of the sensing unit 400P.

[0068] However, Figure 4A The switch transistor Mro, the reset transistor Mrst and the reset transistor Mrc are not limited to Figure 4B operation timing. Figure 4C For the purpose of disclosure Figure 4A Another operation timing diagram of the readout circuit of the embodiment. Figure 4C In one embodiment, the reset transistor Mrst and the reset transistor Mrc can be turned on at the same time, and the reset transistor Mrst and the reset transistor Mrc and the switch transistor Mro are turned on at different times to reset the potential of the circuit node 401 and the entire signal transmission path from the capacitor 420 to the sensing unit 400P. Figure 4CIn the timing of period P41', the readout circuit 400 turns on the reset transistor Mrst and the reset transistor Mrc simultaneously through the reset signal RO_RST and the reset signal RO_RST_C, and turns off the switch transistor Mro through the switching signal RO, so that the potential of the signal transmission path from the sensing unit 400 to the first end of the switch transistor Mro, the circuit node 401, and the signal transmission path from the capacitor 420 to the second end of the switch transistor Mro can be reset to a constant voltage VA respectively. In the period P42', the readout circuit 400 turns off the reset transistor Mrc and the reset transistor Mrst simultaneously through the reset signal RO_RST and the reset signal RO_RST_C, and turns on the switch transistor Mro through the switching signal RO, so that the capacitor 420 stores the current signal Is provided by the sensing unit 400P. During the period P43', the readout circuit 400 turns off the switch transistor Mro, the reset transistor Mrst and the reset transistor Mrc by the switching signal RO, the reset signal RO_RST and the reset signal RO_RST_C, so that the circuit node 401 can have the electric charge corresponding to the electric charge stored in the capacitor 420, so as to turn on the switch transistor Mamp. In this regard, the switch transistor Mamp can provide the corresponding readout current Iout to the current-to-voltage circuit 440 through the constant voltage VB according to the voltage Vs of the circuit node 401. Then, the current-to-voltage circuit 440 can convert the readout current Iout into the readout voltage Vout, and then output the readout voltage Vout through the circuit node 402. Therefore, the readout circuit 400 of the present embodiment can read out a lower or noise-free readout current Iout, and can provide the readout result of the sensing unit 400P in the form of voltage to the back-end signal processing circuit. In addition, in another embodiment, the reset transistor Mrc and the reset transistor Mrst can also partially overlap or not overlap at all during the opening period of the period P41', and the present disclosure is not limited thereto.

[0069] Figure 4D For the purpose of disclosure Figure 4A Another operation timing diagram of the readout circuit of the embodiment. Figure 4D In one embodiment, the reset transistor Mrst and the reset transistor Mrc can be turned on at different times to reset the potential of the circuit node 401 and the signal transmission path from the capacitor 420 to the sensing unit 400P. Figure 4DIn the timing, during period P41", the readout circuit 400 simultaneously turns off the switch transistor Mro and the reset transistor Mrc by switching the signal RO and the reset signal RO_RST_C, and turns on the reset transistor Mrst by the reset signal RO_RST, so that the potential of the signal transmission path from the sensing unit 400P to the first end of the switch transistor Mro can be reset to the constant voltage VA first. During period P42", the readout circuit 400 simultaneously turns on the switch transistor Mro and the reset transistor Mrc by switching the signal RO and the reset signal RO_RST_C, and turns off the reset transistor Mrst by the reset signal RO_RST, so that the potential of the signal transmission path from the circuit node 401 and the first end of the switch transistor Mro to the capacitor 420 can then be reset to the constant voltage VA.

[0070] During period P43″, the readout circuit 400 turns on the switch transistor Mro by switching signal RO, and turns off the reset transistor Mrst and the reset transistor Mrc by resetting signal RO_RST and reset signal RO_RST_C, so that the capacitor 420 stores the current signal Is provided by the sensing unit 400P. During period P44″, the readout circuit 400 turns off the switch transistor Mro, the reset transistor Mrst and the reset transistor Mrc by switching signal RO, reset signal RO_RST and reset signal RO_RST_C, so that the circuit node 401 can have the amount of electricity corresponding to that stored in the capacitor 420, so as to turn on the switch transistor Mamp. In this regard, the switch transistor Mamp can provide a corresponding readout current Iout to the current-to-voltage circuit 440 via a constant voltage VB according to the voltage Vs of the circuit node 401. Then, the current-to-voltage circuit 440 can convert the readout current Iout into a readout voltage Vout, and then output the readout voltage Vout through the circuit node 402. Therefore, the readout circuit 400 of the present embodiment can read a lower or noise-free readout current Iout, and can provide a readout result of the sensing unit 400P in the form of a voltage to the back-end signal processing circuit. In addition, the readout circuit 400 can also first turn on the reset transistor Mrc and turn off the reset transistor Mrst during the period P41", and then turn on the reset transistor Mrst and turn off the reset transistor Mrc during the period P42".

[0071] Figure 5 FIG. 1 is a top view of an electronic device according to an embodiment of the present disclosure. Figure 5 The electronic device 500 includes an array substrate 510 , a row driver 520 , and a column driver 530 . The row driver 520 is disposed on one side of the array substrate 510 , and the row driver 530 is disposed on the other side of the array substrate 510 . Figure 5The configuration positions of the column driver 520 and the row driver 530 are only examples and are not limited to this. The material of the array substrate 510 may be the same as or similar to the material of the above-mentioned substrate, and will not be repeated here. In the present embodiment, the array substrate 510 includes a plurality of sensing units P(1,1)~P(N,M) arranged in an array, where N and M are positive integers greater than 1. The column driver 520 couples the sensing units P(1,1)~P(N,M) through a plurality of column signal lines C_1~C_M, and the row driver 530 couples the sensing units P(1,1)~P(N,M) through a plurality of row signal lines D_1~D_N. The plurality of column signal lines C_1~C_M and the plurality of row signal lines D_1~D_N may be, for example, scan lines or data lines, respectively, but the present disclosure is not limited to this. In this embodiment, the row driver 530 includes a plurality of readout circuits 530_1 to 530_N, and the readout circuits 530_1 to 530_N may each have the above Figure 1 , Figure 2A , Figure 3A or Figure 4A In this embodiment, the sensing units P(1,1)-P(N,M) are driven by the column driver 520 through a plurality of column signal lines C_1-C_M in a time-sharing manner, so that the readout circuits 530_1-530_N can perform the above-mentioned readout operations on the sensing units P(1,1)-P(N,M) in a column-by-column manner. Figure 2B , Figure 3B , Figure 4B or Figure 4C Therefore, the readout circuits 530_1 to 530_N can effectively reset the potentials on the column signal lines D_1 to D_N through the execution of the reset operation to reduce the noise of each readout signal of the sensing units P(1,1) to P(N,M).

[0072] Fig. 6A FIG. 4 is a circuit diagram of a readout circuit according to a fourth embodiment of the present disclosure. Figure 6B For the purpose of disclosure Fig. 6A Operation timing diagram of the readout circuit of the embodiment. Fig. 6A as well as Figure 6B, the readout circuit 600 includes a reset transistor Mrst, a switch circuit 610, a switch circuit 650, a capacitor 620, a capacitor 660, an amplifier circuit 630, an amplifier circuit 670, a current-to-voltage circuit 640, a current-to-voltage circuit 680, a reset transistor Mrc1, and a reset transistor Mrc2. In some other embodiments, the reset transistor Mrc1 and the reset transistor Mrc2 may also be selectively not set. In this embodiment, the readout circuit 600 is used to read out the sensing result of the sensing unit 600P, and also read out the background signal of the sensing unit 600P when no sensing is performed. The sensing unit 600P may be, for example, one or more sensing pixels in the panel of an electronic device. In this embodiment, the switch circuit 610 includes a switch transistor Mro1. The first end of the switch transistor Mro1 is coupled to the sensing unit 600P. The second end of the switch transistor Mro1 is coupled to the circuit node 601. The control end of the switch transistor Mro1 receives the switching signal RO_1. The first end of the reset transistor Mrst is coupled to the first end of the switch transistor Mro1 and the sensing unit 600P. The second end of the reset transistor Mrst is coupled to the constant voltage VA. The control end of the reset transistor Mrst receives the reset signal RO_RST. The first end of the reset transistor Mrc1 is coupled to the first end of the capacitor 620. The second end of the reset transistor Mrc1 is coupled to the second end of the capacitor 620 and the constant voltage VA. The control end of the reset transistor Mrc1 receives the reset signal RO_RST_C_1. The capacitor 620 is coupled to the second end of the switch transistor Mro1 through the circuit node 601. The amplifier circuit 630 includes a switch transistor Mamp1. The control end of the switch transistor Mamp1 is coupled to the circuit node 601, the first end of the switch transistor Mamp1 is coupled to the constant voltage VB, and the second end of the switch transistor Mamp1 is coupled to the current-to-voltage circuit 640.

[0073] The switch circuit 650 includes a reset transistor Mro2. The first end of the switch transistor Mro2 is coupled to the sensing unit 600P, the first end of the reset transistor Mrst and the switch circuit 610. The second end of the switch transistor Mro2 is coupled to the circuit node 602. The control end of the switch transistor Mro2 receives the switching signal RO_2. The first end of the reset transistor Mrst is coupled to the first end of the switch transistor Mro2. The first end of the reset transistor Mrc2 is coupled to the first end of the capacitor 660. The second end of the reset transistor Mrc2 is coupled to the second end of the capacitor 660 and the constant voltage VA. The control end of the reset transistor Mrc2 receives the reset signal RO_RST_C_2. The capacitor 660 is coupled to the second end of the switch transistor Mro2 through the circuit node 603. The amplifier circuit 670 includes a switch transistor Mamp2. The control end of the switch transistor Mamp2 is coupled to the circuit node 604, the first end of the switch transistor Mamp2 is coupled to the constant voltage VB, and the second end of the switch transistor Mamp2 is coupled to the current-to-voltage circuit 680.

[0074] In this embodiment, the switch transistor Mro1, the switch transistor Mro2, the reset transistor Mrst, the reset transistor Mrc1, the reset transistor Mrc2, the switch transistor Mamp1 and the switch transistor Mamp2 may be low temperature polysilicon thin film transistors or metal oxide semiconductor field effect transistors, but the present disclosure is not limited thereto. In addition, the current-to-voltage circuit 640 and the current-to-voltage circuit 680 of this embodiment may also have the above-mentioned Figure 2C The current-to-voltage circuit 240' or Figure 2D The circuit structure of the current-to-voltage circuit 240" will not be described in detail here.

[0075] In this embodiment, the readout circuit 600 may first read out the background noise signal of the sensing unit 600P when no sensing is performed, and then read out the image sensing result of the sensing unit 600P, but the present disclosure is not limited thereto. Figure 6BIn the timing of period P61, the readout circuit 600 turns on the switch transistor Mro1, the reset transistor Mrst and the reset transistor Mrc1 simultaneously by switching the signal RO_1, the reset signal RO_RST and the reset signal RO_RST_C_1, so that the potential of the circuit node 601 and the entire signal transmission path from the capacitor 620 to the sensing unit 600P can be reset to a constant voltage VA. In some embodiments, the potential of the circuit node 601 and the entire signal transmission path from the capacitor 620 to the sensing unit 600P can be reset to approach the constant voltage VA. During period P62, the sensing unit 600P is not sensed. The readout circuit 600 turns on the switch transistor Mro1 by switching the signal RO_1, and turns off the reset transistor Mrst and the reset transistor Mrc1 by the reset signal RO_RST and the reset signal RO_RST_C_1, so that the capacitor 620 stores the current signal In provided by the sensing unit 600P without a sensing result, wherein this current signal In is the background signal. During period P63, the readout circuit 600 turns off the switch transistor Mro1, the reset transistor Mrst and the reset transistor Mrc1 through the switching signal RO_1, the reset signal RO_RST_1 and the reset signal RO_RST_C_1, so that the circuit node 601 can have the charge corresponding to the charge stored in the capacitor 620 to turn on the switch transistor Mamp1. In this regard, the switch transistor Mamp1 can provide the corresponding readout current Iout1 to the current-to-voltage circuit 640 through the constant voltage VB according to the voltage Vn of the circuit node 601. Then, the current-to-voltage circuit 640 can convert the readout current Iout1 into a readout voltage Vout1, and then output the readout voltage Vout1 through the circuit node 602. Therefore, the readout circuit 600 can effectively read the background signal without the sensing result provided by the sensing unit 600P. Next, during period P64, the readout circuit 600 turns on the switch transistor Mro2, the reset transistor Mrst and the reset transistor Mrc2 simultaneously by switching the signal RO_2, the reset signal RO_RST and the reset signal RO_RST_C_2, so that the potential of the circuit node 603 and the entire signal transmission path from the capacitor 660 to the sensing unit 600P can be reset to a constant voltage VA. In some embodiments, the potential of the circuit node 603 and the entire signal transmission path from the capacitor 660 to the sensing unit 600P can be reset to approach the constant voltage VA. During period P65, the sensing unit 600P performs sensing. The readout circuit 600 turns on the switch transistor Mro2 by switching the signal RO_2, and the reset signal RO_RST and the reset signal RO_RST_C_2 turn off the reset transistor Mrst and the reset transistor Mrc2, so that the capacitor 660 stores the sensing unit 600P to provide a current signal Is with a sensing result.During period P66, the readout circuit 600 turns off the switch transistor Mro2, the reset transistor Mrst and the reset transistor Mrc2 by switching the signal RO_2, the reset signal RO_RST and the reset signal RO_RST_C_2, so that the circuit node 603 can have the charge corresponding to the charge stored in the capacitor 660 to turn on the switch transistor Mamp2. In this regard, the switch transistor Mamp2 can provide the corresponding readout current Iout2 to the current-to-voltage circuit 640 via the constant voltage VB according to the voltage Vs of the circuit node 603. Then, the current-to-voltage circuit 640 can convert the readout current Iout2 into a readout voltage Vout2, and then output the readout voltage Vout2 through the circuit node 604. Therefore, the readout circuit 600 can effectively read out the sensing result provided by the sensing unit 600P. In other embodiments, the readout circuit 600 can also first read out the sensing result of the sensing unit 600P, and then read out the background signal of the sensing unit 600P when no sensing is performed.

[0076] Therefore, the readout circuit 600 of this embodiment can read out the sensing result and the background signal of the same sensing unit 600P at different times, and after the back-end processing circuit subtracts the readout voltage Vout2 from the readout voltage Vout1, the readout voltage without background noise can be obtained. In this regard, in one embodiment, the back-end processing circuit can include, for example, Figure 6C Differential amplifier circuit. Figure 6C For the purpose of disclosure Fig. 6A A circuit diagram of a differential amplifier circuit according to an embodiment. Figure 6C , the differential amplifier circuit 690 includes an amplifier 691 and resistors R1 to R4. In the present embodiment, one end of the resistor R1 receives the read voltage Vout1, and the other end of the resistor R1 is coupled to the inverting input terminal of the amplifier 691. One end of the resistor R2 is coupled to the inverting input terminal of the amplifier 691, and the other end of the resistor R2 is coupled to the output terminal of the amplifier 691. One end of the resistor R3 receives the read voltage Vout2, and the other end of the resistor R3 is coupled to the non-inverting input terminal of the amplifier 691. One end of the resistor R4 is coupled to the non-inverting input terminal of the amplifier 691, and the other end of the resistor R4 is coupled to the ground terminal. In the present embodiment, the differential amplifier circuit 690 can satisfy the derivation of the following relations (1) to (4), so that the output terminal of the amplifier 691 can output the read voltage Vout3 after the background noise is removed after the read voltage Vout2 is subtracted from the read voltage Vout1. In the following relations (1) to (4), Ra is the resistance value of the resistor R1. Rb is the resistance value of the resistor R2, Rc is the resistance value of the resistor R3, and Rd is the resistance value of the resistor R4.

[0077]

[0078] Ra=Rc……………Relationship (2)

[0079] Rb=Rd………………Relationship (3)

[0080]

[0081] In this embodiment, Figure 6C The differential amplifier circuit can be directly fabricated on the array substrate of the sensing unit 100P, or disposed on another circuit board to couple to the readout circuit 600 fabricated on the array substrate of the sensing unit 100P. In addition, the method of obtaining the difference between the readout voltage Vout1 and the readout voltage Vout2 disclosed in the present invention is not limited to Figure 6C In one embodiment, the circuit node 602 and the circuit node 604 may also be coupled to another switching circuit or a multiplexer, and a single circuit path may be used to time-share output the read voltage Vout1 and the read voltage Vout2 to a back-end processing circuit disposed on another circuit board for performing a difference operation.

[0082] It is worth noting that the above Figure 5 Each of the readout circuits 530_1 to 530_N of the row driver 530 of the electronic device 500 of the embodiment may also have a Fig. 6A That is, Figure 5 The readout circuits 530_1 to 530_N can perform the above-mentioned readout operations on each column of the sensing units P(1,1) to P(N,M) one by one. Figure 6B of Figure 6B The operation timing is used to obtain the readout voltage with background noise removed for each of the sensing units P(1,1)-P(N,M).

[0083] Figure 7 FIG. 7 is a top view of an electronic device 700 according to another embodiment of the present disclosure. Figure 7, the electronic device 700 includes an array substrate 710, a column driver 720 and a row driver 730. The column driver 720 is configured on one side of the array substrate 710, and the row driver 730 is configured on the other side of the array substrate 710. The material of the array substrate 710 may be the same as or similar to the material of the above-mentioned substrate, and will not be repeated here. In this another embodiment, the array substrate 710 includes a plurality of sensing units P(1,0)'~P(N,M)' arranged in an array, where N and M are positive integers greater than 1. The column driver 720 couples the sensing units P(1,0)'~P(N,M)' through a plurality of column signal lines C_0~C_M, and the row driver 730 couples the sensing units P(0,1)'~P(N,M)' through a plurality of row signal lines D_1~D_N. In this embodiment, the row driver 730 includes a plurality of readout circuits 730_1~730_N, and the readout circuits 730_1~730_N may respectively have the above-mentioned Fig. 6A The circuit architecture of the readout circuit 600. In this another embodiment, the sensing units P(1,0)'~P(N,0)' in the 0th row can be respectively used as reference sensing units for each column. Moreover, these sensing units P(1,0)'~P(N,0)' can be, for example, located on one side of the active area (Active area) of the electronic device panel, and can be respectively shielded by a frame, shielded by being coated with a metal layer, or not coupled to a photosensitive unit to provide a background signal that is closest to the background value. Specifically, before the array substrate 710 performs sensing, the readout circuits 730_1~730_N can be respectively performed as described above. Figure 6B The operation timing of the period P61-P63 is used to obtain the background signal of each of the reference sensing units P(1,0)'-P(N,0)' in the 0th row. Then, when the array substrate 710 performs sensing, each of the readout circuits 730_1-730_N can correspond to each column of the sensing units P(1,1)'-P(N,M)' and repeat the above-mentioned steps. Figure 6B The operation timing of the period P64 to P66 is used to obtain the readout voltage of each of the sensing units P(1,1)' to P(N,M)' without removing the background noise. Therefore, the back-end processing circuit of the electronic device panel 700 can subtract the readout voltage of each of the sensing units P(1,1)' to P(N,M)' without removing the background noise from the background signal of each of the sensing units P(1,0)' to P(N,0)' in the corresponding column to obtain the readout voltage of each of the sensing units P(1,1)' to P(N,M)' with the background noise removed. In addition, the array substrate 710 disclosed in the present invention may also have multiple rows of reference sensing units, and may be configured in other row and column positions in the array substrate 710, and is not limited to Figure 7In the present embodiment, since the sensing units P(1,0)'-P(N,0)' in the 0th row can be respectively used as reference sensing units of each column, the capacitor 620 and the capacitor 660 in the readout circuit 600 can have different capacitance values. For example, the capacitor 620 can store the background signal provided by the sensing units P(1,0)'-P(N,0)', and the capacitor 660 can store the current signal of each of the sensing units P(1,1)'-P(N,M)' without removing the background noise. Then, the capacitance value of the capacitor 620 can be greater than the capacitance value of the capacitor 660, or the capacitance value of the capacitor 620 can be greater than or equal to M times the capacitance value of the capacitor 660.

[0084] In summary, the electronic device disclosed herein has a readout circuit that may include one or more reset transistors, so that the potential of the signal transmission path of the readout circuit can be consistently reset to a fixed potential before the readout operation is performed, thereby effectively reducing the noise of the readout signal output by the readout circuit. In some embodiments of the present disclosure, the sensing unit and the readout circuit of the present disclosure are arranged on the same substrate or formed by the same process, and the sensing result of the sensing unit is output in the form of a voltage to obtain a lower noise or more accurate sensing result of the sensing unit. In other embodiments of the present disclosure, the readout circuit of the present disclosure may additionally read out a background signal to produce a readout signal without background noise in combination with an operation circuit that can perform a difference operation.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device having a readout circuit, characterized in that: The readout circuit comprises: A first switch circuit receives a first current signal; a first amplifier circuit coupled to the first switch circuit via a first circuit node and outputting a first readout current according to a first voltage at the first circuit node; as well as a first current-to-voltage circuit coupled to the first amplifier circuit and converting the first read current into a first read voltage, wherein the first current-to-voltage circuit outputs the first read voltage via a second circuit node between the first current-to-voltage circuit and the first amplifier circuit, The readout circuit further comprises: A first capacitor, wherein a first end of the first capacitor is coupled to the first switch circuit via the first circuit node, and a second end of the first capacitor is coupled to a first constant voltage, wherein the first capacitor stores the first current signal, and the first circuit node provides the first voltage according to the first current signal.

2. The readout circuit according to claim 1, characterized in that The first switch circuit includes a first switch transistor, wherein a first terminal of the first switch transistor receives the first current signal, and a second terminal of the first switch transistor is coupled to the first terminal of the first capacitor through the first circuit node.

3. The readout circuit according to claim 2, characterized in that: The first switch circuit further includes a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the first constant voltage, and a second terminal of the first reset transistor is coupled to the first terminal of the first switch transistor.

4. The readout circuit according to claim 1, characterized in that: Also includes: A second reset transistor, wherein a first terminal of the second reset transistor is coupled to the first terminal of the first capacitor, and a second terminal of the second reset transistor is coupled to the second terminal of the first capacitor.

5. The readout circuit according to claim 1, characterized in that: The first amplifying circuit comprises: A second switch transistor, wherein a control terminal of the second switch transistor is coupled to the first circuit node, a first terminal of the second switch transistor is coupled to a second constant voltage, and a second terminal of the second switch transistor is coupled to the first current-to-voltage circuit.

6. The readout circuit according to claim 1, characterized in that: The first current-to-voltage circuit includes a load transistor or a resistor.

7. The readout circuit according to claim 1, characterized in that: Also includes: A second switch circuit, receiving a second current signal, wherein the second switch circuit is coupled to the first switch circuit; a second capacitor, wherein a first end of the second capacitor is coupled to the second switch circuit via a third circuit node, and a second end of the second capacitor is coupled to the first constant voltage; as well as The second amplifier circuit is coupled to the third circuit node and outputs a second read current according to a second voltage of the third circuit node.

8. The readout circuit according to claim 7, characterized in that: The second current signal is a background signal.

9. The readout circuit according to claim 8, characterized in that: Also includes: A second current-to-voltage circuit is coupled between the second amplifier circuit and the ground voltage, and converts the second read current into a second read voltage, wherein the second current-to-voltage circuit outputs the second read voltage via a fourth circuit node between the second current-to-voltage circuit and the second amplifier circuit, and the difference between the first read voltage and the second read voltage is a third read voltage with background noise removed.

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