Wafer bonding structure and forming method thereof

Abstract

A wafer bonding structure and a method for forming the same, the method comprising a wafer bonding step, a through silicon via forming step and a bonding pad forming step. In the wafer bonding step, the wafers each have a bonding surface, and correspond to and bond to each other through the bonding surface. In the through silicon via forming step, a through silicon via structure is formed on at least one side of a bonding ring structure of one of the wafers, a conductive filler is disposed in the through silicon via structure, and the through silicon via structure overlaps a portion of the bonding ring structure of one of the wafers and a bonding ring structure of the other wafer. In the bonding pad forming step, a bonding pad is formed on an outer surface to form a wafer bonding structure, and the outer surface is a bonding surface relative to the wafer having the through silicon via structure. This helps to improve the bonding strength and conductivity between wafers.

Description

Technical Field

[0001] The present disclosure relates to a wafer bonding structure and a method for forming the same. Background Art

[0002] Today, wafer bonding structures are a mature technology for wafer-level packaging. For wafer bonding structures in three-dimensional wafer-level packaging, they can be used to increase functionality and solve the bottleneck of wire bonding processes.

[0003] However, oxides are easily formed on the bonding surface of the wafer to increase the resistance of the wafer bonding structure. Furthermore, the wafer bonding structure is prone to edge chipping and water vapor penetration during the dicing process. Therefore, for the wafer bonding structure, reducing the formation of oxides on the bonding surface and avoiding edge chipping and water vapor penetration are issues that must be addressed. Summary of the invention

[0004] The present disclosure provides a wafer bonding structure and a method for forming the same, which is connected to and overlapped with a bonding ring structure through a through silicon via structure to improve the mechanical strength and conductivity of the wafer bonding structure.

[0005] According to an embodiment of the present disclosure, a method for forming a wafer bonding structure is provided, comprising a wafer bonding step, a through silicon via forming step, and a bonding pad forming step. In the wafer bonding step, at least two wafers each have a bonding surface, and correspond to and bond to each other through the bonding surface. In the through silicon via forming step, a through silicon via structure is formed on at least one side of a bonding ring structure of one of the wafers, a conductive filler is disposed in the through silicon via structure, and the through silicon via structure overlaps at least one side of the bonding ring structure of one of the wafers and a portion of a bonding ring structure of the other wafer. In the bonding pad forming step, a bonding pad is formed on an outer surface to form a wafer bonding structure, and the outer surface is a bonding surface relative to the wafer having the through silicon via structure. A range in which the through silicon via structure overlaps at least one side of the bonding ring structure of one of the wafers is greater than or equal to 0.05 microns.

[0006] The method for forming the wafer bonding structure according to the above-mentioned embodiment may further include a surface treatment step, wherein the bonding surface of the wafer is subjected to a surface treatment before the wafer bonding step.

[0007] According to the method for forming a wafer bonding structure of the embodiment described in the previous paragraph, the wafer may be exposed to a nitrogen plasma or an oxygen plasma during the wafer bonding step.

[0008] According to the method for forming a wafer bonding structure of the embodiment described in the previous paragraph, in the wafer bonding step, the wafers may be bonded at 250° C. to 350° C. for 1 hour to 3 hours.

[0009] According to the method for forming a wafer bonding structure of the embodiment described in the previous paragraph, the bonding ring structures can be aligned with each other during the wafer bonding step.

[0010] According to the method for forming a wafer bonding structure of the embodiment described in the previous paragraph, an error value of the wafer bonding step can be less than 300 nanometers.

[0011] According to an embodiment of the present disclosure, a wafer bonding structure is provided, comprising at least two wafers, a through silicon via structure, a conductive filler and a bonding pad. The wafers are bonded to each other, the wafers have a bonding surface, and the wafers include a bonding ring structure, wherein the bonding ring structure is disposed in the wafer, one end of the bonding ring structure is connected to the bonding surface, and the other end of the bonding ring structure is connected to an outer surface of the wafer. The through silicon via structure is disposed from the outer surface of one of the wafers to the bonding surface, wherein the through silicon via structure is connected and overlaps at least one side of the bonding ring structure of one of the wafers and a portion of the bonding ring structure of the other wafer. The conductive filler is disposed in the through silicon via structure. The bonding pad is disposed on the outer surface of the wafer including the through silicon via structure. A range in which the through silicon via structure overlaps at least one side of the bonding ring structure of one of the wafers is greater than or equal to 0.05 microns.

[0012] According to the wafer bonding structure of the embodiment described in the previous paragraph, the bonding ring structure may include a first metal layer, at least one metal layer and at least two pin groups. The first metal layer is connected to the bonding surface, and the metal layer is disposed between the outer surface and the first metal layer. One of the pin groups connects the first metal layer and the metal layer, and the other of the pin groups connects the metal layer and the outer surface, wherein the pin group includes at least three pins.

[0013] According to the wafer bonding structure of the embodiment described in the previous paragraph, a range in which the TSV structure overlaps the first metal layer may be greater than or equal to 0.05 micrometers.

[0014] According to the wafer bonding structure of the embodiment described in the previous paragraph, a range in which the TSV structure overlaps the metal layer may be greater than or equal to 0.02 micrometers.

[0015] According to the wafer bonding structure of the embodiment described in the previous paragraph, a width of the pins may be greater than or equal to 0.025 microns.

[0016] According to the wafer bonding structure of the embodiment described in the previous paragraph, the first metal layer and the metal layer can be made of copper.

[0017] According to the wafer bonding structure of the embodiment described in the previous paragraph, a width of the first metal layer may be greater than a width of the metal layer.

[0018] According to the wafer bonding structure of the embodiment described in the previous paragraph, a depth of the TSV structure may be 2 micrometers to 20 micrometers.

[0019] According to the wafer bonding structure of the embodiment described in the previous paragraph, a width of the TSV structure may be 0.1 micrometer to 10 micrometers.

[0020] According to the wafer bonding structure of the above-mentioned embodiment, the conductive filler can be made of copper.

[0021] According to the wafer bonding structure of the embodiment described in the previous paragraph, the bonding pad can be made of aluminum. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flowchart showing a method for forming a wafer bonding structure according to an embodiment of the present invention;

[0023] Figure 2 Show Figure 1 A schematic diagram of a surface treatment step in an embodiment;

[0024] Figure 3 Show Figure 1 A schematic diagram of a wafer bonding step in an embodiment;

[0025] Figure 4 Show Figure 1 A schematic diagram of a step of forming a through silicon via in an embodiment; and

[0026] Figure 5 Show Figure 1 A schematic diagram of a step of forming a bonding pad according to an embodiment.

[0027] Description of reference numerals:

[0028] 100: Method for forming wafer bonding structure

[0029] S101: Surface treatment step

[0030] S102: Wafer bonding step

[0031] S103: Step of forming a through silicon via

[0032] S104: Forming bonding pads Step 200: Wafer bonding structure

[0033] 21,22: Wafer

[0034] 21a, 22a: Joint surface

[0035] 210,220: Engagement ring structure

[0036] 211,221: First metal layer

[0037] 212,213,214,222,223,224: Metal layer

[0038] 215,225: Pin group

[0039] 230: Silicon through hole structure

[0040] 240: Conductive filler

[0041] 250: Bonding pad

[0042] 260: Oxide layer DETAILED DESCRIPTION

[0043] Figure 1 FIG. 1 is a flow chart showing the steps of a method 100 for forming a wafer bonding structure according to an embodiment of the present invention. Figure 1 It can be known that the method 100 for forming a wafer bonding structure includes a surface treatment step S101 , a wafer bonding step S102 , a through silicon via forming step S103 , and a bonding pad forming step S104 .

[0044] Figure 2 Show Figure 1 Schematic diagram of the surface treatment step S101 in the embodiment. Figure 1 and Figure 2 It can be known that each of the at least two wafers has a bonding surface, and a bonding surface of each of the at least two wafers undergoes a surface treatment before the wafer bonding step S102 . Figure 1 In the embodiment, the number of wafers is two, namely wafers 21 and 22, and wafer 21 has a bonding surface 21a, and wafer 22 has a bonding surface 22a, but the invention is not limited thereto. Specifically, the surface treatment step S101 is to densify silicon oxide (not shown) on the bonding surfaces 21a and 22a, thereby avoiding holes on the bonding surfaces 21a and 22a. Furthermore, the roughness of the bonding surfaces 21a and 22a is less than 1.5 nanometers.

[0045] Figure 3 Show Figure 1 Schematic diagram of wafer bonding step S102 in an embodiment. Figure 1 and Figure 3 It can be seen that the wafers 21 and 22 correspond to and are bonded to each other through their bonding surfaces 21a and 22a. Each wafer includes a bonding ring structure. Specifically, Figure 1 In the embodiment, the wafer 21 includes a bonding ring structure 210, the wafer 22 includes a bonding ring structure 220, and the bonding ring structures 210 and 220 are aligned with each other. In addition, an error value of the wafer bonding step S102 can be less than 300 nanometers, but is not limited thereto. In detail, the error value can be confirmed by a wafer test structure.

[0046] Furthermore, in the wafer bonding step S102 , the wafers 21 and 22 are exposed to a nitrogen plasma or an oxygen plasma, and the wafers 21 and 22 are bonded at 250° C. to 350° C. for 1 hour to 3 hours, thereby helping to enhance the bonding strength of the wafers 21 and 22 .

[0047] Figure 4 Show Figure 1 Schematic diagram of step S103 of forming a through silicon via in an embodiment. Figure 1 and Figure 4 It can be seen that after an oxide layer 260 is formed, a TSV structure 230 is formed on at least one side of the bonding ring structure of one of the wafers 21 and 22 , a conductive filler 240 is disposed in the TSV structure 230 , and the TSV structure 230 overlaps one side of the bonding ring structure of one of the wafers 21 and 22 . Figure 1 In the embodiment, the TSV structure 230 is formed on two sides of the bonding ring structure 210 of the wafer 21, and the TSV structure 230 overlaps the two sides of the bonding ring structure 210 of the wafer 21, but the present invention is not limited thereto. It is worth mentioning that the TSV structure 230 overlaps the two sides of the bonding ring structure 210 of the wafer 21, which helps to improve the mechanical strength of the wafer bonding structure 200 and the protection capability of preventing water vapor from penetrating.

[0048] Furthermore, the TSV structure 230 overlaps a portion of the bonding ring structure 220 of the wafer 22. Specifically, the TSV structure 230 is formed from an outer surface (not shown) to the bonding surface 21a of the wafer 21. Thus, the TSV structure 230 with the conductive filler 240 helps to improve the connection strength between the wafers 21 and 22. In addition, the TSV structure 230 with the conductive filler 240 can reduce the resistance between the wafers 21 and 22.

[0049] Specifically, the conductive filler 240 is disposed in the TSV structure 230 by a sputtering and electroplating process, and the outer surface of the wafer 21 is subjected to a chemical mechanical polishing process to avoid unevenness of the outer surface of the wafer 21 .

[0050] Figure 5 Show Figure 1 A schematic diagram of step S104 of forming a bonding pad in an embodiment. Figure 1 and Figure 5 It can be seen that a bonding pad 250 is formed on the outer surface to form the wafer bonding structure 200 , and the outer surface is the bonding surface relative to the wafer having the TSV structure 230 . Figure 1 In one embodiment, after the oxide layer 260 is formed, the bonding pads 250 are formed on the outer surface of the wafer 21 , and the bonding pads 250 are used in a wire bonding process.

[0051] The method for forming a wafer bonding structure of the present invention can improve the bonding strength between wafers and reduce the resistance between wafers.

[0052] Depend on Figure 5 It can be known that the wafer bonding structure 200 of the present invention includes wafers 21 , 22 , a TSV structure 230 , a conductive filler 240 , a bonding pad 250 and an oxide layer 260 .

[0053] Specifically, the wafers 21 and 22 are bonded to each other, the wafer 21 has a bonding surface 21a, and the wafer 22 has a bonding surface 22a. The wafer 21 includes a bonding ring structure 210, which is disposed in the wafer 21, one end of the bonding ring structure 210 is connected to the bonding surface 21a, and the other end of the bonding ring structure 210 is connected to the outer surface of the wafer 21. The wafer 22 includes a bonding ring structure 220, which is disposed in the wafer 22, one end of the bonding ring structure 220 is connected to the bonding surface 22a, and the other end of the bonding ring structure 220 is connected to an outer surface (not shown) of the wafer 22.

[0054] The TSV structure 230 penetrates the outer surface of at least one of the two wafers to the bonding surface, wherein the TSV structure 230 connects and overlaps at least one side of the bonding ring structure of at least one of the two wafers and a portion of the bonding ring structure of at least another of the two wafers. Figure 5 In an embodiment, the silicon through-hole structure 230 is penetrated from the outer surface of the wafer 21 to the bonding surface 21a, wherein the silicon through-hole structure 230 connects and overlaps two sides of the bonding ring structure 210 of the wafer 21 and a portion of the bonding ring structure 220 of the wafer 22. In detail, the silicon through-hole structure 230 connects and overlaps a portion of a first metal layer 221, but is not limited thereto. This helps to improve the conductivity between the wafers 21 and 22. The conductive filler 240 is disposed in the silicon through-hole structure 230. The bonding pad 250 is disposed on the outer surface of the wafer 21 having the silicon through-hole structure 230. The conductive filler 240 can be made of copper, but is not limited thereto.

[0055] Specifically, the oxide layer 260 is disposed on the outer surface of the wafer 21 having the TSV structure 230, and the bonding pad 250 is disposed on the oxide layer 260. Furthermore, the oxide layer 260 may be made of silicon oxide, but is not limited thereto.

[0056] Furthermore, each bonding ring structure includes a first metal layer, at least one metal layer and at least two pin sets. Specifically, Figure 5In an embodiment, the bonding ring structure 210 includes a first metal layer 211, metal layers 212, 213, 214, and a pin group 215, and the bonding ring structure 220 includes a first metal layer 221, metal layers 222, 223, 224, and a pin group 225. The first metal layer 211 is connected to the bonding surface 21a, and the first metal layer 221 is connected to the bonding surface 22a. The metal layers 212, 213, 214 are disposed between the outer surface and the first metal layer 211, and the metal layers 222, 223, 224 are disposed between the outer surface and the first metal layer 221. One of the pin groups 215 connects the first metal layer 211 and the metal layer 214, another of the pin groups 215 connects the metal layers 213 and 214, another of the pin groups 215 connects the metal layers 212 and 213, and another of the pin groups 215 connects the metal layer 212 and the outer surface. One of the pin groups 225 connects the first metal layer 221 and the metal layer 224 , another of the pin groups 225 connects the metal layers 223 and 224 , another of the pin groups 225 connects the metal layers 222 and 223 , and another of the pin groups 225 connects the metal layer 222 and the outer surface. Figure 5 In the embodiment, the number of the pin groups 215 is four, the number of the pin groups 225 is four, and the number of the pin groups 215 and 225 corresponds to the number of the metal layers 212, 213, 214, 222, 223, and 224. Furthermore, the number of metal layers is not limited to the above number. The first metal layers 211 and 221 and the metal layers 212, 213, 214, 222, 223, and 224 can be made of copper. The bonding pad can be made of aluminum.

[0057] Furthermore, each pin group 215, 225 includes at least three pins. The width of each pin may be greater than or equal to 0.025 micrometers, and the number of pins may be greater than or equal to three, but is not limited thereto. This helps to avoid edge chipping and moisture penetration during the dicing process.

[0058] Furthermore, the width of the first metal layer 211 is greater than the widths of the metal layers 212, 213, and 214, and the width of the first metal layer 221 is greater than the widths of the metal layers 222, 223, and 224. Specifically, the width of the metal layer 214 is greater than the width of the metal layer 213, and the width of the metal layer 213 is greater than the width of the metal layer 212; the width of the metal layer 224 is greater than the width of the metal layer 223, and the width of the metal layer 223 is greater than the width of the metal layer 222. This helps to increase the conductivity between the first metal layer and the metal layer.

[0059] Depend on Figures 2 to 5 It can be seen that the width of the first metal layer 221 is greater than the width of the first metal layer 211 . Thus, the TSV structure 230 can be connected to the wafers 21 and 22 without any hindrance, and the TSV structure 230 can overlap a portion of the first metal layer 221 .

[0060] Furthermore, the TSV structure 230 may overlap the first metal layer 211 by a range greater than or equal to 0.05 microns, and the TSV structure 230 may overlap the metal layers 212, 213, and 214 by a range greater than or equal to 0.02 microns. Specifically, the TSV structure 230 may overlap the metal layer 212 by a range greater than or equal to 0.02 microns, the TSV structure 230 may overlap the metal layer 213 by a range greater than or equal to 0.03 microns, and the TSV structure 230 may overlap the metal layer 214 by a range greater than or equal to 0.04 microns, but the present invention is not limited thereto. This helps to increase the conductivity between the wafers 21 and 22.

[0061] Specifically, a depth of the TSV structure 230 may be 2 microns to 20 microns, and a width of the TSV structure 230 may be 0.1 microns to 10 microns. Furthermore, the depth of the TSV structure 230 may be 4 microns to 7 microns, but is not limited thereto. It is worth mentioning that the depth of the TSV structure 230 corresponds to the thickness of the wafer 21, and the width of the TSV structure 230 corresponds to the range where the TSV structure 230 overlaps the first metal layer 211 and the metal layers 212, 213, and 214.

[0062] In detail, the bonding ring structures 210 and 220 correspond to a ground electric potential (ground electric potential, Vss) of the wafer bonding structure 200. In addition, the power supply electric potential (power supply electric potential, VCC) of the wafers 21 and 22 (not shown) can be connected in parallel. The voltage of each power supply voltage of the wafers 21 and 22 is through the lowest resistance. Further, the silicon through-hole structure 230 with the conductive filler 240 provides an additional current connection channel for the bonding ring structures 210 and 220. Thereby, it helps to improve the current path of the ground potential.

[0063] The wafer bonding structure and the method for forming the same of the present invention can help improve the conductivity between wafers and between the first metal layer and the metal layer. Furthermore, it can help provide stronger mechanical protection to avoid edge chipping and moisture penetration during the wafer cutting process. Furthermore, it can help improve the reliability of the wafer bonding structure and the problem of bouncing noise.

[0064] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any technician in the relevant technical field can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on what is defined in the claims.

Claims

1. A method for forming a wafer bonding structure, characterized in that: Include: a wafer bonding step, wherein at least two wafers each have a bonding surface, and are bonded to each other via the bonding surfaces; a step of forming a through silicon via, wherein a through silicon via structure is formed on at least one side of a bonding ring structure of one of the at least two wafers, a conductive filler is disposed in the through silicon via structure, and the through silicon via structure overlaps the at least one side of the bonding ring structure of the one of the at least two wafers and a portion of a bonding ring structure of the other of the at least two wafers; and a step of forming a bonding pad, wherein a bonding pad is formed on an outer surface to form a wafer bonding structure, the outer surface being the bonding surface opposite to the wafer having the TSV structure; Wherein, a range in which the TSV structure overlaps the at least one side of the bonding ring structure of one of the at least two wafers is greater than or equal to 0.05 micrometers.

2. The method for forming a wafer bonding structure according to claim 1, wherein: Also includes: A surface treatment step is performed, wherein the bonding surface of each of the at least two wafers is subjected to a surface treatment before the wafer bonding step.

3. The method for forming a wafer bonding structure according to claim 1, wherein: The at least two wafers are exposed to a nitrogen plasma or an oxygen plasma during the wafer bonding step.

4. The method for forming a wafer bonding structure according to claim 1, wherein: In the wafer bonding step, the at least two wafers are bonded at 250° C. to 350° C. for 1 hour to 3 hours.

5. The method for forming a wafer bonding structure according to claim 1, wherein: At least two bonding ring structures are aligned with each other during the wafer bonding step.

6. The method for forming a wafer bonding structure according to claim 5, wherein: An error value of the wafer bonding step is less than 300 nanometers.

7. A wafer bonding structure, characterized in that: Include: At least two wafers, wherein the at least two wafers are bonded to each other, each of the at least two wafers has a bonding surface, and each of the at least two wafers comprises: A bonding ring structure is disposed in the wafer, one end of the bonding ring structure is connected to the bonding surface, and the other end of the bonding ring structure is connected to an outer surface of the wafer; a through silicon via structure, which is penetrated from the outer surface of one of the at least two wafers to the bonding surface, wherein the through silicon via structure connects and overlaps at least one side of the bonding ring structure of one of the at least two wafers and a portion of the bonding ring structure of the other of the at least two wafers; A conductive filler disposed in the TSV structure; and a bonding pad disposed on the outer surface of the wafer including the TSV structure; Wherein, a range in which the TSV structure overlaps the at least one side of the bonding ring structure of one of the at least two wafers is greater than or equal to 0.05 micrometers.

8. The wafer bonding structure according to claim 7, wherein: Each of the joint ring structures comprises: a first metal layer connected to the bonding surface; At least one metal layer disposed between the outer surface and the first metal layer; and At least two pin groups, one of which connects the first metal layer and the at least one metal layer, and the other of which connects the at least one metal layer and the outer surface, wherein each of the at least two pin groups includes at least three pins.

9. The wafer bonding structure according to claim 8, wherein: The TSV structure overlaps the first metal layer by a range greater than or equal to 0.05 micrometers.

10. The wafer bonding structure according to claim 8, wherein: The TSV structure overlaps the at least one metal layer by a range greater than or equal to 0.02 micrometers.

11. The wafer bonding structure according to claim 8, wherein: A width of each of the at least three pins is greater than or equal to 0.025 micrometers.

12. The wafer bonding structure according to claim 8, wherein: The first metal layer and the at least one metal layer are made of copper.

13. The wafer bonding structure according to claim 8, wherein: A width of the first metal layer is greater than a width of the at least one metal layer.

14. The wafer bonding structure according to claim 7, wherein: A depth of the TSV structure is 2 micrometers to 20 micrometers.

15. The wafer bonding structure according to claim 7, wherein: A width of the TSV structure is 0.1 micrometer to 10 micrometers.

16. The wafer bonding structure according to claim 7, wherein: The conductive filler is made of copper.

17. The wafer bonding structure according to claim 7, wherein: The bonding pad is made of aluminum.

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