Semiconductor packaging substrate and its manufacturing method and semiconductor packaging process

Abstract

A semiconductor packaging carrier and its manufacturing method and semiconductor packaging process, including: an insulating layer and a thin circuit structure formed by a circuit layer and a conductive column embedded in the insulating layer and stacked on each other, and a support structure formed on the insulating layer, and the support structure is provided with a through hole exposing the conductive column, so that before the subsequent packaging operation, the electrical property detection and screening of the packaging carrier can be carried out first, so that the subsequent packaging operation will not mistakenly use a packaging carrier with defective functions, thereby avoiding the loss of electronic components with normal functions.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging substrate, in particular to a semiconductor packaging carrier of a thinned product and a manufacturing method thereof and a semiconductor packaging process. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-function and high-performance trends. In order to improve the wiring precision of multi-layer circuit boards, the industry has developed a build-up technology, that is, to alternately stack multiple dielectric layers and circuit layers on the two surfaces of a core board using the circuit build-up technology, and to open conductive blind holes in the dielectric layer for electrical connection between the upper and lower layers of the circuit.

[0003] However, since the thickness of the core board is about 30 to 50 micrometers (um), it is difficult for the package substrate to meet the thinning requirements. Therefore, in order to meet the requirements of miniaturization, a coreless packaging technology has been developed.

[0004] Figure 1A to Figure 1B It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package, such as patent publication No. TW201913906.

[0005] like Figure 1A As shown, a packaging substrate 1 is provided, which has a circuit layer 11 and a support member 12. The support member 12 has a plurality of openings 120 exposing a portion of the circuit layer 11, and the support member 12 is an insulating plate, a semiconductor plate or a metal plate.

[0006] When the package substrate 1 is subsequently subjected to electrical testing, a testing probe is electrically connected to the circuit layer 11 through the opening 120 .

[0007] like Figure 1B As shown, after confirming that the circuit layer 11 of the packaging substrate 1 is in a normal state, a packaging process is performed, at least one semiconductor chip 10 is arranged on the packaging substrate 1, and the semiconductor chip 10 is electrically connected to the circuit layer 11, and the semiconductor chip 10 is coated with a coating layer 13. After the packaging process, the support member 12 can be removed by chemical etching.

[0008] It should be understood that when it is detected that the circuit layer 11 of the packaging substrate 1 is in an abnormal state, the defective packaging substrate 1 is scrapped and the packaging process is not performed on the defective packaging substrate 1.

[0009] However, in the conventional method for manufacturing semiconductor packages, the support member 12 is an insulating plate, a semiconductor plate or a metal plate, so it is not easy to form the opening 120, and the alignment error of the opening 120 is too large, so that when the electrical property test of the package substrate 1 is subsequently performed, the test probe is easily inserted into the wrong opening 120 and accidentally touches the circuit layer 11. Therefore, the electrical test and screening operation for the package substrate 1 before the packaging operation is prone to errors, resulting in errors during the packaging process (such as Figure 1B As shown in the figure, it is easy to place a semiconductor chip 10 with normal function on a package substrate 1 with defective function, so that the originally normal semiconductor chip 10 and the defective package substrate 1 must be scrapped together, thereby greatly increasing the overall production cost of the semiconductor package 1.

[0010] In addition, the patent No. TW I531038 is also provided with a support carrier having an opening, but it still has the problem of too large positioning error of the opening.

[0011] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0012] In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor package carrier and a manufacturing method thereof and a semiconductor package process, which can reduce the overall manufacturing cost of the electronic package and improve subsequent production efficiency.

[0013] The first aspect of the present invention provides a semiconductor package carrier, comprising: a circuit structure, including: a plurality of circuit layers, each having a first electrical surface and a second electrical surface relative to each other; a plurality of conductive pillars, each having a first end surface and a second end surface relative to each other, and being vertically arranged on the first electrical surface of the circuit layer with its second end surface; a plurality of insulating layers, each having a first surface and a second surface relative to each other, and being used to cover the circuit layer and the conductive pillars, so that the first end surface of the conductive pillar on one side is exposed to the first surface of the insulating layer, and the second electrical surface of the circuit layer on the other side is exposed to the second surface of the insulating layer; and a supporting structure, which is arranged on the first surface of the insulating layer on one side of the circuit structure, and the supporting structure is formed with at least one through hole to expose the first end surface of the conductive pillar, wherein the supporting structure is a photosensitive insulating material, and the supporting structure is a removable disposable structure.

[0014] The second aspect of the present invention provides a method for manufacturing a semiconductor package carrier, comprising: providing a carrier; forming a circuit layer and a conductive column on the carrier, wherein the circuit layer has a first electrical surface and a second electrical surface opposite to each other, and the conductive column has a first end surface and a second end surface opposite to each other, wherein the circuit layer is attached to the carrier with its second electrical surface, and the conductive column is erected on the first electrical surface of the circuit layer with its second end surface; forming an insulating layer having a first surface and a second surface opposite to each other on the carrier, so that the insulating layer covers the circuit layer and the conductive column, wherein the first end surface of the conductive column is The first surface of the insulating layer is exposed, and the second electrical surface of the circuit layer is exposed on the second surface of the insulating layer, so that the insulating layer, the circuit layer and the conductive column form a thin circuit structure; a supporting structure is formed on the first surface of the insulating layer, the supporting structure is a photosensitive insulating material, and the supporting structure is formed with at least one through hole to expose the first end surface of the conductive column, and the supporting structure is a removable disposable structure; and the carrier is removed to expose the second surface of the insulating layer and the second electrical surface of the circuit layer, wherein the circuit structure and the supporting structure form a thin packaging carrier.

[0015] In the aforementioned manufacturing method, the through holes of the support structure are formed by lithography.

[0016] In the aforementioned semiconductor package carrier and its manufacturing method, the supporting structure is a photosensitive dielectric material or a photosensitive dry film.

[0017] The third aspect of the present invention provides a semiconductor packaging process, comprising: providing a semiconductor packaging carrier as described in the first aspect above; combining at least one electronic component to the second surface of the insulating layer so that the electronic component is electrically connected to the circuit layer; forming a packaging layer on the second surface of the insulating layer so that the packaging layer covers the electronic component; and completely removing the supporting structure to expose the first surface of the insulating layer and the first end face of the conductive column.

[0018] In the aforementioned semiconductor packaging process, methods for removing the support structure include chemical methods, laser, plasma, sandblasting or mechanical grinding.

[0019] The aforementioned semiconductor packaging process further includes forming a conductive element on the first surface of the insulating layer after completely removing the support structure, so that the conductive element is electrically connected to the first end surface of the conductive column.

[0020] As can be seen from the above, the semiconductor packaging carrier and its manufacturing method and packaging process of the present invention mainly use photosensitive insulating material as the supporting structure to facilitate the formation of through holes, and the alignment of the through holes is extremely accurate without the problem of excessive alignment error. Before performing the semiconductor packaging operation, the electrical property detection operation can be performed on the packaging carrier to first screen out the packaging carriers with normal functions. Therefore, compared with the prior art, the present invention can avoid the misuse of defective packaging carriers during the packaging operation, so the problem of consuming normal electronic components will not occur, thereby reducing the overall production cost of the electronic package and improving subsequent production efficiency.

[0021] In addition, the temporary rigid support design of the support structure can make the circuit structure as thin as possible, and the total thickness of the circuit structure and the support structure combined can meet the general packaging specifications. Therefore, in addition to the packaging carrier not being warped before the packaging process, only general packaging equipment is needed to complete the packaging operation of the thin electronic package, without spending a huge amount of money to modify or purchase packaging equipment that meets the thin packaging specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A to Figure 1B A cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package;

[0023] FIG. 2A to FIG. 2F is a cross-sectional schematic diagram of a method for manufacturing a semiconductor package carrier of the present invention; and

[0024] FIG. 3A to FIG. 3D for Figure 2F A cross-sectional schematic diagram of a subsequent packaging process.

[0025] The reference numerals are described as follows:

[0026] 1: Package substrate

[0027] 10: Semiconductor chips

[0028] 11: Circuit layer

[0029] 12: Support

[0030] 120: Opening

[0031] 13: Cladding layer

[0032] 2: Semiconductor packaging substrate

[0033] 2a: Support structure

[0034] 2b: Line structure

[0035] 20: Loading plate

[0036] 200: Plate body

[0037] 201: Copper layer

[0038] 21: Circuit layer

[0039] 21a: First electrical surface

[0040] 21b: Second electrical surface

[0041] 22: Conductive column

[0042] 22a: First end surface

[0043] 22b: Second end face

[0044] 23: Insulation layer

[0045] 23a, 23a', 23a": first surface

[0046] 23b: Second surface

[0047] 260: Perforation

[0048] 4: Electronic packaging

[0049] 40: Electronic components

[0050] 400: Conductor

[0051] 41: Encapsulation layer

[0052] 42: Conductive elements

[0053] t: thickness. DETAILED DESCRIPTION

[0054] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0055] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of people familiar with this technology, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0056] FIG. 2A to FIG. 2FIt is a cross-sectional schematic diagram of a method for manufacturing a semiconductor package carrier 2 according to the present invention.

[0057] In this embodiment, the semiconductor package carrier 2 is a coreless type, and is used as a carrier for a flip-chip chip scale package (FCCSP).

[0058] like Figure 2A As shown, a carrier board 20 is provided, and a circuit layer 21 is formed on the carrier board 20 by a patterning process. The circuit layer 21 has a first electrical surface 21a and a second electrical surface 21b opposite to each other, and the circuit layer 21 is attached to the carrier board 20 with its second electrical surface 21b. Then, a plurality of conductive pillars 22 are formed on the circuit layer 21 by electroplating by a patterning process. The conductive pillars 22 have a first end surface 22a and a second end surface 22b opposite to each other, and the conductive pillars 22 are vertically arranged on the first electrical surface 21a of the circuit layer 21 with their second end surfaces 22b.

[0059] In this embodiment, the carrier board 20 is a substrate such as an insulating board, a ceramic board, a copper foil substrate or a glass board, but there is no particular limitation. Specifically, this embodiment is described using a copper foil substrate, and the two sides of the board body 200 have copper layers 201 .

[0060] like Figure 2B As shown, an insulating layer 23 is formed on the carrier board 20, so that the insulating layer 23 covers the circuit layer 21 and the plurality of conductive pillars 22, and the thickness t (as shown in FIG. Figure 2C As shown) can be less than or equal to 60 microns (um), such as ranging from 20 to 60 microns.

[0061] In this embodiment, the insulating layer 23 has a first surface 23 a ′ and a second surface 23 b opposite to each other, and the insulating layer 23 is bonded to the carrier board 20 via the second surface 23 b .

[0062] In addition, the insulating layer 23 is formed on the carrier board 20 by molding, coating or laminating, and the material forming the insulating layer 23 is a dielectric material, which can be an epoxy resin (Epoxy), or a molding compound (Molding Compound) or a primer (Primer), such as an epoxy molding compound (Epoxy Molding Compound, referred to as EMC), wherein the epoxy molding resin contains a filler, and the filler content is 70 to 90wt%.

[0063] like Figure 2CAs shown, part of the material of the first surface 23a' of the insulating layer 23 is removed so that the first surface 23a" of the insulating layer 23 and the first end surface 22a of the conductive column 22 are flush (i.e., coplanar), and the first end surface 22a of the conductive column 22 is exposed on the first surface 23a" of the insulating layer 23.

[0064] In addition, in another embodiment, part of the material of the first end surface 22a of the conductive pillar 22 can be selectively removed (such as by etching or other subtractive processes) so that the first end surface 22a of the conductive pillar 22 can be recessed and lower than the first surface 23a" of the insulating layer 23.

[0065] like Figure 2D As shown, at least one circuit layer 21, at least one conductive column 22 and at least one insulating layer 23 may be further provided on the first surface 23a″ of the insulating layer 23, so that the circuit layers 21 (three layers as shown in the figure), the conductive columns 22 (three layers as shown in the figure) and the insulating layers 23 (three layers as shown in the figure) serve as a thin circuit structure 2b. It should be understood that the thin circuit structure 2b may be composed of a single layer of circuit layers 21, conductive columns 22 and insulating layers 23, or may be composed of multiple layers of circuit layers 21, conductive columns 22 and insulating layers 23 according to actual needs.

[0066] In this embodiment, the first surface 23a of the outermost insulating layer 23 and the first end surface 22a of the outermost conductive column 22 are flush (i.e., coplanar), and the first end surface 22a of the outermost conductive column 22 is exposed to the first surface 23a of the outermost insulating layer 23. It should be understood that the first end surface 22a of the conductive column 22 can also be set to be concave or protruding from the first surface 23a of the insulating layer 23, that is, the first end surface 22a of the conductive column 22 can be set to be flush, concave, or protruding from the first surface 23a of the insulating layer 23 according to actual needs.

[0067] In addition, a surface treatment layer (not shown) may be selectively formed on the first end surface 22a of the outermost conductive pillar 22, and the surface of the surface treatment layer may be concave, flush, or protruding from the first surface 23a of the outermost insulating layer 23. For example, the material forming the surface treatment layer may be one of copper surface protectant, organic solderability preservative (OSP), electroplated nickel palladium gold, chemical nickel palladium gold (ENEPIG), electroplated nickel gold (Ni / Au), tin plating, silver plating, or a combination thereof.

[0068] like Figure 2E As shown, a support structure 2a made of an insulating material is formed on the first surface 23a of the circuit structure 2b, and the support structure 2a is a removable and disposable structure.

[0069] In this embodiment, the support structure 2a can be made of a photosensitive insulating material, a photosensitive dry film, or an epoxy resin substrate, such as bismaleimide triazine (BT), FR-4, FR-5 and other insulating materials (photosensitive insulating materials are the best choice), and is formed on the first surface 23a of the insulating layer 23 by, for example, molding, coating or lamination.

[0070] In addition, at least one through hole 260 is formed on the support structure 2a at a position corresponding to the conductive pillar 22 to expose the first end surface 22a (or the surface treatment layer thereon) of the outermost conductive pillar 22. In this embodiment, the through hole 260 can be formed by exposure and development, laser, plasma, sandblasting, etc.

[0071] like Figure 2F As shown, the entire carrier board 20 is removed to completely expose the second surface 23 b of the insulating layer 23 , and the second electrical surface 21 b of the circuit layer 21 is exposed on the second surface 23 b of the insulating layer 23 .

[0072] In this embodiment, the carrier board 20 and the metal layer 201 are removed by etching (or other subtractive processes), so that a local area of ​​the second electrical surface 21b of the circuit layer 21 is slightly etched, so that the second electrical surface 21b of the circuit layer 21 is recessed and lower than the second surface 23a of the insulating layer 23.

[0073] In addition, a planarization process may be selectively performed to make the second surface 23 b of the insulating layer 23 and the second electrical surface 21 b of the circuit layer 21 flush with each other.

[0074] In addition, in another embodiment, a patterned electroplating process may be selectively performed to form conductive bumps (not shown) on the second electrical surface 21 b of the circuit layer 21 , which is beneficial to the subsequent chip packaging process.

[0075] Accordingly, a semiconductor packaging carrier 2 (i.e., a combination of a support structure 2a having a through hole 260 and a thinned circuit structure 2b) having a total thickness greater than or equal to 100 microns can be obtained to meet the specification requirements of the general semiconductor packaging equipment currently available in the packaging factory (because when the thickness of the semiconductor packaging carrier 2 is too thin, it is necessary to spend a huge amount of money to modify or purchase semiconductor packaging equipment that meets the thin packaging specifications).

[0076] In addition, when performing electrical testing on the semiconductor package carrier 2, a portion of the contact terminals (not shown) of the test equipment is inserted into the through holes 260 to contact the first end surface 22a (or the surface treatment layer thereon) of the conductive column 22 on one side, and another portion of the contact terminals (not shown) of the test equipment is contacted with the second electrical surface 21b of the circuit layer 21 on the other side, so that the electrical status of the circuit layer 21 and the conductive column 22 can be detected, and the semiconductor package carrier 2 with defective functions can be eliminated in advance.

[0077] Therefore, the manufacturing method of the present invention uses a photosensitive insulating material as the support structure 2a to facilitate the formation of the through hole 260, and the alignment of the through hole 260 is extremely accurate without the problem of excessive alignment error. It can not only provide temporary support rigidity for the thin circuit structure 2b, but also expose the conductive column 22 through the through hole 260, so that the thin semiconductor package carrier 2 can be pre-tested and screened for electrical properties to avoid the subsequent semiconductor packaging process from misusing the semiconductor package carrier 2 with defective functions, resulting in unnecessary loss of electronic components with normal functions and increased production costs. Therefore, the present invention can completely eliminate the shortcomings of existing related products such as the inability to perform electrical testing and screening, and can make the thin semiconductor package carrier 2 with a thin circuit structure 2b fully meet the specifications of the existing packaging equipment of the packaging factory, thereby avoiding the packaging factory from spending huge amounts of money to modify or purchase packaging equipment that meets the thin packaging specifications.

[0078] In the subsequent packaging process, taking the semiconductor packaging substrate 2 as an example, the following steps are performed: FIG. 3A to FIG. 3D The subsequent packaging process is shown.

[0079] like Figure 3A As shown, at least one electronic component 40 is disposed on the second surface 23b of the insulating layer 23 of the semiconductor package carrier 2 which has been electrically tested and screened and has normal functions.

[0080] In the present embodiment, the electronic component 40 is an active component, a passive component or a combination of the two, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the electronic component 40 is a semiconductor chip, which is electrically connected to the circuit layer 21 of the semiconductor package carrier 2 by a flip chip method through a plurality of conductors 400 including, for example, copper bumps, solder bumps, etc. Alternatively, the electronic component 40 can also be electrically connected to the circuit layer 21 by a wire bonding method through a plurality of conductors such as welding wires (not shown); or, the electronic component 40 can directly contact the circuit layer 21. However, the method for electrically connecting the electronic component 40 to the circuit layer 21 is not limited to the above.

[0081] like Figure 3BAs shown, a packaging layer 41 is formed on the second surface 23b of the insulating layer so that the packaging layer 41 covers the electronic component 40. Therefore, the packaging layer 41 provides the covering and supporting rigidity to prevent the finished package from deformation or damage.

[0082] In this embodiment, the packaging layer 41 can be a film for lamination process, a packaging colloid for molding process or a glue material for printing process to cover the electronic component 40 and the plurality of conductors 400, and the material forming the packaging layer 41 is polyimide (PI), epoxy resin (epoxy) or a molded packaging material. Alternatively, the packaging layer 41 can be a primer, which can be formed between the semiconductor package carrier 2 and the electronic component 40 to cover the plurality of conductors 400. It should be understood that the packaging method of the electronic component 40 is not limited to the above.

[0083] like Figure 3C As shown, the support structure 2a is completely removed by chemical means, laser, plasma, sandblasting, or mechanical grinding to expose the first surface 23a of the insulating layer 23 and the first end surface 22a of the conductive column 22 (or the surface treatment layer thereon).

[0084] Accordingly, a thinned electronic package 4 can be formed, wherein the total thickness of the thinned circuit structure 2b and the support structure 2a providing temporary support rigidity can meet the general packaging equipment specifications of the packaging factory, so there is no need to spend huge amounts of money to modify or purchase packaging equipment that meets the thin packaging specifications, and the packaging process of the thinned electronic package 4 can be successfully completed. Furthermore, due to the coating and support rigidity provided by the packaging layer 41, even if the support structure 2a is completely removed, the final thinned electronic package 4 can still maintain appropriate rigidity without causing problems such as deformation and damage.

[0085] like Figure 3D As shown, a plurality of conductive elements 42 such as solder balls may be formed on the first surface 23a of the insulating layer 23, so that the conductive elements 42 are electrically connected to the first end surface 22a of the conductive column 22 (or the surface treatment layer thereon) so as to be further combined with a circuit board (PCB).

[0086] Therefore, in the manufacturing method of the present invention, a photosensitive insulating material is mainly used as the support structure 2a to facilitate the formation of the through hole 260, and the alignment of the through hole 260 is extremely accurate without the problem of excessive alignment error. Before the packaging operation of the electronic component 40 is performed, the electrical property detection and screening of the thinned semiconductor package carrier 2 is first performed through the through hole 260 to eliminate the semiconductor package carrier 2 with functional defects in advance, so as to avoid placing the electronic component 40 with normal function on the semiconductor package carrier 2 with functional defects, so as to avoid the problem of unnecessary consumption of the electronic component 40 with normal function, so as to effectively reduce the overall manufacturing cost of the thinned electronic package 4.

[0087] In addition, the overall structural rigidity of the semiconductor package carrier 2 is strengthened by the support structure 2a, so that the thinned circuit structure 2b will not be warped or deformed before the packaging process is carried out, and the total thickness of the support structure 2a and the thinned circuit structure 2b combined can meet the specification requirements of general packaging equipment in the packaging factory, so that the thinned semiconductor package carrier 2 of the present invention can be provided as a packaging carrier for electronic components 40, and only general packaging equipment is required to complete the packaging process of the thinned electronic package 4, thereby saving the high cost of modifying or purchasing thinned packaging equipment.

[0088] The embodiment of the present invention can provide a semiconductor package carrier 2 (such as Figure 2F ) includes: a circuit structure 2b and a support structure 2a, and the circuit structure 2b includes a plurality of circuit layers 21, a plurality of conductive pillars 22 and a plurality of insulating layers 23.

[0089] The circuit layer 21 has a first electrical surface 21 a and a second electrical surface 21 b opposite to each other.

[0090] The conductive pillar 22 has a first end surface 22 a and a second end surface 22 b opposite to each other, and the second end surface 22 b is vertically disposed on the first electrical surface 21 a of the circuit layer 21 .

[0091] The insulating layer 23 covers the circuit layer 21 and the conductive column 22, and the insulating layer 23 has a first surface 23a and a second surface 23b opposite to each other, so that the first end surface 22a of the conductive column 22 on one side is exposed to the first surface 23a of the insulating layer 23, and the second electrical surface 21b of the circuit layer 21 on the other side is exposed to the second surface 23b of the insulating layer 23.

[0092] The support structure 2a is disposed on the first surface 23a of the insulating layer 23 on one side of the circuit structure 2b, and the support structure 2a is formed with at least one through hole 260 corresponding to the conductive column 22 to expose the first end surface 22a of the conductive column 22, wherein the support structure 2a is a photosensitive insulating material and is a removable disposable structure.

[0093] In one embodiment, the support structure 2a is a photosensitive dielectric material or a photosensitive dry film.

[0094] In summary, in the semiconductor package carrier 2 and the manufacturing method thereof of the present invention, the photosensitive insulating material support structure 2a is mainly designed with a through hole 260, so that before the semiconductor packaging operation is performed, the electrical property detection of the semiconductor package carrier 2 can be performed first, so as to pre-eliminate the semiconductor package carrier 2 with functional defects to avoid the semiconductor package carrier 2 with functional defects from being mistakenly used during the packaging operation, thereby avoiding the problem of unnecessary consumption of electronic components 40 with normal functions, thereby effectively reducing the overall manufacturing cost of the thin electronic package 4 and improving the subsequent production efficiency.

[0095] In addition, by virtue of the temporary rigid support design of the support structure 2a, the circuit structure 2b can be made as thin as possible, and the total thickness after the circuit structure 2b and the support structure 2a are combined can meet the specification requirements of general packaging equipment. Therefore, in addition to the fact that the thinned semiconductor packaging carrier 2 will not warp before the packaging process, only general packaging equipment is required to complete the packaging operation of the thinned electronic package 4, without spending a huge amount of money to modify or purchase packaging equipment that meets the thin packaging specifications.

[0096] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Anyone skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A semiconductor package substrate, characterized in that: include: The circuit structure includes: A plurality of circuit layers, each having a first electrical surface and a second electrical surface opposite to each other; A plurality of conductive pillars, each having a first end face and a second end face opposite to each other, and the second end face is vertically disposed on the first electrical surface of the circuit layer; A plurality of insulating layers, each having a first surface and a second surface opposite to each other, and used to cover the circuit layer and the conductive column, so that the first end surface of the conductive column on one side is exposed to the first surface of the insulating layer, and the second electrical surface of the circuit layer on the other side is exposed to the second surface of the insulating layer; as well as The support structure is arranged on the first surface of the insulating layer on one side of the circuit structure, and the support structure is formed with at least one through hole to expose the entire first end surface of the conductive column, wherein the support structure is a photosensitive insulating material and is a removable disposable structure.

2. The semiconductor package carrier according to claim 1, wherein: The supporting structure is a photosensitive dielectric material or a photosensitive dry film.

3. A method for manufacturing a semiconductor package substrate, characterized in that: include: Providing a carrier plate; A circuit layer and a conductive column are formed on the carrier board, wherein the circuit layer has a first electrical surface and a second electrical surface opposite to each other, and the conductive column has a first end surface and a second end surface opposite to each other, wherein the circuit layer is attached to the carrier board with its second electrical surface, and the conductive column is vertically arranged on the first electrical surface of the circuit layer with its second end surface; An insulating layer having a first surface and a second surface opposite to each other is formed on the carrier board, so that the insulating layer covers the circuit layer and the conductive column, wherein the first end surface of the conductive column is exposed on the first surface of the insulating layer, and the second electrical surface of the circuit layer is exposed on the second surface of the insulating layer, so that the insulating layer, the circuit layer and the conductive column form a thin circuit structure; Forming a support structure on the first surface of the insulating layer, the support structure is a photosensitive insulating material, and the support structure is formed with at least one through hole to expose the entire first end surface of the conductive column, and the support structure is a removable and disposable structure; and The carrier is removed to expose the second surface of the insulating layer and the second electrical surface of the circuit layer, wherein the circuit structure and the support structure form a thinned packaging carrier.

4. The method for manufacturing a semiconductor package carrier according to claim 3, wherein: The through holes of the support structure are formed by photolithography.

5. The method for manufacturing a semiconductor package substrate as claimed in claim 3, wherein: The supporting structure is a photosensitive dielectric material or a photosensitive dry film.

6. A semiconductor packaging process, characterized in that: include: Providing a semiconductor package carrier according to any one of claims 1 to 2; Bonding at least one electronic component to the second surface of the insulating layer so that the electronic component is electrically connected to the circuit layer; forming a packaging layer on the second surface of the insulating layer so that the packaging layer covers the electronic component; as well as The support structure is completely removed to expose the first surface of the insulating layer and the first end surface of the conductive column.

7. The semiconductor packaging process according to claim 6, wherein: Methods for removing the support structure include chemical means, laser, plasma, sandblasting or mechanical grinding.

8. The semiconductor packaging process according to claim 6, wherein: The method further includes forming a conductive element on the first surface of the insulating layer after completely removing the supporting structure, so that the conductive element is electrically connected to the first end surface of the conductive column.

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