Transistor and method of forming semiconductor device

Abstract

An embodiment of the present application provides a transistor device and a method for manufacturing the same, the transistor device comprising: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a double-layer semiconductor channel comprising: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer such that the second channel layer contacts the side and top surfaces of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first resistance, and the second channel layer has a second resistance different from the first resistance. According to other embodiments of the present application, a method for forming a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to transistors and methods of forming semiconductor devices. Background Art

[0002] In the semiconductor industry, there is a constant desire to increase the areal density of integrated circuits. To this end, transistors are becoming smaller and smaller. However, the rate at which transistors can be made smaller is slowing down. Moving peripheral transistors from the front-end of the line (FEOL) of manufacturing to the back-end of the line (BEOL) can be advantageous because functionality can be added at the BEOL while valuable chip area can be gained in the FEOL. Transistors using oxide semiconductors are an attractive option for BEOL integration because such transistors can be processed at low temperatures, thus not damaging previously manufactured devices. For example, thin-film transistors (TFTs) often use oxide semiconductor materials.

[0003] Various memory cell elements (e.g., magnetoresistive random access memory (MRAM) and resistive random access memory (RRAM or ReRAM)) can utilize transistors to select or activate memory cells. However, since the size of CMOS transistors may be limited, the use of CMOS transistors as select transistors may limit the device density of the memory cell element. Summary of the Invention

[0004] According to one embodiment of the present application, a transistor is provided, comprising: a substrate; a word line disposed on the substrate; a gate dielectric layer disposed on the word line; a double-layer semiconductor channel, comprising: a first channel layer disposed on the gate dielectric layer and having a first resistance; and a second channel layer disposed on the first channel layer and having a second resistance different from the first resistance, such that the second channel layer contacts the side and top surfaces of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer.

[0005] According to another embodiment of the present application, a transistor is provided, comprising: a substrate; a word line disposed on the substrate; a gate dielectric layer disposed on the word line; a double-layer channel disposed on the gate dielectric layer and comprising: a first channel layer disposed on the gate dielectric layer; and a second channel layer comprising a semiconductor material and disposed on the first channel layer, such that the second channel layer contacts the side and top surfaces of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer, wherein, in response to a voltage applied to the word line, the first channel layer has a first resistance, and the second channel layer has a second resistance higher than the first resistance.

[0006] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: depositing a first dielectric layer on a semiconductor substrate; forming a word line in the first dielectric layer; depositing a gate dielectric layer above the word line; forming a double-layer channel on the gate dielectric layer, by: depositing a first channel layer having a first resistance on the gate dielectric layer; and depositing a second channel layer having a second resistance different from the first resistance on the first channel layer, so that the second channel layer contacts the side and top surfaces of the first channel layer, wherein the second channel layer comprises a semiconductor material, depositing a second dielectric layer on the second channel layer; and forming a source electrode and a drain electrode in the second dielectric layer.

[0007] Embodiments of the present application relate to a double-channel transistor and a method for forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. Indeed, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A is a vertical cross-sectional view of a first exemplary structure before forming an array of transistors according to an embodiment of the present disclosure.

[0010] Figure 1B is a vertical cross-sectional view of a first exemplary structure during formation of an array of transistors according to an embodiment of the present disclosure.

[0011] Figure 1C is a vertical cross-sectional view of the first exemplary structure after forming an upper level metal interconnect structure according to an embodiment of the present disclosure.

[0012] Figure 2A is a vertical cross-sectional view showing an intermediate structure of an embodiment transistor after a dielectric is deposited over a substrate.

[0013] Figure 2B is a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after forming wordline trenches in a dielectric deposited over a substrate.

[0014] Figure 2C is a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after depositing a metal fill material in the word line trench to form a word line.

[0015] Figure 2D is a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after depositing a gate dielectric layer and a first channel material over a word line and a first dielectric layer.

[0016] Figure 2Eis a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after patterning a first channel material to form a first channel layer.

[0017] Figure 2F is a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after depositing a second channel material over the first channel layer and the gate dielectric layer.

[0018] Figure 2G is a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after patterning a second channel material to form a second channel layer.

[0019] Figure 2H is a vertical cross-sectional view illustrating the intermediate structure of an embodiment transistor after depositing a second dielectric layer over the second channel layer and the gate dielectric layer.

[0020] Figure 2I is a vertical cross-sectional view illustrating an intermediate structure of an embodiment transistor after forming an active area electrode via cavity in a second dielectric layer.

[0021] Figure 2J is a vertical cross-sectional view illustrating an embodiment transistor after forming an active area electrode in an active area electrode via cavity.

[0022] Figure 3A is a top semi-transparent view of a transistor according to a first embodiment of the present disclosure.

[0023] Figure 3B According to various embodiments of the present disclosure Figure 3A A vertical cross-sectional view of the transistor taken along line AA'.

[0024] Figure 4A is a vertical cross-sectional view showing an intermediate structure of a transistor according to another embodiment after depositing a gate dielectric layer and a first channel material over the word line and the first dielectric layer.

[0025] Figure 4B is a vertical cross-sectional view illustrating an intermediate structure of a transistor according to another embodiment after patterning a first channel material to form a first channel layer.

[0026] Figure 4C is a vertical cross-sectional view illustrating an intermediate structure of a transistor according to another embodiment after depositing a second channel material over a first channel layer and a gate dielectric layer.

[0027] Figure 4D is a vertical cross-sectional view illustrating an intermediate structure of a transistor according to another embodiment after patterning a second channel material to form a second channel layer.

[0028] Figure 4Eis a vertical cross-sectional view illustrating an intermediate structure of a transistor according to another embodiment after depositing a second dielectric layer over the second channel layer and the gate dielectric layer.

[0029] Figure 4F is a vertical cross-sectional view illustrating an intermediate structure of a transistor according to another embodiment after forming an active area electrode via cavity in a second dielectric layer.

[0030] Figure 4G is a vertical cross-sectional view illustrating a transistor according to another embodiment after forming an active area electrode in an active area electrode via cavity.

[0031] Figure 5A is a top semi-transparent view of transistor 500 according to various embodiments of the present disclosure.

[0032] Figure 5B According to various embodiments of the present disclosure Figure 5A A vertical cross-sectional view of the transistor taken along line AA'.

[0033] Figure 6A is a top semi-transparent view of transistor 600 according to various embodiments of the present disclosure.

[0034] Figure 6B According to various embodiments of the present disclosure Figure 6A A vertical cross-sectional view of the transistor taken along line AA'.

[0035] Figure 7A is a top semi-transparent view of transistor 700 according to various embodiments of the present disclosure.

[0036] Figure 7B According to various embodiments of the present disclosure Figure 7A A vertical cross-sectional view of the transistor taken along line AA'.

[0037] Figure 8 is a flow chart of a method of forming a double-layer channel transistor according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. Such repetition is merely for simplicity and clarity and does not, by itself, represent a relationship between the various embodiments and / or configurations discussed.

[0039] In addition, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each element having the same figure label is assumed to have the same material composition and have a thickness within the same thickness range. As used herein, the words "substantially" and "approximately" refer to a variation of + / - 5%.

[0040] The present disclosure relates to semiconductor devices, and in particular to double-layer channel transistor devices and methods of forming the same.

[0041] A memory device includes a grid of independently functional memory cells formed on a substrate. The memory device may include volatile memory cells or non-volatile (NV) memory cells. Emerging memory technologies seek to store more data at a lower cost than the expensive silicon chips used in popular consumer electronics. Such emerging memory devices may be used to replace existing memory technologies such as flash memory in the near future. Although existing resistive random access memories are generally adequate for their intended purposes, they are not fully satisfactory in all aspects as devices are scaled down.

[0042] In some memory devices, CMOS transistors can be used as select transistors. However, the size limitations of CMOS transistor technology may be a limiting factor in improving the size and memory cell density of memory devices. Various embodiments described herein provide improved transistors, for example, thin film transistors (TFTs) that can be used as select transistors in various devices. The improved transistors of various embodiments may include a double-layer channel, wherein the semiconductor materials used in the two channel layers may provide different resistances to improve channel mobility and reduce parasitic resistance.

[0043] refer to Figure 1A , according to various embodiments of the present disclosure, a first exemplary structure according to an embodiment of the present disclosure is shown before forming an array of memory structures. The first exemplary structure includes a substrate 8 including a semiconductor material layer 10. Substrate 8 may include: a bulk semiconductor substrate such as a silicon substrate, wherein the semiconductor material layer extends continuously from the top surface of substrate 8 to the bottom surface of substrate 8; or a semiconductor-on-insulator layer including the semiconductor material layer 10 as the top semiconductor layer located above a buried insulator layer (such as a silicon oxide layer). The exemplary structure may include various device regions, which may include a memory array region 50, in which at least one array of non-volatile memory cells may be subsequently formed.

[0044] For example, at least one array of nonvolatile memory cells may include resistive random access memory (RRAM or ReRAM), magnetic / magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and phase change memory (PCM) devices. The exemplary structure may also include a peripheral logic region 52, where electrical connections between each array of nonvolatile memory cells and peripheral circuitry including field-effect transistors may be subsequently formed. The areas of the memory array region 50 and the logic region 52 may be used to form various elements of the peripheral circuitry.

[0045] During FEOL operations, semiconductor devices such as field effect transistors (FETs) may be formed on and / or in the semiconductor material layer 10. For example, a shallow trench isolation structure 12 may be formed in the upper portion of the semiconductor material layer 10 by forming a shallow trench and then filling the shallow trench with a dielectric material such as silicon oxide. Other suitable dielectric materials are within the contemplated scope of the present disclosure. Various doped wells (not explicitly shown) may be formed in various regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0046] A gate structure 20 may be formed above the top surface of the substrate 8 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate cap dielectric layer. Each gate structure 20 may include a vertical stack of a gate dielectric 22, a gate electrode 24, and a gate cap dielectric 28, which are referred to herein as a gate stack (22, 24, 28). An ion implantation process may be performed to form an extended implant region, which may include a source extension region and a drain extension region. A dielectric gate spacer 26 may be formed around the gate stack (22, 24, 28). Each component of the gate stack (22, 24, 28) and the dielectric gate spacer 26 constitutes the gate structure 20. An additional ion implantation process may be performed that uses the gate structure 20 as a self-aligned implant mask to form a deep active region. Such a deep active region may include a deep source region and a deep drain region. The upper portion of the deep active region may overlap with a portion of the extended implant region. Each combination of an extended implant region and a deep active region can constitute an active region 14, which can be a source region or a drain region, depending on the electrical bias. In some embodiments, the active region 14 can be epitaxially grown. A semiconductor channel 15 can be formed below each gate stack (22, 24, 28) between an adjacent pair of active regions 14. A metal-semiconductor alloy region 18 can be formed on the top surface of each active region 14. Field effect transistors can be formed on the semiconductor material layer 10. Each field effect transistor can include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one of which serves as a source region and the other as a drain region), and an optional metal-semiconductor alloy region 18. A complementary metal oxide semiconductor (CMOS) circuit 75 can be provided on the semiconductor material layer 10, which can include peripheral circuitry for a subsequently formed transistor array.

[0047] Various interconnect hierarchical structures may then be formed, which may be formed before forming the selector field effect transistor array and are referred to herein as lower interconnect hierarchical structures (L0, L1, L2). In embodiments where a two-dimensional array of transistors may be sequentially formed above two levels of interconnect hierarchical metal lines, the lower interconnect hierarchical structures (L0, L1, L2) may include a contact hierarchical structure L0, a first interconnect hierarchical structure L1, and a second interconnect hierarchical structure L2. The contact hierarchical structure L0 may include a planarization dielectric layer 31A comprising a planarization dielectric material such as silicon oxide and various contact via structures 41V formed within the planarization dielectric layer 31A that contact a corresponding one of the active region 14 or the gate electrode 24. The first interconnect hierarchical structure L1 includes a first interconnect hierarchical dielectric layer 31B and a first metal line 41L formed within the first interconnect hierarchical dielectric layer 31B. The first interconnect hierarchical dielectric layer 31B is also referred to as a first line-level dielectric layer. The first metal line 41L may contact a corresponding one of the contact via structures 41V. The second interconnection level structure L2 includes a second interconnection level dielectric layer 32, which may include a first via level dielectric material layer and a second line level dielectric material layer or a stack of line and via level dielectric material layers. A second interconnection level metal interconnect structure (42V, 42L) may be formed in the second interconnection level dielectric layer 32, which includes a first metal via structure 42V and a second metal line 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second interconnection level dielectric layer 32.

[0048] refer to Figure 1B , an array 95 of nonvolatile memory cells and transistor selection devices can be formed in the memory array region 50 above the second interconnect hierarchy L2. Details of the structure and processing steps of the array 95 of nonvolatile memory cells and transistor selection devices are described in detail later below. A third interconnect hierarchy dielectric layer 33 can be formed during the formation of the array 95 of nonvolatile memory cells and transistor selection devices. The collection of all structures formed at the level of the array 95 of nonvolatile memory cells and transistor selection device transistors is referred to herein as the third interconnect hierarchy L3.

[0049] refer to Figure 1C, a third interconnection level metal interconnect structure (43V, 43L) may be formed in the third interconnection level dielectric layer 33. The third interconnection level metal interconnect structure (43V, 43L) may include a second metal through-hole structure 43V and a third metal line 43L. Additional interconnection level structures may then be formed, which are referred to herein as upper interconnection level structures (L4, L5, L6, L7). For example, the upper interconnection level structures (L4, L5, L6, L7) may include a fourth interconnection level structure L4, a fifth interconnection level structure L5, a sixth interconnection level structure L6, and a seventh interconnection level structure L7. The fourth interconnection level structure L4 may include a fourth interconnection level dielectric layer 34, in which a fourth interconnection level metal interconnect structure (44V, 44L) is formed, which may include a third metal through-hole structure 44V and a fourth metal line 44L. The fifth interconnection level structure L5 may include a fifth interconnection level dielectric layer 35, in which a fifth interconnection level metal interconnect structure (45V, 45L) is formed, which may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnection level structure L6 may include a sixth interconnection level dielectric layer 36, in which a sixth interconnection level metal interconnect structure (46V, 46L) is formed, which may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnection level structure L7 may include a seventh interconnection level dielectric layer 37, in which a sixth metal via structure 47V (which is a seventh interconnection level metal interconnect structure) and a metal bonding pad 47B are formed. The metal bonding pad 47B may be configured for solder bonding (which may employ C4 ball bonding or wire bonding), or may be configured for metal-to-metal bonding (such as copper-to-copper bonding).

[0050] Each interconnect level dielectric layer may be referred to as an interconnect level dielectric layer (ILD) layer 30. Each interconnect level metal interconnect structure may be referred to as a metal interconnect structure 40. Each continuous combination of a metal via structure and a metal line thereon within the same interconnect level structure (L2-L7) may be sequentially formed into two different structures using two single damascene processes, or may be simultaneously formed into a single structure using a dual damascene process. Each metal interconnect structure 40 may include a corresponding metal liner (such as a TiN, TaN, or WN layer having a thickness in the range of 2 nm to 20 nm) and a corresponding metal fill material (such as W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof). Other suitable materials for use as metal liners and metal fill materials are within the contemplated scope of the present disclosure. Various etch stop dielectric layers and dielectric cap layers may be interposed between vertically adjacent pairs of ILD layers 30, or may be incorporated into one or more ILD layers 30.

[0051] Although the present disclosure is described using an embodiment in which the array 95 of nonvolatile memory cells and transistor select devices can be formed as a component of the third interconnect hierarchy L3, in some embodiments, the array 95 of nonvolatile memory cells and transistor select devices can be formed as a component of any other interconnect hierarchy (e.g., L1-L7). Furthermore, although the present disclosure is described using an embodiment in which a set of eight interconnect hierarchies is formed, embodiments in which a different number of interconnect hierarchies is used are expressly contemplated herein. Additionally, embodiments in which two or more arrays 95 of nonvolatile memory cells and transistor select devices can be provided within multiple interconnect hierarchies in the memory array region 50 are expressly contemplated herein. Although the present disclosure is described using an embodiment in which the array 95 of nonvolatile memory cells and transistor select devices can be formed within a single interconnect hierarchy, in some embodiments, the array 95 of nonvolatile memory cells and transistor select devices can be formed over two vertically adjacent interconnect hierarchies. In addition, although various embodiments of the present disclosure are described below by illustrating the transistor selection device as a thin film transistor (TFT), other forms of transistor selection devices are contemplated and can be formed and used. For example, planar, gate-all-around, and fin transistors, as well as other forms of transistors that benefit from a double-layer channel, can be formed and used as transistor devices.

[0052] A semiconductor transistor device includes a source electrode and a drain electrode that contact a channel and overlap a gate electrode separated from the channel by a gate insulating layer. However, such a configuration may cause the current flow path to extend through the body of the channel, thereby causing the channel length to be extended. In addition, parasitic resistance may appear where the source electrode and / or drain electrode contacts the channel. Therefore, due to the increased channel resistance, a transistor device such as a TFT may have a degraded channel mobility. Thus, it is necessary to provide a transistor with reduced channel resistance. Various embodiments disclosed herein provide a double-layer channel transistor with reduced channel resistance and improved channel mobility.

[0053] refer to Figure 2A , a first dielectric layer 102 may be deposited on a substrate 100. The substrate 100 may be any suitable substrate, such as a semiconductor substrate, and may include control elements formed during the FEOL process. The substrate 100 may also be an interconnect level dielectric layer, such as the second interconnect level dielectric layer 32. The first dielectric layer 102 may be formed of any suitable dielectric material, such as silicon oxide (SiO2), or a high-k dielectric material, such as silicon nitride (SiN4), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf 0.5 Zr 0.5O2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium dioxide-aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), etc. Other suitable dielectric materials may also be within the intended scope of the present disclosure. Any suitable deposition process may be used to deposit the first dielectric layer 102. Here, suitable deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD) or sputtering, laser ablation, etc.

[0054] refer to Figure 2B A photoresist layer 101 may be applied over the first dielectric layer 102. The photoresist layer 101 may be photolithographically patterned to form a line and space pattern comprising strips of photoresist material extending laterally along a first horizontal direction. An anisotropic etching process may be performed to etch unmasked portions of the first dielectric layer 102. Line trenches 103 extending laterally along the first horizontal direction may be formed in areas not masked by the strips of photoresist material. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0055] refer to Figure 2C , word lines 110 may be formed in word line trenches 103. Specifically, a conductive material may be deposited over first dielectric layer 102 and filled in word line trenches 103. A planarization process, such as CMP, may then be performed to planarize the upper surfaces of first dielectric layer 102 and word lines 110 and remove any excess conductive material from the upper surface of first dielectric layer 102. Word lines 110 may be formed from any suitable conductive material using any suitable deposition method as described herein. These suitable deposition methods may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, and the like. Word lines 110 may be formed from any of copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, and the like. Other suitable conductive materials for forming word lines 110 are within the contemplated scope of the present disclosure.

[0056] refer to Figure 2D, a gate dielectric layer 116 and a first channel material 120L can be deposited over the first dielectric layer 102 and the word lines 110. The gate dielectric material of the gate dielectric layer 116 may include a gate dielectric material such as silicon oxide, silicon oxynitride, a dielectric metal oxide, or a combination thereof. In some embodiments, the gate dielectric layer 116 may include a ferroelectric material such as PbZr / TiO3, BaTiO3, PbTiO3, etc. However, other suitable dielectric materials are within the intended scope of the present disclosure. The thickness of the gate dielectric layer 116 may be in a range from 1 nm to 12 nm, such as from 2 nm to 6 nm, but smaller and larger thicknesses may also be used. Typically, the gate dielectric layer 116 may be formed on the first dielectric layer 102 and the word lines 110. The gate dielectric layer 116 may be formed by depositing a gate dielectric material on the first dielectric layer 102 and the word lines 110.

[0057] As described herein, the first channel material 120L may be deposited using any suitable deposition process. In various embodiments, the first channel material 120L may be made of a semiconductor material such as polysilicon, amorphous silicon, or a semiconductor material such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaO x 、InO x The dopant level in the metal oxide semiconductor material can be selected so that the leakage current through the metal oxide semiconductor material during device operation is negligible. For example, the dopant level in the metal oxide semiconductor material can be 1.0×10 10 / cm 3 to 2.0×10 16 / cm 3 range, but smaller or larger dopant concentrations may also be used.

[0058] The first channel material 120L may be deposited, for example, by chemical vapor deposition. The first channel material 120L may be deposited as a layer having an overall uniform thickness, such as a thickness in the range of 2 nm to 60 nm, such as in the range of 4 nm to 20 nm, although lesser or greater thicknesses may also be used.

[0059] refer to Figure 2EA photoresist layer 101 may be applied over the first channel material 120L. The photoresist layer 101 may be photolithographically patterned to form a line pattern comprising strips of photoresist material extending laterally along a first horizontal direction. An anisotropic etching process may be performed to etch unmasked portions of the first channel material 102L. A first channel layer 120 extending along the first horizontal direction may be formed by etching away the unmasked portions of the first channel material 120L. An anisotropic etching process that is selective to the underlying gate dielectric layer 116 may be performed on the first channel material 120L. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0060] refer to Figure 2F , the second channel material 122H may be conformally deposited on the first channel layer 120 and the gate insulating layer 116. In various embodiments, the second channel material 120H may be made of a semiconductor material such as polysilicon, amorphous silicon, or a semiconductor material such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaO x 、InO x However, the first channel material 120L and the second channel material 122H may be formed of respective semiconductor materials having different resistances (eg, different “on” resistances), band gaps, and / or threshold voltages.

[0061] Specifically, the second channel material 122H may include any suitable semiconductor material, as long as the second channel material 122H has a higher resistance, bandgap, and / or threshold voltage than the material of the first channel layer 120 (i.e., the first channel material 120L). The second channel material 122H may directly contact the top surface and side surfaces of the first channel layer 120.

[0062] refer to Figure 2G The second channel material 122H may be patterned to form the second channel layer 122. Specifically, a patterned photoresist layer 101 may be formed on the second channel material 122H, and the second channel material 122H may be etched using any suitable etching process (such as a wet etching process or a dry etching process) using the photoresist layer 101 as a mask to form the second channel layer 122.

[0063] In some embodiments, the etching process may optionally include etching a portion of the gate insulating layer 116. Specifically, a portion of the gate insulating layer 116 that does not overlap with the second channel layer 122 may be optionally removed during the etching process.

[0064] In various embodiments, the first channel layer 120 and the second channel layer 122 may have different resistances. For example, in some embodiments, the first channel layer 120 may have a lower resistance than the second channel layer 122. The first channel layer 120 may be formed of a semiconductor material (e.g., semiconductor material 120L) having a lower resistance, band gap, and / or threshold voltage than the semiconductor material (e.g., semiconductor material 122L) of the second channel layer 122. In other words, when a voltage is applied to the word line 110, the first channel layer 120 may have a lower resistance than the second channel layer 122. For example, the first channel layer 120 may be formed of polysilicon, InO, ITO, SnO2, or a first type of IGZO, and the second channel layer 122 may be formed of Ga2O3, GZO, or a second type of IGZO. The first type of IGZO may have a lower Ga at% or a higher In at% than the second type of IGZO. In some embodiments, the sheet resistance of the first channel layer 120 may be at 1e. 3 Ω / square to 1e 4 Ω / square, and the sheet resistance of the second channel layer 122 may be within the range of 4e 3 Ω / square to 2e 4 The sheet resistance is in the range of Ω / square. The sheet resistance is related to the channel mobility.

[0065] refer to Figure 2H A second dielectric layer 106 may be deposited on the second channel layer 122 and the gate insulating layer 116. Specifically, the photoresist layer 101 may be removed, for example, by ashing, and the second dielectric layer 106 may be formed by depositing any suitable dielectric material using any suitable deposition process as described herein.

[0066] refer to Figure 2I A photoresist layer 101 may be applied over the second dielectric layer 106. The photoresist layer 101 may be photolithographically patterned to form two openings in the photoresist layer 101. An anisotropic etching process may be used to form active area electrode via cavities 105 in the second dielectric layer 106, with the top surface of the second channel layer 122 exposed at the bottom of each active area electrode via cavity 105. The anisotropic etching may use any suitable etching process, such as a wet etching process or a dry etching process, to form the active area electrode via cavity 105. The photoresist layer 101 may then be removed, for example, by ashing.

[0067] refer to Figure 2J, active region (source and drain) electrodes 112, 114 may be formed in the active region electrode via cavity 105. Specifically, a conductive material may be deposited on the second dielectric layer 106 and in the active region electrode via cavity 105. A planarization process, such as CMP, may then be performed to planarize the upper surfaces of the source and drain electrodes 112, 114 and the second dielectric layer 106 to remove excess metal fill material and form a coplanar top surface of the source and drain electrodes 112, 114 and the second dielectric layer 106. After the source and drain electrodes 112, 114 are completed, the double-layer channel transistor 200 may be formed.

[0068] Figure 3A is a top view of a double-layer channel transistor 300 with partially transparent layers according to various embodiments of the present disclosure. The partially transparent layers illustrate the positioning of certain elements relative to each other in the embodiment double-layer channel transistor 300. Figure 3B It is along Figure 3A The corresponding vertical cross-sectional view taken along the line AA' of FIG. Figure 3A and Figure 3B , a double-layer channel transistor 300 may be formed on a semiconductor substrate 100 during a back-end-of-line (BEOL) process. Specifically, as Figure 1A-1C As shown, the double-layer channel transistor 300 can be included in an interconnect structure of a semiconductor device. The embodiment transistor includes a double-layer channel 125, which includes a buried first channel layer 120. Specifically, at least a portion of the first channel layer 120 can be embedded in the second channel layer 122. The first channel layer 120 can be formed of a semiconductor or conductive material that has a lower resistance than the second channel layer 122 when a voltage is applied to the word line 110. For example, the first channel layer 120 can include polysilicon, InO, ITO, SnO2, or a first type of IGZO, and the second channel layer 122 can include Ga2O3, GZO, or a second type of IGZO. The first type of IGZO can have a lower Ga at% or a higher In at% than the second type of IGZO. In some embodiments, the sheet resistance of the first channel layer 120 can be in the range of 1e 3 Ω / square to 1e 4 Ω / square. For example, the first channel layer 120 may be conductive and include a metal such as copper, aluminum, gold, silver, platinum, alloys thereof, etc. The sheet resistance of the second channel layer 122 may be in the range of 4e 3 Ω / square to 2e 4 The sheet resistance is in the range of Ω / square. The sheet resistance is related to the channel mobility.

[0069] The source electrode 112 and the drain electrode 114 may be disposed on the double-layer channel 125. Specifically, the source electrode 112 may be electrically coupled to the source region of the double-layer channel 125, and the drain electrode 114 may be electrically coupled to the drain region of the double-layer channel 125. As described herein, the source electrode 112 and the drain electrode 114 may be formed of any suitable conductive material.

[0070] The word line 110 may have a width G greater than the width W of the first channel layer 120. Therefore, the first channel layer 120 may completely overlap the word line 110 in a vertical direction (e.g., a direction perpendicular to the plane of the substrate 100). The portion of the word line 110 overlapping the double-layered channel 125 may serve as a gate electrode of the transistor 300.

[0071] The source electrode 112 and the drain electrode 114 may be separated from each other by a channel width C. The channel width C may be smaller than the width G of the word line 110, such that the source electrode 112 and the drain electrode 114 overlap opposing portions of the word line 110. In some embodiments, the channel width C may be smaller than the width W of the first channel layer 120. In this way, the source electrode 112 and the drain electrode 114 may vertically overlap opposing portions of the first channel layer 120 and opposing portions of the word line 110. However, in some embodiments, the channel width C may be larger than the width W of the first channel layer 120 and may be smaller than the width G of the word line 110. In this way, the source electrode 112 and the drain electrode 114 may vertically overlap only opposing portions of the word line 110.

[0072] In operation, when a gate voltage is applied to the word line 110, current can flow from the source electrode 112 to the drain electrode 114 through the double-layer channel 125. Specifically, because the first channel layer 120 has a lower resistance than the second channel layer 122, at least some of the current can preferentially flow through the first channel layer 120 when the current passes through the double-layer channel 125. In other words, the current can flow from the source electrode 112 through the width W of the first channel layer 120 into the first region 122S (e.g., the source region) of the second channel layer 122, and before flowing into the drain electrode 114, flow into the second region 122D (e.g., the drain region) of the second channel layer 122, as shown in FIG. Figure 3B As shown by the dotted arrow in .

[0073] Therefore, since the first channel layer 120 provides a lower resistance path for current compared to the second channel layer 122, the first channel layer 120 can be configured to reduce the total channel resistance of the transistor 200. In addition, before entering the first channel layer 120 and after leaving the first channel layer 120, since the current flows through the source region 122S of the second channel layer 122 and the drain region 122D of the second channel layer 122, the source region 122S and the drain region 122D of the second channel layer 122 can serve as current control regions because the threshold voltage of the second channel layer 122 can be higher than the threshold voltage of the first channel layer 120. Therefore, the total resistance of the effective channel (R total ) can be represented by the following series resistances: R total =R 沟道_源极112 +(R 第二沟道源极区域122S +R 第一沟道层120 +R 第二沟道漏极区域122D )+R 沟道_漏极114 The total resistance can be reduced by including a lower resistance material of the first channel layer 120. The threshold voltage V th It may be defined by the energy gap (Eg) of the second channel layer 122 material having a higher energy gap compared to the energy gap of the first channel layer 120 material.

[0074] In another embodiment, and with reference to Figure 4A-4G , you can use Figure 2A-2J The same process steps as shown are used to form the double-layer channel transistor 400. As described above, in the double-layer channel transistor 300, the second channel layer 122 can be formed of a material having a higher resistance than the material used to form the first channel layer 120. However, referring to Figure 5B In the illustrated double-layer channel transistor 400, unlike the double-layer channel 125 of the double-layer channel transistor 300, the first channel layer 120 of the double-layer channel 125A may have a higher resistance, bandgap, and / or threshold voltage than the second channel layer 122. For example, in the double-layer channel transistor 400, the first channel layer 120 and the second channel layer 122 may be formed of a semiconductor material, such that the first channel layer 120 has a higher resistance, bandgap, and / or threshold voltage than the second channel layer 122.

[0075] In some embodiments, the second channel layer 122 may be formed of a semiconductor material, and the first channel layer 120 may be formed of a resistive material having a higher resistance than the semiconductor material of the second channel layer 122 (when a voltage is applied to the word line 110 ).

[0076] Figure 4A-4G 4 is a vertical cross-sectional view showing various steps for manufacturing a double-layer channel transistor 400 according to various embodiments of the present disclosure. Figure 4A , you can Figure 2CA gate dielectric layer 116 and a first channel material 120H are deposited over the first dielectric layer 102 and the word lines 110 of the intermediate structure shown. The gate dielectric material of the gate dielectric layer 116 may include a gate dielectric material such as silicon oxide, silicon oxynitride, a dielectric metal oxide, or a combination thereof. Other suitable dielectric materials are within the contemplated scope of the present disclosure. The thickness of the gate dielectric layer 116 may be in a range from 1 nm to 12 nm, such as from 2 nm to 6 nm, although smaller and larger thicknesses may also be used. Typically, the gate dielectric layer 116 may be formed over the first dielectric layer 102 and the word lines 110. The gate dielectric layer 116 may be formed by depositing a gate dielectric material over the first dielectric layer 102 and the word lines 110.

[0077] As described herein, the first channel material 120H may be deposited using any suitable deposition process. In various embodiments, the first channel material 120H may be made of a semiconductor material such as polysilicon, amorphous silicon, or a semiconductor material such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaO x 、InO x The dopant level in the metal oxide semiconductor material can be selected so that the leakage current through the metal oxide semiconductor material during device operation is negligible. For example, the dopant level in the metal oxide semiconductor material can be 1.0×10 10 / cm 3 to 2.0×10 16 / cm 3 range, but smaller or larger dopant concentrations may also be used.

[0078] The first channel material 120H may be deposited, for example, by chemical vapor deposition.The first channel material 120H may be a layer having an overall uniform thickness, such as a thickness in the range of 2 nm to 60 nm, such as in the range of 4 nm to 20 nm, although lesser or greater thicknesses may also be used.

[0079] refer to Figure 4B, a photoresist layer 101 may be applied over the first channel material 120H. The photoresist layer 101 may be photolithographically patterned to form a line pattern comprising strips of photoresist material extending laterally along a first horizontal direction. An anisotropic etching process may be performed to etch unmasked portions of the first channel material 102H. A channel layer 120 extending along the first horizontal direction may be formed by etching away the unmasked portions of the first channel material 120H. An anisotropic etching process that is selective to the underlying gate dielectric layer 116 may be performed on the first channel material 120H. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process. The photoresist layer 101 may then be removed, for example, by ashing.

[0080] refer to Figure 4C , the second channel material 122L may be conformally deposited on the first channel layer 120 and the gate insulating layer 116. In various embodiments, the second channel material 120L may be made of a semiconductor material such as polysilicon, amorphous silicon, or a semiconductor material such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaO x 、InO x However, the first channel material 120H and the second channel material 122L may be formed of respective semiconductor materials having different resistances (eg, different “on” resistances), band gaps, and / or threshold voltages.

[0081] Specifically, the second channel material 122L can be deposited using any suitable deposition method and any suitable semiconductor material, as long as the second channel material 122L has a lower resistance, bandgap, and / or threshold voltage than the material of the first channel layer 120 (i.e., the first channel material 120H). The second channel material 122L can directly contact the top surface and side surfaces of the first channel layer 120.

[0082] In various embodiments, the first channel material 120H and the second channel material 122L may have different resistances, band gaps, and / or threshold voltages. For example, in some embodiments, the first channel material 120H may have a higher resistance than the second channel material 122L.

[0083] refer to Figure 4D The second channel material 122L may be patterned to form the second channel layer 122. Specifically, a patterned photoresist layer 101 may be formed on the second channel material 122L, and the second channel material 122L may be etched using any suitable etching process (such as a wet etching process or a dry etching process) using the photoresist layer 101 as a mask to form the second channel layer 122.

[0084] In some embodiments, the etching process may optionally include etching a portion of the gate insulating layer 116. Specifically, a portion of the gate insulating layer 116 that does not overlap with the second channel layer 122 may be optionally removed during the etching process.

[0085] When a voltage is applied to the word line 110, the first channel layer 120 may have a higher resistance than the second channel layer 122. For example, the first channel layer 120 may include amorphous silicon, Ga2O3, GZO, or a first type of IGZO, and the second channel layer 122 may include polysilicon, InO, ITO, SnO2, or a second type of IGZO, wherein the first type of IGZO has a higher Ga at% or a lower In at% than the second type of IGZO. In some embodiments, the sheet resistance of the first channel layer 120 may be 4e 3 Ω / square to 2e 4 Ω / square, and the sheet resistance of the second channel layer 122 may be within the range of 1e 3 Ω / square to 1e 4 In the range of Ω / square.

[0086] refer to Figure 4E A second dielectric layer 106 may be deposited on the second channel layer 122 and the gate insulating layer 116. Specifically, the photoresist layer 101 may be removed, for example, by ashing, and the second dielectric layer 106 may be formed by depositing any suitable dielectric material using any suitable deposition process as described herein.

[0087] refer to Figure 4F A photoresist layer 101 may be applied over the second dielectric layer 106. The photoresist layer 101 may be photolithographically patterned to form two openings in the photoresist layer 101. An anisotropic etching process may be used to etch the second dielectric layer 106 to form active area electrode via cavities 105 in the second dielectric layer 106, with the top surface of the second channel layer 122 exposed at the bottom of each active area electrode via cavity 105. The anisotropic etching process may use any suitable etching process, such as a wet etching process or a dry etching process, to form the active area electrode via cavity 105. The photoresist layer 101 may then be removed, for example, by ashing.

[0088] refer to Figure 4G, active region (source and drain) electrodes 112, 114 may be formed in the active region electrode through-hole cavity 105. Specifically, a conductive material may be deposited on the second dielectric layer 106 and in the active region electrode through-hole cavity 105. A planarization process, such as CMP, may then be performed to planarize the upper surfaces of the source and drain electrodes 112, 114 and the second dielectric layer 106 to remove excess metal fill material and form a coplanar top surface of the source and drain electrodes 112, 114 and the second dielectric layer 106. After the source and drain electrodes 112, 114 are completed, the double-layer channel transistor 400 may be formed.

[0089] Figure 5A is a top semi-transparent plan view of a double-layer channel transistor 500 according to various embodiments of the present disclosure. Figure 5B It is along Figure 5A A vertical cross-sectional view taken along line AA'. Figure 5A and Figure 5B The double-layer channel transistor 500 may include a double-layer channel 125A disposed between the gate insulating layer 116, the source electrode 112, and the drain electrode 114. The double-layer channel 125A may include a first channel layer 120 and a second channel layer 122 covering a top surface and side surfaces of the first channel layer 120.

[0090] A channel width C taken between the source electrode 112 and the drain electrode 114 may be smaller than a width W of the first channel layer 120. The width W of the first channel layer 120 may be smaller than a width G of the word line 110. The source electrode 112 and the drain electrode 114 may vertically overlap with opposing portions of the word line 110. In some embodiments, the source electrode 112 and the drain electrode 114 may also vertically overlap with opposing portions of the first channel layer 120.

[0091] During operation of the dual-layer channel transistor 500, when a voltage is applied to the word line 110, the portion of the word line 110 disposed below the dual-layer channel 125A can function as a gate electrode. Specifically, current can flow from the source electrode 112 through the portion of the second channel layer 122 disposed above the first channel layer 120, into the source region 122S of the second channel layer 122, and into the drain region 122D of the second channel layer 122 before entering the drain electrode 114, as indicated by the dashed arrow. Due to the relatively higher resistance of the first channel layer 120 compared to the second channel layer 122, current can preferentially flow through the second channel layer 122 rather than through the first channel layer 120. In other words, since the current is directed away from the bulk of the dual-layer channel 125A by the first channel layer 120, the first channel layer 120 can be configured to shorten the current path through the dual-layer channel 125A. Because the second channel 122 has a lower resistance, more current can flow through the second channel 122 compared to the first channel 120, as shown by the dashed line in the figure. This can also be explained by the Ec band shift. For example, the electron affinity of the second channel 122 is greater than that of the first channel 120, indicating that charge can easily accumulate in the second channel 122. In this case, as the gate voltage increases, the current tends to flow through the second channel 122 before flowing through the first channel 120. Therefore, the resistance of the double-layer channel 125A can be reduced. The buried first channel layer 120 can enhance carrier mobility to reduce scattering effects.

[0092] Figure 6A is a top semi-transparent plan view of a double-layer channel transistor 600 according to another embodiment of the present disclosure. Figure 6B It is along Figure 6A The double-layer channel transistor 600 may be similar to Figure 3A and Figure 3B As shown, a double-layer channel transistor 300 is shown. As such, only the differences therebetween will be discussed in detail, and like reference numerals refer to like elements.

[0093] refer to Figure 6A and Figure 6B, the channel width C between the source electrode 112 and the drain electrode 114 of the double-layer channel transistor 600 can be greater than the channel width C of the double-layer channel transistor 300. In other words, the channel width C can be greater than the width G of the word line 110. In this way, the source electrode 112 and the drain electrode 114 can not vertically overlap with the word line 110 or the first channel layer 120. In the portion of the double-layer channel 125 located above the word line 110, the current can be controlled by the gate voltage applied to the word line 110, and the source electrode 112 and the drain electrode 114 do not directly overlap with the word line 110. Therefore, the parasitic capacitance in the double-layer channel 125 adjacent to the source electrode 112 and the drain electrode 114 can be reduced.

[0094] Figure 7A is a top plan view of a double-layer channel transistor 700 according to another embodiment of the present disclosure. Figure 7B It is along Figure 7A The double-layer channel transistor 700 may be similar to Figures 4A-5B The double-layer channel transistors 400 and 500 are shown. As such, only the differences between them will be discussed in detail, and like reference numerals refer to like elements.

[0095] refer to Figure 7A and Figure 7B , the channel width C between the source electrode 112 and the drain electrode 114 of the double-layer channel transistor 700 may be greater than Figures 4A-5B In other words, the channel width C may be greater than the width G of the word line 110 . In this way, the source electrode 112 and the drain electrode 114 may not vertically overlap with the word line 110 or the first channel layer 120 .

[0096] Figure 8 is a flow chart of a method of forming a double-layer channel transistor 200, 300, 400, 500, 600, and 700 according to various embodiments of the present disclosure. Figure 8 and Figures 2A-7BIn operation 801, a first dielectric layer 102 may be deposited over a substrate 100. In operation 802, the first dielectric layer 102 may be patterned to form wordline trenches 103. In operation 803, a metal fill material may be deposited over the first dielectric layer 102 and in the wordline trenches 103 to form wordlines 110. The first dielectric layer 102 and the wordlines 110 may be planarized such that the top surfaces of the first dielectric layer 102 and the wordlines are coplanar. In operation 804, a gate dielectric layer 116 and a first channel layer 120 (L / H) material may be sequentially deposited over the first dielectric layer 102 and the wordlines 110. In operation 805, the first channel layer 120 (L / H) material may be patterned to form a first channel layer 120. In operation 806, a second channel layer 122 (H / L) material may be deposited over the first channel layer 120 and the gate dielectric layer 116.

[0097] In the embodiments forming the dual-layer channel transistors 200, 300, and 600, the second channel material 122H has a higher resistance, bandgap, and / or threshold voltage than the first channel material 120L. In the embodiments forming the dual-layer channel transistors 400, 500, and 700, the second channel material 122L has a lower resistance, bandgap, and / or threshold voltage than the first channel material 120H. In operation 807, the second channel layer 122 (H / L) may be patterned to form the second channel layer 122. In operation 808, a second dielectric layer 106 may be deposited over the second channel layer 122 and the gate dielectric layer 116. In operation 809, the second dielectric layer 106 may be patterned to form the active area electrode via cavity 105. In operation 810, a metal fill material may be deposited over the second dielectric layer 106 and in the active area electrode via cavity 105 to form a source electrode 112 and a drain electrode 114. The second dielectric layer 106 and the source electrode 112 and the drain electrode 114 may be planarized so that the top surfaces of the second dielectric layer 102, the source electrode 112, and the drain electrode 114 are coplanar.

[0098] In various embodiments, operations 809 and 810 may be modified so that the active area electrode via cavity 105 may be positioned further apart so that the source electrode 112 and the drain electrode 114 are separated by a channel width C that is greater than the width W of the word line 110 to form Figure 6A 、 Figure 6B and Figure 7A 、 Figure 7B Double-channel transistors 600 and 700 .

[0099] According to various embodiments, a transistor including a double-layer channel including a low-resistance channel layer and a high-resistance channel layer is provided. The double-layer channel can be configured to reduce the total channel resistance of the double-layer channel transistor by reducing the resistance of at least a portion of the double-layer channel and / or by reducing the length of a current path flowing through the double-layer channel.

[0100] Various embodiments provide a double-layer channel transistor 200, 300, 400, 500, 600, 700, which includes: a substrate 100; a word line 110, disposed on the substrate 100; a gate dielectric layer 116, disposed on the word line 110; a double-layer semiconductor channel 125, including a first channel layer 120 having a first resistance and disposed on the gate dielectric layer 116 and a second channel layer 122 having a second resistance different from the first resistance and disposed on the first channel layer 120, such that the second channel layer 122 contacts the side and top surfaces of the first channel layer 120; and a source electrode 112 and a drain electrode 114, electrically coupled to the second channel layer 122.

[0101] Various embodiments provide a method for forming a dual-layer channel transistor 200, 300, 400, 500, 600, 700, wherein the method includes the following operations: depositing a first dielectric layer 102 on a semiconductor substrate 100; forming a word line 110 in the first dielectric layer 102; depositing a gate dielectric layer 116 over the word line 110; forming a dual-layer channel 125 on the gate dielectric layer 116 by the following steps: depositing a first channel layer 120L having a first resistance on the gate dielectric layer 116; depositing a second channel layer 122 having a second resistance different from the first resistance on the first channel layer 120, such that the second channel layer 122 contacts the side and top surfaces of the first channel layer 120. The embodiment method also includes the following operations: depositing a second dielectric layer 106 on the second channel layer 122; and forming a source electrode 112 and a drain electrode 114 in the second dielectric layer 106.

[0102] According to one embodiment of the present application, a transistor is provided, comprising: a substrate; a word line disposed on the substrate; a gate dielectric layer disposed on the word line; a double-layer semiconductor channel, comprising: a first channel layer disposed on the gate dielectric layer and having a first resistance; and a second channel layer disposed on the first channel layer and having a second resistance different from the first resistance, such that the second channel layer contacts a side surface and a top surface of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer. In some embodiments, the first resistance is higher than the second resistance. In some embodiments, the first channel layer comprises amorphous silicon, Ga2O3, GZO, or a first type of IGZO; the second channel layer comprises polysilicon, InO, ITO, SnO2, or a second type of IGZO; and the first type of IGZO has a higher Ga at% or a lower In at% than the second type of IGZO. In some embodiments, the second resistance is higher than the first resistance. In some embodiments, the first channel layer comprises polysilicon, InO, ITO, SnO2, or a second type of IGZO; the second channel layer comprises amorphous silicon, Ga2O3, GZO, or a first type of IGZO; and the first type of IGZO has a higher Ga at% or a lower In at% than the second type of IGZO. In some embodiments, the width of the first channel layer is less than the width of the word line. In some embodiments, the source electrode and the drain electrode overlap opposite portions of the word line in a vertical direction perpendicular to the plane of the substrate. In some embodiments, the source electrode and the drain electrode overlap opposite portions of the first channel layer in a vertical direction. In some embodiments, the width between the source electrode and the drain electrode is greater than the width of the word line. In some embodiments, the first channel layer has a higher bandgap than the second channel layer. In some embodiments, the first channel layer has a lower bandgap than the second channel layer. In some embodiments, the transistor further comprises a first dielectric layer disposed on the substrate, wherein the word line is embedded in the first dielectric layer. In some embodiments, the transistor further comprises a second dielectric layer disposed on the second channel layer and embedded in the source and drain electrodes. In some embodiments, the first channel layer has a different threshold voltage than the second channel layer.

[0103] According to another embodiment of the present application, a transistor is provided, comprising: a substrate; a word line disposed on the substrate; a gate dielectric layer disposed on the word line; a double-layer channel disposed on the gate dielectric layer and comprising: a first channel layer disposed on the gate dielectric layer; and a second channel layer comprising a semiconductor material and disposed on the first channel layer, such that the second channel layer contacts the side and top surfaces of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer, wherein, in response to a voltage applied to the word line, the first channel layer has a first resistance, and the second channel layer has a second resistance higher than the first resistance. In some embodiments, the first channel layer comprises a metal or a metal alloy having the first resistance. In some embodiments, the first channel layer is configured to reduce the total resistance of the transistor's effective channel by shortening the length of a conductive path through the double-layer channel.

[0104] According to another embodiment of the present application, a method for forming a semiconductor device is provided, comprising: depositing a first dielectric layer on a semiconductor substrate; forming a word line in the first dielectric layer; depositing a gate dielectric layer above the word line; forming a double-layer channel on the gate dielectric layer, by: depositing a first channel layer having a first resistance on the gate dielectric layer; and depositing a second channel layer having a second resistance different from the first resistance on the first channel layer, such that the second channel layer contacts a side surface and a top surface of the first channel layer, wherein the second channel layer comprises a semiconductor material, and depositing a second dielectric layer on the second channel layer; and forming a source electrode and a drain electrode in the second dielectric layer. In some embodiments, wherein: depositing the first channel layer comprises depositing amorphous silicon, Ga2O3, GZO, or a first type of IGZO; depositing the second channel layer comprises depositing polysilicon, InO, ITO, SnO2, or a second type of IGZO; and the first type of IGZO has a higher Ga at% or a lower In at% than the second type of IGZO. In some embodiments, wherein: depositing the first channel layer includes depositing polysilicon, InO, ITO, SnO2 or a second type of IGZO; depositing the second channel layer includes depositing amorphous silicon, Ga2O3, GZO or a first type of IGZO; and the first type of IGZO has a higher Ga at% or a lower In at% than the second type of IGZO.

[0105] The components of several embodiments have been discussed above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art will appreciate that it is easy to use this disclosure as a basis to design or change other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various variations, replacements, and changes may be made without departing from the spirit and scope of the present invention.

Claims

1. A transistor comprising: substrate; A word line is provided on the substrate; a gate dielectric layer disposed on the word line; Double-layer semiconductor channel, comprising: a first channel layer disposed on the gate dielectric layer and having a first resistance; and a second channel layer disposed on the first channel layer and having a second resistance different from the first resistance, such that the second channel layer contacts a side surface and a top surface of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer; The first resistor is higher than the second resistor.

2. The transistor according to claim 1, wherein The thickness of the first channel layer is in the range of 2 nm to 60 nm.

3. The transistor according to claim 2, wherein: The first channel layer includes amorphous silicon, Ga2O3, GZO or a first type of IGZO; The second channel layer includes polysilicon, InO, ITO, SnO2 or a second type of IGZO; and The first type IGZO has a higher Ga at % or a lower In at % than the second type IGZO.

4. The transistor according to claim 1, wherein The sheet resistance of the first channel layer is 4e 3 Ω / square to 2e 4 In the range of Ω / square.

5. The transistor according to claim 1, wherein The sheet resistance of the second channel layer is 1e 3 Ω / square to 1e 4 In the range of Ω / square. The transistor according to claim 1 , wherein: The width of the first channel layer is smaller than the width of the word line.

7. The transistor according to claim 6, wherein The source electrode and the drain electrode overlap opposite portions of the word line in a vertical direction perpendicular to a plane of the substrate.

8. The transistor according to claim 1, wherein The source electrode and the drain electrode overlap opposite portions of the first channel layer in a vertical direction.

9. The transistor according to claim 6, wherein A width between the source electrode and the drain electrode is greater than a width of the word line.

10. The transistor according to claim 1, wherein The first channel layer has a higher band gap than the second channel layer.

11. The transistor according to claim 1, wherein The first channel layer has a lower band gap than the second channel layer.

12. The transistor according to claim 1, further comprising a first dielectric layer disposed on the substrate, wherein The word lines are embedded in the first dielectric layer. 13 . The transistor according to claim 12 , further comprising a second dielectric layer disposed on the second channel layer and embedding the source electrode and the drain electrode.

14. The transistor according to claim 1, wherein The first channel layer has a different threshold voltage from that of the second channel layer.

15. A transistor comprising: substrate; A word line is provided on the substrate; a gate dielectric layer disposed on the word line; A double-layer channel is disposed on the gate dielectric layer and comprises: a first channel layer disposed on the gate dielectric layer; and a second channel layer comprising a semiconductor material and disposed on the first channel layer such that the second channel layer contacts a side surface and a top surface of the first channel layer; and a source electrode and a drain electrode electrically coupled to the second channel layer, The first channel layer has a first resistance in response to a voltage applied to the word line, and the second channel layer has a second resistance lower than the first resistance.

16. The transistor according to claim 15, wherein The first channel layer includes a metal or a metal alloy having the first resistance.

17. The transistor according to claim 15, wherein The first channel layer is configured to reduce an overall resistance of an effective channel of the transistor by shortening a length of a conductive path through the double-layer channel.

18. A method of forming a semiconductor device, comprising: depositing a first dielectric layer on the semiconductor substrate; forming a word line in the first dielectric layer; depositing a gate dielectric layer over the word line; forming a double-layer channel on the gate dielectric layer by: depositing a first channel layer having a first resistance on the gate dielectric layer; and depositing a second channel layer having a second resistance different from the first resistance on the first channel layer so that the second channel layer contacts a side surface and a top surface of the first channel layer, wherein the second channel layer comprises a semiconductor material, depositing a second dielectric layer on the second channel layer; and forming a source electrode and a drain electrode in the second dielectric layer; The first resistor is higher than the second resistor.

19. The method for forming a semiconductor device according to claim 18, wherein: in: Depositing the first channel layer includes depositing amorphous silicon, Ga2O3, GZO, or a first type of IGZO; Depositing the second channel layer includes depositing polysilicon, InO, ITO, SnO2, or a second type of IGZO; and The first type IGZO has a higher Ga at % or a lower In at % than the second type IGZO.

20. The method for forming a semiconductor device according to claim 18, wherein: The thickness of the gate dielectric layer ranges from 1 nm to 12 nm.

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