Signal Receiver and Its Operating Method

Abstract

A signal receiver and an operation method thereof are provided. The signal receiver includes: a data sampler that receives a differential input signal having a first input signal and a second input signal, and determines a bit value of the differential input signal based on a first reference voltage and a second reference voltage; and a reference voltage generator that performs a pre-tuning operation and a post-tuning operation to generate the reference voltage. The reference voltage generator performs the pre-tuning operation by generating a first initial voltage and a second initial voltage and adjusting one of the initial voltages to generate a third voltage and a fourth voltage. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by: based on a first comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and the second input signal, increasing or decreasing the third voltage to generate the first reference voltage, and decreasing or increasing the fourth voltage to generate the second reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0041137 filed on April 3, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concepts disclosed herein relate to electronic devices, and more particularly, to a signal receiver and an operating method thereof. Background Art

[0004] Electronic devices include various functional blocks or devices configured to provide various functions. To provide these functions, the various functional blocks or devices may exchange data. Typically, data transmission between these functional blocks or devices is performed by transmitting one bit within one unit interval (UI) using a modulation scheme, such as a non-return-to-zero (NRZ) scheme.

[0005] As the performance of electronic devices increases, it is expected to achieve high communication speeds between functional blocks or devices. To this end, a modulation scheme (e.g., PAM-4) can be used to transmit multiple bits (e.g., two bits) within one unit interval. In the PAM-4 scheme, a signal receiver determines the bit value of a received input signal by using a predetermined plurality of reference voltages (e.g., three reference voltages). However, if distortion occurs in the input signal, the bit value cannot be properly determined by the reference voltage. Summary of the Invention

[0006] Embodiments of the inventive concept provide a signal receiver with improved reliability and an operating method thereof.

[0007] According to an exemplary embodiment of the present invention, a signal receiver includes: a data sampler configured to receive a differential input signal having a first input signal and a second input signal, the second input signal being a complementary signal of the first input signal, and determine a bit value of the differential input signal based on a first reference voltage and a second reference voltage; and a reference voltage generator configured to perform a pre-tuning operation and a post-tuning operation to generate the first reference voltage and the second reference voltage. The reference voltage generator performs the pre-tuning operation by: generating a first initial voltage and a second initial voltage based on the first input signal and the second input signal, and adjusting one of the first initial voltage and the second initial voltage to generate a third voltage and a fourth voltage. After performing the pre-tuning operation, the reference voltage generator performs the post-tuning operation by: increasing or decreasing the third voltage to generate the first reference voltage, and decreasing or increasing the fourth voltage to generate the second reference voltage, based on a first comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and the second input signal.

[0008] According to an exemplary embodiment of the present invention, a method of operating a signal receiver includes: receiving a differential input signal having a first input signal and a second input signal, the second input signal being a complementary signal of the first input signal; performing a pre-tuning operation, the pre-tuning operation including: generating a first peak voltage, a second peak voltage, and a common voltage based on the first input signal and the second input signal, wherein the first peak voltage is greater than the second peak voltage, and wherein the common voltage is between the first peak voltage and the second peak voltage; setting a first initial voltage and a second initial voltage, wherein the first initial voltage and the second initial voltage are between the first peak voltage and the second peak voltage; and increasing or decreasing one of the first initial voltage and the second initial voltage to generate a first voltage and a second voltage until the first voltage and the second voltage satisfy a first condition; after performing the pre-tuning operation, performing a post-tuning operation to generate a first optimized reference voltage and a second optimized reference voltage; the post-tuning operation including: gradually increasing or decreasing the first voltage and gradually decreasing or increasing the second voltage to generate the first optimized reference voltage and the second optimized reference voltage until the first optimized reference voltage and the second optimized reference voltage satisfy a second condition, wherein during the post-tuning operation, the increased or decreased first voltage and the decreased or increased second voltage satisfy the first condition; and determining a bit value of the differential input signal based on the first optimized reference voltage and the second optimized reference voltage.

[0009] According to an exemplary embodiment of the present invention, a method of operating a signal receiver includes: performing an initialization operation to generate a first reference voltage and a second reference voltage; receiving a differential input signal having a first input signal and a second input signal from an external device, where the second input signal is a complementary signal of the first input signal; determining a first bit value of the differential input signal based on the first reference voltage and the second reference voltage, where the differential input signal is an N-level PAM multi-level signal and N is greater than or equal to 4; detecting whether the differential input signal is distorted based on the determined first bit value of the differential input signal; in response to detecting the distortion, performing a pre-tuning operation by: adjusting one of the first reference voltage and the second reference voltage based on the first input signal and the second input signal to generate a first voltage and a second voltage; performing a post-tuning operation by: increasing or decreasing the first voltage to generate a first optimized reference voltage and decreasing or increasing the second voltage to generate a second optimized reference voltage based on a first comparison result between the first voltage and the first input signal and a second comparison result between the second voltage and the second input signal; and determining a bit value of the differential input signal based on the first optimized reference voltage and the second optimized reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the inventive concept will become apparent by describing in detail its exemplary embodiments with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram showing an electronic device according to an embodiment of the inventive concept.

[0012] Figure 2A and Figure 2B is a graph showing a data eye for describing 4-level pulse amplitude modulation.

[0013] Figure 3 is a block diagram showing a signal receiver according to an embodiment of the inventive concept.

[0014] Figure 4 is a diagram showing Figure 3 a data sampler.

[0015] Figure 5 is a diagram showing Figure 3 a reference voltage generator.

[0016] Figure 6 is a diagram showing Figure 5 a peak voltage tracking circuit.

[0017] Figure 7 is a diagram showing Figure 5Diagram of a common voltage tracking circuit.

[0018] Figure 8 Shows Figure 5 Diagram of a reference voltage tracking circuit.

[0019] Figure 9 Shows Figure 8 Diagram of a pre - tuning control unit.

[0020] Figure 10 Shows Figure 3 Flowchart of the operation of a signal receiver.

[0021] Figures 11A to 11D Is a diagram for describing how a signal receiver tracks and optimizes a reference voltage based on Figure 10 the flowchart.

[0022] Figure 12 Shows Figure 3 Flowchart of the operation of a signal receiver.

[0023] Figure 13 Is a block diagram of a memory system according to an embodiment of the inventive concept.

[0024] Figure 14 Is a block diagram of an electronic device according to the inventive concept. Detailed Description of the Invention

[0025] Hereinafter, embodiments of the inventive concept will be described in detail and clearly to such an extent that an ordinary person skilled in the art can easily implement the inventive concept.

[0026] Hereinafter, components described using terms such as "component" and "unit" in the specification and functional blocks shown in the drawings can be implemented by software, hardware, or a combination thereof. For example, the software can be machine code, firmware, embedded code, or application software. For example, the hardware can include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, micro - electromechanical systems (MEMS), passive components, or a combination thereof.

[0027] In addition, unless otherwise defined, all terms including technical or scientific terms used herein have the same meaning as understood by a person skilled in the art to which the inventive concept belongs. Terms defined in a commonly used dictionary should be interpreted as having the same meaning as their context in the relevant technical field unless clearly defined in the specification, and should not be interpreted as having an ideal or overly formal meaning.

[0028] Figure 1 Is a block diagram of an electronic device according to an embodiment of the inventive concept. Figure 2Aand Figure 2B is a graph showing a data eye for describing 4-level pulse amplitude modulation. In Figure 2A and Figure 2B 's graph, the horizontal axis represents time and the vertical axis represents voltage level. Hereinafter, to describe the technical idea of the inventive concept, it is assumed that the signal transmitted / received through the channel CH or the input signal is a signal modulated based on 4-level pulse amplitude modulation (PAM-4). However, the inventive concept is not limited thereto. For example, the signal transmitted / received through the channel CH or the input signal may be a signal modulated based on an N-level pulse amplitude modulation (PAM-N) scheme (N is an integer greater than 2) or various other signal modulation schemes.

[0029] Referring to Figure 1 , the electronic device 10 may include a first communication device 11 and a second communication device 12. The first communication device 11 and the second communication device 12 may perform communication through the channel CH. In an exemplary embodiment, both the first communication device 11 and the second communication device 12 may be implemented in the form of a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a wearable device, or in the form of a computing device such as a personal computer, a server, a workstation, or a laptop. Alternatively, both the first communication device 11 and the second communication device 12 may be one of various functional blocks (e.g., intellectual property (IP) blocks) included in the same semiconductor chip.

[0030] The channel CH may be a signal line (i.e., a wired communication channel) electrically connecting the first communication device 11 and the second communication device 12. The present invention is not limited thereto. In an example embodiment, the channel CH may be a wireless communication channel. Both the first communication device 11 and the second communication device 12 may transmit / receive various types of signals such as electrical signals, optical signals, and wireless signals. Hereinafter, for ease of description, it is assumed that the first communication device 11 and the second communication device 12 operate based on electrical signals.

[0031] In an exemplary embodiment, the first communication device 11 and the second communication device 12 may exchange data based on 4-level pulse amplitude modulation (PAM-4). 4-level pulse amplitude modulation may indicate a modulation scheme in which two data bits are transmitted during one data transmission period (e.g., Figure 2A and Figure 2B 's first period PR1).

[0032] For example, during one data transmission period, the first communication device 11 may send two bits (e.g., one of four different bit values 11, 10, 01, and 11) to the second communication device 12. Hereinafter, parentheses may be used to refer to bit values. For example, as Figure 2AAs shown, data bit

[11] can correspond to a first voltage Va, data bit

[10] can correspond to a second voltage Vb, data bit

[00] can correspond to a third voltage Vc, and data bit

[01] can correspond to a fourth voltage Vd.

[0033] The first communication device 11 can send an input signal based on a signal level corresponding to a combination of two bits to the second communication device 12. The second communication device 12 can receive the input signal from the first communication device 11 and can determine two data bits received from the first communication device 11 based on a result of comparing a reference voltage with a voltage of the received input signal.

[0034] For example, as Figure 2A shown, in a case where the first communication device 11 sends an input signal based on the first voltage Va corresponding to data bit

[11] to the second communication device 12, the second communication device 12 can determine that the voltage of the received input signal is higher than the first reference voltage Vref1, that is, can determine that the received input signal corresponds to data bit

[11] . Similarly, the second communication device 12 can determine a data bit corresponding to the received input signal based on results of comparing the received input signal with the first reference voltage Vref1, the common voltage VCM, and the second reference voltage Vref2.

[0035] As Figure 2A shown, in an ideal 4-level pulse amplitude modulation PAM-4, differences (e.g., △V1, △V2, and △V3) between the first to fourth voltages Va to Vd can be equal, and reference voltages for determining bit values of input signals can be set to the first reference voltage Vref1, the common voltage VCM, and the second reference voltage Vref2. In this case, the first reference voltage Vref1 can be an intermediate level between the first voltage Va and the second voltage Vb, the common voltage VCM can be an intermediate level between the second voltage Vb and the third voltage Vc, and the second reference voltage Vref2 can be an intermediate level between the third voltage Vc and the fourth voltage Vd.

[0036] In an exemplary embodiment, when an input signal sent from the first communication device 11 passes through the channel CH, the input signal may be distorted. In this case, the second communication device 12 may not be able to accurately determine a bit value corresponding to the input signal received from the first communication device 11.

[0037] For example, as Figure 2BAs shown, in the 4-level pulse amplitude modulation PAM-4' with distortion, the differences (e.g., ΔV1', ΔV2', and ΔV3') between the first to fourth voltages Va' to Vd' may be different. Under this condition, when the second communication device 12 uses the first reference voltage Vref1, the common voltage VCM, and the second reference voltage Vref2, the second communication device 12 may not be able to properly determine the bit value corresponding to the input signal transmitted from the first communication device 11. For example, when the first communication device 11 transmits an input signal corresponding to the data bit

[10] , in the 4-level pulse amplitude modulation PAM-4' with distortion, the second communication device 12 may receive an input signal corresponding to the second voltage Vb'. Since the second voltage Vb' is less than the common voltage VCM and greater than the second reference voltage Vref2, the second communication device 12 may inaccurately determine the bit value corresponding to the received input signal as

[00] instead of

[10] . To avoid such inaccurate determination of the second communication device 12 due to the channel CH or various other factors, the 4-level pulse amplitude modulation PAM-4' of the second communication device 12 can generate or track optimized reference voltages (e.g., Vref1_opt', VCM_opt', and Vref2_opt'), and use the optimized reference voltages to determine the bit value of the received input signal.

[0038] In an exemplary embodiment, Figure 2B The distortion of the input signal shown is illustrated as a downward distortion in which all voltage levels corresponding to the bit values are decreased, but the inventive concept is not limited thereto. For example, the distortion of the input signal may include an upward distortion in which all voltage levels corresponding to the bit values are increased, or various types of distortions in which the differences between the voltage levels corresponding to the bit values are different.

[0039] A communication device or a signal receiver according to an embodiment of the inventive concept may generate or track an optimized reference voltage based on an input signal. The configuration and operation method of a signal receiver according to an embodiment of the inventive concept will be described more fully below.

[0040] Figure 3 is a block diagram showing a signal receiver according to an embodiment of the inventive concept. In an exemplary embodiment, Figure 3 The signal receiver 100 may be included in Figure 1 the first communication device 11 or the second communication device 12, and may be configured to receive an input signal through the channel CH.

[0041] Referring to Figure 1 and Figure 3, the signal receiver 100 may include a data sampler 110 and a reference voltage generator 120. The data sampler 110 may receive an input signal DIN through a channel CH. In an exemplary embodiment, the input signal DIN may be a signal modulated by 4-level pulse amplitude modulation PAM-4. The input signal DIN may be a differential signal, which may be implemented using a differential pair of two complementary signals. The data sampler 110 may determine a bit value corresponding to the received input signal DIN based on a first reference voltage Vref1_opt and a second reference voltage Vref2_opt. The configuration of the data sampler 110 will be described in more detail with reference to Figure 4 The configuration of the data sampler 110 will be described in more detail.

[0042] In an exemplary embodiment, the first reference voltage Vref1_opt and the second reference voltage Vref2_opt may be reference voltages Vref1_opt and Vref2_opt optimized with respect to the received input signal DIN. For example, the reference voltage generator 120 may receive a preprocessed signal SUM and / SUM from the data sampler 110. The preprocessed signal / SUM corresponds to the complementary signal of the preprocessed signal SUM. In an exemplary embodiment, the preprocessed signals SUM and / SUM may be signals preprocessed by the data sampler 110 based on the input signal DIN. That is, the preprocessed signals SUM and / SUM may be signals corresponding to the input signal DIN. The reference voltage generator 120 may generate the first reference voltage Vref1_opt and the second reference voltage Vref2_opt based on the preprocessed signals SUM and / SUM. The configuration and operation of the reference voltage generator 120 will be described more comprehensively below with reference to the drawings.

[0043] As described above, the signal receiver 100 according to an embodiment of the inventive concept may generate optimized reference voltages Vref1_opt and Vref2_opt based on the input signal DIN. In this way, even when various distortions occur in the channel CH, the signal receiver 100 may accurately determine the bit value corresponding to the input signal by using the optimized reference voltages Vref1_opt and Vref2_opt.

[0044] Figure 4 is a block diagram showing Figure 3 a data sampler. For simplicity of illustration and ease of description, components unnecessary for describing the configuration of the data sampler 110 are omitted. In Figure 4 , signal lines are shown by a single solid line, but the inventive concept is not limited thereto. For example, one signal may indicate two complementary signals of a differential signal.

[0045] Below, for ease of description, the reference symbol "_opt" is used. The reference symbol "_opt" can indicate a component optimized according to an embodiment of the present invention. For example, both "Vref1" and "Vref1_opt" can be used to indicate a first reference voltage. In this case, "Vref1" can indicate the first reference voltage identified during the optimization process, and "Vref1_opt" can indicate the first reference voltage in a state where the optimization is completed, that is, the first reference voltage after the optimization is completed. However, the present invention is not limited to this. For example, the meaning of each figure mark and term should be understood based on the context of the embodiment of the present invention.

[0046] Reference Figure 1 、 Figure 3 and Figure 4 The data sampler 110 may include: a pre-processing circuit 111 , first to third comparators 112 a , 112 b and 112 c , an output decoder 113 and a clock generator 114 .

[0047] The preprocessing circuit 111 can receive an input signal DIN via a channel CH. The preprocessing circuit 111 can preprocess the received input signal DIN to output preprocessed signals SUM and / SUM. For example, the preprocessing circuit 111 can include analog signal processing circuits such as a continuous time linear equalizer (CTLE) and a preamplifier. The input signal DIN can be preprocessed by the preprocessing circuit 111 including the aforementioned analog signal processing circuits. In an exemplary embodiment, the preprocessed signals SUM and / SUM can be differential signals.

[0048] Each of the first to third comparators 112a, 112b, and 112c can compare the preprocessed signals SUM and / SUM with a corresponding reference voltage of the first reference voltage Vref1_opt and the second reference voltage Vref2_opt, or compare the preprocessed signals SUM and / SUM, and can output a comparison result. For example, the first comparator 112a can compare the preprocessed signals SUM and / SUM with the first reference voltage Vref1_opt. The first comparator 112a can output a first comparison result DT1 as a comparison result. The second comparator 112b can compare the preprocessed signals SUM and / SUM. The second comparator 112b can output a second comparison result DT2 as a comparison result. The third comparator 112c can compare the preprocessed signals SUM and / SUM with the second reference voltage Vref2_opt. The third comparator 112c can output a third comparison result DT3 as a comparison result.

[0049] The output decoder 113 may generate output data DOUT based on first to third comparison results DT1, DT2, and DT3 from the first to third comparators 112a, 112b, and 112c. For example, in the case of 4-level pulse amplitude modulation PAM-4 described with reference to Figure 2A when the first to third comparison results DT1, DT2, and DT3 are all logic high (i.e., in the case of Vref1_opt > SUM, SUM > / SUM, and Vref2_opt > SUM), the output data DOUT may be

[11] . When the first comparison result DT1 is logic low and the second comparison result DT2 and the third comparison result DT3 are logic high (i.e., in the case of Vref1_opt < SUM, SUM > / SUM, and Vref2_opt > SUM), the output data DOUT may be

[10] . When the first comparison result DT1 and the second comparison result DT2 are logic low and the third comparison result DT3 is logic high (i.e., in the case of Vref1_opt < SUM, SUM < / SUM, and Vref2_opt > SUM), the output data DOUT may be

[00] . When the first to third comparison results DT1 to DT3 are logic low (i.e., in the case of Vref1_opt < SUM, SUM < / SUM, and Vref2_opt < SUM), the output data DOUT may be

[01] . The output decoder 113 may determine the output data DOUT based on the above scheme and may output the determined output data DOUT.

[0050] In an exemplary embodiment, as described with reference to Figure 2A using three reference voltages, two bit values (i.e., one of four input signal states) in 4-level pulse amplitude modulation PAM-4 can be identified. In contrast, since the input signal DIN received by the signal receiver 100 according to an embodiment of the inventive concept is a differential signal, two reference voltages Vref1_opt and Vref2_opt can be used to identify two bit values (i.e., one of four input signal states). For ease of description, hereinafter, it is assumed that the input signal DIN is a differential signal, but the inventive concept is not limited thereto.

[0051] The clock generator 114 may generate a clock signal CK. The clock signal CK may be provided to the first to third comparators 112a to 112c, and the first to third comparators 112a to 112c may perform the above-described comparison operation in synchronization with the clock signal CK.

[0052] In an exemplary embodiment, the first reference voltage Vref1_opt and the second reference voltage Vref2_opt may be reference voltages generated by the reference voltage generator 120 described with reference to Figure 3 description.

[0053] In an exemplary embodiment, Figure 4 the data sampler 110 may be configured to sample an input signal through a single path, but the inventive concept is not limited thereto. For example, the data sampler 110 may be configured to determine bit values of the input signal through various decoding schemes (e.g., through an even path / odd path scheme).

[0054] Figure 5 is a block diagram showing Figure 3 a reference voltage generator. Hereinafter, for ease of description, the reference voltage generator 120 receives signals (i.e., SUM, / SUM) preprocessed by the data sampler 110, but the inventive concept is not limited thereto. For example, the reference voltage generator 120 may use the received input signal DIN as a differential signal instead of the preprocessed signals (i.e., SUM, / SUM).

[0055] Referring to Figure 1 , Figure 3 and Figure 5 , the reference voltage generator 120 may include a peak voltage tracking circuit 121, a common voltage tracking circuit 122, and a reference voltage tracking circuit 123.

[0056] The peak voltage tracking circuit 121 may track a first peak voltage Vp1 and a second peak voltage Vp2 based on the preprocessed signals SUM and / SUM. For example, the first peak voltage Vp1 may indicate an upper limit level of the preprocessed signals SUM and / SUM, and the second peak voltage Vp2 may indicate a lower limit level of the preprocessed signals SUM and / SUM. In an exemplary embodiment, the first peak voltage Vp1 may correspond to Figure 2A a first voltage Va of Figure 2A , and the second peak voltage Vp2 may correspond to

[0057] a fourth voltage Vd of

[0058] The reference voltage tracking circuit 123 can receive a first peak voltage Vp1 and a second peak voltage Vp2 from the peak voltage tracking circuit 121, and can receive a common voltage VCM or an optimized common voltage VCM_opt from the common voltage tracking circuit 122. The reference voltage tracking circuit 123 can track or generate a first reference voltage Vref1_opt and a second reference voltage Vref2_opt based on the received voltages Vp1, Vp2, and VCM_opt. The configuration and operation of the reference voltage tracking circuit 123 will be described more fully below with reference to the accompanying drawings.

[0059] Figure 6 is a block diagram of the Figure 5 peak voltage tracking circuit shown. Referring to Figure 5 and Figure 6 , the peak voltage tracking circuit 121 can include a first voltage dividing unit 121a (i.e., a first voltage divider), a peak switch control unit 121b (i.e., a peak switch control circuit), a first comparison unit CMP11 (i.e., a first comparator), and a second comparison unit CMP12 (i.e., a second comparator).

[0060] The first voltage dividing unit 121a can include a first resistor string RS1 and a peak switch PSW. The first resistor string RS1 can include a plurality of resistors connected in series between a power supply voltage VDD and a ground voltage VSS. The peak switch PSW can be configured to output the voltage V1 of the first node and the voltage V2 of the second node by switching between the plurality of resistors in the first resistor string RS1. The peak switch PSW can perform the above-described switching operation in response to a first peak switch signal PSS1 and a second peak switch signal PSS2 from the peak switch control unit 121b. The voltage V1 of the first node can be output as the first peak voltage Vp1, and the voltage V2 of the second node can be output as the second peak voltage Vp2.

[0061] The first comparison unit CMP11 can be configured to compare a first preprocessed signal SUM with the voltage V1 of the first node and output a first comparison value C1 as a comparison result. The second comparison unit CMP12 can be configured to compare a second preprocessed signal / SUM with the voltage V2 of the second node and output a second comparison value C2 as a comparison result.

[0062] The peak switch control unit 121b may generate a first peak switch signal PSS1 and a second peak switch signal PSS2 based on a first comparison value C1 of the first comparison unit CMP11 and a second comparison value C2 of the second comparison unit CMP12. For example, when the first comparison value C1 of the first comparison unit CMP11 indicates that the voltage V1 of the first node is lower than the upper limit level of the first preprocessing signal SUM, the peak switch control unit 121b may generate the first peak switch signal PSS1 to increase the voltage V1 of the first node. The peak switch PSW may perform a switching operation in response to the first peak switch signal PSS1 to increase the voltage V1 of the first node.

[0063] When the second comparison value C2 of the second comparison unit CMP12 indicates that the voltage V2 of the second node is higher than the lower limit value of the second preprocessing signal / SUM, the peak switch control unit 121b may generate the second peak switch signal PSS2 to decrease the voltage V2 of the second node. The peak switch PSW may perform a switching operation in response to the second peak switch signal PSS2 to decrease the voltage V2 of the second node.

[0064] When the voltage V1 of the first node is equal to the upper limit level of the first preprocessing signal SUM, the first voltage V1 of the first node may be determined as the first peak voltage Vp1. When the voltage V2 of the second node is equal to the lower limit value of the second preprocessing signal / SUM, the voltage V2 of the second node may be determined as the second peak voltage Vp2.

[0065] The peak voltage tracking circuit 121 may track or generate the first peak voltage Vp1 and the second peak voltage Vp2 by repeatedly performing the above-described comparison operation and switching operation. When the first peak voltage Vp1 and the second peak voltage Vp2 are completely tracked (i.e., determined), the peak switch control unit 121b may output an enable signal EN. In an exemplary embodiment, the enable signal EN, the first peak voltage Vp1, and the second peak voltage Vp2 may be provided to the reference voltage tracking circuit 123.

[0066] The above-described embodiment of tracking or generating the first peak voltage Vp1 and the second peak voltage Vp2 by using the first voltage dividing unit 121a including the first resistor string RSl and the peak switch PSW is described, but the inventive concept is not limited thereto. For example, the peak voltage tracking circuit 121 may track or generate the first peak voltage Vp1 and the second peak voltage Vp2 by using various types of voltage generators configured to gradually increase / decrease the output voltage.

[0067] Figure 7 is shown Figure 5Diagram of a common voltage tracking circuit. Hereinafter, for simplicity of illustration and ease of description, a resistor element may be represented by using the reference numeral "R". In this case, "R" may indicate a resistor element or may indicate the resistance value of a resistor element. The resistance value of a resistor element marked with "2R" may be twice the resistance value of a resistor element marked with "R".

[0068] Referring to Figure 5 and Figure 7 , the common voltage tracking circuit 122 may include two resistors "R" and a comparison unit CMP21 (i.e., a comparator). A first preprocessing signal SUM may be input to a first input terminal (+) of the comparison unit CMP21 through one resistor "R", while a second preprocessing signal / SUM may be input to the first input terminal (+) of the comparison unit CMP21 through another resistor "R". The voltage at the first input terminal (+) of the comparison unit CMP21 may correspond to the average voltage of the first preprocessing signal SUM and the second preprocessing signal / SUM, which corresponds to the value of (SUM + / SUM) / 2.

[0069] The output terminal of the comparison unit CMP21 may be connected to a second input terminal (-) of the comparison unit CMP21. The comparison unit CMP21 may be implemented by using a unity-gain buffer. The output of the comparison unit CMP21 may be an optimized common voltage VCM_opt.

[0070] As described above, the common voltage or the optimized common voltage VCM_opt may be an intermediate value or an average value of the input signal DIN or the preprocessing signals SUM and / SUM. The optimized common voltage VCM_opt may be represented by Equation 1 below.

[0071]

[0072] The reference symbols included in Equation 1 above have been described, and thus, additional description will be omitted to avoid repetition. As described above, since the first preprocessing signal SUM and the second preprocessing signal / SUM are differential signals, the common voltage or the optimized common voltage VCM_opt may be generated by using the first preprocessing signal SUM and the second preprocessing signal / SUM without a separate tracking operation. The optimized common voltage VCM_opt may be provided to the reference voltage tracking circuit 123.

[0073] Figure 8 is a diagram showing Figure 5 of the reference voltage tracking circuit. Figure 9 is a diagram showing Figure 8 of the pre-tuning control unit. Referring to Figure 5 , Figure 8 and Figure 9, the reference voltage tracking circuit 123 may include a second voltage dividing unit 123a (i.e., a second voltage divider), a pre-tuning control unit 123b (i.e., a pre-tuning control circuit), a reference switch control unit 123c (i.e., a reference switch control circuit), and a first comparison unit CMP31 and a second comparison unit CMP32 (i.e., a first comparator and a second comparator).

[0074] The second voltage dividing unit 123a may include a second resistor string RS2 and a reference switch RSW. The second resistor string RS2 may include a plurality of resistors connected in series between a first peak voltage Vp1 and a second peak voltage Vp2. The reference switch RSW may be configured to output the voltage V3 of a third node and the voltage V4 of a fourth node by switching between the plurality of resistors in the second resistor string RS2. The reference switch RSW may perform a switching operation in response to a first reference switch signal RSS1 and a second reference switch signal RSS2 from the reference switch control unit 123c to output the voltages V3 and V4.

[0075] The pre-tuning control unit 123b may output a pre-tuning signal PTEN based on the first peak voltage Vp1, the second peak voltage Vp2, the common voltage VCM_opt, the voltage V3 of the third node, and the voltage V4 of the fourth node. For example, in a 4-level pulse amplitude modulation PAM-4’ showing distortion Figure 2B in which it is assumed that each of the optimized reference voltages Vref1_otp, VCM_opt, and Vref2_otp is the middle value of the corresponding data eye, the following equation 2 can be established.

[0076]

[0077]

[0078]

[0079] The reference symbols included in the above equation 2 have been described above, so additional description will be omitted to avoid repetition. In equation 2, Va’ may be the first peak voltage Vp1, and Vd’ may be the second peak voltage Vp2. Equation 3 can be established by summarizing equation 2.

[0080]

[0081] The reference symbols included in Equation 3 above have been described, so additional description will be omitted to avoid repetition. In Equation 3, the sum of the first reference voltage Vref1_opt and the second reference voltage Vref2_opt may be equal to the sum of the average value of the first peak voltage Vp1 and the second peak voltage Vp2 and the common voltage VCM_opt. The first peak voltage Vp1, the second peak voltage Vp2, and the common voltage VCM_opt on the right side of Equation 3 above are values determined by the peak voltage tracking circuit 121 and the common voltage tracking circuit 122, so the sum of the first reference voltage Vref1_opt and the second reference voltage Vref2_opt can be determined.

[0082] The pre-tuning control unit 123b may be configured to compare the sum of the voltage V3 of the third node and the voltage V4 of the fourth node with the sum of the common voltage VCM_opt and the average value of the first peak voltage Vp1 and the second peak voltage Vp2, and output a pre-tuning signal PTEN as a comparison result.

[0083] In an exemplary embodiment, when implementing the pre-tuning control unit 123b based on Equation 3, since the sum of the first reference voltage Vref1_opt and the second reference voltage Vref2_opt may exceed the power supply voltage VDD, the pre-tuning control unit 123b can be implemented based on the result of halving both sides of Equation 3.

[0084] For example, as Figure 9 shown, the pre-tuning control unit 123b may include a plurality of resistors "R" and 2R, and comparators CMP41, CMP42, and CMP43.

[0085] The voltage V3 of the third node and the voltage V4 of the fourth node output from the reference switch RSW can both be input to the first input terminal (+) of the comparator CMP41 through the corresponding resistor 2R, and the output Vx of the comparator CMP41 can be input to the second input terminal (-) of the comparator CMP41. The comparator CMP41 can be implemented using a unity gain buffer. The output Vx of the comparator CMP41 is referred to as the "first intermediate voltage". In an exemplary embodiment, the voltage V3 of the third node may correspond to the first reference voltage Vref1_opt in Equation 3 above, and the voltage V4 of the fourth node may correspond to the second reference voltage Vref2_opt in Equation 3 above. The first intermediate value Vx may be a value corresponding to the result of halving the left side of Equation 3 (i.e., the average value of the first reference voltage Vref1_opt and the second reference voltage Vref2_opt).

[0086] Both the first peak voltage Vp1 and the second peak voltage Vp2 output from the peak voltage tracking circuit 121 can be input to the first input terminal (+) of the comparator CMP42 through the corresponding resistors 2R, and the common voltage VCM_opt output from the common voltage tracking circuit 122 can be input to the first input terminal (+) of the comparison unit CMP42 through the resistor "R". The output Vy of the comparator CMP42 can be input to the second input terminal (-) of the comparator CMP42. The comparator CMP42 can be implemented using a unity gain buffer. The output Vy of the comparator CMP42 is referred to as the "second intermediate voltage". The second intermediate voltage Vy can be a value corresponding to the result of halving the right side of Equation 3 above (i.e., the average of the common voltage VCM_opt and the average of the first peak voltage Vp1 and the second peak voltage Vp2).

[0087] The comparator CMP43 can compare the first intermediate voltage Vx with the second intermediate voltage Vy and can output a pre-tuning signal PTEN according to the comparison result. When the first intermediate voltage Vx is different from the second intermediate voltage Vy, the pre-tuning signal PTEN can be enabled. In an exemplary embodiment, when the first intermediate voltage Vx is higher than (or greater than) the second intermediate voltage Vy, the pre-tuning signal PTEN can be output so that pre-tuning is performed based on the first mode. When the first intermediate voltage Vx is lower than (or less than) the second intermediate voltage Vy, the pre-tuning signal PTEN can be output so that pre-tuning is performed based on the second mode. In an exemplary embodiment, the pre-tuning mode can be changed differently according to the initial value of the voltage V3 of the third node, the initial value of the voltage V4 of the fourth node, and the initial value of the common voltage VCM_opt. The pre-tuning mode will be described more fully with reference to Figures 11A to 11D the pre-tuning mode is described more fully.

[0088] Return Figure 8 , the first comparison unit CMP31 (i.e., the first comparator) can compare the voltage V3 of the third node with the first pre-processing signal SUM and can output a first comparison result OUTp. The second comparison unit CMP32 (i.e., the second comparator) can compare the voltage V4 of the fourth node with the second pre-processing signal / SUM and can output a second comparison result OUTn.

[0089] The reference switch control unit 123c can generate a first reference switch signal RSS1 and a second reference switch signal RSS2 in response to an enable signal EN from the peak voltage tracking circuit 121. The reference switch control unit 123c can generate a first reference switch signal RSS1 and a second reference switch signal RSS2 based on the pre-tuning signal PTEN, the first comparison result OUTp, and the second comparison result OUTn.

[0090] For example, first, the reference switch control unit 123c starts the operation of tracking the reference voltage in response to the enable signal EN. When the first intermediate voltage Vx and the second intermediate voltage Vy of the pre-tuning control unit 123b are different, the pre-tuning signal PTEN can be output (i.e., enabled). The reference switch control unit 123c can generate one of the first reference switch signal RSS1 and the second reference switch signal RSS2 based on the pre-tuning signal PTEN. In an exemplary embodiment, when the first intermediate voltage Vx is higher than the second intermediate voltage Vy, the pre-tuning signal PTEN can correspond to the first mode, in which the reference switch control unit 123c can generate the first reference switch signal RSS1 to reduce the voltage V3 of the third node. The reference switch RSW can reduce the voltage V3 of the third node in response to the first reference switch signal RSS1. When the first intermediate voltage Vx is lower than the second intermediate voltage Vy, the pre-tuning signal PTEN can correspond to the second mode, in which the reference switch control unit 123c can generate the second reference switch signal RSS2 to increase the voltage V4 of the fourth node. The reference switch RSW can increase the voltage V4 of the fourth node in response to the second reference switch signal RSS2. The above configuration is only an example, and the first reference switch signal RSS1 and the second reference switch signal RSS2 generated in response to the pre-tuning signal PTEN can be variously changed or modified according to various conditions (e.g., the magnitude of the common voltage VCM_opt and the initial values of the voltage V3 of the third node and the voltage V4 of the fourth node).

[0091] The reference switch control unit 123c may repeat the above operation until the first intermediate voltage Vx and the second intermediate voltage Vy of the pre-tuning control unit 123b are equal. When the first intermediate voltage Vx and the second intermediate voltage Vy of the pre-tuning control unit 123b are equal, the pre-tuning signal PTEN may be disabled. In this case, the reference switch control unit 123c may generate a first reference switch signal RSS1 and a second reference switch signal RSS2 based on the first comparison result OUTp from the comparison units CMP31 and CMP32 and the second comparison result OUTn. For example, when the first comparison result OUTp from the comparison units CMP31 and CMP32 and the second comparison result OUTn are different, the reference switch control unit 123c may generate the first reference switch signal RSS1 to increase / decrease the voltage V3 of the third node, and may generate the second reference switch signal RSS2 to decrease / increase the voltage V4 of the fourth node. In an exemplary embodiment, the increment / decrement of the voltage V3 of the third node may be equal to the decrement / increment of the voltage V4 of the fourth node so that the magnitude of the first intermediate voltage Vx of the pre-tuning control unit 123b remains unchanged. That is, the increment / decrement of the voltage V3 of the third node and the decrement / increment of the voltage V4 of the fourth node may be set to the same magnitude (or unit magnitude).

[0092] The reference switch control unit 123c may repeat the above operation until the first comparison result OUTp from the comparison units CMP31 and CMP32 and the second comparison result OUTn are the same. In an exemplary embodiment, when the first comparison result OUTp from the comparison units CMP31 and CMP32 and the second comparison result OUTn are the same, the voltage V3 of the third node may be determined as the first reference voltage Vref1_opt, and the voltage V4 of the fourth node may be determined as the second reference voltage Vref2_opt.

[0093] As described above, the reference voltage tracking circuit 123 may control one of the voltage V3 of the third node and the voltage V4 of the fourth node based on the pre-tuning signal PTEN from the pre-tuning control unit 123b (i.e., the result of comparing the first intermediate voltage Vx and the second intermediate voltage Vy), and then control the voltage V3 of the third node and the voltage V4 of the fourth node based on the first comparison result OUTp from the comparison units CMP31 and CMP32 and the second comparison result OUTn, respectively, to track or generate the optimized reference voltages Vref1_opt and Vref2_opt. In an exemplary embodiment, the optimized reference voltages Vref1_opt and Vref2_opt may be used to determine the output data DOUT associated with the input signal DIN at the data sampler 110 described in the reference Figure 4 to the input signal DIN at the data sampler 110 described in the reference.

[0094] Figure 10 It shows Figure 3 For ease of description, additional descriptions associated with the above components will be omitted to avoid repetition. Figure 3 The signal receiver 100 performs the following Figure 10 The operation of the flowchart is described, but the present invention is not limited thereto. Figure 10 The operations of the flowchart may be performed by the reference voltage generator 120 or any other electronic device.

[0095] For ease of description, the following describes a configuration in which the signal receiver 100 generates a reference voltage based on the input signal DIN. However, the present invention is not limited thereto. For example, as described above, the reference voltage may be tracked or generated using preprocessed signals SUM and / SUM obtained by preprocessing the input signal DIN.

[0096] Reference Figure 1 and Figures 3 to 10 In operation S110, the signal receiver 100 may receive an input signal DIN through a channel CH. In an exemplary embodiment, the input signal DIN as a differential signal may be a signal modulated by 4-level pulse amplitude modulation PAM-4.

[0097] In operation S120, the signal receiver 100 may track or generate peak voltages (i.e., Vp1 and Vp2) based on the input signal DIN. The first peak voltage Vp1 may be a voltage corresponding to an upper limit level (i.e., a maximum voltage level) of the input signal DIN, and the second peak voltage Vp2 may be a voltage corresponding to a lower limit level (i.e., a minimum voltage level) of the input signal DIN.

[0098] In operation S130, the signal receiver 100 may determine the reference Figure 8The initial voltage of the voltage V3 of the described third node and the initial voltage of the voltage V4 of the fourth node are used to track or generate the reference voltages Vref1_opt and Vref2_opt. For example, the first initial voltage of the voltage V3 of the third node can be set to "2 / 3*(Vp1 + Vp2)", while the second initial voltage of the voltage V4 of the fourth node can be set to "1 / 3*(Vp1 + Vp2)". Alternatively, the first initial voltage of the voltage V3 of the third node and the second initial voltage of the voltage V4 of the fourth node can be set to the same voltage "1 / 2*(Vp1 + Vp2)". Alternatively, the first initial voltage of the voltage V3 of the third node can be set to the first peak voltage Vp1, and the second initial voltage of the voltage V4 of the fourth node can be set to the second peak voltage Vp2. However, the inventive concept is not limited thereto. For example, the initial reference voltages of the voltage V3 of the third node and the voltage V4 of the fourth node can be set differently within the range from the first peak voltage Vp1 to the second peak voltage Vp2.

[0099] In operation S140, the signal receiver 100 may determine whether a first condition is satisfied. For example, the first condition may indicate a condition based on Equation 3 above. The first condition may indicate a condition that the first intermediate voltage Vx and the second intermediate voltage Vy described with reference to Figure 9 are equal.

[0100] When the first condition is not satisfied, in operation S141, the signal receiver 100 may adjust one of the reference voltages. For example, as described with reference to Figure 8 and Figure 9 when the condition based on Equation 3 above (i.e., Vx = Vy) is not satisfied, at least one of the voltage V3 of the third node and the voltage V4 of the fourth node may be adjusted to satisfy the condition based on Equation 3 above (i.e., Vx = Vy). In an exemplary embodiment, the signal receiver 100 may repeatedly perform operation S140 and operation S141 until the first condition (i.e., Vx = Vy) is satisfied.

[0101] When the first condition is satisfied, in operation S150, the signal receiver 100 may determine whether a second condition is satisfied. For example, the second condition may indicate a condition that the first comparison result OUTp and the second comparison result OUTn of the comparison units CMP31 and CMP32 described with reference to Figure 8 are the same.

[0102] When the second condition is not satisfied, in operation S151, the signal receiver 100 may adjust the reference voltage. For example, as described with reference to Figure 8As described, the reference switch control unit 123c may generate a first reference switch signal RSS1 and a second reference switch signal RSS2 such that the first comparison result OUTp and the second comparison result OUTn from the comparison units CMP31 and CMP32 are the same. In this case, the first reference switch signal RSS1 may be generated such that the voltage V3 of the third node increases / decreases, and the second reference switch signal RSS2 may be generated such that the voltage V4 of the fourth node decreases / increases. In an exemplary embodiment, the increment / decrement of the voltage V3 of the third node may be equal to the decrement / increment of the voltage V4 of the fourth node. This may be used to maintain satisfaction of the first condition.

[0103] When the second condition is satisfied, in operation S160, the signal receiver 100 may determine the adjusted reference voltage as the optimized reference voltage (i.e., Vref1_opt and Vref2_opt).

[0104] In an exemplary embodiment, the signal receiver 100 may determine the bit value of the input signal DIN or the bit value of any other signal received after the input signal DIN by using the thus determined optimized reference voltages Vref1_opt and Vref2_opt.

[0105] In an exemplary embodiment, operations S140 and S141 may indicate pre-tuning operations or coarse-tuning operations of the signal receiver 100 or the reference voltage generator 120, and operations S150 and S151 may indicate post-tuning operations or fine-tuning operations of the signal receiver 100 or the reference voltage generator 120.

[0106] Figures 11A to 11D is a diagram for describing how the signal receiver tracks the optimized reference voltage based on Figure 10 . For ease of description, additional descriptions associated with the above components will be omitted to avoid repetition. Assume that before performing the operation of tracking the optimized reference voltage, the first peak voltage Vp1 and the second peak voltage Vp2 are determined by the peak voltage tracking circuit 121, and the common voltage VCM_opt is determined by the common voltage tracking circuit 122. As described with reference to Figure 6 and Figure 7 , the first peak voltage Vp1, the second peak voltage Vp2, and the common voltage VCM_opt are determined based on the input signal DIN and the preprocessed signals SUM and / SUM, and thus additional descriptions will be omitted to avoid repetition.

[0107] First, with reference to Figure 8 , Figure 9 and Figure 11A , assume that the received input signal DIN has as Figure 11AThe waveform of the 4-level pulse amplitude modulation PAM-4’. In this case, compared with the ideal 4-level pulse amplitude modulation PAM-4, the 4-level pulse amplitude modulation PAM-4’ may have a downward-distorted data eye (i.e., a data eye in which all optimized reference voltages are reduced). For the 4-level pulse amplitude modulation PAM-4’, the first reference voltage and the second reference voltage optimized for the 4-level pulse amplitude modulation PAM-4’ may be Vref1_opt’ and Vref2_opt’.

[0108] First, during a first time period T1, the initial voltage of the voltage V3 of the third node may be set to a first initial voltage Vint1, and the initial voltage of the voltage V4 of the fourth node may be set to a second initial voltage Vint2. The first initial voltage Vint1 may correspond to the voltage “2 / 3*(Vp1 + Vp2)”, and the second initial voltage Vint2 may correspond to the voltage “1 / 3*(Vp1 + Vp2)”.

[0109] During the first time period T1, due to the downward distortion of the 4-level pulse amplitude modulation PAM-4’ compared with the ideal 4-level pulse amplitude modulation PAM-4, a first intermediate voltage Vx corresponding to the sum of the voltage V3 of the third node and the voltage V4 of the fourth node may be greater than a second intermediate voltage Vy (i.e., VCM_opt + (Vp1 + Vp2) / 2). In this case, the pre-tuning control unit 123b may output a first pre-tuning signal PTEN1 corresponding to a first mode in the pre-tuning signal PTEN. The first mode may indicate a mode in which the voltage V3 of the third node among the voltages V3 and V4 gradually decreases.

[0110] The reference switch control unit 123c may generate a first reference switch signal RSS1 in response to the first pre-tuning signal PTEN1 to decrease the voltage V3 of the third node (i.e., DOWN), and may generate a second reference switch signal RSS2 in response to the first pre-tuning signal PTEN1 to hold the voltage V4 of the fourth node (i.e., HOLD). The reference switch RSW may decrease the voltage V3 of the third node by a given magnitude in response to the first reference switch signal RSS1 indicating “DOWN”, and may hold the voltage V4 of the fourth node in response to the second reference switch signal RSS2 indicating “HOLD”. The voltage V4 of the fourth node may be held in the same manner during the first time period T1 and the second time period T2, and the voltage V3 of the third node in the second time period T2 may be lower than the voltage V3 of the third node in the first time period T1.

[0111] During a second time T2, a first intermediate voltage Vx may be greater than a second intermediate voltage Vy. In this case, as in the operation during the first time T1, a first reference switching signal RSS1 may be generated such that the voltage V3 of the third node decreases (i.e., DOWN), and a second reference switching signal RSS2 may be generated such that the voltage V4 of the fourth node is held (i.e., HOLD). Thus, during a third time T3, the voltage V3 of the third node may decrease by a given magnitude while the voltage V4 of the fourth node may be held. In response to a first pre-tuning signal PTEN1, during the first time T1 to the third time T3, the voltage V3 of the third node may gradually decrease and the voltage V4 of the fourth node may be maintained identically.

[0112] During a third time T3, the first intermediate voltage Vx may be equal to the second intermediate voltage Vy. A first condition described in operation S140 with reference to Figure 10 may be satisfied. In this case, the pre-tuning control unit 123b may deactivate the pre-tuning signal PTEN.

[0113] As described above, since the first condition is satisfied, the reference switching control unit 123c may determine whether a second condition (i.e., OUTp = OUTn) is satisfied during the third time T3. As Figure 11A shown, during the third time T3, since the first comparison result OUTp and the second comparison result OUTn are different, the reference switching control unit 123c may generate a first reference switching signal RSS1 such that the voltage V3 of the third node increases (e.g., UP), and may generate a second reference switching signal RSS2 such that the voltage V4 of the fourth node decreases (e.g., DOWN). In response to the first reference switching signal RSS1 and the second reference switching signal RSS2, the reference switch RSW may increase the voltage V3 of the third node by a given magnitude and may decrease the voltage V4 of the fourth node by a given magnitude.

[0114] During a fourth time T4 to a sixth time T6, the reference voltage generator 120 may perform operations similar to those performed during the third time T3 until the first comparison result OUTp and the second comparison result OUTn are the same. During the fourth time T4 to the sixth time T6, the reference voltage generator 120 may gradually increase the voltage V3 of the third node and may gradually decrease the voltage V4 of the fourth node.

[0115] During the sixth time T6, the first comparison result OUTp and the second comparison result OUTn may be the same, so that the second condition can be satisfied. The first comparison result OUTp and the second comparison result OUTn being the same may mean that the voltage V3 of the third node and the voltage V4 of the fourth node are the optimized reference voltages Vref1_opt’ and Vref2_opt’ for the received input signal DIN. In a state where the first comparison result OUTp and the second comparison result OUTn are the same, the voltage V3 of the third node and the voltage V4 of the fourth node may be used as the first optimized reference voltage Vref1_opt’ and the second optimized reference voltage Vref2_opt’ respectively.

[0116] In an exemplary embodiment, when the second condition is satisfied, during the sixth time T6, the reference switch control unit 123c may generate a first reference switch signal RSS1 and a second reference switch signal RSS2 both having the value “HOLD” to hold the voltage V3 of the third node and the voltage V4 of the fourth node.

[0117] As described above, the reference voltage tracking circuit 123 may set the voltage V3 of the third node and the voltage V4 of the fourth node to a first initial value Vint1 and a second initial value Vint2 respectively in response to the pre-tuning signal PTEN1 during the first time T1. In this case, when the first intermediate voltage Vx is greater than the second intermediate voltage Vy, the reference voltage generator 120 or the reference voltage tracking circuit 123 may gradually decrease the voltage V3 of the third node until the first condition is satisfied, and then may gradually increase the voltage V3 of the third node and gradually decrease the voltage V4 of the fourth node until the second condition is satisfied. When the first condition and the second condition are satisfied, the voltage V3 of the third node and the voltage V4 of the fourth node may be used as the optimized reference voltages Vref1_opt’ and Vref2_opt’.

[0118] Next, referring to Figure 8 、 Figure 9 and Figure 11B , assume that the received input signal DIN has a waveform of 4-level pulse amplitude modulation PAM-4” as shown in Figure 11B . In this case, compared with the ideal 4-level pulse amplitude modulation PAM-4, the 4-level pulse amplitude modulation PAM-4” may have an upward-distorted data eye (i.e., a data eye with all optimized reference voltages increased). The reference voltages optimized for the 4-level pulse amplitude modulation PAM-4” may be a first optimized reference voltage Vref1_opt” and a second optimized reference voltage Vref2_opt”.

[0119] Because Figure 11B 's overall operation is similar to the operation described with reference to Figure 11A , the main description will beFigure 11A The difference between Figure 11B and. As Figure 11B shown, during the first time period T1, the initial voltage of the voltage V3 of the third node and the initial voltage of the voltage V4 of the fourth node can be set to the first initial voltage Vint1 and the second initial voltage Vint2, respectively.

[0120] In this case, according to the levels of the signals V3, V4, Vp1, Vp2, and VCM_opt, during Figure 11B the first time period T1, due to the upward distortion of the 4-level pulse amplitude modulation PAM-4 compared with the ideal 4-level pulse amplitude modulation PAM-4 Figure 11B of "4-level pulse amplitude modulation PAM-4", the first intermediate voltage Vx can be lower than the second intermediate voltage Vy. The pre-tuning control unit 123b can output the second pre-tuning signal PTEN2 corresponding to the second mode in the pre-tuning signal PTEN. The second mode can indicate the mode in which the voltage V4 of the fourth node among the voltages V3 and V4 gradually increases.

[0121] During the first time period T1 and the second time period T2, the reference switch control unit 123c can generate a first reference switch signal RSS1 indicating "HOLD" and a second reference switch signal RSS2 indicating "UP" based on the second pre-tuning signal PTEN2. During the second time period T2 and the third time period T3, based on the first reference switch signal RSS1 indicating "HOLD" and the second reference switch signal RSS2 indicating "UP", the voltage V3 of the third node can be held identically, and the voltage V4 of the fourth node can be gradually increased.

[0122] During the third time period T3, the first intermediate voltage Vx can be equal to the second intermediate voltage Vy, so that the first condition can be satisfied. During the fourth time period T4 to the sixth time period T6, the reference voltage generator 120 or the reference voltage tracking circuit 123 can gradually increase the voltage V3 of the third node and can gradually decrease the voltage V4 of the fourth node. This operation is similar to the operation described with reference to Figure 11A and thus additional description will be omitted to avoid repetition.

[0123] Then, referring to Figure 8 , Figure 9 and Figure 11C , assuming that the received input signal DIN has as Figure 11CThe waveform of "4-level Pulse Amplitude Modulation PAM-4" as shown. In this case, compared with the ideal 4-level Pulse Amplitude Modulation PAM-4, the 4-level Pulse Amplitude Modulation PAM-4" may have an upward-distorted data eye (i.e., a data eye with all optimized reference voltages increased). The first reference voltage and the second reference voltage optimized for PAM-4" can be the first optimized reference voltage Vref1_opt" and the second optimized reference voltage Vref2_opt".

[0124] Different from the embodiments in Figure 11A and Figure 11B the initial voltage of the voltage V3 of the third node can be set to the first peak voltage Vp1, and the initial voltage of the voltage V4 of the fourth node can be set to the second peak voltage Vp2.

[0125] During the first time Tl and the second time T2, the first intermediate voltage Vx can be lower than the second intermediate voltage Vy, so a second pre-tuning signal PTEN2 corresponding to the second mode can be generated. During the second time T2 and the third time T3, the reference voltage generator 120 or the reference voltage tracking circuit 123 can gradually increase the voltage V4 of the fourth node in response to the second pre-tuning signal PTEN2.

[0126] After the first condition is satisfied during the third time T3, the reference voltage generator 120 or the reference voltage tracking circuit 123 can generate a first reference switch signal RSS1 to gradually decrease the voltage V3 of the third node (i.e., DOWN), and can generate a second reference switch signal RSS2 to gradually increase the voltage V4 of the fourth node (i.e., UP). During the fourth time T4 to the sixth time T6, the voltage V3 of the third node can gradually decrease based on the first reference switch signal RSS1 indicating "DOWN", and the voltage V4 of the fourth node can gradually increase based on the second reference switch signal RSS2 indicating "UP". The second condition can be satisfied during the sixth time T6, and the voltage V3 of the third node and the voltage V4 of the fourth node determined during the sixth time T6 can be used as the optimized reference voltages Vref1_opt" and Vref2_opt".

[0127] Referring to Figure 8 、 Figure 9 and Figure 11D assuming that the received input signal DIN has as Figure 11DThe waveform of the "4-level Pulse Amplitude Modulation PAM-4" shown. Compared with the ideal 4-level Pulse Amplitude Modulation PAM-4, this 4-level Pulse Amplitude Modulation PAM-4" can have an upward-distorted data eye (i.e., a data eye with all optimized reference voltages increased). The reference voltages optimized for the 4-level Pulse Amplitude Modulation PAM-4" can be the first optimized reference voltage Vref1_opt and the second optimized reference voltage Vref2_opt.

[0128] Unlike Figures 11A to 11C the embodiment of Figure 11D In [a certain context], during a first time T1 in response to a first pre-tuning signal PTEN1, the initial voltage of the voltage V3 of the third node and the initial voltage of the voltage V4 of the fourth node can be set to the same voltage (e.g., the intermediate voltage Vcen). The intermediate voltage Vcen can be the intermediate value between the first peak voltage Vp1 and the second peak voltage Vp2.

[0129] During the first time Tl, the first intermediate voltage Vx can be lower than the second intermediate voltage Vy. In this case, the pre-tuning control unit 123b can output a first pre-tuning signal PTEN1 corresponding to the first mode. Unlike Figure 11B the embodiment of Figure 11D In the embodiment of [a certain context], when the first intermediate voltage Vx is lower than the second intermediate voltage Vy and when the initial reference voltage of the voltage V3 of the third node and the initial reference voltage of the voltage V4 of the fourth node are set to the intermediate voltage Vcen, the first pre-tuning signal PTEN1 is output instead of the second pre-tuning signal PTEN2. In Figure 11D the case of the embodiment of [a certain context], when the pre-tuning control unit 123b outputs the second pre-tuning signal PTEN2 instead of the first pre-tuning signal PTEN1, the voltage V4 of the fourth node used as the second reference voltage Vref2_opt can increase step by step, so that the reference voltage cannot be tracked.

[0130] The pre-tuning control unit 123b can be configured to select the first mode or the second mode based on the initial voltage of the voltage V3 of the third node, the initial voltage of the voltage V4 of the fourth node, and the comparison result between the first intermediate voltage Vx and the second intermediate voltage Vy. For example, the pre-tuning control unit 123b is configured to select one of the first mode and the second mode based on the initial voltage of the voltage V3, the initial voltage of the voltage V4, and the comparison result between the first intermediate voltage Vx and the second intermediate voltage Vy.

[0131] During a second time T2, when a first reference switch signal RSS1 indicates "UP", the voltage V3 of the third node may increase by a given magnitude. A first condition (i.e., Vx = Vy) may be satisfied during the second time T2. As described above, during a third time T3 to a sixth time T6, the voltage V3 of the third node may increase step by step based on the first reference switch signal RSS1 indicating "UP", and the voltage V4 of the fourth node may decrease step by step based on a second reference switch signal RSS2 indicating "DOWN". During the sixth time T6, a second condition (i.e., OUTp = OUTn) may be satisfied. In this case, the voltage V3 of the third node may be used as a first reference voltage Vref1_opt, and the voltage V4 of the fourth node may be used as a second reference voltage Vref2_opt.

[0132] As referred to Figures 11A to 11D as described, the reference voltage generator 120 or the reference voltage tracking circuit 123 may track or generate optimized reference voltages Vref1_opt and Vref2_opt for the input signal DIN. Thus, even if distortion occurs in the input signal DIN due to various factors, the optimized reference voltages Vref1_opt and Vref2_opt can be dynamically tracked. Therefore, the reliability of the signal receiver can be improved.

[0133] Figure 12 is a flowchart showing Figure 3 the operation of the signal receiver. For ease of description, additional descriptions associated with the above components will be omitted to avoid repetition. Referring to Figure 3 and Figure 12 , in operation S210, the signal receiver 100 may perform an initialization operation. For example, the signal receiver 100 may be included in Figure 1 the second communication device 12, and the first communication device 11 and the second communication device 12 may perform an initialization operation before normal operation to improve the reliability of communication. In this case, the first communication device 11 may send an input signal DIN as a test signal to the second communication device 12. In an exemplary embodiment, the input signal DIN may have a given pattern or may have a random pattern. The second communication device 12 may perform an initialization operation based on the input signal DIN received through the channel CH. In an exemplary embodiment, the signal receiver 100 of the second communication device 12 may track or generate an optimized reference voltage Vref_opt corresponding to the received input signal DIN based on the optimized reference voltage tracking / generation method described with reference to Figures 3 to 11D the description.

[0134] In operation S220, the signal receiver 100 may perform communication by using the optimized reference voltage Vref_opt generated in operation S210. For example, the signal receiver 100 may receive a second input signal from an external device (e.g., Figure 1 the first communication device 11), and may determine a bit value corresponding to the second input signal by using the optimized reference voltage Vref_opt.

[0135] In operation S230, the signal receiver 100 may determine whether distortion has occurred. For example, a case where the bit value determined by the signal receiver 100 is different from the originally expected bit value may be determined as distortion having occurred. In an exemplary embodiment, whether distortion has occurred may be determined by a separate distortion detection circuit. In an exemplary embodiment, whether distortion has occurred may be detected by an external device (e.g., Figure 1 the first communication device 11) that sends an input signal DIN to the signal receiver 100 of the second communication device 12. When it is determined that no distortion has occurred, the signal receiver 100 continues to perform operation S220. Figure 1 When it is determined that distortion has occurred, in operation S240, the signal receiver 100 may re-track the optimized reference voltage Vref_opt. For example, when distortion occurs, it may not be possible to accurately determine the input signal DIN by using the optimized reference voltage Vref_opt generated previously in operation S210. In this case, the signal receiver 100 may re-track the optimized reference voltage based on the optimized reference voltage tracking / generation method described with reference to

[0136] In an exemplary embodiment, in the operation of tracking the optimized reference voltage, the initial voltage of the voltage V3 of the third node and the initial voltage of the voltage V4 of the fourth node (refer to Figures 3 to 11D ) may be the previously generated optimized reference voltage (e.g., the optimized reference voltage generated in operation S210). Except that the initial voltage of the voltage V3 of the third node and the initial voltage of the voltage V4 of the fourth node are the previous optimized reference voltages, the remaining operations are similar to the above operations, and thus, additional description will be omitted to avoid repetition. Figure 8 ) may be the previously generated optimized reference voltage (e.g., the optimized reference voltage generated in operation S210). Except that the initial voltage of the voltage V3 of the third node and the initial voltage of the voltage V4 of the fourth node are the previous optimized reference voltages, the remaining operations are similar to the above operations, and thus, additional description will be omitted to avoid repetition.

[0137] In operation S250, the signal receiver 100 may perform communication by using the optimized reference voltage re-tracked in operation S240. Except that the optimized reference voltage is re-tracked, the operations of the signal receiver 100 for communication or determining the bit value of the input signal are similar to the above operations, and thus, additional description will be omitted to avoid repetition.

[0138] As described above, the signal receiver 100 according to an embodiment of the inventive concept may generate an optimized reference voltage for an input signal DIN. In this case, even if the input signal DIN is distorted due to various factors, the optimized reference voltage can be dynamically or actively tracked, so that the reliability of the signal receiver 100 can be improved.

[0139] Figure 13 is a block diagram illustrating a memory system according to an embodiment of the inventive concept. Referring to Figure 13 , the memory system 1000 may include a memory controller 1100 and a storage device 1200. The memory controller 1100 may be configured to control the storage device 1200. For example, the memory controller 1100 may store data “DATA” in the storage device 1200, or may read the data “DATA” stored in the storage device 1200. The storage device 1200 may operate under the control of the memory controller 1100. In an exemplary embodiment, the storage device 1200 may include: a volatile storage device (e.g., a static random access memory (SRAM) or a dynamic random access memory (DRAM)) in which data stored disappears when power is turned off, or a non-volatile storage device (e.g., a flash memory device, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM)) that can retain the stored data even when power is turned off.

[0140] In an exemplary embodiment, the memory controller 1100 and the storage device 1200 may exchange data “DATA” modulated based on 4-level pulse amplitude modulation (PAM-4). In this case, both the memory controller 1100 and the storage device 1200 may include the signal receiver 100 described with reference to Figures 3 to 12 , or may be configured to track / generate an optimized reference voltage based on the operation method described with reference to Figures 3 to 12 .

[0141] In an exemplary embodiment, the memory controller 1100 and the storage device 1200 may also exchange any other control signals (e.g., commands, addresses, and control signals) in addition to the data “DATA”. In this case, in addition to the data “DATA”, other control signals (e.g., commands, addresses, and control signals) may also be modulated based on 4-level pulse amplitude modulation (PAM-4). For other control signals, both the memory controller 1100 and the storage device 1200 may include the signal receiver 100 described with reference to Figures 3 to 12 , or may be configured to track / generate an optimized reference voltage based on the operation method described with reference to Figures 3 to 12 .

[0142] In an exemplary embodiment, an optimized reference voltage tracking / generation operation according to an embodiment of the inventive concept may be performed during an initialization process, a training process, or a calibration process of the memory system 1000.

[0143] Figure 14 is a block diagram illustrating an electronic device according to the inventive concept. Referring to Figure 14 , the electronic device 2000 may include a main processor 2100, a touch panel 2200, a touch driver integrated circuit (TDI) 2202, a display panel 2300, a display driver integrated circuit (DDI) 2302, a system memory 2400, a storage device 2500, an audio processor 2600, a communication block 2700, and an image processor 2800. In an exemplary embodiment, the electronic device 2000 may be one of various electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smart phone, a tablet PC, a laptop computer, and a wearable device.

[0144] The main processor 2100 may control the overall operation of the electronic device 2000. The main processor 2100 may control / manage the operations of the components of the electronic device 2000. The main processor 2100 may process various operations to operate the electronic device 2000.

[0145] The touch panel 2200 may be configured to sense a touch input from a user under the control of the touch driver integrated circuit 2202. The display panel 2300 may be configured to display image information under the control of the display driver integrated circuit 2302.

[0146] The system memory 2400 may store data for the operation of the electronic device 2000. For example, the system memory 2400 may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), and / or a non-volatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0147] The storage device 2500 may store data regardless of whether power is supplied. For example, the storage device 2500 may include at least one of various non-volatile memories such as a flash memory, a PRAM, an MRAM, a ReRAM, and a FRAM. For example, the storage device 2500 may include an embedded memory and / or a removable memory of the electronic device 2000.

[0148] The audio processor 2600 may process an audio signal by using the audio signal processor 2610. The audio processor 2600 may receive an audio input through the microphone 2620, or may provide an audio output through the speaker 2630.

[0149] The communication block 2700 may exchange signals with an external device / system through the antenna 2710. The transceiver 2720 and the modulator / demodulator (MODEM) 2730 of the communication block 2700 may process the signals exchanged with the external device / system based on at least one of various wireless communication protocols such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID).

[0150] The image processor 2800 may receive light through the lens 2810. The image device 2820 and the image signal processor (ISP) 2830 included in the image processor 2800 may generate image information about an external object based on the received light.

[0151] In an exemplary embodiment, Figure 14 the various components included in the electronic device 2000 or the various functional blocks included in each component may exchange information based on a 4-level Pulse Amplitude Modulation (PAM-4) scheme through various communication paths or channels. In this case, Figure 14 the various components included in the electronic device 2000 or the functional blocks included in each component may include the signal receiver 100 described with reference to Figures 3 to 12 or may be configured to track / generate an optimized reference voltage based on the operation method described with reference to Figures 3 to 12 In accordance with the inventive concept, the signal receiver may dynamically track or generate an optimized reference voltage for a received input signal. Accordingly, a signal receiver and an operation method thereof having improved reliability are provided.

[0152] Although the inventive concept has been described with reference to exemplary embodiments of the present invention, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the invention as set forth by the appended claims.

[0153] ​

Claims

1. A signal receiver, comprising: a data sampler configured to receive a differential input signal having a first input signal and a second input signal, and determine a bit value of the differential input signal based on a first reference voltage and a second reference voltage, wherein the second input signal is a complementary signal of the first input signal; and a reference voltage generator configured to perform a pre-tuning operation and a post-tuning operation to generate the first reference voltage and the second reference voltage, wherein the reference voltage generator is further configured to perform the pre-tuning operation by: generating a first initial voltage and a second initial voltage based on the first input signal and the second input signal, and adjusting one of the first initial voltage and the second initial voltage to generate a third voltage and a fourth voltage, and wherein the reference voltage generator is further configured to, after performing the pre-tuning operation, perform the post-tuning operation by: increasing or decreasing the third voltage to generate the first reference voltage based on a first comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and the second input signal, and decreasing or increasing the fourth voltage to generate the second reference voltage.

2. The signal receiver according to claim 1, Among them, wherein the reference voltage generator comprises: a peak voltage tracking circuit configured to generate a first peak voltage and a second peak voltage based on the first input signal and the second input signal, wherein the first peak voltage indicates a highest voltage level of the differential input signal and the second peak voltage indicates a lowest voltage level of the differential input signal; a common voltage tracking circuit configured to generate a common voltage, which is an average value of the first input signal and the second input signal; and a reference voltage tracking circuit configured to: perform the pre-tuning operation based on the first peak voltage, the second peak voltage, the common voltage, the third voltage and the fourth voltage; and perform the post-tuning operation in response to a comparison result between completion of the pre-tuning operation and a comparison result between the first comparison result and the second comparison result, such that the third voltage is increased or decreased by a first amount to generate the first reference voltage, and the fourth voltage is decreased or increased by the first amount to generate the second reference voltage.

3. The signal receiver according to claim 2, Among them, wherein the peak voltage tracking circuit is configured to output an enable signal after generating the first peak voltage and the second peak voltage, and wherein the reference voltage tracking circuit is further configured to receive the first peak voltage, the second peak voltage and the enable signal, and start the pre-tuning operation in response to the enable signal.

4. The signal receiver according to claim 2, Among them, wherein the peak voltage tracking circuit comprises: A first comparator configured to compare a voltage of a first node with the first input signal to output a third comparison result; A second comparator configured to compare a voltage of a second node with the second input signal to output a fourth comparison result; A peak switch control circuit configured to output a first peak switch signal and a second peak switch signal based on the third comparison result and the fourth comparison result; and A first voltage divider connected between a power supply voltage and a ground voltage, connected to the first comparator and the second comparator through the first node and the second node respectively, and the first voltage divider is configured to adjust the voltage of the first node and the voltage of the second node based on the first peak switch signal and the second peak switch signal respectively, wherein the voltage of the first node and the voltage of the second node as outputs of the first voltage divider correspond to the first peak voltage and the second peak voltage respectively.

5. The signal receiver according to claim 2, Among them, The common voltage tracking circuit includes: A first unity gain buffer; A first resistor connected to an input terminal of the first unity gain buffer and configured to receive the first input signal; and A second resistor connected to the input terminal of the first unity gain buffer and configured to receive the second input signal, wherein the first resistor and the second resistor are connected in parallel to the input terminal of the first unity gain buffer, and wherein a resistance value of the first resistor is equal to a resistance value of the second resistor.

6. The signal receiver according to claim 2, Among them, The reference voltage tracking circuit includes: A second voltage divider connected between the first peak voltage and the second peak voltage; A pre-tuning control circuit configured to output a pre-tuning signal based on the first peak voltage, the second peak voltage, the common voltage, a voltage of a third node and a voltage of a fourth node, wherein the pre-tuning control circuit is connected to the second voltage divider through the third node and the fourth node; A third comparator connected to the second voltage divider through the third node and configured to compare the voltage of the third node with the first input signal to output a third comparison result; A fourth comparator connected to the second voltage divider through the fourth node and configured to compare the voltage of the fourth node with the second input signal to output a fourth comparison result; and A reference switch control circuit configured to output a first reference switch signal and a second reference switch signal to the second voltage divider based on the pre-tuning signal, the third comparison result and the fourth comparison result, Wherein, the second voltage divider is configured to control the voltage of the third node and the voltage of the fourth node in response to the first reference switch signal and the second reference switch signal.

7. The signal receiver according to claim 6, Among them, The pre-tuning control circuit includes: A second unity-gain buffer; A third resistor connected between the third node and the input terminal of the second unity-gain buffer; A fourth resistor connected between the fourth node and the input terminal of the second unity-gain buffer; A third unity-gain buffer; A fifth resistor connected to the input terminal of the third unity-gain buffer, the fifth resistor being configured to receive the first peak voltage; A sixth resistor connected to the input terminal of the third unity-gain buffer, the sixth resistor being configured to receive the second peak voltage; A seventh resistor connected to the input terminal of the third unity-gain buffer, the seventh resistor being configured to receive the common voltage, Wherein, the fifth resistor, the sixth resistor and the seventh resistor are connected in parallel to the input terminal of the third unity-gain buffer; and A fifth comparator configured to compare the output of the second unity-gain buffer and the output of the third unity-gain buffer, and output the pre-tuning signal as a result of the comparison.

8. The signal receiver according to claim 7, Among them, The reference voltage generator performs the pre-tuning operation in response to the output of the second unity-gain buffer and the output of the third unity-gain buffer being different from each other, Wherein, the reference switch control circuit is configured to generate the first reference switch signal in response to the pre-tuning signal of the first mode output from the pre-tuning control circuit, so that the voltage of the third node decreases, the pre-tuning signal of the first mode corresponds to the case where the output of the second unity-gain buffer is greater than the output of the third unity-gain buffer, and Wherein, the reference switch control circuit is configured to generate the second reference switch signal in response to the pre-tuning signal of the second mode, so that the voltage of the fourth node increases, the pre-tuning signal of the second mode corresponds to the case where the output of the second unity-gain buffer is less than the output of the third unity-gain buffer.

9. The signal receiver according to claim 8, Among them, The pre-tuning control circuit is configured to generate a deactivate pre-tuning signal in response to the output of the second unity-gain buffer and the output of the third unity-gain buffer being the same as each other. Wherein, the reference voltage generator is configured to perform the post-tuning operation in response to the deactivate pre-tuning signal output from the pre-tuning control circuit, such that the reference switch control circuit generates the first reference switch signal to decrease the voltage of the third node, and generates the second reference switch signal to increase the voltage of the fourth node.

10. The signal receiver according to claim 9, Among them, The reference voltage generator is configured to repeat the post-tuning operation until the third comparison result of the third comparator is the same as the fourth comparison result of the fourth comparator.

11. The signal receiver according to claim 1, Among them, The differential input signal is an N-level PAM multi-level signal, where N is greater than or equal to 4.

12. The signal receiver according to claim 11, Among them, The data sampler is configured to: When the first input signal is higher than the first reference voltage, determine that the bit value of the differential input signal is a first value; When the first input signal is lower than the second reference voltage, determine that the bit value of the differential input signal is a second value; When the first input signal is lower than the first reference voltage and higher than the second reference voltage, and the first input signal is higher than the second input signal, determine that the bit value of the differential input signal is a third value; And When the first input signal is lower than the first reference voltage and higher than the second reference voltage, and the first input signal is lower than the second input signal, determine that the bit value of the differential input signal is a fourth value.

13. A method for operating a signal receiver, the method comprising: Receiving a differential input signal having a first input signal and a second input signal, the second input signal being a complementary signal of the first input signal; Performing a pre-tuning operation, the pre-tuning operation comprising: Generating a first peak voltage, a second peak voltage, and a common voltage based on the first input signal and the second input signal, wherein the first peak voltage is greater than the second peak voltage, and wherein the common voltage is between the first peak voltage and the second peak voltage; Setting a first initial voltage and a second initial voltage, wherein the first initial voltage and the second initial voltage are between the first peak voltage and the second peak voltage; and Increasing or decreasing one of the first initial voltage and the second initial voltage to generate a first voltage and a second voltage until the first voltage and the second voltage satisfy a first condition; after performing the pre-tuning operation, performing a post-tuning operation to generate a first optimized reference voltage and a second optimized reference voltage; The post-tuning operation includes: gradually increasing or decreasing the first voltage and gradually decreasing or increasing the second voltage to generate a first optimized reference voltage and a second optimized reference voltage until the first optimized reference voltage and the second optimized reference voltage satisfy a second condition, wherein during the post-tuning operation, the increased or decreased first voltage and the decreased or increased second voltage satisfy the first condition; and Determine the bit value of the differential input signal based on the first optimized reference voltage and the second optimized reference voltage.

14. The method according to claim 13, Among them, wherein the first condition refers to the condition that the sum of the first voltage and the second voltage is equal to the sum of the common voltage and the intermediate value between the first peak voltage and the second peak voltage, and wherein the second condition refers to the condition that the comparison result between the first optimized reference voltage and the first input signal is the same as the comparison result between the second optimized reference voltage and the second input signal.

15. The method according to claim 13, Among them, wherein the increment or decrement by which the first voltage increases or decreases step by step is equal to the decrement or increment by which the second voltage decreases or increases step by step.

16. The method according to claim 13, Among them, wherein the first initial voltage is 2 / 3 of the sum of the first peak voltage and the second peak voltage, and the second initial voltage is 1 / 3 of the sum of the first peak voltage and the second peak voltage, wherein when the sum of the first voltage and the second voltage is greater than the sum of the common voltage and the intermediate value between the first peak voltage and the second peak voltage, the first voltage is generated by decreasing the first initial voltage, and the second voltage is generated by maintaining the second initial voltage, and wherein when the sum of the first voltage and the second voltage is less than the sum of the common voltage and the intermediate value between the first peak voltage and the second peak voltage, the first voltage is generated by maintaining the first initial voltage, and the second voltage is generated by increasing the second initial voltage.

17. The method according to claim 13, Among them, wherein the first initial voltage and the second initial voltage have the same voltage, which is the intermediate value between the first peak voltage and the second peak voltage, wherein when the sum of the first voltage and the second voltage is greater than the sum of the common voltage and the intermediate value between the first peak voltage and the second peak voltage, the first voltage is generated by maintaining the first initial voltage, and the second voltage is generated by decreasing the second initial voltage, and wherein when the sum of the first voltage and the second voltage is less than the sum of the common voltage and the intermediate value between the first peak voltage and the second peak voltage, the first voltage is generated by increasing the first initial voltage, and the second voltage is generated by maintaining the second initial voltage.

18. The method according to claim 13, Among them, wherein the differential input signal is an N-level PAM multi-level signal, and N is greater than or equal to 4.

19. A method for operating a signal receiver, the method comprising: Performing an initialization operation to generate a first reference voltage and a second reference voltage; Receiving a differential input signal having a first input signal and a second input signal from an external device, wherein the second input signal is a complementary signal of the first input signal; Determine a first bit value of the differential input signal based on the first reference voltage and the second reference voltage, where the differential input signal is an N-level PAM multi-level signal and N is greater than or equal to 4; Detect whether the differential input signal is distorted based on the determined first bit value of the differential input signal; In response to detecting the distortion, perform a pre-tuning operation by: based on the first input signal and the second input signal, adjusting one of the first reference voltage and the second reference voltage to generate a first voltage and a second voltage; Perform a post-tuning operation by: based on a first comparison result between the first voltage and the first input signal and a second comparison result between the second voltage and the second input signal, increasing or decreasing the first voltage to generate a first optimized reference voltage, and decreasing or increasing the second voltage to generate a second optimized reference voltage; and Determine the bit value of the differential input signal based on the first optimized reference voltage and the second optimized reference voltage.

20. The method according to claim 19, Among them, Perform adjusting one of the first reference voltage and the second reference voltage until the first voltage and the second voltage satisfy a first condition, wherein perform increasing or decreasing the first voltage and decreasing or increasing the second voltage until the first optimized reference voltage and the second optimized reference voltage satisfy a second condition, wherein the first voltage increased or decreased and the second voltage decreased or increased during performing the post-tuning operation satisfy the first condition, wherein the first condition refers to such a condition that the sum of the first voltage and the second voltage is equal to the sum of a common voltage and a middle value between a first peak voltage and a second peak voltage, wherein the second condition refers to such a condition that the comparison result between the first optimized reference voltage and the first input signal is the same as the comparison result between the second optimized reference voltage and the second input signal, and wherein the first peak voltage refers to the highest voltage level of the differential input signal, the second peak voltage refers to the lowest voltage level of the differential input signal, and the common voltage refers to the average value of the first input signal and the second input signal.

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