Semiconductor packaging device and manufacturing method thereof

Abstract

The present disclosure relates to a semiconductor packaging device and a method for manufacturing the same. The semiconductor packaging device includes: a substrate and a redistribution layer, the substrate and the redistribution layer being electrically connected via a conductive line; and a capacitor electrically connected to the conductive line. In the semiconductor packaging device and method for manufacturing the same provided by the present disclosure, by providing a capacitor in the line between the substrate and the redistribution layer and utilizing the capacitor as a decoupling element, the coupling phenomenon between the substrate line and the redistribution layer line can be eliminated, thereby eliminating signal noise caused by the coupling and preventing mutual interference between the substrate line and the redistribution line at high frequencies, thereby improving the quality of signal transmission in the semiconductor packaging device and thereby improving the performance of the electronic device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and more particularly to a semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] In fan-out substrate (FOSub) structures, coupling between the redistribution layer (RDL) and substrate circuits causes signal noise within the circuits. This signal noise is transmitted from the RDL circuits to the substrate circuits, and vice versa, affecting the signals within the circuits. When the overall package structure operates at low frequencies, the impact of this signal noise is minimal. However, when the overall package structure operates at high frequencies, this signal noise can significantly impact signal quality.

[0003] Therefore, it is necessary to propose a new technical solution to solve at least one of the above technical problems. Summary of the Invention

[0004] The present disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0005] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0006] First circuit layer;

[0007] a second circuit layer, electrically connected to the second circuit layer via a conductive line;

[0008] A capacitor is electrically connected to the conductive line.

[0009] In some optional implementations, the capacitor is located between the first circuit layer and the second circuit layer.

[0010] In some optional embodiments, the capacitor includes at least two conductive layers, and an insulating layer is provided between adjacent conductive layers.

[0011] In some optional embodiments, the capacitor has at least one protrusion structure.

[0012] In some optional embodiments, the at least two conductive layers include at least two first conductive layers and at least two second conductive layers, the at least two first conductive layers are electrically connected to each other, and the at least two second conductive layers are electrically connected to each other.

[0013] In some optional embodiments, a dielectric material is provided on the surface of the capacitor, and a first conductive hole and a second conductive hole are provided on the dielectric material;

[0014] The first end of each of the first conductive vias is electrically connected to the first conductive layer, and the second ends of the first conductive vias are located in the same horizontal plane and are electrically connected to each other;

[0015] The first end of each second conductive via is electrically connected to the second conductive layer, and the second ends of the second conductive vias are located in the same horizontal plane and are electrically connected to each other.

[0016] In some optional embodiments, the first end of the first conductive via contacts the first conductive layer and the insulating layer simultaneously, and the first end of the second conductive via contacts the second conductive layer and the insulating layer simultaneously.

[0017] In some optional embodiments, the horizontal cross-section of the protrusion structure is circular or square.

[0018] In some optional embodiments, the conductive line includes a first conductive via.

[0019] In some optional embodiments, the capacitor is electrically connected to the conductive line through a second conductive via.

[0020] In some optional implementations, the bottom surface of the capacitor is located on the first circuit layer; or

[0021] The bottom surface of the capacitor is located on the second circuit layer.

[0022] In some optional embodiments, the bottom surface of the capacitor is located on the first circuit layer, and the top of the protruding structure is electrically connected to the second circuit layer through a third conductive through-hole.

[0023] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0024] forming a capacitor;

[0025] Joining the first circuit layer, the second circuit layer and the capacitor into a whole;

[0026] A conductive line is formed between the first wiring layer and the second wiring layer, and the capacitor is electrically connected to the conductive line.

[0027] In some optional embodiments, forming a capacitor includes:

[0028] Conductive layers and insulating layers are alternately formed on a carrier to obtain the capacitor.

[0029] In some optional embodiments, the capacitor includes at least two first conductive layers and at least two second conductive layers; and

[0030] The forming of the capacitor further comprises:

[0031] forming a dielectric material on a surface of the capacitor;

[0032] A first conductive via and a second conductive via are formed in the dielectric material, wherein a first end of each of the first conductive vias is electrically connected to the first conductive layer, and a second end of each of the first conductive vias is located at the same horizontal plane and electrically connected to each other, and a first end of each of the second conductive vias is electrically connected to the second conductive layer, and a second end of each of the second conductive vias is located at the same horizontal plane and electrically connected to each other.

[0033] In some optional implementations, the capacitor is formed on the second circuit layer; and

[0034] The step of joining the first circuit layer, the second circuit layer and the capacitor into a whole comprises: joining the second circuit layer together with the capacitor to the first circuit layer; or

[0035] The capacitor is formed separately; and

[0036] The step of joining the first circuit layer, the second circuit layer and the capacitor into a whole comprises: first joining the capacitor to the first circuit layer, and then joining the second circuit layer to the capacitor.

[0037] In some optional implementations, forming a conductive line between the first circuit layer and the second circuit layer, and electrically connecting the capacitor to the conductive line includes:

[0038] forming a first conductive through hole on the second circuit layer, the capacitor, and the first circuit layer to electrically connect the first circuit layer and the second circuit layer and obtain the conductive circuit;

[0039] A second conductive via is formed on the second wiring layer and the capacitor to electrically connect the capacitor to the conductive wiring.

[0040] In the semiconductor packaging device and manufacturing method provided by the present disclosure, by setting a capacitor in the circuit between the first circuit layer and the second circuit layer, and using the capacitor as a decoupling element, the coupling phenomenon between the first circuit layer circuit and the second circuit layer circuit can be eliminated, thereby eliminating the signal noise caused by the coupling, avoiding mutual interference between the first circuit layer circuit and the redistribution circuit at high frequencies, which is beneficial to improving the quality of signal transmission in the semiconductor packaging device, thereby improving the performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0042] Figure 1 is a schematic diagram of a semiconductor packaging device in the prior art;

[0043] Figure 2-Figure 10 are first to ninth schematic diagrams of a semiconductor package device according to an embodiment of the present invention;

[0044] Figure 11-14 is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0045] Explanation of symbols:

[0046] 11. First circuit structure; 12. Second circuit structure; 13. Conductive structure; 100. First circuit layer; 200. Second circuit layer; 300. Capacitor; 310. First conductive layer; 320. Second conductive layer; 330. Insulating layer; 340. First conductive hole; 350. Second conductive hole; 360. Dielectric material; 370. Protrusion structure; 390. Connecting line; 400. Adhesive layer; 510. First conductive via; 520. Second conductive via; 530. Third conductive via; 910. Carrier; 920. Photoresist; 930. Opening; 940. Seed layer; 950. Through hole. DETAILED DESCRIPTION

[0047] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present invention and the technical effects produced by the present invention through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0048] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0049] It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0050] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0051] Figure 1 Schematic diagram of a semiconductor packaging device in the prior art. Figure 1 As shown, a conventional semiconductor package device includes a first circuit structure 11 and a second circuit structure 12, which are electrically connected via a conductive structure 13. First circuit structure 11 is, for example, a substrate, and second circuit structure 12 is, for example, a redistribution layer. In this semiconductor package device, coupling occurs between first and second circuit structures 11, 12. When the overall package structure operates at high frequencies, this coupling can cause signal noise in the circuits, significantly impacting signal quality.

[0052] Figure 2-Figure 10 1 to 9 are first to ninth schematic diagrams of a semiconductor package device according to an embodiment of the present invention.

[0053] like Figure 2 As shown, the semiconductor package device in this embodiment includes a first circuit layer 100 , a second circuit layer 200 and a capacitor 300 .

[0054] In this embodiment, first circuit layer 100 and second circuit layer 200 are electrically connected via a conductive line, which includes first conductive vias 510. Capacitor 300 is electrically connected to second circuit layer 200 via second conductive vias 520, thereby electrically connecting capacitor 300 to the conductive line between first circuit layer 100 and second circuit layer 200. First circuit layer 100 is, for example, a substrate, and second circuit layer 200 is, for example, a redistribution layer.

[0055] In this embodiment, the first circuit layer 100 and the second circuit layer 200 are substantially parallel to each other, and the capacitor 300 is located between the first circuit layer 100 and the second circuit layer 200. The first circuit layer 100 and the second circuit layer 200 are connected by an adhesive layer 400, and the capacitor 300 is partially embedded in the adhesive layer 400.

[0056] In this embodiment, the capacitor 300 is embedded in the semiconductor package device, which is beneficial for reducing the size of the semiconductor package device.

[0057] Figure 3 FIG. 3 shows the specific structure of the capacitor 300 in this embodiment. Figure 3As shown, capacitor 300 includes at least two conductive layers, including at least two first conductive layers 310 and at least two second conductive layers 320. The at least two first conductive layers 310 are electrically connected to each other, and the at least two second conductive layers 320 are electrically connected to each other. The first conductive layer 310 can serve as the positive electrode of capacitor 300, and the second conductive layer 320 can serve as the negative electrode of capacitor 300 (or vice versa). An insulating layer 330 is provided between adjacent conductive layers (e.g., a first conductive layer 310 and an adjacent second conductive layer 320).

[0058] In this embodiment, the capacitor 300 has a multi-layer structure, which is beneficial for increasing the capacitance of the capacitor 300 .

[0059] In this embodiment, the capacitor 300 has at least one protrusion structure 370. The protrusion structure 370 is provided to increase the volume of the capacitor 300, thereby further increasing the capacitance of the capacitor 300.

[0060] In this embodiment, the horizontal cross-section of the protrusion structure 370 can adopt various shapes. Figure 4 As shown, the horizontal cross section of the protrusion structure 370 is circular, the diameter of the horizontal cross section gradually changes in the vertical direction, and the overall shape is a truncated cone. Figure 8 As shown, the horizontal cross-section of the protrusion structure 370 is a square, and the overall shape can be a prism or a terrace.

[0061] In this embodiment, a dielectric material 360 is provided on the surface of the capacitor 300. A first conductive via 340 and a second conductive via 350 are provided on the dielectric material 360. The first end of each first conductive via 340 is electrically connected to the first conductive layer 310, and the second ends of each first conductive via 340 are located at the same level and electrically connected to each other. The first end of each second conductive via 350 is electrically connected to the second conductive layer 320, and the second ends of each second conductive via 350 are located at the same level and electrically connected to each other.

[0062] In this embodiment, the first end of the first conductive via 340 contacts both the first conductive layer 310 and the insulating layer 330 , and the first end of the second conductive via 350 contacts both the second conductive layer 320 and the insulating layer 330 .

[0063] In this embodiment, the conductive layers at different levels can be connected to the same level through the first conductive hole 340 and the second conductive hole 350, which is conducive to making the external connection of the capacitor 300 more convenient. Figure 10 As shown, the conductive layers at different levels are connected to the same level through the connecting line 390 .

[0064] In this embodiment, the plurality of first conductive vias 340 and the plurality of second conductive vias 350 may be arranged in rows and columns to increase the number of external connection points of the capacitor 300. Figure 4 As shown, a plurality of first conductive vias 510 are arranged in a row and electrically connected to each other, and a plurality of second conductive vias 350 are arranged in a row and electrically connected to each other. Figure 7 As shown, the plurality of first conductive vias 340 are connected to form a trench. Similarly, the plurality of second conductive vias 350 are connected to form a trench.

[0065] In this embodiment, the bottom surface of the capacitor 300 may be located on the second circuit layer 200 (eg Figure 5 The first circuit layer 100 may also be located on the first circuit layer 100 (as shown in the upper part). Figure 5 shown below).

[0066] In this embodiment, if Figure 6 As shown, the bottom surface of the capacitor 300 may be located on the first circuit layer 100 , and the top of the protrusion structure 370 may be electrically connected to the second circuit layer 200 through the third conductive via 530 .

[0067] In this embodiment, if Figure 3 As shown, the first conductive via 340 and the second conductive via 350 may be located on the same side as the protrusion structure 370. Figure 9 As shown, the first conductive via 340 and the second conductive via 350 may be located on opposite sides of the protrusion structure 370 .

[0068] In the semiconductor packaging device of this embodiment, by providing a capacitor 300 in the circuit between the first circuit layer 100 and the second circuit layer 200, and utilizing the capacitor 300 as a decoupling element, the coupling phenomenon between the circuit of the first circuit layer 100 and the circuit of the second circuit layer 200 can be eliminated, thereby eliminating signal noise caused by the coupling and preventing mutual interference between the circuit of the first circuit layer 100 and the second circuit layer 200 at high frequencies. This is beneficial to improving the quality of signal transmission in the semiconductor packaging device, thereby improving the performance of the electronic device.

[0069] This embodiment also provides a method for manufacturing a semiconductor packaging device. Figure 11-14 As shown, the method includes the following steps:

[0070] In the first step, capacitor 300 is formed.

[0071] like Figure 11As shown, a first conductive layer 310 can be formed on a carrier 910 by physical vapor deposition (PVD), a photoresist 920 is then deposited on the first conductive layer 310 and a photolithographic pattern is formed, and then the protrusion structure 370 is formed by electroplating. After removing the photoresist 920, an insulating layer 330 is formed on the first conductive layer 310, and a second conductive layer 320 is formed on the insulating layer 330.

[0072] By repeating the above steps, we can get Figure 12 The structure shown at the top of FIG. On this basis, a stepped structure can be formed on each layer, and a dielectric material 360 is provided on the surface of the capacitor 300. Thereafter, an opening 930 is provided on the dielectric material 360 and a seed layer 940 is formed on the surface of the dielectric material 360, and then the first conductive vias 340 and the second conductive vias 350 are formed by electroplating. The first end of each first conductive via 340 is electrically connected to the first conductive layer 310, and the second ends of each first conductive via 340 are located at the same horizontal plane and are electrically connected to each other. The first end of each second conductive via 350 is electrically connected to the second conductive layer 320, and the second ends of each second conductive via 350 are located at the same horizontal plane and are electrically connected to each other.

[0073] In the second step, the first circuit layer 100 , the second circuit layer 200 and the capacitor 300 are bonded together into a whole.

[0074] In the first case, the capacitor 300 is formed separately. In this case, the capacitor 300 can be connected to the first circuit layer 100 through the adhesive layer 400, and then the second circuit layer 200 is connected to the capacitor 300, so as to obtain the following structure: Figure 13 The structure shown at the top.

[0075] In the second case, the capacitor 300 is formed on the second wiring layer 200 (eg Figure 14 As shown), the second circuit layer 200 together with the capacitor 300 is integrally bonded to the first circuit layer 100 to obtain Figure 13 The structure shown at the top.

[0076] In the third step, a conductive line is formed between the first circuit layer 100 and the second circuit layer 200 , and the capacitor 300 is electrically connected to the conductive line.

[0077] like Figure 13As shown, through holes 950 can be formed on the second circuit layer 200 and the adhesive layer 400 by laser drilling or other methods, and then first conductive vias 510 and second conductive vias 520 can be formed by electroplating or other methods. The first conductive vias 510 electrically connect the first circuit layer 100 and the second circuit layer 200 to form a conductive circuit, and the second conductive vias 520 electrically connect the capacitor 300 to the conductive circuit.

[0078] The method for manufacturing the semiconductor packaging device in this embodiment can achieve the technical effects of the semiconductor packaging device described above, and will not be described in detail here.

[0079] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: First circuit layer; a second circuit layer electrically connected to the first circuit layer via a conductive line; a capacitor electrically connected to the conductive line, the capacitor comprising at least two conductive layers and at least one protrusion structure, with an insulating layer provided between adjacent conductive layers; The at least two conductive layers include at least two first conductive layers and at least two second conductive layers, the at least two first conductive layers are electrically connected to each other, and the at least two second conductive layers are electrically connected to each other; A dielectric material is provided on the surface of the capacitor, and a first conductive hole and a second conductive hole are provided on the dielectric material; The first end of each of the first conductive vias is electrically connected to the first conductive layer, and the second ends of the first conductive vias are located in the same horizontal plane and are electrically connected to each other; The first end of each second conductive via is electrically connected to the second conductive layer, and the second ends of the second conductive vias are located in the same horizontal plane and are electrically connected to each other.

2. The semiconductor package device according to claim 1, wherein The capacitor is located between the first circuit layer and the second circuit layer.

3. The semiconductor package device according to claim 1, wherein A first end of the first conductive via contacts the first conductive layer and the insulating layer simultaneously, and a first end of the second conductive via contacts the second conductive layer and the insulating layer simultaneously.

4. The semiconductor package device according to claim 1, wherein The conductive circuit includes a first conductive via.

5. The semiconductor package device according to claim 1, wherein The capacitor is electrically connected to the conductive line through a second conductive via.

6. The semiconductor package device according to claim 1, wherein The bottom surface of the capacitor is located on the first circuit layer; or The bottom surface of the capacitor is located on the second circuit layer.

7. The semiconductor package device according to claim 1, wherein The bottom surface of the capacitor is located on the first circuit layer, and the top of the protrusion structure is electrically connected to the second circuit layer through a third conductive through-hole.

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