Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor package device and a manufacturing method thereof. The semiconductor package device includes a lead frame having opposite first and second surfaces, a first chip disposed on the first surface with an active surface facing the first surface, and a protective layer covering the first surface and at least a portion of the first chip, wherein a non-active surface of the first chip is at least partially exposed by the protective layer. The semiconductor package device has the non-active surface of the first chip at least partially exposed by the protective layer, which is beneficial for heat dissipation of the non-active surface of the first chip.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular, to a semiconductor packaging device and a manufacturing method thereof. BACKGROUND

[0002] A common advanced embedded active system integration (aEASI) is to paste a chip on a lead frame with a non-active surface, and to dissipate heat from the chip through the lead frame. Since the lead frame is covered by a dielectric material, the heat dissipation capacity of the lead frame is limited. As the power of the chip becomes larger and larger, the heat dissipation problem becomes more and more serious. SUMMARY

[0003] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0004] a lead frame having opposite first and second surfaces;

[0005] a first chip disposed on the first surface with an active surface facing the first surface;

[0006] a protective layer covering the first surface and at least part of the first chip, and a non-active surface of the first chip being at least partially exposed from the protective layer.

[0007] In some optional embodiments, the device further comprises:

[0008] a circuit layer disposed on the second surface, and the first chip being electrically connected to the circuit layer.

[0009] In some optional embodiments, the circuit layer comprises a redistribution layer.

[0010] In some optional embodiments, the device further comprises:

[0011] a second chip disposed on the second surface with a non-active surface facing the second surface, and the second chip being electrically connected to the first chip through the circuit layer.

[0012] In some optional embodiments, the device further comprises:

[0013] a heat dissipation component disposed on the non-active surface of the first chip.

[0014] In some optional embodiments, the device further comprises:

[0015] an electrical connector disposed on the active surface of the first chip and penetrating through the lead frame.

[0016] In a second aspect, the present disclosure provides a semiconductor package device, comprising:

[0017] a leadframe having a first surface and a second surface opposite to each other;

[0018] a first chip disposed on the first surface with an active surface facing the first surface;

[0019] a second chip disposed on the second surface with a non-active surface facing the second surface;

[0020] a circuit layer, the first chip is electrically connected with the second chip through the circuit layer.

[0021] In some optional embodiments, the active surface of the first chip and the active surface of the second chip both face the circuit layer.

[0022] In some optional embodiments, the device further comprises:

[0023] a protective layer covering the first surface and at least part of the first chip, the non-active surface of the first chip is at least partially exposed from the protective layer.

[0024] In some optional embodiments, the device further comprises:

[0025] a heat dissipation component disposed on the non-active surface of the first chip.

[0026] In some optional embodiments, the device further comprises:

[0027] an adhesive layer disposed between the leadframe and the circuit layer, covering at least part of the active surface of the first chip, the active surface of the second chip and the second surface.

[0028] In some optional embodiments, the device further comprises:

[0029] a passive electronic component disposed on the second surface.

[0030] In some optional embodiments, the passive electronic component is electrically connected with the first chip.

[0031] In a third aspect, the present disclosure provides a method for manufacturing a semiconductor package device, comprising:

[0032] providing a leadframe having a first surface and a second surface opposite to each other and an opening;

[0033] attaching a first chip with an active surface corresponding to the opening on the first surface;

[0034] attaching a second chip with a non-active surface on the second surface;

[0035] providing a circuit layer and a dielectric layer, the circuit layer being provided with an adhesive layer, the dielectric layer being provided with a protective layer;

[0036] pressing the protective layer corresponding to the first surface and the adhesive layer corresponding to the second surface, so that the non-active surface of the first chip at least partially abuts the dielectric layer;

[0037] electrically connecting the active surface of the first chip to the circuit layer through the opening;

[0038] electrically connecting the active surface of the second chip to the circuit layer, so that the first chip is electrically connected to the second chip through the circuit layer.

[0039] In some optional embodiments, the method further comprises:

[0040] forming a heat dissipation component on the dielectric layer corresponding to the non-active surface of the first chip, the heat dissipation component being attached to the non-active surface of the first chip.

[0041] In the semiconductor packaging device and the manufacturing method thereof provided by the present disclosure, by designing the semiconductor packaging device to include a lead frame having opposite first and second surfaces, a first chip disposed on the first surface with an active surface facing the first surface, and a protective layer covering the first surface and at least part of the first chip, with the non-active surface of the first chip at least partially exposed outside the protective layer. In this way, the non-active surface of the first chip is at least partially in direct contact with the outside of the protective layer, and the non-active surface of the first chip does not need to be in contact with the lead frame and can directly dissipate heat to the outside, avoiding the problem of limited heat dissipation caused by the power increase of the first chip due to the heat dissipation capacity limitation caused by the lead frame being covered by the dielectric material, thereby improving the overall heat dissipation performance of the semiconductor packaging device. BRIEF DESCRIPTION OF DRAWINGS

[0042] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the accompanying drawings:

[0043] Figure 1 is a longitudinal cross-sectional structure schematic diagram of one embodiment of a semiconductor packaging device according to the present disclosure;

[0044] Figures 2A to 2E is a longitudinal cross-sectional structure schematic diagram of different embodiments of a semiconductor packaging device according to the present disclosure;

[0045] Figure 3A and 3B is a top view and longitudinal cross-sectional structure schematic diagram of a semiconductor packaging device at a manufacturing stage according to one embodiment of the present disclosure;

[0046] Figures 3C to 3E is a longitudinal sectional structure schematic diagram of a semiconductor package device at a manufacturing stage according to one embodiment of the present disclosure.

[0047] Symbol explanation: 11 - lead frame; 11a - first surface; 11b - second surface; 12 - first chip; 12a - first chip active surface; 12b - first chip non-active surface; 123 - electrical connection; 13 - second chip; 13a - second chip active surface; 13b - second chip non-active surface; 14 - protective layer; 15 - adhesive layer; 16 - circuit layer; 17 - dielectric layer; 18 - heat dissipation component; 19 - passive electronic component; 20 - wire; 21 - first carrier plate; 22 - second carrier plate; D R - via diameter; D T - through-hole diameter; T D - dielectric layer thickness; T T - protective layer thickness; T B - adhesive layer thickness; T L - lead frame thickness; O S - lead frame opening width; D E - horizontal distance between first chip edge and lead frame opening edge. DETAILED DESCRIPTION

[0048] The specific embodiments of the present disclosure will be described below with reference to the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the content recorded in the present specification. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0049] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and do not have technical significance to limit the conditions that the present disclosure can be implemented, so any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects produced by the present disclosure and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and not to limit the scope of the present disclosure that can be implemented, the change or adjustment of the relative relationship without substantially changing the technical content should also be considered as the scope of the present disclosure that can be implemented.

[0050] It should be further noted that the longitudinal section of the embodiments of the present disclosure can be a corresponding front view direction section, the transverse section can be a corresponding right view direction section, and the horizontal section can be a corresponding top view direction section.

[0051] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0052] Reference Figure 1 , Figure 1 is a longitudinal section structure schematic diagram of one embodiment of the semiconductor package device according to the present disclosure.

[0053] As Figure 1 shown, the semiconductor package device 100 can include a lead frame 11, a first chip 12, a second chip 13, a protective layer 14, and a circuit layer 16. Among them:

[0054] The lead frame 11 has opposite first and second surfaces 11a and 11b.

[0055] The lead frame is a chip carrier of an integrated circuit, which is a key structural part for realizing the electrical connection between the internal circuit lead-out end of the chip and the external lead wire through a bonding material (gold wire, aluminum wire, copper wire), and forming an electrical circuit. In the present disclosure, the lead frame 11 can include a lead frame composed of a metal material or a non-metal material. Here, the metal material may, for example, be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. The non-metal material can include an organic material or a non-metal inorganic material, wherein the organic material may, for example, be polyaniline or the like, and the inorganic material may, for example, be graphene or the like.

[0056] The first chip 12 is disposed on the first surface 11a, and the active surface 12a of the first chip 12 faces the first surface 11a.

[0057] The second chip 13 is disposed on the second surface 11b, and the non-active surface 13b of the second chip 13 faces the second surface 11b.

[0058] The type of the first chip 12 is not specifically limited in the present disclosure, and the first chip 12 may, for example, include a die, an ASIC (Application Specific Integrated Circuit) chip, a PMIC (Power Management Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip, etc.

[0059] The protective layer 14 covers the first surface 11a and at least part of the first chip 12, and the non-active surface 12b of the first chip is at least partially exposed from the protective layer 14.

[0060] The protective layer 14 can include liquid and / or thin film organic materials, such as non-conductive plastic (NCP), non-conductive film (NCF), anisotropic conductive adhesive film (ACF), anisotropic conductive adhesive plastic (ACP), polyimide (PI), epoxy, resin, PP (PrePreg, semi-cured resin or semi-cured sheet), ABF (Ajinomoto Build-up Film), glue, polyamide (PA), etc. This is only an example of the material of the protective layer 14, not a specific limitation.

[0061] The non-active surface 12b of the first chip is at least partially exposed from the protective layer 14, so that the first chip 12 can dissipate heat through the at least partially exposed non-active surface 12b of the first chip 12 from the protective layer 14, thereby reducing the impact of the limited heat dissipation capacity of the current lead frame 11 on the heat dissipation of the first chip 12, and improving the heat dissipation effect of the non-active surface 12b of the first chip.

[0062] The circuit layer 16 can be a redistribution layer composed of conductive traces and dielectric materials. It is to be noted that any currently known or future developed redistribution layer forming technique can be used in the process, which is not limited in the present application, for example, the redistribution layer can be formed by photolithography, plating, electroless plating, etc., which are not limited. Here, the dielectric materials can include organic and / or inorganic materials, wherein the organic materials can be, for example, polyamide (PA), PI, epoxy, poly-p-phenylenebenzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP, ABF, etc., and the inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive materials can include seed layers and metal layers. Here, the seed layers can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layers can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0063] In some optional embodiments, as shown in FIG. 1C, the first chip active surface 12a and the second chip active surface 13a both face the circuit layer 16. This shortens the electrical connection path between the first chip 12 and the second chip 13 and the circuit layer 16, reduces the electrical resistance of the electrical connection path, and the shorter electrical connection path can accelerate the heat transfer and improve the heat dissipation rate of the first chip active surface 12a and the second chip active surface 13a. Figure 1

[0064] The following refers to Figure 2A , Figure 2A is a longitudinal cross-sectional structure schematic diagram of one embodiment 200A of a semiconductor packaging device according to the present disclosure. Figure 2A The semiconductor packaging device 200A shown in FIG. 1C is similar to the semiconductor packaging device 100 shown in FIG. 1A, except that the semiconductor packaging device 200A can further include an electrical connection member 123 and an adhesive layer 15, wherein: Figure 1

[0065] The electrical connection member 123 is disposed on the first chip active surface 12a and penetrates the lead frame 11.

[0066] The electrical connection member 123 is electrically connected to the first chip 12, and the circuit layer 16 is electrically connected to the electrical connection member 123 to achieve electrical connection between the circuit layer 16 and the first chip 12.

[0067] ​​The electrical connecting member 123 can reduce the depth of the via hole provided on the circuit layer 16 during the electrical connection between the circuit layer 16 and the first chip 12. Due to the limitation of the photolithography process, the depth of the via hole is positively correlated with the diameter of the opening of the via hole on the circuit layer 16. Therefore, reducing the depth of the via hole can reduce the size of the opening on the circuit layer 16, and further increase the input / output (I / O) number of the device 200A.

[0068] The adhesive layer 15 is provided between the lead frame 11 and the circuit layer 16, and the electrical connecting member 15 covers at least part of the active surface of the first chip 12, the active surface of the second chip 13 and the second surface 11b.

[0069] The material of the adhesive layer 15 can be the same as or different from that of the protective layer 14.

[0070] Reference will now be made to Figure 2B , Figure 2B is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200B of a semiconductor packaging device according to the present disclosure. Figure 2B The semiconductor packaging device 200B shown is similar to the semiconductor packaging device 200A shown in Figure 2A , except that the semiconductor packaging device 200B can further include a heat dissipation component 18, wherein:

[0071] The heat dissipation component 18 is provided on the non-active surface 12b of the first chip.

[0072] Heat can be transferred between the non-active surface 12b of the first chip and the heat dissipation component 18. Heat can be transferred from the non-active surface 12b of the first chip to the heat dissipation component 18 to improve the heat dissipation speed of the non-active surface 12b of the first chip. The heat dissipation component 18 can include a heat dissipation circuit.

[0073] In some optional embodiments, as shown in Figure 2B , the heat dissipation component 18 can be provided on the dielectric layer 17 and contact the non-active surface 12b of the first chip.

[0074] Reference will now be made to Figure 2C , Figure 2C is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200C of a semiconductor packaging device according to the present disclosure. Figure 2C The semiconductor packaging device 200C shown is similar to the semiconductor packaging device 200B shown in Figure 2B , except that the semiconductor packaging device 200C can further include a passive electronic element 19, wherein:

[0075] The passive electronic element 19 is provided on the second surface 11b. The passive electronic element 19 can be electrically connected with the first chip 12.

[0076] In some optional embodiments, as shown inFigure 2C As shown, the semiconductor packaging device 200C can further include wire 20 disposed on the adhesive layer 15, and the first chip 12 can be electrically connected to the lead frame 11 through the wire 20.

[0077] Reference will now be made to Figure 2D , Figure 2D is a schematic diagram of a longitudinal cross-sectional structure of one embodiment 200D of a semiconductor packaging device according to the present disclosure. Figure 2D The semiconductor packaging device 200D shown is similar to the semiconductor packaging device 200B shown in Figure 2B , except that in the semiconductor packaging device 200D, the adhesive layer 15 can include a mixed material composed of an organic material and an inorganic material, where the organic material can be the same or different organic material as included in the protective layer 14, and the inorganic material can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The mixed material of the organic material and the inorganic material can increase the strength of the adhesive layer 15 after curing, and can improve the support for the semiconductor packaging device 200D, thereby improving the overall strength of the semiconductor packaging device 200D.

[0078] Reference will now be made to Figure 2E , Figure 2E shows the dimension labels of the main structures in the semiconductor packaging device 200B according to the present disclosure Figure 2B embodiment, where:

[0079] D R is the diameter of the via disposed on the dielectric layer 17, 5um≤D R ≤20um.

[0080] T D is the thickness of the dielectric layer 17 or the line layer 16, 5um≤T D ≤10um, and 1≤D R / T D ≤4.

[0081] D T is the diameter of the via through the dielectric layer 17 and the protective layer 14, 50um≤D T ≤100um.

[0082] T T is the thickness of the protective layer 14, 25um≤T T ≤100um, and 0.5≤D T / T T ≤3.5.

[0083] T B is the thickness of the adhesive layer 15, 50um≤T B ≤200um.

[0084] T L T is a thickness of the lead frame 11, 50um ≤ T ≤ 200um. L ≤200um.

[0085] O S O is an opening width of the lead frame 11, O > 50um. S >50um.

[0086] D E D is a distance between an edge of the first chip 12 and an edge of the opening of the lead frame 11, D > 10um. E >10um.

[0087] Reference is made to Figures 3A to 3E , Figure 3A and 3B are schematic views of horizontal and longitudinal cross-sectional structures of a semiconductor package device at a manufacturing stage according to an embodiment of the present disclosure, Figure 3A and Figure 3B are schematic views of longitudinal cross-sectional structures of a semiconductor package device at a manufacturing stage according to an embodiment of the present disclosure, with the lower part being a longitudinal cross-sectional structure and the upper part being a corresponding horizontal cross-sectional structure. Figures 3C to 3E is a schematic view of a longitudinal cross-sectional structure of a semiconductor package device at a manufacturing stage according to an embodiment of the present disclosure.

[0088] Reference is made to Figure 3A , a lead frame 11 and a first chip 12 are provided.

[0089] Here, the lead frame 11 has opposite first and second surfaces 11a and 11b and an opening.

[0090] Here, the opening of the lead frame 11 can be a pre-provided standard lead frame opening or can be an opening obtained by etching or mechanical drilling according to a practical application requirement.

[0091] Then, an electrical connection 123 is provided on the active surface 12a of the first chip 12.

[0092] Next, the active surface 12a of the first chip 12 is attached to the first surface 11a corresponding to the opening, so that the electrical connection 123 passes through the lead frame 11 via the opening of the lead frame 11.

[0093] Here, the active surface 12a of the first chip 12 can be attached to the first surface 11a corresponding to the opening by providing an adhesive on the edge of the active surface 12a of the first chip 12. The adhesive can include, for example, epoxy.

[0094] Reference is made to Figure 3B , the lead frame 11 is flipped so that the second surface 11b faces upward.

[0095] Then, the second chip 13 is provided, and the second chip non-active surface 13b is attached to the second surface 11b.

[0096] Here, the second chip non-active surface 13b can be attached to the second surface 11b by means of an adhesive provided on the second chip non-active surface 13b.

[0097] Referring to Figure 3C , the first carrier plate 21 is provided.

[0098] Here, the first carrier plate 21 is provided with a circuit layer 16, and the circuit layer 16 is provided with an adhesive layer 15.

[0099] Then, the second carrier plate 22 is provided, and the second carrier plate 22 is provided with a dielectric layer 17, and the dielectric layer 17 is provided with a protective layer 14.

[0100] Next, the protective layer 14 is pressed against the first surface 11a, and the adhesive layer 15 is pressed against the second surface 11b by means of a semi-polymerization semi-hardening process of a thermosetting resin (B-Stage), so that the first chip non-active surface 12b at least partially abuts against the dielectric layer 17.

[0101] Referring to Figure 3D After the protective layer 14 and the adhesive layer 15 are heated to be cured, the first carrier plate 21 and the second carrier plate 22 are removed, respectively.

[0102] Referring to Figure 3E The first chip active surface 12a is electrically connected to the circuit layer 16 through the opening.

[0103] Here, the first chip active surface 12a can be electrically connected to the circuit layer 16 through the opening by means of a via provided between the circuit layer 16 and the electrical connection 123.

[0104] Then, the second chip active surface 13a is electrically connected to the circuit layer 16, so that the first chip 12 is electrically connected to the second chip 13 through the circuit layer 16.

[0105] In the electrical connection process, flip chip bonding (FCB), thermal compression bonding (FCB), or similar techniques can be used.

[0106] Then, a heat dissipation component 18 is formed on the dielectric layer 17 corresponding to the first chip non-active surface 12b, and the heat dissipation component 18 is attached to the first chip non-active surface 12b.

[0107] Here, for example, part of the dielectric layer 17 can be removed by laser lithography to form a cavity communicating with the dielectric layer 17 and the first chip non-active surface 12b, a seed layer is formed on the surface of the cavity by physical vapor deposition (PVD), and a plating layer is formed on the seed layer by electroplating to form the heat dissipation component 18.

[0108] Finally, a controlled collapsed chip connection (C4) method is used to dispose solder bumps on the bottom of the circuit layer 16.

[0109] The method for manufacturing a semiconductor packaging device provided by the present disclosure can achieve similar technical effects as the aforementioned semiconductor packaging device, which will not be repeated here.

[0110] Although the present disclosure has been described and illustrated with reference to specific embodiments, the description and illustrations have been made by way of example only. It is understood that variations in form and detail can be made without departing from the true spirit and scope of the disclosure as defined by the following claims. The drawings are not necessarily to scale. There can be differences in the exact dimensions of the structures depicted in the drawings due to, e.g., manufacturing processes, variations in the manufacturing process, and the like. The technical reproduction of the disclosure can differ from the actual implementation. Other embodiments of the disclosure can not be specifically illustrated. The specification and drawings should be considered illustrative only, and not restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit, and scope of the disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be appreciated that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated otherwise, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A semiconductor package device, comprising: a lead frame having opposite first and second surfaces; a first chip disposed on the first surface with an active surface facing the first surface; a protective layer covering the first surface and at least part of the first chip, a non-active surface of the first chip being exposed at least partially from the protective layer; the device further comprising: a heat dissipation component disposed on the non-active surface of the first chip, wherein the heat dissipation component is disposed on a dielectric layer and contacts the non-active surface of the first chip, heat being transferred between the non-active surface of the first chip and the heat dissipation component; an electrical connector disposed on the active surface of the first chip and passing through an opening of the lead frame, the electrical connector being free of contact with the lead frame; a circuit layer disposed on the second surface, the first chip being electrically connected to the circuit layer; an adhesive layer disposed between the lead frame and the circuit layer.

2. The apparatus of claim 1, wherein, the device further comprising: a second chip disposed on the second surface with a non-active surface facing the second surface, the second chip being electrically connected to the first chip via the circuit layer. 3.A semiconductor package device, comprising: a lead frame having opposite first and second surfaces; a first chip disposed on the first surface with an active surface facing the first surface; a second chip disposed on the second surface with a non-active surface facing the second surface; a circuit layer, the first chip being electrically connected to the second chip via the circuit layer; the device further comprising: a heat dissipation component disposed on the non-active surface of the first chip, wherein the heat dissipation component is disposed on a dielectric layer and contacts the non-active surface of the first chip, heat being transferred between the non-active surface of the first chip and the heat dissipation component; an electrical connector disposed on the active surface of the first chip and passing through an opening of the lead frame, the electrical connector being free of contact with the lead frame; an adhesive layer disposed between the lead frame and the circuit layer.

4. The apparatus of claim 3, wherein, the device further comprising: a protective layer covering the first surface and at least part of the first chip, a non-active surface of the first chip being exposed at least partially from the protective layer.

5. The apparatus of claim 3, wherein, the device further comprising: an adhesive layer covering at least part of the active surface of the first chip, the active surface of the second chip and the second surface. 6.A method of manufacturing a semiconductor package device, comprising: providing a lead frame having opposite first and second surfaces and an opening; disposing an electrical connector on an active surface of a first chip, the electrical connector passing through the opening of the lead frame, the electrical connector being free of contact with the lead frame; attaching the active surface of the first chip to the first surface corresponding to the opening; attaching a non-active surface of a second chip to the second surface; providing a circuit layer having an adhesive layer disposed thereon and a dielectric layer having a protective layer disposed thereon; pressing the protective layer corresponding to the first surface and the adhesive layer corresponding to the second surface, so that the non-active surface of the first chip abuts against the dielectric layer at least partially, and the adhesive layer is interposed between the lead frame and the circuit layer. The first chip active surface is electrically connected to the circuit layer through the opening; The second chip active surface is electrically connected to the circuit layer, so that the first chip is electrically connected to the second chip through the circuit layer; A heat dissipation component is formed on the dielectric layer corresponding to the non-active surface of the first chip, and the heat dissipation component is attached to the non-active surface of the first chip.

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