A sleep and wake-up circuit for energy storage BMS

Abstract

The present invention discloses an energy storage BMS sleep and wake-up circuit, including a battery cluster, a BCU sleep and wake-up circuit, a contactor and a plurality of BMU sleep and wake-up circuits; the positive pole of the battery cluster is connected to the energy storage converter via the contactor, and one cell in the battery cluster corresponds to one BMU sleep and wake-up circuit, wherein each BMU sleep and wake-up circuit is connected to the corresponding cell in the battery cluster, and the BCU sleep and wake-up circuit is connected to the control end of the contactor, the energy storage converter and each BMU sleep and wake-up circuit. The circuit has the functions of sleep, low power consumption and wake-up, and is relatively easy to implement.

Description

Technical Field

[0001] The present invention relates to a sleep and wake-up circuit, and in particular to a sleep and wake-up circuit for an energy storage BMS. Background Art

[0002] Current energy storage systems consist of multiple battery clusters. A single battery cluster consists of multiple cells connected in series. Each battery cluster is equipped with a battery management system (BMS). This system includes a BCU and BMU, which monitor the voltage, current, and temperature of individual cells and the entire battery cluster. It also calculates key parameters such as SOC and SOH. Based on these results, the battery cluster performs charge and discharge control, protection, and alarm functions.

[0003] In current energy storage systems, after the system is powered on, the battery management system (BCU) and BMU are always in a charged and full-load operating state. However, in current energy storage power stations, the energy storage system often remains idle for a long time, neither charging nor discharging. During this period, the BCU and BMU operating at full load not only increase the power consumption of the entire energy storage system, but also, when the energy storage system is idle for a long time without timely charging, the battery voltage will continue to decrease due to the consumption of the BMU detection circuit and the self-discharge of the battery cells, eventually leading to battery over-discharge.

[0004] After the energy storage system is powered on, the battery management system BCU and BMU are always in a powered working state. Unless the power is manually cut off, the battery management system BCU and BMU will not be powered off, and the battery management system BCU and BMU will not enter a sleep or low-power state. The entire system consumes a lot of power, and the BMU will continue to consume battery power. Currently, there are no related sleep, low-power, and wake-up functions in the energy storage battery system.

[0005] The existing technology has the following disadvantages:

[0006] The battery management system BCU and BMU do not have a sleep function, related wake-up circuits, or methods for entering low power consumption. This results in high power consumption, especially when the system is idle, which generates unnecessary consumption.

[0007] If the battery management system is not in low-power or hibernation mode and the energy storage system is idle for a long time, the battery cells will self-discharge, even though there is no load discharge. At the same time, the BMU detection circuit is always active and connected to the battery cells. The BMU's operation and detection power consumption exacerbates the discharge of the battery cells. This prolonged state can easily lead to over-discharge of the battery, compromising safety and potentially causing asset loss.

[0008] Currently, if the energy storage battery management system enters sleep mode, it requires certain external activation circuits, which requires adding some redundant hardware or logical interactions between systems, increasing the difficulty of the system. Summary of the Invention

[0009] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide an energy storage BMS sleep and wake-up circuit, which has the functions of sleep, low power consumption and wake-up, and is relatively easy to implement.

[0010] To achieve the above objectives, the energy storage BMS sleep and wake-up circuit described in the present invention includes a battery cluster, a BCU sleep and wake-up circuit, a contactor and several BMU sleep and wake-up circuits; the positive pole of the battery cluster is connected to the energy storage converter via the contactor, and several cells in the battery cluster correspond to one BMU sleep and wake-up circuit, wherein each BMU sleep and wake-up circuit is connected to the corresponding cell in the battery cluster, and the BCU sleep and wake-up circuit is connected to the control end of the contactor, the energy storage converter and each BMU sleep and wake-up circuit.

[0011] The BMU sleep wake-up circuit includes a first CPU chip, a first optocoupler, a first resistor and a first CAN communication transceiver chip;

[0012] The wake_up pin of the first CPU chip is connected to pin 3 of the first optocoupler and pin 8 of the first CAN communication transceiver chip; pin 1 of the first optocoupler is connected to the CAN1_H pin of the first CAN communication transceiver chip and the CAN1_H pin of the second CAN communication transceiver chip in the BCU sleep wake-up circuit via the first resistor, and pin 2 of the first optocoupler is connected to the CAN1_L pin of the first CAN communication transceiver chip and the CAN1_L pin of the second CAN communication transceiver chip in the BCU sleep wake-up circuit; the TXD_CAN1 pin of the first CPU chip is connected to pin 1 of the first CAN communication transceiver chip, and the RXD_CAN1 pin of the first CPU chip is connected to pin 4 of the first CAN communication transceiver chip.

[0013] The BCU sleep wake-up circuit includes a second CAN communication transceiver chip, a third CAN communication transceiver chip, a second CPU chip, a second optocoupler, a third optocoupler, a second resistor, a third resistor and a 485 communication transceiver chip;

[0014] Pin 8 of the second CAN communication transceiver chip is connected to the GPIO4 pin of the second CPU chip, pin 1 of the second CAN communication transceiver chip is connected to the TXD_CAN2 pin of the second CPU chip, and pin 4 of the second CAN communication transceiver chip is connected to the RXD_CAN2 pin of the second CPU chip; the RXD_UART1 pin of the second CPU chip is connected to pin 1 of the 485 communication transceiver chip, the TXD_UART1 pin of the second CPU chip is connected to pin 4 of the 485 communication transceiver chip, pin 7 of the 485 communication transceiver chip is connected to pin 2 of the second optocoupler via a second resistor, pin 7 of the 485 communication transceiver chip is connected to the energy storage converter, and pin 6 of the 485 communication transceiver chip is connected to the 485 communication transceiver chip. Pin No. 1 is connected to pin No. 1 of the second optocoupler and the energy storage converter, the wake_up pin of the second CPU chip is connected to pin No. 3 of the second optocoupler and pin No. 3 of the third optocoupler, the GPIO3 pin of the second CPU chip is connected to pin No. 8 of the third CAN communication transceiver chip, the TXD_CAN1 pin of the second CPU chip is connected to pin No. 1 of the third CAN communication transceiver chip, the RXD_CAN1 pin of the second CPU chip is connected to pin No. 4 of the third CAN communication transceiver chip, pin No. 1 of the third optocoupler is connected to the CAN1_H pin of the third CAN communication transceiver chip and the energy storage converter via the third resistor, and pin No. 2 of the third optocoupler is connected to the CAN_L pin of the third CAN communication transceiver chip and the energy storage converter.

[0015] The first CAN communication transceiver chip, the second CAN communication transceiver chip and the third CAN communication transceiver chip are all TJA1051.

[0016] The model of the 485 communication transceiver chip is MAX485.

[0017] The first CPU chip and the second CPU chip are both LPC2294.

[0018] After the battery cluster is powered on, the BCU sleep / wake-up circuit detects the system status and obtains relevant information from the BMU sleep / wake-up circuit through CAN communication. When the battery cell status, BCU sleep / wake-up circuit, and BMU sleep / wake-up circuit are normal, the BCU sleep / wake-up circuit controls the contactor to close, and the battery cluster becomes chargeable and dischargeable.

[0019] The energy storage converter controls the charging or discharging of the battery cluster according to the superior instructions. Before charging or discharging, the energy storage converter obtains the current chargeable power or dischargeable power of the battery cluster through communication with the BCU sleep wake-up circuit, and adjusts the charging power and discharging power of the battery cluster in real time.

[0020] When the BMU sleep wake-up circuit detects that the battery cluster has been idle for more than 1 hour, the energy storage converter has stopped sending information to the BCU sleep wake-up circuit. The second CPU chip in the BCU sleep wake-up circuit closes the peripheral port and enters the sleep state. At the same time, the BCU sleep wake-up circuit no longer sends instructions to the BMU sleep wake-up circuit. After the BMU sleep wake-up circuit fails to receive instructions from the BCU sleep wake-up circuit for more than 1 hour, the first CPU chip also enters the sleep state.

[0021] When the system needs to charge or discharge, the energy storage converter sends a communication command to the BCU sleep wake-up circuit to obtain the current chargeable power and dischargeable power of the battery cluster. Under this condition, the BCU sleep wake-up circuit and the BMU sleep wake-up circuit can be awakened by communication.

[0022] When the energy storage converter sends an instruction to the BCU sleep wake-up circuit via the 485 communication mode, the 485 communication mode enters the working state from the idle state, turning on the second optocoupler in the BCU sleep wake-up circuit and applying a high level to the wake_up pin of the second CPU chip. At this time, the second CPU chip wakes up and detects the system status. At the same time, it sends an instruction to the BMU sleep wake-up circuit via the CAN communication mode. The BMU sleep wake-up circuit turns on the first optocoupler in the BMU sleep wake-up circuit based on the CAN bus differential level, and applies a high level to the wake_up pin of the first CPU chip in the BMU sleep wake-up circuit. At this time, the BMU sleep wake-up circuit wakes up, and the BCU sleep wake-up circuit can obtain relevant information about the BMU sleep wake-up circuit. When the BCU sleep wake-up circuit status and the BMU sleep wake-up circuit status are normal, the contactor is closed, and charging and discharging are performed in response to the instructions of the energy storage converter.

[0023] When the energy storage converter sends an instruction to the BCU sleep wake-up circuit, the CAN1 bus enters the working state from the idle state. The voltage difference between the CAN_H pin and the CAN_L pin of the second CPU chip is used to turn on the third optocoupler and apply a high level to the wake_up pin of the second CPU chip. At this time, the second CPU chip wakes up and detects the system status, and sends an instruction to the BMU sleep wake-up circuit. The BMU sleep wake-up circuit internally turns on the first optocoupler based on the CAN bus differential level and applies a high level to the wake_up pin of the first CPU chip. At this time, the BMU sleep wake-up circuit wakes up and obtains relevant information of the BMU sleep wake-up circuit. After the BCU sleep wake-up circuit detects that the system status and the status of the BMU sleep wake-up circuit are normal, it closes the contactor and responds to the instructions of the energy storage converter to charge and discharge.

[0024] The present invention has the following beneficial effects:

[0025] The energy storage BMS sleep and wake-up circuit described in the present invention wakes up or puts the BMU sleep and wake-up circuit and the BCU sleep and wake-up circuit into sleep mode according to the communication differential level during specific operation, so as to avoid unnecessary consumption when the system is idle. At the same time, the sleep and wake-up of the present invention are judged by the differential level, and the system complexity is relatively low. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural schematic diagram of the present invention;

[0027] Figure 2 This is a schematic diagram of the BMU sleep and wake-up circuit;

[0028] Figure 3 This is a schematic diagram of the BCU sleep and wake-up circuit.

[0029] Among them, 1 is the BMU sleep wake-up circuit, 2 is the BCU sleep wake-up circuit, and 3 is the battery cluster. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments, and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts disclosed in the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0031] The accompanying drawings illustrate schematic diagrams of the structures of the disclosed embodiments of the present invention. These figures are not drawn to scale; for the purpose of clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] refer to Figure 1 、 Figure 2 and Figure 3The energy storage BMS sleep and wake-up circuit of the present invention includes a battery cluster 3, a BCU sleep and wake-up circuit 2, and several BMU sleep and wake-up circuits 1; the positive electrode of the battery cluster 3 is connected to the energy storage converter PCS via a contactor, and several cells in the battery cluster 3 correspond to one BMU sleep and wake-up circuit 1, wherein each BMU sleep and wake-up circuit 1 is connected to the corresponding cell in the battery cluster 3, and the BCU sleep and wake-up circuit 2 is connected to the control end of the contactor, the energy storage converter PCS, and each BMU sleep and wake-up circuit 1.

[0033] The BMU sleep wake-up circuit 1 includes a first CPU chip U1, a first optocoupler U3, a first resistor R1 and a first CAN communication transceiver chip U2;

[0034] The wake_up pin of the first CPU chip U1 is connected to pin 3 of the first optocoupler U3 and pin 8 of the first CAN communication transceiver chip U2; pin 1 of the first optocoupler U3 is connected to the CAN1_H pin of the first CAN communication transceiver chip U2 and the CAN1_H pin of the second CAN communication transceiver chip U4 in the BCU sleep wake-up circuit 2 via the first resistor R1, and pin 2 of the first optocoupler U3 is connected to the CAN1_L pin of the first CAN communication transceiver chip U2 and the CAN1_L pin of the second CAN communication transceiver chip U4 in the BCU sleep wake-up circuit 2; the TXD_CAN1 pin of the first CPU chip U1 is connected to pin 1 of the first CAN communication transceiver chip U2, and the RXD_CAN1 pin of the first CPU chip U1 is connected to pin 4 of the first CAN communication transceiver chip U2;

[0035] The BCU sleep wake-up circuit 2 includes a second CAN communication transceiver chip U4, a third CAN communication transceiver chip U5, a second CPU chip U6, a second optocoupler U7, a third optocoupler U8, a second resistor R2, a third resistor R3 and a 485 communication transceiver chip U9;

[0036] Pin 8 of the second CAN communication transceiver chip U4 is connected to the GPIO4 pin of the second CPU chip U6, pin 1 of the second CAN communication transceiver chip U4 is connected to the TXD_CAN2 pin of the second CPU chip U6, and pin 4 of the second CAN communication transceiver chip U4 is connected to the RXD_CAN2 pin of the second CPU chip U6; the RXD_UART1 pin of the second CPU chip U6 is connected to pin 1 of the 485 communication transceiver chip U9, the TXD_UART1 pin of the second CPU chip U6 is connected to pin 4 of the 485 communication transceiver chip U9, pin 7 of the 485 communication transceiver chip U9 is connected to pin 2 of the second optocoupler U7 via the second resistor R2, pin 7 of the 485 communication transceiver chip U9 is connected to the energy storage converter PCS, and pin 6 of the 485 communication transceiver chip U9 is connected to the 485 communication transceiver chip U9. It is connected to pin 1 of the second optocoupler U7 and the energy storage converter PCS, the wake_up pin of the second CPU chip U6 is connected to pin 3 of the second optocoupler U7 and pin 3 of the third optocoupler U8, the GPIO3 pin of the second CPU chip U6 is connected to pin 8 of the third CAN communication transceiver chip U5, the TXD_CAN1 pin of the second CPU chip U6 is connected to pin 1 of the third CAN communication transceiver chip U5, the RXD_CAN1 pin of the second CPU chip U6 is connected to pin 4 of the third CAN communication transceiver chip U5, pin 1 of the third optocoupler U8 is connected to the CAN1_H pin of the third CAN communication transceiver chip U5 and the energy storage converter PCS via the third resistor R3, and pin 2 of the third optocoupler U8 is connected to the CAN_L pin of the third CAN communication transceiver chip U5 and the energy storage converter PCS.

[0037] The first CAN communication transceiver chip U2, the second CAN communication transceiver chip U4 and the third CAN communication transceiver chip U5 are all TJA1051; the 485 communication transceiver chip U9 is MAX485; the first CPU chip U1 and the second CPU chip U6 are both LPC2294.

[0038] The working process of the present invention is:

[0039] 1) Charging and discharging of battery cluster 3

[0040] After the battery cluster 3 is powered on, the BCU sleep / wake-up circuit 2 detects the system status and obtains relevant information from the BMU sleep / wake-up circuit 1 through CAN communication. When the battery cell status, the BCU sleep / wake-up circuit 2, and the BMU sleep / wake-up circuit 1 are normal, the BCU sleep / wake-up circuit 2 controls the contactor to close, and the battery cluster 3 becomes chargeable and dischargeable.

[0041] The energy storage converter PCS controls the charging or discharging of the battery cluster 3 according to the superior instructions. Before charging or discharging, the energy storage converter PCS obtains the current chargeable power or dischargeable power of the battery cluster 3 through communication with the BCU sleep wake-up circuit 2, and adjusts the charging power and discharging power of the battery cluster 3 in real time. That is, before the energy storage converter PCS controls charging or discharging, it needs to first obtain the relevant information of the BCU sleep wake-up circuit 2. During the charging and discharging process, the BCU sleep wake-up circuit 2 sends the relevant information according to the communication instructions of the energy storage converter PCS.

[0042] 2) BCU sleep wake-up circuit 2 and BMU sleep wake-up circuit 1 sleep

[0043] When the BMU sleep wake-up circuit 1 detects that the battery cluster 3 has been idle for more than 1 hour, the energy storage converter PCS stops sending information to the BCU sleep wake-up circuit 2. The second CPU chip U6 in the BCU sleep wake-up circuit 2 closes the peripheral port and enters the sleep state. At the same time, the BCU sleep wake-up circuit 2 no longer sends instructions to the BMU sleep wake-up circuit 1. After the BMU sleep wake-up circuit 1 fails to receive instructions from the BCU sleep wake-up circuit 2 for more than 1 hour, the first CPU chip U1 also enters the sleep state.

[0044] At this time, because the battery cluster 3 has been idle for a long time, the BCU sleep wake-up circuit 2 and the BMU sleep wake-up circuit 1 both enter a sleep state. At the same time, because the peripherals of the second CPU chip U6 are all turned off and the contactor is disconnected, the battery cluster 3 will no longer charge or discharge. In this case, the BMU sleep wake-up circuit 1 and the BCU sleep wake-up circuit 2 operate with extremely low power consumption, while also minimizing the consumption of the battery cluster 3.

[0045] 3) Communication wakeup of BCU sleep wakeup circuit 2 and BMU sleep wakeup circuit 1

[0046] When the system needs to charge or discharge, the energy storage converter PCS sends a communication command to the BCU sleep wake-up circuit 2 to obtain the current chargeable power and dischargeable power of the battery cluster 3. Under this condition, the BCU sleep wake-up circuit 2 and the BMU sleep wake-up circuit 1 can be awakened by communication.

[0047] When the energy storage converter PCS sends an instruction to the BCU sleep wake-up circuit 2 via the 485 communication mode, the 485 communication mode enters the working state from the idle state, turning on the second optocoupler U7 in the BCU sleep wake-up circuit 2 and applying a high level to the wake_up pin of the second CPU chip U6. At this time, the second CPU chip U6 wakes up and detects the system status. At the same time, it sends an instruction to the BMU sleep wake-up circuit 1 via the CAN communication mode. The BMU sleep wake-up circuit 1 relies on the CAN bus differential level to turn on the first optocoupler U3 inside the BMU sleep wake-up circuit 1 and applies a high level to the wake_up pin of the first CPU chip U1 in the BMU sleep wake-up circuit 1. At this time, the BMU sleep wake-up circuit 1 wakes up, and the BCU sleep wake-up circuit 2 can obtain relevant information of the BMU sleep wake-up circuit 1. When the BCU sleep wake-up circuit 2 detects that the system status and the status of the BMU sleep wake-up circuit 1 are normal, it closes the contactor and responds to the instruction of the energy storage converter PCS to charge and discharge.

[0048] When the energy storage converter PCS sends an instruction to the BCU sleep wake-up circuit 2, the CAN1 bus enters the working state from the idle state. The voltage difference between the CAN_H pin and the CAN_L pin of the second CPU chip U6 turns on the third optocoupler U8 and applies a high level to the wake_up pin of the second CPU chip U6. At this time, the second CPU chip U6 wakes up and detects the system status, and sends an instruction to the BMU sleep wake-up circuit 1. The BMU sleep wake-up circuit 1 internally turns on the first optocoupler U3 based on the CAN bus differential level and applies a high level to the wake_up pin of the first CPU chip U1. At this time, the BMU sleep wake-up circuit 1 wakes up, and the BCU sleep wake-up circuit 2 can obtain relevant information of the BMU sleep wake-up circuit 1. After the BCU sleep wake-up circuit 2 detects that the system status and the status of the BMU sleep wake-up circuit 1 are normal, it closes the contactor and responds to the instructions of the energy storage converter PCS to charge and discharge.

Claims

1. A BMS sleep and wake-up circuit, characterized in that: The invention comprises a battery cluster (3), a BCU sleep wake-up circuit (2), a contactor and a plurality of BMU sleep wake-up circuits (1); the positive electrode of the battery cluster (3) is connected to an energy storage converter (PCS) via the contactor, and a plurality of cells in the battery cluster (3) correspond to one BMU sleep wake-up circuit (1), wherein each BMU sleep wake-up circuit (1) is connected to a corresponding cell in the battery cluster (3), and the BCU sleep wake-up circuit (2) is connected to a control end of the contactor, the energy storage converter (PCS) and each BMU sleep wake-up circuit (1); The BMU sleep and wake-up circuit (1) comprises a first CPU chip (U1), a first optical coupler (U3), a first resistor (R1) and a first CAN communication transceiver chip (U2); The wake_up pin of the first CPU chip (U1) is connected to the No. 3 pin of the first optical coupler (U3) and the No. 8 pin of the first CAN communication transceiver chip (U2); the No. 1 pin of the first optical coupler (U3) is connected to the CAN1_H pin of the first CAN communication transceiver chip (U2) and the CAN1_H pin of the second CAN communication transceiver chip (U4) in the BCU sleep wake-up circuit (2) via the first resistor (R1); the No. 2 pin of the first optical coupler (U3) is connected to the CAN1_L pin of the first CAN communication transceiver chip (U2) and the CAN1_L pin of the second CAN communication transceiver chip (U4) in the BCU sleep wake-up circuit (2); the TXD_CAN1 pin of the first CPU chip (U1) is connected to the No. 1 pin of the first CAN communication transceiver chip (U2); the RXD_CAN1 pin of the first CPU chip (U1) is connected to the No. 4 pin of the first CAN communication transceiver chip (U2); The BCU sleep wake-up circuit (2) comprises a second CAN communication transceiver chip (U4), a third CAN communication transceiver chip (U5), a second CPU chip (U6), a second optical coupler (U7), a third optical coupler (U8), a second resistor (R2), a third resistor (R3) and a 485 communication transceiver chip (U9); Pin 8 of the second CAN communication transceiver chip (U4) is connected to the GPIO4 pin of the second CPU chip (U6), pin 1 of the second CAN communication transceiver chip (U4) is connected to the TXD_CAN2 pin of the second CPU chip (U6), and pin 4 of the second CAN communication transceiver chip (U4) is connected to the RXD_CAN2 pin of the second CPU chip (U6); the RXD_UART1 pin of the second CPU chip (U6) is connected to the 485 The first pin of the communication transceiver chip (U9) is connected to the pin 1 of the communication transceiver chip (U9), the TXD_UART1 pin of the second CPU chip (U6) is connected to the pin 4 of the 485 communication transceiver chip (U9), the first pin 7 of the 485 communication transceiver chip (U9) is connected to the pin 2 of the second optical coupler (U7) via the second resistor (R2), the first pin 7 of the 485 communication transceiver chip (U9) is connected to the energy storage converter (PCS), the first pin 6 of the 485 communication transceiver chip (U9) is connected to the pin 7 of the second optical coupler (U7), and the second pin 7 of the 485 communication transceiver chip (U9) is connected to the energy storage converter (PCS). The first pin of the second optocoupler (U7) is connected to the energy storage converter (PCS), the wake_up pin of the second CPU chip (U6) is connected to the third pin of the second optocoupler (U7) and the third pin of the third optocoupler (U8), the GPIO3 pin of the second CPU chip (U6) is connected to the eighth pin of the third CAN communication transceiver chip (U5), the TXD_CAN1 pin of the second CPU chip (U6) is connected to the first pin of the third CAN communication transceiver chip (U5), and the TXD_CAN2 pin of the second CPU chip (U6) is connected to the first pin of the third CAN communication transceiver chip (U5). The pins are connected, the RXD_CAN1 pin of the second CPU chip (U6) is connected to the No. 4 pin of the third CAN communication transceiver chip (U5), the No. 1 pin of the third optical coupler (U8) is connected to the CAN1_H pin of the third CAN communication transceiver chip (U5) and the energy storage converter (PCS) via the third resistor (R3), and the No. 2 pin of the third optical coupler (U8) is connected to the CAN_L pin of the third CAN communication transceiver chip (U5) and the energy storage converter (PCS); After the battery cluster (3) is powered on, the BCU sleep wake-up circuit (2) detects the system status and obtains relevant information of the BMU sleep wake-up circuit (1) through CAN communication. When the battery cell status, the BCU sleep wake-up circuit (2) and the BMU sleep wake-up circuit (1) are normal, the BCU sleep wake-up circuit (2) controls the contactor to close, and the battery cluster (3) is in a chargeable and dischargeable state. The energy storage converter (PCS) controls the charging or discharging of the battery cluster (3) according to the superior instruction. Before charging or discharging, the energy storage converter (PCS) obtains the current chargeable power or dischargeable power of the battery cluster (3) through communication with the BCU sleep wake-up circuit (2), and adjusts the charging power and discharging power of the battery cluster (3) in real time based on the information. When the BMU sleep wake-up circuit (1) detects that the battery cluster (3) has been idle for more than 1 hour, the energy storage converter (PCS) has stopped sending information to the BCU sleep wake-up circuit (2), the second CPU chip (U6) in the BCU sleep wake-up circuit (2) closes the peripheral port and enters a sleep state, and at the same time, the BCU sleep wake-up circuit (2) no longer sends instructions to the BMU sleep wake-up circuit (1). After the BMU sleep wake-up circuit (1) fails to receive instructions from the BCU sleep wake-up circuit (2) for more than 1 hour, the first CPU chip (U1) also enters a sleep state.

2. The energy storage BMS sleep and wake-up circuit according to claim 1, characterized in that: The first CAN communication transceiver chip (U2), the second CAN communication transceiver chip (U4) and the third CAN communication transceiver chip (U5) are all of the TJA1051 type.

3. The energy storage BMS sleep and wake-up circuit according to claim 1, characterized in that: The model of the 485 communication transceiver chip (U9) is MAX485.

4. The energy storage BMS sleep and wake-up circuit according to claim 1, characterized in that: The models of the first CPU chip (U1) and the second CPU chip (U6) are both LPC2294.

5. The energy storage BMS sleep and wake-up circuit according to claim 1, characterized in that: When the system needs to be charged or discharged, the energy storage converter (PCS) sends a communication instruction to the BCU sleep wake-up circuit (2) to obtain the current chargeable power and dischargeable power of the battery cluster (3). Under this condition, the BCU sleep wake-up circuit (2) and the BMU sleep wake-up circuit (1) can be awakened by communication; When the energy storage converter (PCS) sends a command to the BCU sleep wake-up circuit (2) via the 485 communication mode, the 485 communication mode enters the working state from the idle state, so that the second optical coupler (U7) in the BCU sleep wake-up circuit (2) is turned on and a high level is applied to the wake_up pin of the second CPU chip (U6). At this time, the second CPU chip (U6) wakes up and detects the system status, and at the same time sends a command to the BMU sleep wake-up circuit (1) via the CAN communication mode. The BMU sleep wake-up circuit (1) relies on the CAN bus differential current to The first optocoupler (U3) inside the BMU sleep wake-up circuit (1) is turned on, and a high level is applied to the wake_up pin of the first CPU chip (U1) in the BMU sleep wake-up circuit (1). At this time, the BMU sleep wake-up circuit (1) wakes up, and the BCU sleep wake-up circuit (2) can obtain relevant information of the BMU sleep wake-up circuit (1); when the BCU sleep wake-up circuit (2) detects that the system status and the BMU sleep wake-up circuit (1) are normal, the contactor is closed, and at the same time, the charge and discharge are performed in response to the instruction of the energy storage converter (PCS); When the energy storage converter (PCS) sends an instruction to the BCU sleep wake-up circuit (2), the CAN1 bus enters the working state from the idle state, and the voltage difference between the CAN_H pin and the CAN_L pin of the second CPU chip (U6) is used to turn on the third optical coupler (U8), and a high level is applied to the wake_up pin of the second CPU chip (U6). At this time, the second CPU chip (U6) wakes up and detects the system state, and at the same time sends an instruction to the BMU sleep wake-up circuit (1). The BMU sleep wake-up circuit (1) internally turns on the first optical coupler (U3) based on the CAN bus differential level, and applies a high level to the wake_up pin of the first CPU chip (U1). At this time, the BMU sleep wake-up circuit (1) wakes up, and the BCU sleep wake-up circuit (2) obtains relevant information of the BMU sleep wake-up circuit (1). After the BCU sleep wake-up circuit (2) detects that the system state and the state of the BMU sleep wake-up circuit (1) are normal, it closes the contactor and responds to the instruction of the energy storage converter (PCS) to charge and discharge.

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