Method and apparatus for starting a converter to a pre-bias voltage

Abstract

Methods, devices, systems, and articles of manufacture are described for starting a converter (104) to a pre-biased voltage. The methods, devices, systems, and articles of manufacture provide an apparatus comprising: an error amplifier (108) comprising a feedback network (220, 214, 216) and a differential difference amplifier (DDA) (312), the DDA coupled to a power converter (104), a voltage generator (106), and a feedback network coupled to a third input (318) of the DDA, a fourth input (320) of the DDA, and an output (322) of the DDA; a multiplexer (310) coupled to the voltage generator (106), the DDA, and the output (322) of the DDA; A second input terminal (316) and a first input terminal (314) of the DDA; a first switch (132) coupled in parallel with the feedback network (220, 214, 216); a second switch (134) coupled to the delay unit (110) and the oscillator (112); and a flip-flop (302) including an output terminal (308), the flip-flop (302) coupled to the voltage generator (106), the power converter (104), and the output terminal (308) of the flip-flop (302) coupled to the multiplexer (310), the first switch (132), and the second switch (134).

Description

Technical Field

[0001] The present description relates generally to delay-based pulse width modulation power converters and, more particularly, to methods and apparatus for starting the converter to a pre-bias voltage. Background Art

[0002] Power converters (e.g., buck converters, buck-boost converters, etc.) and / or various power electronic devices operate in response to pulse width modulated signals generated by a pulse width modulated (PWM) signal generator. In some power converter and / or various power electronic device applications, switches (e.g., transistors) are controlled by ramp-based PWM techniques (e.g., analog control). Recently, manufacturers of power converters and / or various power electronic devices have developed delay-based PWM techniques as an alternative to ramp-based PWM techniques. Delay-based PWM techniques involve utilizing a delayed PWM generator to generate a signal whose pulse width is a function of a delay. Summary of the Invention BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of an example power converter system including an example controller.

[0004] Figure 2 is a schematic diagram of an example power converter system showing Figure 1 Further details of the controller.

[0005] Figure 3 is a schematic diagram of an example power converter system showing Figure 1 Alternative details for the controller.

[0006] Figure 4 It shows Figure 1 An example voltage feedforward controller, Figure 2 An example of a voltage feedforward controller and / or Figure 3 Schematic diagram of further details of an example voltage feedforward controller.

[0007] Figure 5 It shows Figure 1 An example reference voltage generator, Figure 2 An example reference voltage generator and / or Figure 3 Schematic diagram of further details of an example reference voltage generator.

[0008] Figure 6 It is an icon Figure 1 An example power converter system, Figure 2 Example power converter systems and / or Figure 3 FIG2 is a timing diagram of the operation of an example power converter system.

[0009] Figure 7 It is an icon Figure 1 An example power converter system, Figure 2 Example power converter systems and / or Figure 3 Additional operation timing diagrams of the example power converter system are provided.

[0010] Figure 8 It is an icon Figure 1 An example reference voltage generator, Figure 2 An example reference voltage generator and / or Figure 3 FIG2 is a timing diagram of an example reference voltage generator operation.

[0011] Figure 9 It means that it can be executed to achieve Figure 1 、 2 and a flowchart of example machine-readable instructions for an example controller of 3.

[0012] The accompanying drawings are not drawn to scale. Generally, the same reference numbers will be used throughout the drawings and accompanying written description to refer to the same or like parts.

[0013] When identifying multiple elements or components that can be referenced individually, the descriptors first, second, third, etc. are used herein. Unless otherwise specified, such descriptors do not imply any priority or temporal ordering, but are merely labels that refer to multiple elements or components separately to facilitate understanding of the described examples. In some examples, the descriptor first may be used to refer to an element in the detailed description, while a different descriptor such as second or third may be used to refer to the same element in the claims. In such cases, such descriptors are used solely to facilitate ease of reference to multiple elements or components. DETAILED DESCRIPTION

[0014] Some direct current to direct current (DC-DC) converters and / or other power electronic devices (e.g., alternating current (AC) inverters) utilize multiple switches (e.g., transistors) controlled by a controller that generates a PWM signal. In such applications, the controller includes a PWM signal generator to generate and / or otherwise provide a PWM signal to the converter in response to monitoring the output voltage of a coupled DC-DC converter. In some applications, the PWM signal generator is a delayed pulse width modulator (DPWM) (e.g., a pulse width modulator that generates a pulse width modulated signal based on a delay time and / or period, a delay-based pulse width modulator) rather than an analog-based PWM signal generator. DPWM has an advantage over analog-based PWM signal generators because DPWM is able to generate narrower pulses (e.g., pulses less than 30 nanoseconds) in the PWM signal without jitter, while analog-based PWM signal generators may not be able to generate such narrow pulses.

[0015] Rather than generating a PWM signal by comparing a control signal voltage to a ramp-based signal (e.g., a sawtooth signal), as in analog-based PWM generators, a DPWM generates and / or otherwise creates a PWM signal by introducing a delay corresponding to a desired pulse width. The DPWM includes delay cells that are controllable by at least one control signal. The control signal is generated by a controller and indicates the length of the delay to be introduced by each of a plurality of delay cells (e.g., 1.0 nanoseconds, 1.2 nanoseconds, etc.). In some examples, the DPWM is included in the controller.

[0016] In some cases, a voltage may be applied to the output of a power converter before the controller enables the power converter. For example, a processor integrated circuit (IC) may require a first voltage level (e.g., 1.2 volts) for core power, but a second voltage level (e.g., 3.3 volts) for input and output power. In such an example, during startup, the first voltage level may be reached before the second voltage level is enabled. Internal circuitry and / or leakage in the processor IC may cause a subcircuit of the processor IC coupled to a node that is to be at the second voltage level to be at or below the first voltage level.

[0017] Situations like these pose a problem for power converters because the controller can control the power converter by ramping the converter's duty cycle from a value corresponding to zero volts to meet the duty cycle of the desired output voltage. Many power converters employ synchronous rectification, which allows current to flow from the power converter's output to the power converter's input during certain states of the power converter. While synchronous rectification is beneficial during steady-state operation of the power converter, it can cause problems during converter startup when a pre-biased voltage level is present at the output. The problem arises because the duty cycle at startup does not correspond to the voltage at the power converter's output. This voltage level difference causes current from the power converter's output to flow from the power converter's output to the input (e.g., the current is negative relative to the converter, as the power converter draws current from the pre-biased voltage level at the load). This is disadvantageous because the controller used for the power converter may not be designed to support control in discontinuous conduction mode (DCM) operation. Conventional PWM methods cannot accommodate such negative currents in DCM operation because it is impractical to set the PWM signal to the desired value before connecting it to the power converter.

[0018] The examples in this article allow a power converter to start up when connected to a pre-biased output. Examples herein provide a device including: an error amplifier including a feedback network and a differential difference amplifier (DDA), the DDA including a first input, a second input, a third input, a fourth input, and an output, the second input of the DDA being configured to be coupled to an output of a power converter, the third input of the DDA being configured to be coupled to a first output of a voltage generator, and the feedback network being coupled to the third input of the DDA, the fourth input of the DDA, and the output of the DDA; a multiplexer including a control terminal, the multiplexer being configured to be coupled to a second output of the voltage generator, the multiplexer being coupled to the second input of the DDA and the first input of the DDA; a first switch including a control terminal, the first switch being coupled in parallel with the feedback network; a second switch including a control terminal, the second switch being configured to be coupled to a delay unit and an oscillator; and a flip-flop including an output, the flip-flop being configured to be coupled to the second output of the voltage generator and the output of the power converter, with the output of the flip-flop being coupled to the control terminal of the multiplexer, the control terminal of the first switch, and the control terminal of the second switch.

[0019] Rather than clamping the output of the error amplifier to a specified value corresponding to a voltage level higher than the output voltage level, the methods, apparatus, and articles of manufacture herein allow the error amplifier to control the duration of a delay cell in a DPWM based on a reference voltage until the pulse width of the DPWM is equal to or higher than a value associated with a voltage level at the output of the power converter that is greater than or equal to a pre-bias voltage. Furthermore, the examples herein prevent the error amplifier from sag back to the voltage level across the error amplifier, thereby preventing transients at the output of the power converter.

[0020] In addition, examples herein prevent negative current (e.g., reverse current) by disabling a power converter until a soft-start voltage corresponding to the power converter is equal to or greater than a voltage level corresponding to a pre-bias voltage. Consistent with the description, coupling is defined as a direct or indirect connection (e.g., through one or more intermediate structures and / or layers, such as resistors, capacitors, inductors, transistors, voltage clamps, switches, buffer amplifiers, etc.). Consistent with the description, soft start and / or its derivatives (e.g., soft start, soft-start, soft-startup, soft starting, etc.) refer to a structure or function that controls the rate of current flow and, therefore, the rate of change of the output voltage when a switch begins to conduct and prevents the current level from exceeding a predetermined and / or sensed value that does not damage components of the switch or components coupled to the switch. Consistent with the description, equality is defined as a relationship between two or more quantities that is within a percentage tolerance range (e.g., a 5% tolerance) of each other.

[0021] Figure 1 1 is a block diagram of an example power converter system 100 including an example controller 102. The example power converter system 100 further includes an example power stage 104, an example load 136, an example power source 138, and an example voltage input 140. The example controller 102 controls the power stage 104 to provide a desired voltage level to the load 136, wherein the desired voltage level is based on a preset or predetermined voltage level V obtained by the controller 102 at the voltage input 140. SET The example controller 102 includes an example reference voltage generator 106, an example error amplifier 108, an example delay unit 110, an example oscillator 112, an example analog-to-digital converter (ADC) 114, an example feed-forward voltage controller 116, an example voltage divider 117, an example comparator 118 (including an example first input 120, an example second input 122, and an example output 124), an example latch 125, an example first switch 126, an example first inverter 127, an example second switch 128, an example third switch 130, an example second inverter 131, an example fourth switch 132, an example fifth switch 134, and an example third inverter 135.

[0022] exist Figure 1 In FIG, an example controller 102 is coupled to an example power stage 104. Figure 1 In FIG, the example power stage 104 is coupled to the example controller 102, the example load 136, and the example power source 138. Figure 1 In FIG, the example reference voltage generator 106 is coupled to the example voltage input 140, to the example error amplifier 108 via the example second switch 128 and the example third switch 130, to the example feed-forward voltage controller 116 and to the second input 122 of the example comparator 118. Figure 1 , the example error amplifier 108 is coupled to the example power stage 104 via the example first switch 126 , to the example reference voltage generator 106 via the example second switch 128 and the example third switch 130 , to the example delay unit 110 , and to the example fourth switch 132 .

[0023] exist Figure 1 In , the example delay unit 110 is coupled to the example error amplifier 108, to the example oscillator 112 via the example fifth switch 134, to the example ADC 114, and to the example power stage 104. Figure 1 In FIG, the example oscillator 112 is coupled to the example delay unit 110 and to the example feed-forward voltage controller 116 via the example fifth switch 134. Figure 1 In , the example ADC 114 is coupled to the example delay unit 110 and the example feed-forward voltage controller 116. Figure 1In FIG, the example feed-forward voltage controller 116 is coupled to the example reference voltage generator 106, the example oscillator 112, the example ADC 114, and the example power supply 138. Figure 1 In FIG, a first input terminal 120 of the example comparator 118 is coupled to the example power stage 104 via a voltage divider 117. Figure 1 In the example of , the second input 122 of the example comparator 118 is coupled to the example reference voltage generator 106. Figure 1 , the output 124 of the comparator 118 is coupled to an example latch 125. The example latch 125 is coupled to an example first switch 126 via a first inverter 127, to an example second switch 128, to an example third switch 130 via a second inverter 131, to an example fourth switch 132, and to an example fifth switch 134 via a third inverter 135.

[0024] exist Figure 1In the example, each of the example first switch 126, the example second switch 128, the example third switch 130, the example fourth switch 132, and the example fifth switch 134 includes a first terminal (e.g., a current terminal), a second terminal (e.g., a current terminal), and a third terminal (e.g., a control terminal). In the illustrated example, the first terminal of the example first switch 126 is coupled to the example power stage 104 via the voltage divider 117, the second terminal of the example first switch 126 is coupled to the example error amplifier 108, and the third terminal of the example first switch 126 is coupled to the output 124 of the example comparator 118 via the latch 125 and the first inverter 127. In the illustrated example, the first terminal of the example second switch 128 is coupled to the example reference voltage generator 106, the second terminal of the example second switch 128 is coupled to the example error amplifier 108, and the third terminal of the example second switch 128 is coupled to the output 124 of the example comparator 118 via the latch 125. In the illustrated example, a first terminal of the example third switch 130 is coupled to the example reference voltage generator 106, a second terminal of the example third switch 130 is coupled to the example error amplifier 108, and a third terminal of the example third switch 130 is coupled to the output 124 of the example comparator 118 via a latch 125 and a second inverter 131. In the illustrated example, a first terminal of the example fourth switch 132 is coupled to the example error amplifier 108, a second terminal of the example fourth switch 132 is coupled to the example error amplifier 108, and a third terminal of the example fourth switch 132 is coupled to the output 124 of the example comparator 118 via a latch 125. In the illustrated example, a first terminal of the example fifth switch 134 is coupled to the example oscillator 112, a second terminal of the example fifth switch 134 is coupled to the example delay unit 110, and a third terminal of the example fifth switch 134 is coupled to the output 124 of the example comparator 118 via a latch 125 and a third inverter 135.

[0025] exist Figure 1 , the power stage 104 is a DC-DC converter controlled by the controller 102. The power stage 104 receives power to be converted from the power source 138. In the examples herein, the power stage 104 is a DC-DC power converter, such as a boost converter, a buck-boost converter, or the like. Alternatively, the power stage 104 can be any power stage (e.g., a DC-DC converter, an AC-DC converter, an AC-AC converter, etc.) in any suitable telecommunications application, data communications application, server, automotive application (e.g., a traction inverter in an electric vehicle (EV)), industrial application (e.g., a bridge inverter, a motor drive, etc.). In other examples, the power stage 104 can be two synchronous switches, additional power converter control logic, or a combination thereof. In Figure 1In FIG, the power stage 104 generates an output voltage signal. In addition, the output voltage signal is monitored by the controller 102, more specifically, by the error amplifier 108 as a feedback voltage signal VFB. Figure 1 In the embodiment of the present invention, load 136 can be an LED array in an EV, a motor, a server, an industrial and / or residential appliance, a data communication server, or any suitable load. In other examples, load 136 can be one or more inductors, capacitors, resistors, or a combination thereof to filter the output of power stage 104.

[0026] exist Figure 1 In the example, the power supply 138 is an unregulated linear power supply. For example, the power supply 138 is the output of a diode rectifier. In other examples, other power supplies suitable for the application can be used. The example power supply 138 generates an input voltage signal V IN .

[0027] exist Figure 1 In FIG, the reference voltage generator 106 is a combination of one or more voltage regulators, amplifiers, comparators, and other logic for regulating one or more voltage levels in the controller 102. For example, the reference voltage generator 106 generates a first voltage signal V SOFT For example, the first voltage signal V SOFT At a reference voltage level corresponding to a soft start of the power stage 104, so that the power stage 104 ramps up to a desired and / or predetermined voltage level (eg, corresponding to V SET In addition, the example reference voltage generator 106 generates a trimming voltage signal V TON (eg, at a second voltage level) to serve as a reference voltage level for the error amplifier 108. In the example herein, the trimming voltage signal V generated by the reference voltage generator 106 is TON is temperature compensated (e.g., changes in response to changes in external temperature and / or silicon die temperature and / or otherwise alters). For example, as the temperature of the delay unit 110 increases and / or decreases from a previous temperature, the trim voltage signal VTON generated by the reference voltage generator 106 changes accordingly to ensure proper operation at all temperatures. For example, the trim voltage signal V generated by the reference voltage generator 106 TON Corresponding to the desired duration (eg, 1.2 nanoseconds) of each delay unit 110. In addition, the trimming voltage signal V generated by the example reference voltage generator 106 is TON The fine-tuning voltage signal V generated by the reference voltage generator 106 is changed at different temperatures to maintain the desired duration of each delay unit 110. For example, when the temperature of the delay unit 110 increases, the fine-tuning voltage signal V generated by the reference voltage generator 106 is increased. TONis reduced to maintain the desired duration of the delay cell 110. In an alternative embodiment, when the temperature of the example delay cell 110 decreases, the trimming voltage signal V generated by the reference voltage generator 106 is TON Increase to maintain the desired duration on the delay unit 110. In additional or alternative examples, the fine-tuning voltage signal V generated by the reference voltage generator 106 TON It is increased to compensate for a temperature rise of the delay unit 110 and is decreased to compensate for a temperature drop of the delay unit 110 .

[0028] exist Figure 1 In FIG, the example error amplifier 108 is a circuit that generates a control signal based on one or more inputs from the example power stage 104 and the reference voltage generator 106. For example, the error amplifier 108 can be a combination of a resistor, capacitor, and / or inductor feedback network and an operational amplifier. In other examples, the error amplifier can be a combination of a resistor, capacitor, and / or inductor feedback network and a differential difference amplifier. During steady-state operation, if the output voltage signal of the power stage 104 deviates from a desired level (for example, if the feedback voltage signal V FB In some examples herein, the error amplifier 108 may include multiple error amplifiers, such as a two-pole-one-zero amplifier and / or a one-pole-one-zero amplifier, to generate the control signal.

[0029] exist Figure 1 In the example, the example delay unit 110 includes a plurality of example delay units to generate a PWM signal. In the example of this article, the delay unit 110 generates a PWM signal by IN , the signal generated by the oscillator 112 and the first voltage signal V SOFT One or more of the delay elements (e.g., more generally, the output of ADC 114) introduce a delay to the example oscillator signal to generate a PWM signal. Delay element 110 is used to provide a PWM signal to power stage 104 to provide power to example load 136. Figure 1 In FIG. 1 , the duration of each delay cell in the delay cells 110 is determined based on the control signal generated by the error amplifier 108 .

[0030] exist Figure 1 In , oscillator 112 is a phase-locked loop oscillator. In other examples, oscillator 112 is a capacitor (RC) oscillator, a ring oscillator, a crystal oscillator, or any other suitable oscillator for the application. Figure 1 In the embodiment, the oscillator 112 generates an oscillation signal. Figure 1In the example, the oscillating signal can be a periodic and / or non-periodic signal generated to initiate generation of the PWM signal and / or otherwise set the frequency of operation of the delay unit 110. For example, when the oscillator 112 outputs the oscillating signal, the delay unit 110 generates a corresponding rising edge on the PWM signal when the oscillating signal is at a falling edge. In such an example, the PWM signal remains at a logic high value for a delay duration associated with the number of active delay units 110. The number of active delay units 110 is indicated by the example ADC 114.

[0031] exist Figure 1 In the example ADC 114, the current analog-to-digital converter is a current analog-to-digital converter. The ADC 114 converts the analog current level into a digital output (e.g., a binary count value). For example, the example ADC 114 converts the analog current level into an eight-bit binary signal to indicate the number of delay cells 110 to be activated. In other examples herein, the ADC 114 may be any other suitable decoder that indicates the number of delay cells 110 to be activated.

[0032] exist Figure 1 In the example, the feed-forward voltage controller 116 is an analog multiplier. The feed-forward voltage controller 116 generates an analog current signal for use by the ADC 114. For example, the feed-forward voltage controller 116 generates an analog current signal based on the first voltage signal V SOFT 、Input voltage signal V IN , one or more of the frequencies of the oscillator signals generated by the oscillator 112, and one or more constants corresponding to the scaling factors to generate the analog current signal. The scaling factors are suitable for the design of the controller 102. For example, the scaling factors are related to the duration of each delay unit 110. The example feed-forward voltage controller 116 sets the number of delay units 110 to be activated via the ADC 114. In this way, the example feed-forward voltage controller 116 sets the delay (e.g., duration) of the pulse width of the PWM signal generated by the delay unit 110 via the ADC 114 by setting the number of delay units 110 to be activated. In this way, the delay unit 110 generates a PWM signal by introducing a delay to the example oscillator signal, the delay being based on the output of the feed-forward voltage controller 116 (e.g., based on the input voltage V IN , the signal generated by the oscillator 112 and the first voltage signal V SOFT ).

[0033] exist Figure 1 , example voltage divider 117 is a resistor divider network that allows the voltage level at the output voltage of power stage 104 to be measured and / or otherwise monitored by error amplifier 108 and / or, more generally, controller 102 without the possibility of damaging error amplifier 108 and / or, more generally, controller 102.

[0034] exist Figure 1 In the example, the comparator 118 is an analog comparator. In other examples, the comparator 118 is a digital comparator, a comparator controller, a trigger (e.g., a Schmitt trigger), one or more integrated circuits, logic circuits, microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or controllers from any desired family or manufacturer. The comparator 118 can be a semiconductor-based (e.g., silicon-based) device. The comparator 118 compares the feedback voltage signal V received at the first input 120 with the feedback voltage signal V FB and the first voltage signal V received at the second input terminal 122 SOFT , and determine the first voltage signal V SOFT Is the amplitude of the feedback voltage signal V FB For example, the threshold voltage corresponds to the first voltage signal V based on the application SOFT The amplitude of the feedback voltage signal V FB The example comparator 118 is also based on at least the first voltage signal V SOFT and feedback voltage signal V FB The example comparator 118 configures one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134 via the control signal generated at the output 124 when operation of the controller 102 begins. In additional or alternative examples, the example comparator 118 configures one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134 via the control signal generated at the output 124 when operation of the controller 102 begins.

[0035] exist Figure 1 , latch 125 is a device that holds a logic value at an output of latch 125 that corresponds to a logic value received at an input of latch 125. For example, latch 125 is an SR latch. In other examples, latch 125 is a D flip-flop, a JK latch, a gated SR latch, a gated JK latch, a gated D flip-flop, an Earle latch, or any other suitable latch.

[0036] exist Figure 1In the embodiment of the present invention, each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 can be implemented by a transistor. For example, each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 is a negative-channel (n-channel) metal oxide semiconductor field effect transistor (MOSFET). In other examples, the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 can be implemented by a bipolar junction transistor (BJT), a junction gate field effect transistor (JFET), a heterojunction bipolar transistor (HBT), any transistor suitable for the application, and / or any combination thereof. Although one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134 may be implemented using many combinations of BJTs, JFETs, HBTs, or any suitable transistors, it may be desirable in a particular controller to implement each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 with the same switch type (e.g., all n-type BJTs, all p-type BJTs, all positive-channel (p-channel) MOSFETs, etc.). In a further example, each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, or any combination thereof, is implemented as one or more multiplexers.

[0037] exist Figure 1 In the embodiment, each of the first inverter 127, the second inverter 131, and the third inverter 135 is a device that inverts the logic values ​​received at the input terminals of the first inverter 127, the second inverter 131, and the third inverter 135, respectively, and outputs the inverted logic values ​​at the output terminals of the first inverter 127, the second inverter 131, and the third inverter 135, respectively. Figure 1 In the embodiment, each of the first inverter 127, the second inverter 131, and the third inverter 135 is a NOT logic gate. In another example, each of the first inverter 127, the second inverter 131, and the third inverter 135 can be a combination of one or more logic gates / logic circuits that invert the logic value of a received signal and output the inverted logic value. In an analog embodiment, each of the first inverter 127, the second inverter 131, and the third inverter 135 can be an inverting amplifier.

[0038] exist Figure 1 In operation, the example comparator 118 configures the error amplifier 108 as a voltage follower, wherein the trimming voltage signal V TONAs input. For example, the example comparator 118 configures the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 to configure the error amplifier 108 to operate as a voltage follower. More specifically, the example comparator 118 opens the first switch 126, closes the second switch 128, opens the third switch 130, closes the fourth switch 132, and opens the fifth switch 134. By configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134, the comparator 118 disables the error amplifier 108 from operating based on the feedback voltage signal V FB The comparator 118 controls the duration of each delay cell in the delay cell 110. Conversely, by configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134, the comparator 118 enables the error amplifier 108 to adjust the voltage signal V FB The duration of each delay unit in the delay unit 110 is controlled. In addition, the example feed-forward voltage controller 116 is based on the first voltage signal V SOFT Divide by the input voltage signal V IN The output of the delay unit 110 (e.g., the PWM signal on-time) is set by multiplying the period of the oscillator 112 by the period of the oscillator 112. In addition, the example comparator 118 disables the PWM signal of the delay unit 110 by disconnecting the oscillator 112 from the delay unit 110 by configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134.

[0039] exist Figure 1 In operation, the comparator 118 monitors the first voltage signal V SOFT To determine the first voltage signal V SOFT Whether the soft start function has been started. For example, the comparator 118 monitors the first voltage signal V SOFT And when the comparator 118 detects the first voltage signal V SOFT When the voltage on the SOFT The soft start function has been started. When the example comparator 118 determines that the first voltage signal V SOFT The soft start function has been started (for example, the first voltage signal V SOFT When the feedback voltage signal V FB and the first voltage signal V SOFT To determine the first voltage signal V SOFT Is the feedback voltage signal V FB within the threshold difference.

[0040] exist Figure 1 In operation, when the example comparator 118 determines the first voltage signal V SOFT The feedback voltage signal V FB When the difference is within the threshold value, the example comparator 118 enables the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT To control the power stage 104. For example, when the example comparator 118 determines that the first voltage signal V SOFT The feedback voltage signal V FB , the example comparator 118 configures one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134. More specifically, when the example comparator 118 determines that the first voltage signal V SOFT The feedback voltage signal V FB When the difference between the first and second switches V and V is within the threshold value, the example comparator 118 closes the first switch 126, opens the second switch 128, closes the third switch 130, opens the fourth switch 132, and closes the fifth switch 134. By configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134, the comparator 118 enables the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT The duration of each delay cell in the delay cells 110 is controlled. Furthermore, the example comparator 118 enables the PWM signal for the delay cells 110 by configuring (e.g., opening and / or closing) one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134.

[0041] Figure 2 is a schematic diagram of an example power converter system 200 showing Figure 1 1. Further details of the controller 102 of the power converter system 200 are provided. The power converter system 200 includes an example controller 102, an example power stage 104, an example load 136, an example power supply 138, and an example voltage input 140. The example controller 102 includes an example reference voltage generator 106, an example error amplifier 108, an example delay unit 110, an example oscillator 112, an example ADC 114, an example feed-forward voltage controller 116, an example voltage divider 117, an example comparator 118 (including an example first input 120, an example second input 122, and an example output 124), an example latch 125, an example first switch 126, an example first inverter 127, an example second switch 128, an example third switch 130, an example second inverter 131, an example fourth switch 132, an example fifth switch 134, and an example third inverter 135.

[0042] exist Figure 2 , the example power stage 104 includes an example sixth switch 202, an example seventh switch 204, an example inductor 206, an example first capacitor 208, an example ground reference node 210, and an example inverter 212. The example error amplifier 108 includes an example first resistor 214, an example second capacitor 216, an example operational amplifier 218, and an example second resistor 220. The example operational amplifier 218 includes an inverting input 222, a non-inverting input 224, and an output 226. Figure 2 , each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, the sixth switch 202, and the seventh switch 204 includes a first terminal (e.g., a current terminal), a second terminal (e.g., a current terminal), and a third terminal (e.g., a control terminal).

[0043] exist Figure 2 , an example controller 102 is coupled to an example power stage 104. The example power stage 104 is coupled to the example controller 102, an example load 136, an example power source 138, and an example voltage input 140.

[0044] exist Figure 2 , a second terminal of the example sixth switch 202 is coupled to the power supply 138, a first terminal of the example sixth switch 202 is coupled to the switch node SW, and a third terminal of the example sixth switch 202 is coupled to the delay unit 110. Figure 2 , a second terminal of the example seventh switch 204 is coupled to the switch node SW, a first terminal of the example seventh switch 204 is coupled to the ground reference node 210, and a third terminal of the example seventh switch 204 is coupled to the inverter 212. The example inductor 206 is coupled between the switch node SW and the output voltage node V O The example first capacitor 208 is coupled between the example output voltage node V O and ground reference node 210. Figure 2 , a ground reference node 210 is coupled to the first capacitor 208 and the first terminal of the seventh switch 204. An example inverter 212 is coupled to the third terminal of the seventh switch 204 and the delay unit 110.

[0045] exist Figure 2 In FIG, the example reference voltage generator 106 is coupled to the non-inverting input 224 of the operational amplifier 218, to the second input 122 of the comparator 118, and to the feed-forward voltage controller 116 via the second switch 128 and the third switch 130. Figure 2, the first resistor 214 is coupled in series to the second capacitor 216. Together, the first resistor 214 and the second capacitor 216 are coupled in parallel between the inverting input 222 and the output 226 of the operational amplifier 218 and form an operational amplifier feedback network. Figure 2 130 , the second capacitor 216 is coupled in parallel with the first and second terminals of the fourth switch 132. In an alternative example, the first and second terminals of the fourth switch 132 are coupled in parallel with the first resistor 214 and the second capacitor 216. In the illustrated example, the inverting terminal 222 of the operational amplifier 218 is coupled to the second terminal of the first switch 126 and the first resistor 214. An example non-inverting terminal 224 of the operational amplifier 218 is coupled to the reference voltage generator 106 via the second switch 128 and the third switch 130. In the illustrated example, the second resistor 220 is coupled to the first terminal of the first switch 126 and the output voltage node V of the power stage 104 via the voltage divider 117. O .

[0046] exist Figure 2 , the example delay cell 110 is coupled to the output 226 of the operational amplifier 218, to the example oscillator 112 via the example fifth switch 134, to the example ADC 114, to the third terminal of the example sixth switch 202, and to the inverter 212. The example oscillator 112 is coupled to the example delay cell 110 via the example fifth switch 134 and to the example feed-forward voltage controller 116. The example ADC 114 is coupled to the example delay cell 110 and the example feed-forward voltage controller 116. The example feed-forward voltage controller 116 is coupled to the example reference voltage generator 106, the example oscillator 112, the example ADC 114, and the example power supply 138. The example first input 120 of the comparator 118 is coupled to the output voltage node V of the example power stage 104 via the voltage divider 117. O , a second input 122 of the example comparator 118 is coupled to the example reference voltage generator 106, and an output 124 of the comparator 118 is coupled to an example latch 125. The latch 125 is coupled to a third terminal of an example first switch 126 via a first inverter 127, to a third terminal of an example second switch 128, to a third terminal of an example third switch 130 via a second inverter 131, to a third terminal of an example fourth switch 132, and to a third terminal of an example fifth switch 134 via a third inverter 135.

[0047] exist Figure 2 , a first terminal of the example first switch 126 is coupled to the output voltage node V of the example power stage 104 via the second resistor 220 and the voltage divider 117. OA second terminal of the example first switch 126 is coupled to the inverting terminal 222 of the operational amplifier 218. A third terminal of the example first switch 126 is coupled to the output 124 of the example comparator 118 via a latch 125 and a first inverter 127. In the illustrated example, a first terminal of the example second switch 128 is coupled to the example reference voltage generator 106, and a second terminal of the example second switch 128 is coupled to the non-inverting terminal 224 of the example operational amplifier 218. A third terminal of the example second switch 128 is coupled to the output 124 of the example comparator 118 via a latch 125. In the illustrated example, a first terminal of the example third switch 130 is coupled to the example reference voltage generator 106, and a second terminal of the example third switch 130 is coupled to the non-inverting terminal 224 of the example operational amplifier 218. A third terminal of the example third switch 130 is coupled to the output 124 of the example comparator 118 via a latch 125 and a second inverter 131. In the illustrated example, the first and second terminals of the example fourth switch 132 are coupled to the second capacitor 216, such that the fourth switch 132 is coupled in parallel to the second capacitor 216. The third terminal of the example fourth switch 132 is coupled to the output 124 of the example comparator 118 via the latch 125. In other examples, the first and second terminals of the example fourth switch 132 are coupled to the first resistor 214 and the second capacitor 216, such that the fourth switch 132 is coupled in parallel to the first resistor 214 and the second capacitor 216. In the illustrated example, the first terminal of the example fifth switch 134 is coupled to the example oscillator 112, and the second terminal of the example fifth switch 134 is coupled to the example delay unit 110. The third terminal of the example fifth switch 134 is coupled to the output 124 of the example comparator 118 via the latch 125 and the third inverter 135.

[0048] exist Figure 2 In the embodiment of the present invention, power stage 104 is a DC-DC buck converter. A DC power converter functions by temporarily storing input energy in electronic components (e.g., inductors, capacitors, inductive elements, capacitive elements, etc.) and then releasing the energy at a different voltage at load 136. In power stage 104, inverter 212 is a NOT gate. The example inverter 212 ensures that when sixth switch 202 is closed, seventh switch 204 is open, and when seventh switch 204 is closed, sixth switch 202 is enabled. In other examples, inverter 212 can be a combination of logic circuits that ensure that sixth switch 202 and seventh switch 204 are not closed at the same time.

[0049] exist Figure 2 When the sixth switch 202 is closed and the seventh switch 204 is open, the current flows from the power supply 138 (eg, the input voltage signal V IN) flows to the inductor 206 which is charged at a linear rate. When the inductor 206 is charging, the inductor 206 is charged by the current I flowing through the inductor 206. SW Energy is stored in the magnetic field generated. Moreover, when the sixth switch 202 is closed and the seventh switch 204 is open, the first capacitor 208 is also charged to the desired output voltage level, and the load 136 is provided with current from the power supply 138. When the sixth switch 202 is open, the seventh switch 204 is closed, so that the current I SW The energy stored in the magnetic field of the inductor 206 dissipates, and as it dissipates, a current (eg, I SW When the sixth switch 202 is turned off, the current I flowing through the power stage 104 SW The current from the inductor 206 flows to the first capacitor 208 and the load 136, and the first capacitor 208 is at the output voltage node V of the power stage 104. O The desired output voltage is maintained at 134 and the load 136 receives power. SW The current flows through the ground reference node 210 and the seventh switch 204 back to the inductor 206. The switching pattern described above allows continuous current to flow into the load 136.

[0050] exist Figure 2 In the example, load 136 is a subcircuit of the microcontroller. In other examples, load 136 can be an LED array in an EV, a motor, a server, an industrial and / or residential appliance, a data communication server, or any suitable load.

[0051] exist Figure 2 In the example, the power supply 138 is an unregulated linear power supply. For example, the power supply 138 is the output of a diode rectifier. In other examples, other power supplies suitable for the application can be used. The example power supply 138 generates an input voltage signal V IN .

[0052] exist Figure 2 In FIG, the reference voltage generator 106 is a combination of one or more voltage regulators, amplifiers, comparators, and other logic that regulates one or more voltage levels in the controller 102. For example, the reference voltage generator 106 generates a first voltage signal V at a first voltage level. SOFT For example, the first voltage signal V SOFT At a reference voltage level corresponding to a soft start of the power stage 104, so that the power stage 104 ramps up to a desired and / or predetermined voltage level (eg, corresponding to V SET In addition, the example reference voltage generator 106 generates a trimming voltage signal V TON(eg, at a second voltage level) to serve as a reference voltage level for the operational amplifier 218. In the example herein, the fine-tuning voltage signal V generated by the reference voltage generator 106 is TON is temperature compensated (e.g., changes in response to changes in external temperature and / or silicon die temperature and / or otherwise varies). For example, as the temperature of delay cell 110 increases and / or decreases from a previous temperature, the trim voltage signal V generated by reference voltage generator 106 may be adjusted. TON For example, the trim voltage signal V generated by the reference voltage generator 106 is changed accordingly to ensure correct operation at all temperatures. TON Corresponding to the desired duration (eg, 1.2 nanoseconds) of each delay unit 110. In addition, the trimming voltage signal V generated by the example reference voltage generator 106 is TON The fine-tuning voltage signal V generated by the reference voltage generator 106 is changed at different temperatures to maintain the desired duration of each delay unit 110. For example, when the temperature of the delay unit 110 increases, the fine-tuning voltage signal V generated by the reference voltage generator 106 is increased. TON is reduced to maintain the desired duration of the delay cell 110. In an alternative embodiment, when the temperature of the example delay cell 110 decreases, the trimming voltage signal V generated by the reference voltage generator 106 is TON Increase to maintain the desired duration on the delay unit 110. In additional or alternative examples, the fine-tuning voltage signal V generated by the reference voltage generator 106 TON It is increased to compensate for a temperature rise of the delay unit 110 and is decreased to compensate for a temperature drop of the delay unit 110 .

[0053] exist Figure 2 , the example error amplifier 108 includes a first resistor 214, a second capacitor 216, an operational amplifier 218, and a second resistor 220. Collectively, the first resistor 214, the second capacitor 216, the operational amplifier 218, and the second resistor 220 generate a control signal V at an output 226 based on one or more inputs from the example power stage 104 and the reference voltage generator 106. ERROR The error amplifier 108 monitors the output voltage node V of the power stage 104 via the voltage divider 117. O The output voltage level at the feedback voltage signal V FB .exist Figure 2 In FIG, the first resistor 214, the second capacitor 216, and the second resistor 220 are an operational amplifier feedback network that sets the gain of the error amplifier 108 so that the error amplifier 108 can control the power stage 104 to generate a voltage at the output voltage node V O The desired output voltage level (e.g., corresponding to V SETDuring steady-state operation, if the output voltage node V O The output voltage signal at the output voltage deviates from the desired level (for example, if the feedback voltage signal V FB increases and / or decreases above normal operating levels during transients), the operational amplifier feedback network (e.g., first resistor 214, second capacitor 216, and second resistor 220) causes the operational amplifier 218 to generate a control signal V at the output 226. ERROR To adjust the duration of the delay of each delay unit included in the delay unit 110.

[0054] exist Figure 2 In the example, the example delay unit 110 includes a plurality of example delay units to generate a PWM signal. In the example of this article, the delay unit 110 generates a PWM signal by IN , the signal generated by the oscillator 112 and the first voltage signal V SOFT One or more of the delay cells 110 (e.g., more generally, the output of the ADC 114) introduce a delay to the example oscillator signal to generate a PWM signal. The delay cells 110 are used to adjust the duty cycle of the PWM signal to the power stage 104 to provide power to the example load 136. For example, the output of the ADC 114 determines the number of delay cells 110 that are selected (e.g., enabled). The duty cycle of the PWM signal corresponds to the number of delay cells 110 that are enabled multiplied by the duration of each delay cell 110. Figure 2 , the duration of each delay cell in delay cells 110 is determined based on the control signal generated by error amplifier 108. For example, a higher voltage level on the control signal corresponds to a longer duration of each delay cell 110, while a lower voltage level on the control signal corresponds to a shorter duration of each delay cell 110.

[0055] exist Figure 2 In the example, the oscillator 112 is a phase-locked loop oscillator. In other examples, the oscillator 112 is a capacitor (RC) oscillator, a ring oscillator, a crystal oscillator, or any other suitable oscillator for the application. The example oscillator 112 generates an oscillation signal. Figure 2 In the example, the oscillating signal can be a periodic and / or non-periodic signal generated to initiate the generation of the PWM signal and / or otherwise set the frequency of operation of the delay unit 110. For example, when the oscillator 112 outputs the oscillating signal, the delay unit 110 generates a corresponding rising edge on the PWM signal when the oscillating signal is at a falling edge. In such an example, the PWM signal remains at a logic high value for a delay duration associated with the number of active delay units 110. The number of active delay units 110 is indicated by the example ADC 114.

[0056] exist Figure 2 In the example ADC 114, the current analog-to-digital converter is a current analog-to-digital converter. The ADC 114 converts the analog current level into a digital output (e.g., a binary count value). For example, the example ADC 114 converts the analog current level into an eight-bit binary signal to indicate the number of delay cells 110 to be activated. In other examples herein, the ADC 114 may be any other suitable decoder that indicates the number of delay cells 110 to be activated.

[0057] exist Figure 2 In FIG. 1 , the example feed-forward voltage controller 116 is an analog multiplier. The example feed-forward voltage controller 116 generates an analog current signal for use by the ADC 114. For example, the feed-forward voltage controller 116 generates an analog current signal based on the first voltage signal V SOFT 、Input voltage signal V IN , one or more of the frequencies of the oscillator signal generated by the oscillator 112, and one or more constants corresponding to the scaling factors generate an analog current signal. The scaling factors are suitable for the design of the controller 102. For example, the scaling factors are related to the duration of each delay unit 110. The example feed-forward voltage controller 116 sets the number of delay units 110 to be activated via the ADC 114. In this way, the example feed-forward voltage controller 116 sets the delay (e.g., duration) of the pulse width of the PWM signal generated by the delay unit 110 via the ADC 114 by setting the number of delay units 110 to be activated. In this way, the delay unit 110 generates a PWM signal by introducing a delay to the example oscillator signal, the delay being based on the output of the feed-forward voltage controller 116 (e.g., based on the input voltage VIN, the signal generated by the oscillator 112, and the first voltage signal V SOFT ).

[0058] exist Figure 2 , the example voltage divider 117 is a resistor divider network that allows the output voltage node V O The voltage level at is measured and / or otherwise monitored by the operational amplifier 218 and / or, more generally, by the error amplifier 108 without the possibility of damaging the operational amplifier 218 and / or, more generally, the error amplifier 108 .

[0059] exist Figure 2 In FIG, the comparator 118 is an analog comparator including a first input 120, a second input 122, and an output 124. Figure 2 In the embodiment, the comparator 118 compares the feedback voltage signal V received at the first input terminal 120 with the feedback voltage signal V FB and the first voltage signal V received at the second input terminal 122 SOFT , and determine the first voltage signal V SOFT Is the amplitude of the feedback voltage signal VFB For example, the threshold voltage corresponds to the first voltage signal V based on the application SOFT The amplitude of the feedback voltage signal V FB The example comparator 118 is also based on the first voltage signal V SOFT and feedback voltage signal V FB The comparison of configures one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132 or the fifth switch 134 via a control signal generated at the output 124. Figure 2 , the example comparator 118 configures one or more of the first switch 126 , the second switch 128 , the third switch 130 , the fourth switch 132 , or the fifth switch 134 via a control signal generated at the output 124 at the start of operation of the controller 102 .

[0060] exist Figure 2 , latch 125 is a device that holds a logic value at an output of latch 125 that corresponds to a logic value received at an input of latch 125. For example, latch 125 is an SR latch. In other examples, latch 125 is a D flip-flop, a JK latch, a gated SR latch, a gated JK latch, a gated D flip-flop, an Earle latch, or any other suitable latch.

[0061] exist Figure 2 In FIG, each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, the sixth switch 202, and the seventh switch 204 can be implemented by a transistor. For example, each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, and the sixth switch 202 is an n-channel MOSFET. Figure 2, the seventh switch 204 is a p-channel MOSFET. In other examples, the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, the sixth switch 202, and the seventh switch 204 are BJTs, JFETs, HBTs, any suitable transistors for the application, and / or any combination thereof. Although one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134 may be implemented using many combinations of BJTs, JFETs, HBTs, or any suitable transistors, it may be desirable to implement each of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 with the same switch type in a particular controller (e.g., all n-type BJTs, all p-type BJTs, all p-channel MOSFETs, etc.). In a further example, each of the first switch 126 , the second switch 128 , the third switch 130 , the fourth switch 132 , the fifth switch 134 , or any combination thereof is implemented as one or more multiplexers.

[0062] exist Figure 2 In the embodiment, each of the first inverter 127, the second inverter 131, and the third inverter 135 is a device that inverts the logic values ​​received at the input terminals of the first inverter 127, the second inverter 131, and the third inverter 135, respectively, and outputs the inverted logic values ​​at the output terminals of the first inverter 127, the second inverter 131, and the third inverter 135, respectively. Figure 2 In the embodiment, each of the first inverter 127, the second inverter 131, and the third inverter 135 is a NOT logic gate. In another example, each of the first inverter 127, the second inverter 131, and the third inverter 135 can be a combination of one or more logic gates / logic circuits that invert the logic value of a received signal and output the inverted logic value. In an analog embodiment, each of the first inverter 127, the second inverter 131, and the third inverter 135 can be an inverting amplifier.

[0063] exist Figure 2 In operation, the example comparator 118 configures the error amplifier 108 as a voltage follower, wherein the trimming voltage signal V TONAs an input to the non-inverting input terminal 224. For example, the example comparator 118 configures the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134 to configure the error amplifier 108 to operate as a voltage follower. More specifically, the example comparator 118 opens the first switch 126, closes the second switch 128, opens the third switch 130, closes the fourth switch 132, and opens the fifth switch 134. By configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134, the comparator 118 disables the error amplifier 108 from operating based on the feedback voltage signal V FB The comparator 118 controls the duration of each delay cell in the delay cell 110. Conversely, by configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134, the comparator 118 enables the error amplifier 108 to adjust the voltage signal V FB The duration of each delay unit in the delay unit 110 is controlled. In addition, the example feed-forward voltage controller 116 is based on the first voltage signal V SOFT Divide by the input voltage signal V IN The output of the delay unit 110 (e.g., the PWM signal on-time) is set by multiplying the period of the oscillator 112 by the period of the oscillator 112. In addition, the example comparator 118 disables the PWM signal of the delay unit 110 by disconnecting the oscillator 112 from the delay unit 110 by configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134.

[0064] exist Figure 2 In operation, the comparator 118 monitors the first voltage signal V SOFT To determine the first voltage signal V SOFT Whether the soft start function has been started. For example, the comparator 118 monitors the first voltage signal V SOFT And when the comparator 118 detects the first voltage signal V SOFT When the voltage on the SOFT The soft start function has been started. When the example comparator 118 determines that the first voltage signal V SOFT The soft start function has been started (for example, the first voltage signal V SOFT When the feedback voltage signal V FB and the first voltage signal V SOFT To determine the first voltage signal V SOFT Is the feedback voltage signal V FB within the threshold difference.

[0065] exist Figure 2 In operation, when the example comparator 118 determines the first voltage signal V SOFT The feedback voltage signal V FB When the difference is within the threshold value, the example comparator 118 enables the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT To control the power stage 104. For example, when the example comparator 118 determines that the first voltage signal V SOFT The feedback voltage signal V FB , the example comparator 118 configures one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134. More specifically, when the example comparator 118 determines that the first voltage signal V SOFT The feedback voltage signal V FB When the difference between the first and second switches V and V is within the threshold value, the example comparator 118 closes the first switch 126, opens the second switch 128, closes the third switch 130, opens the fourth switch 132, and closes the fifth switch 134. By configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134, the comparator 118 enables the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT The duration of each delay cell in the delay cells 110 is controlled. Furthermore, the example comparator 118 enables the PWM signal for the delay cells 110 by configuring (e.g., opening and / or closing) one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, and the fifth switch 134.

[0066] Figure 3 is a schematic diagram of an example power converter system 300 showing Figure 1 1. Alternative details of the controller 102 of FIG. The power converter system 300 includes the example controller 102, the example power stage 104, the example load 136, the example power supply 138, and the example voltage input 140. The example controller 102 includes the example reference voltage generator 106, the example error amplifier 108, the example delay unit 110, the example oscillator 112, the example ADC 114, the example feed-forward voltage controller 116, the example voltage divider 117, the example flip-flop 302, the example latch 125, the example fourth switch 132, the example fifth switch 134, the example third inverter 133, and the example eighth switch 310. The example flip-flop 302 includes an example first input 304, an example second input 306, and an example output 308.

[0067] exist Figure 3, the example power stage 104 includes an example sixth switch 202, an example seventh switch 204, an example inductor 206, an example first capacitor 208, an example ground reference node 210, and an example inverter 212. The example error amplifier 108 includes an example first resistor 214, an example second capacitor 216, an example differential difference amplifier 312, and an example second resistor 220. The example differential difference amplifier 312 includes a first non-inverting input 314, a first inverting input 316, a second non-inverting input 318, a second inverting input 320, and an output 322. Figure 2 , the fourth switch 132, the fifth switch 134, the sixth switch 202, and the seventh switch 204 include a first terminal (eg, a current terminal), a second terminal (eg, a current terminal), and a third terminal (eg, a control terminal). Figure 3 , the eighth switch 310 includes a first terminal (eg, a current terminal), a second terminal (eg, a current terminal), a third terminal (eg, a current terminal), and a fourth terminal (eg, a control terminal).

[0068] exist Figure 3 , an example controller 102 is coupled to an example power stage 104. The example power stage 104 is coupled to the example controller 102, an example load 136, an example power source 138, and an example voltage input 140.

[0069] exist Figure 3 In FIG, a second terminal of the example sixth switch 202 is coupled to the power supply 138, a first terminal of the example sixth switch 202 is coupled to the switch node SW, and a third terminal of the example sixth switch 202 is coupled to the delay unit 110. Figure 3 In FIG, a second terminal of the example seventh switch 204 is coupled to the switch node SW, a first terminal of the example seventh switch 204 is coupled to the ground reference node 210, and a third terminal of the example seventh switch 204 is coupled to the inverter 212. The example inductor 206 is coupled between the switch node SW and the output voltage node V O The example first capacitor 208 is coupled between the example output voltage node V O and a ground reference node 210. The ground reference node 210 is coupled to the first capacitor 208 and a first terminal of the seventh switch 204. An example inverter 212 is coupled to a third terminal of the seventh switch 204 and the delay unit 110.

[0070] exist Figure 3, the example reference voltage generator 106 is coupled to a first non-inverting input 314 of a differential difference amplifier 312 via an eighth switch 310, to a second non-inverting input 318 of the differential difference amplifier 312, to a second inverting input 316 of the differential difference amplifier 312 via a second resistor 220, to a first input 304 of a flip-flop 302, to the feed-forward voltage controller 116, and to the power stage 104. Figure 3 , the first resistor 214 is coupled in series to the second capacitor 216. Together, the first resistor 214 and the second capacitor 216 are coupled in parallel between the second inverting input terminal 320 and the output terminal 322 of the differential difference amplifier 312 and form a differential difference amplifier feedback network. Figure 3 , the second capacitor 216 is coupled in parallel with the first and second terminals of the fourth switch 132. In an alternative example, the first and second terminals of the fourth switch 132 are coupled in parallel with the first resistor 214 and the second capacitor 216. In the example shown, the first non-inverting terminal 314 of the differential difference amplifier 312 is coupled to the third terminal of the eighth switch 310. Figure 3 In the embodiment, the first inverting input terminal 316 of the differential difference amplifier 312 is coupled to the output voltage node V of the power stage 104 via the voltage divider 117. O .exist Figure 3 In FIG, the second non-inverting input terminal 318 of the differential difference amplifier 312 is coupled to the reference voltage generator 106. Figure 3 In the example shown, the second inverting input 320 of the differential difference amplifier 312 is coupled to the reference voltage generator 106 via the second resistor 220. In the example shown, the second resistor 220 is coupled to the reference voltage generator 106 and the second inverting input 320 of the differential difference amplifier 312.

[0071] exist Figure 3 , the example delay cell 110 is coupled to the output 322 of the differential difference amplifier 312, to the example oscillator 112 via the example fifth switch 134, to the example ADC 114, to the third terminal of the example sixth switch 202, and to the inverter 212. The example oscillator 112 is coupled to the example delay cell 110 via the example fifth switch 134 and to the example feed-forward voltage controller 116. The example ADC 114 is coupled to the example delay cell 110 and the example feed-forward voltage controller 116. The example feed-forward voltage controller 116 is coupled to the example reference voltage generator 106, the example oscillator 112, the example ADC 114, and the example power supply 138. The example first input 304 of the flip-flop 302 is coupled to the reference voltage generator 106 (e.g., the first voltage signal V SOFT ), the second input terminal 306 of the example flip-flop 302 is coupled to the output voltage node VO , and the output 308 of the flip-flop 302 is coupled to the example latch 125. The latch 125 is coupled to the third terminal of the example fourth switch 132, to the third terminal of the example fifth switch 134 via the third inverter 135, and to the fourth terminal of the example eighth switch 310.

[0072] exist Figure 3 , the first and second terminals of the example fourth switch 132 are coupled to the second capacitor 216, such that the fourth switch 132 is coupled in parallel to the second capacitor 216. The third terminal of the example fourth switch 132 is coupled to the output 308 of the example flip-flop 302 via the latch 125 and the third inverter 135. In other examples, the first and second terminals of the example fourth switch 132 are coupled to the first resistor 214 and the second capacitor 216, such that the fourth switch 132 is coupled in parallel to the first resistor 214 and the second capacitor 216. In the example shown, the first terminal of the example fifth switch 134 is coupled to the example oscillator 112, and the second terminal of the example fifth switch 134 is coupled to the example delay unit 110. The third terminal of the example fifth switch 134 is coupled to the output 308 of the example flip-flop 302 via the latch 125. Figure 3 In the embodiment, the first terminal of the eighth switch 310 is coupled to the reference voltage generator 106 and receives the first voltage signal V SOFT , the second terminal of the eighth switch 310 is coupled to the output voltage node V O And receive feedback voltage signal V FB , a third terminal of the eighth switch 310 is coupled to the first non-inverting input terminal of the differential amplifier 312, and a fourth terminal of the eighth switch 310 is coupled to the output terminal of the flip-flop 302. Figure 3 In FIG. 1 , power stage 104 is a DC-DC buck converter. A DC power converter functions by temporarily storing input energy in electronic components (e.g., inductors, capacitors, inductive elements, capacitive elements, etc.) and then releasing that energy at a different voltage at load 136. In power stage 104, inverter 212 is a NOT gate. The example inverter 212 ensures that when sixth switch 202 is closed, seventh switch 204 is open, and when seventh switch 204 is closed, sixth switch 202 is open. In other examples, inverter 212 may be a combination of logic circuits that ensure that sixth switch 202 and seventh switch 204 are not closed at the same time.

[0073] exist Figure 3 When the sixth switch 202 is closed and the seventh switch 204 is open, the current flows from the power supply 138 (eg, the input voltage signal V IN ) flows to the inductor 206 which is charged at a linear rate. When the inductor 206 is charged, the inductor 206 is charged by the current I flowing through the inductor 206.SW Energy is stored in the magnetic field generated. In addition, when the sixth switch 202 is closed and the seventh switch 204 is open, the first capacitor 208 is also charged to the desired output voltage level, and the load 136 is provided with current from the power supply 138. When the sixth switch 202 is open, the seventh switch 204 is closed, so that the current I SW The energy stored in the magnetic field of the inductor 206 dissipates, and as it dissipates, a current (eg, I SW When the sixth switch 202 is turned off, the current I flowing through the power stage 104 SW The current from the inductor 206 flows to the first capacitor 208 and the load 136, and the first capacitor 208 is at the output voltage node V of the power stage 104. O The desired output voltage is maintained at 134 and the load 136 receives power. SW The current flows through the ground reference node 210 and the seventh switch 204 back to the inductor 206. The switching pattern described above allows continuous current to flow into the load 136.

[0074] exist Figure 3 In the example, load 136 is a subcircuit of the microcontroller. In other examples, load 136 can be an LED array in an EV, a motor, a server, an industrial and / or residential appliance, a data communication server, or any suitable load.

[0075] exist Figure 3 In the example, the power supply 138 is an unregulated linear power supply. For example, the power supply 138 is the output of a diode rectifier. In other examples, other power supplies suitable for the application can be used. The example power supply 138 generates an input voltage signal V IN .

[0076] exist Figure 3 In FIG, the reference voltage generator 106 is a combination of one or more voltage regulators, amplifiers, comparators, and other logic for regulating one or more voltage levels in the controller 102. For example, the reference voltage generator 106 generates a first voltage signal V SOFT For example, the first voltage signal V SOFT At a reference voltage level corresponding to a soft start of the power stage 104, so that the power stage 104 ramps up to a desired and / or predetermined voltage level (eg, corresponding to V SET In addition, the example reference voltage generator 106 generates a trimming voltage signal V TON(eg, at a second voltage level) to serve as a reference voltage level for the differential amplifier 312. In the example herein, the fine-tuning voltage signal V generated by the reference voltage generator 106 is TON is temperature compensated (e.g., changes in response to changes in external temperature and / or silicon die temperature and / or otherwise varies). For example, as the temperature of delay cell 110 increases and / or decreases from a previous temperature, the trim voltage signal V generated by reference voltage generator 106 may be adjusted. TON For example, the trim voltage signal V generated by the reference voltage generator 106 is changed accordingly to ensure correct operation at all temperatures. TON Corresponding to the desired duration (eg, 1.2 nanoseconds) of each delay unit 110. In addition, the trimming voltage signal V generated by the example reference voltage generator 106 is TON The fine-tuning voltage signal V generated by the reference voltage generator 106 is changed at different temperatures to maintain the desired duration of each delay unit 110. For example, when the temperature of the delay unit 110 increases, the fine-tuning voltage signal V generated by the reference voltage generator 106 is increased. TON is reduced to maintain the desired duration of the delay cell 110. In an alternative embodiment, when the temperature of the example delay cell 110 decreases, the trimming voltage signal V generated by the reference voltage generator 106 is TON Increase to maintain the desired duration on the delay unit 110. In additional or alternative examples, the fine-tuning voltage signal V generated by the reference voltage generator 106 TON It is increased to compensate for a temperature rise of the delay unit 110 and is decreased to compensate for a temperature drop of the delay unit 110 .

[0077] exist Figure 3 , the example error amplifier 108 includes a first resistor 214, a second capacitor 216, a differential difference amplifier 312, and a second resistor 220. Collectively, the first resistor 214, the second capacitor 216, the differential difference amplifier 312, and the second resistor 220 generate a control signal V at an output 322 based on one or more inputs from the example power stage 104 and the reference voltage generator 106. ERROR The error amplifier 108 monitors the output voltage node V of the power stage 104 via the voltage divider 117. O The output voltage level at the feedback voltage signal V FB In the example, the first resistor 214, the second capacitor 216, and the second resistor 220 are a differential difference amplifier feedback network that sets the gain of the error amplifier 108 so that the error amplifier 108 can control the power stage 104 to generate a voltage at the output voltage node V O The desired output voltage level (e.g., corresponding to V SETDuring steady-state operation, if the output voltage node V O The output voltage signal at the output voltage deviates from the desired level (for example, if the feedback voltage signal V FB Increase and / or decrease to above normal operating levels during transients), the differential amplifier feedback network (e.g., first resistor 214, second capacitor 216, and second resistor 220) causes the differential amplifier 312 to generate a control signal V at the output 322. ERROR The delay unit 110 is configured to adjust the duration of the delay of each delay unit included in the delay unit 110. For example, the differential difference amplifier 312 determines the difference between the voltage level at the first non-inverting input terminal 314 and the voltage level at the first inverting input terminal 316. After determining the difference between the voltage level at the first non-inverting input terminal 314 and the voltage level at the first inverting input terminal 316, the differential difference amplifier 312 multiplies the gain of the differential difference amplifier feedback network (e.g., the gain of the feedback network coupled between the second non-inverting input terminal 318, the second inverting input terminal 320, and the output terminal 322) by the difference between the voltage level at the first non-inverting input terminal 314 and the voltage level at the first inverting input terminal 316.

[0078] exist Figure 3 In the example, the example delay unit 110 includes a plurality of example delay units to generate a PWM signal. In the example of this article, the delay unit 110 generates a PWM signal by IN , the signal generated by the oscillator 112 and the first voltage signal V SOFT One or more of the delay cells 110 (e.g., more generally, the output of the ADC 114) introduce a delay to the example oscillator signal to generate a PWM signal. The delay cells 110 are used to adjust the duty cycle of the PWM signal to the power stage 104 to provide power to the example load 136. For example, the output of the ADC 114 determines the number of delay cells 110 that are selected (e.g., enabled). The duty cycle of the PWM signal corresponds to the number of delay cells 110 that are enabled multiplied by the duration of each delay cell 110. Figure 3 , the duration of each delay cell in delay cells 110 is determined based on the control signal generated by error amplifier 108. For example, a higher voltage level on the control signal corresponds to a longer duration of each delay cell 110, while a lower voltage level on the control signal corresponds to a shorter duration of each delay cell 110.

[0079] exist Figure 3 In the example, the oscillator 112 is a phase-locked loop oscillator. In other examples, the oscillator 112 is a capacitor (RC) oscillator, a ring oscillator, a crystal oscillator, or any other suitable oscillator for the application. The example oscillator 112 generates an oscillation signal. Figure 3 In the example, the oscillating signal can be a periodic and / or non-periodic signal generated to initiate the generation of the PWM signal and / or otherwise set the frequency of operation of the delay unit 110. For example, when the oscillator 112 outputs the oscillating signal, the delay unit 110 generates a corresponding rising edge on the PWM signal when the oscillating signal is at a falling edge. In such an example, the PWM signal remains at a logic high value for a delay duration associated with the number of active delay units 110. The number of active delay units 110 is indicated by the example ADC 114.

[0080] exist Figure 3 In the example ADC 114, the current analog-to-digital converter is a current analog-to-digital converter. The ADC 114 converts the analog current level into a digital output (e.g., a binary count value). For example, the example ADC 114 converts the analog current level into an eight-bit binary signal to indicate the number of delay cells 110 to be activated. In other examples herein, the ADC 114 may be any other suitable decoder that indicates the number of delay cells 110 to be activated.

[0081] exist Figure 3 In FIG. 1 , the example feed-forward voltage controller 116 is an analog multiplier. The example feed-forward voltage controller 116 generates an analog current signal for use by the ADC 114. For example, the feed-forward voltage controller 116 generates an analog current signal based on the first voltage signal V SOFT 、Input voltage signal V IN , one or more of the frequencies of the oscillator signals generated by the oscillator 112, and one or more constants corresponding to the scaling factors generate an analog current signal. The scaling factors are suitable for the design of the controller 102. For example, the scaling factors are related to the duration of each delay unit 110. The example feed-forward voltage controller 116 sets the number of delay units 110 to be activated via the ADC 114. In this way, the example feed-forward voltage controller 116 sets the delay (e.g., duration) of the pulse width of the PWM signal generated by the delay unit 110 via the ADC 114 by setting the number of delay units 110 to be activated. In this way, the delay unit 110 generates a PWM signal by introducing a delay to the example oscillator signal, the delay being based on the output of the feed-forward voltage controller 116 (e.g., based on the input voltage V IN , the signal generated by the oscillator 112 and the first voltage signal V SOFT ).

[0082] exist Figure 3 , the example voltage divider 117 is a resistor divider network that allows the output voltage node V OThe voltage level at φ is measured and / or otherwise monitored by the differential difference amplifier 312 and / or, more generally, by the error amplifier 108 without the possibility of damaging the differential difference amplifier 312 and / or, more generally, the error amplifier 108 .

[0083] exist Figure 3 In FIG, the trigger 302 is a Schmitt trigger, including a first input terminal 304, a second input terminal 306 and an output terminal 308. Figure 3 , the trigger 302 compares the first voltage signal V received at the first input terminal 304 with the first voltage signal V SOFT and the feedback voltage signal V received at the second input terminal 306 FB , and determine the first voltage signal V SOFT Is the amplitude of the feedback voltage signal V FB For example, the threshold voltage corresponds to the first voltage signal V based on the application SOFT The amplitude of the feedback voltage signal V FB The example trigger 302 is also based on the first voltage signal V SOFT and feedback voltage signal V FB The comparison of configures one or more of the fourth switch 132, the fifth switch 134 or the eighth switch 310 via a control signal generated at the output 308. Figure 3 , the example flip-flop 302 configures one or more of the fourth switch 132 , the fifth switch 134 , or the eighth switch 310 via a control signal generated at the output 308 at the start of operation of the controller 102 .

[0084] exist Figure 3 , latch 125 is a device that holds a logic value at an output of latch 125 that corresponds to a logic value received at an input of latch 125. For example, latch 125 is an SR latch. In other examples, latch 125 is a D flip-flop, a JK latch, a gated SR latch, a gated JK latch, a gated D flip-flop, an Earle latch, or any other suitable latch.

[0085] exist Figure 3 In FIG, each of the fourth switch 132, the fifth switch 134, the sixth switch 202, and the seventh switch 204 can be implemented by a transistor. For example, each of the fourth switch 132, the fifth switch 134, and the sixth switch 202 is an n-channel MOSFET. Figure 3, the seventh switch 204 is a p-channel MOSFET. In other examples, the fourth and fifth switches 132, 134, the sixth and seventh switches 202, 204 are BJTs, JFETs, HBTs, any suitable transistors for the application, and / or any combination thereof. Although one or more of the fourth and fifth switches 132, 134 may be implemented using many combinations of BJTs, JFETs, HBTs, or any suitable transistors, it may be desirable to implement each of the fourth and fifth switches 132, 134 with the same switch type in a particular controller (e.g., all n-type BJTs, all p-type BJTs, all p-channel MOSFETs, etc.). Figure 3 In the embodiment of the present invention, the eighth switch 310 is a two-to-one multiplexer. In other examples, the eighth switch 310 is a combination of logic circuits.

[0086] exist Figure 2 In the embodiment, the third inverter 135 is a device that inverts the logic value received at the input of the third inverter 135 and outputs the inverted logic value at the output of the third inverter 135. An example of the third inverter 135 is a NOT logic gate. In another example, the third inverter 135 can be a combination of one or more logic gates / logic circuits that invert the logic value of the received signal and output the inverted logic value. In an analog embodiment, the third inverter 135 can be an inverting amplifier.

[0087] exist Figure 3 In operation, the example flip-flop 302 configures the error amplifier as a voltage follower, wherein the trimming voltage signal V TON As an input to the second non-inverting input terminal 318 and the second inverting input terminal 320 via the second resistor 220. For example, the example flip-flop 302 configures the fourth switch 132, the fifth switch 134, and the eighth switch 310 to configure the error amplifier 108 to operate as a voltage follower. More specifically, the example flip-flop 302 closes the fourth switch 132, opens the fifth switch 134, and switches the eighth switch 310 so that the second terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. By configuring one or more of the fourth switch 132, the fifth switch 134, or the eighth switch 310, the flip-flop 302 generates a voltage signal based on the feedback voltage signal V FB The error amplifier 108 is disabled to control the duration of each delay unit in the delay unit 110. In contrast, by configuring one or more of the fourth switch 132, the fifth switch 134, or the eighth switch 310, the trigger 302 enables the error amplifier 108 to adjust the voltage signal V TON The duration of each delay unit in the delay unit 110 is controlled. In addition, the example feed-forward voltage controller 116 is based on the first voltage signal V SOFT Divide by the input voltage signal VIN The output of the delay unit 110 (e.g., the PWM signal on-time) is set by multiplying the period of the oscillator 112. Furthermore, by configuring one or more of the fourth switch 132, the fifth switch 134, or the eighth switch 310, the example flip-flop 302 disables the PWM signal of the delay unit 110 by disconnecting the oscillator 112 from the delay unit 110.

[0088] exist Figure 3 In operation, the trigger 302 monitors the first voltage signal V SOFT To determine the first voltage signal V SOFT Whether the soft start function has been started. For example, the trigger 302 monitors the first voltage signal V SOFT And when the trigger 302 detects the first voltage signal V SOFT When the voltage on the SOFT The soft start function has been started. When the example trigger 302 determines that the first voltage signal V SOFT The soft start function has been started (for example, the first voltage signal V SOFT When the feedback voltage signal V FB and the first voltage signal V SOFT To determine the first voltage signal V SOFT Is the feedback voltage signal V FB within the threshold difference.

[0089] exist Figure 3 In operation, when the example trigger 302 determines the first voltage signal V SOFT The feedback voltage signal V FB When the threshold difference is within the threshold, the example trigger 302 enables the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT To control the power stage 104. For example, when the example trigger 302 determines that the first voltage signal V SOFT The feedback voltage signal V FB , the example trigger 302 configures one or more of the fourth switch 132, the fifth switch 134, or the eighth switch 310. More specifically, when the example trigger 302 determines that the first voltage signal V SOFT The feedback voltage signal V FBWhen the error amplifier 108 is within the threshold difference of the feedback voltage signal V, the example trigger 302 opens the fourth switch 132, closes the fifth switch 134, and switches the eighth switch 310 so that the first terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. By configuring one or more of the fourth switch 132, the fifth switch 134, or the eighth switch 310, the trigger 302 enables the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V. FB and the first voltage signal V SOFT The duration of each delay unit in the delay unit 110 is controlled. In addition, the example flip-flop 302 enables the PWM signal of the delay unit 110 by configuring (eg, opening and / or closing) one or more of the fourth switch 132 , the fifth switch 134 , and the eighth switch 310 .

[0090] Figure 4 It shows Figure 1 An example of a feed-forward voltage controller 116, Figure 2 An example feed-forward voltage controller 116 and / or Figure 3 A schematic diagram of an example feed-forward voltage controller 116 is provided with further details. Figure 4 , the example feed-forward voltage controller 116 includes an example third resistor 402, an example fourth resistor 404, an example first voltage-controlled current source 406, an example voltage supply node 408, an example frequency-to-current converter, an example fifth resistor 412, an example sixth resistor 414, an example second voltage-controlled current source 416, an example current multiplier 418, an example seventh resistor 420, an example third voltage-controlled current source 422, and an example ground reference node 210.

[0091] exist Figure 4 , a third resistor 402 is coupled to the example power supply 138, a fourth resistor 404, and a first voltage-controlled current source 406. The example fourth resistor 404 is coupled to the third resistor 402, the first voltage-controlled current source 406, and the ground reference node 210. The example third resistor 402 and the example fourth resistor 404 together form a voltage divider to step down the voltage level of the power supply 138 (e.g., the input voltage signal VIN) to a voltage level that is safe for the first voltage-controlled current source 406.

[0092] exist Figure 4 , a first voltage-controlled current source 406 is coupled to the third resistor 402, the fourth resistor 404, the voltage supply node 408, the ground reference node 210, and the current multiplier 418. The example first voltage-controlled current source 406 is a device that generates a current proportional to a voltage set by a voltage divider (e.g., the third resistor 402 and the fourth resistor 404) and corresponding to an input voltage signal V IN The current I VINFor example, the first voltage-controlled current source 406 can be implemented by a buffer amplifier coupled to a BJT transistor. For example, in operation of such an embodiment, the voltage level set by the voltage divider (e.g., the third resistor 402 and the fourth resistor 404) is input to the buffer amplifier, and the example buffer amplifier biases the base of the BJT with a current necessary to induce the voltage level set by the voltage divider across the resistor included in the first voltage-controlled current source 406. In such an embodiment, the collector of the BJT is coupled to the voltage supply node 408 via the resistor and the voltage supply signal V generated at the voltage supply node 408 is DD Current is supplied to the collector of the BJT. The emitter of the BJT supplies current, which induces a voltage level across the resistor set by the voltage divider. The current supplied by the emitter of the BJT, I VIN is sent to the current multiplier 418 .

[0093] exist Figure 4 In FIG. 4 , an example frequency-to-current converter 410 is coupled to the example oscillator 112, the example voltage supply node 408, the example ground reference node 210, and the example current multiplier 418. The example frequency-to-current converter 410 converts and generates a current I proportional to the frequency of the oscillator signal generated by the oscillator 112. OSC For example, the frequency-to-current converter 410 can be implemented as a resistor-inductor (RL) filter. In such an embodiment, the current output to the current multiplier 418 is controlled by the gain (e.g., transfer function) of the RL filter. The gain of the example RL filter is related to the frequency of the input signal (e.g., the oscillator signal generated by the oscillator 112). Therefore, the current I output from the frequency-to-current converter 410 to the current multiplier 418 is OSC The gain of the frequency-to-current converter 410 is related to the frequency of the oscillator signal generated by the oscillator 112 .

[0094] exist Figure 4 , the fifth resistor 412 is coupled to the example reference voltage generator 106, the sixth resistor 414, and the second voltage-controlled current source 416. The example fifth resistor 412 is coupled to the sixth resistor 414, the second voltage-controlled current source 416, and the ground reference node 210. The example fifth resistor 412 and the example sixth resistor 414 together form a voltage divider to divide the voltage level of the reference voltage generator 106 (e.g., the first voltage signal V SOFT ) gradually decreases to a voltage level that is safe for the second voltage-controlled current source 416.

[0095] exist Figure 4, a second voltage-controlled current source 416 is coupled to the fifth resistor 412, the sixth resistor 414, the voltage supply node 408, the ground reference node 210, and the current multiplier 418. The example second voltage-controlled current source 416 is a device that generates a current proportional to the voltage set by the voltage divider (e.g., the fifth resistor 412 and the sixth resistor 414) and corresponding to the first voltage signal V SOFT The current I VSOFT For example, the second voltage-controlled current source 416 can be implemented by a buffer amplifier coupled to a BJT transistor. For example, in operation of such an embodiment, the voltage level set by the voltage divider (e.g., the fifth resistor 412 and the sixth resistor 414) is input to the buffer amplifier, and the example buffer amplifier biases the base of the BJT with a current necessary to induce the voltage level set by the voltage divider across the resistor included in the second voltage-controlled current source 416. In such an embodiment, the collector of the BJT is coupled to the voltage supply node 408 via a resistor and the voltage supply signal V generated at the voltage supply node 408 is DD Current is supplied to the collector of the BJT. The emitter of the BJT supplies current, which induces a voltage level across the resistor set by the voltage divider. The current supplied by the emitter of the BJT, I VSOFT is sent to the current multiplier 418 .

[0096] exist Figure 4 , the example current multiplier 418 is coupled to the first voltage-controlled current source 406, the frequency-to-current converter 410, the second voltage-controlled current source 416, the ground reference node 210, and to the third voltage-controlled current source 422 via the seventh resistor 420. The example current multiplier 418 multiplies the current I provided by the first voltage-controlled current source 406 by VIN The current I provided by the frequency-to-current converter 410 OSC and the current I provided by the second voltage-controlled current source 416 VSOFT For example, the current multiplier 418 can be implemented by one or more cascaded current mirrors. The example current multiplier 418 multiplies the current I provided by the first voltage-controlled current source 406 by VIN , the current I provided by the frequency-to-current converter 410 OSC and the current I provided by the second voltage-controlled current source 416 VSOFT Multiply to generate the output current I according to the following formula 1 OUT :

[0097] Formula-1

[0098]

[0099] exist Figure 4 In Equation 1, the current I VSOFT Current IOSC Current I VIN and the scaling factor k. Figure 4 The scaling factor is related to the duration of each delay unit 110. The resulting output current I OUT The voltage is provided to the third voltage-controlled current source 422 via the seventh resistor 420 .

[0100] exist Figure 4 In FIG. 4 , the second voltage-controlled current source 416 is coupled to the current multiplier 418, to the voltage supply node 408, to the ground reference node 210, and to the ADC 114 via the seventh resistor 420. The example third voltage-controlled current source 422 is a circuit that generates a current I OUT The voltage drop across the seventh resistor 420 causes a current I ON For example, the third voltage-controlled current source 422 can be implemented by a buffer amplifier coupled to a BJT transistor. For example, in operation of such an embodiment, a voltage level set by the voltage drop across the seventh resistor 420 is input to the buffer amplifier, and the exemplary buffer amplifier biases the base of the BJT with the current required to induce the voltage level set by the voltage drop across the seventh resistor 420 across the resistor included in the third voltage-controlled current source 422. In such an embodiment, the collector of the BJT is coupled to the voltage supply node 408 via a resistor, and the voltage supply signal V generated at the voltage supply node 408 is DD Current is supplied to the collector of the BJT. The emitter of the BJT supplies current, which induces a voltage level across the resistor set by the voltage divider. The current supplied by the emitter of the BJT, I ON is transmitted to ADC 114.

[0101] Figure 5 It shows Figure 1 An example reference voltage generator 106, Figure 2 An example reference voltage generator 106 and / or Figure 3 FIG2 is a schematic diagram illustrating further details of an example reference voltage generator 106. The example reference voltage generator 106 includes an example bandgap voltage source 502, an example first voltage amplifier 504, an example second voltage amplifier 506, an example digital-to-analog converter 508, an example comparator 510 including an input 512, an input 514, and an output 516, an example oscillator 518, and an example voltage supply node 408.

[0102] exist Figure 5 In FIG, a bandgap voltage source 502 is coupled to a voltage supply node 408, a first voltage amplifier 504, and a second voltage amplifier 506. Figure 5In FIG. 5 , the bandgap voltage source 502 is a circuit that generates a signal having a voltage level (e.g., 1.25 volts) independent of operating temperature and voltage supply variations. In addition, the example bandgap voltage source 502 is configured to generate a current I that is inversely proportional to the temperature of the reference voltage generator 106. INVERSE In this way, as the temperature of the reference voltage generator 106 increases, the current I INVERSE decreases and as the temperature of the reference voltage generator 106 decreases, the current I INVERSE For example, the bandgap voltage source 502 can be implemented by a Brokaw bandgap circuit. In other examples, the bandgap voltage source 502 can be a circuit that generates a bandgap reference voltage and a current I INVERSE any circuit.

[0103] exist Figure 5 , the example first voltage amplifier 504 is coupled to the bandgap voltage source 502, the first terminal of the second switch 128, the second resistor 220, and the second non-inverting input 318 of the differential amplifier 312. The example first voltage amplifier 504 is configured to generate a differential signal based on the current I INVERSE Generate fine-tuning voltage signal V TON For example, the first voltage amplifier 504 can be implemented by a transimpedance amplifier. In other examples, the example first voltage amplifier 504 can be implemented by any suitable amplifier. In the example, the second voltage amplifier 506 is coupled to the bandgap voltage source 502 and the digital-to-analog converter 508. The example second voltage amplifier 506 is a device configured to generate a signal having an arbitrary voltage level, which is set to be greater than the voltage level that can be used as V via the voltage input terminal 140. SET The second voltage amplifier 506 can be implemented as a non-inverting amplifier. In other examples, the second voltage amplifier 506 can be implemented as any suitable amplifier.

[0104] exist Figure 5 In the example, the digital-to-analog converter 508 is coupled to the second voltage amplifier 506, the second input 514 of the comparator 510, the oscillator 518, the feedforward voltage controller 116, the second input 122 of the comparator 118, the second input 122 of the comparator 118, the first terminal of the third switch 130, and the first input 304 of the flip-flop 302. The example digital-to-analog converter 508 is a device that samples the input voltage at a specified frequency. For example, the digital-to-analog converter 508 can be implemented as a 12-bit digital-to-analog converter. In other examples, any suitable digital-to-analog converter can be used.

[0105] exist Figure 5In FIG, an example comparator 510 is coupled to the voltage input 140 at a first input 512, to the digital-to-analog converter 508 at a second input 514, and to the oscillator 518 at an output 516. The example comparator 510 is an analog comparator including the first input 512, the second input 514, and the output 516. Figure 5 In the embodiment, the comparator 510 compares the voltage signal generated by the DAC 508 with the voltage received from the voltage input terminal (eg, V SET signal), and determines whether the amplitude of the voltage signal received from the digital-to-analog converter 508 is within V SET For example, the threshold voltage corresponds to the magnitude of the voltage signal generated by the digital-to-analog converter 508 being within a threshold value based on the applied V SET When the comparator 510 determines that the voltage signal generated by the digital-to-analog converter 508 is within V SET When the ΔV signal is within the threshold voltage of the ΔV signal, the comparator 510 generates a control signal at the output 516 .

[0106] exist Figure 5 In the example oscillator 518, the example oscillator 518 is coupled to the example digital-to-analog converter 508 and the example comparator 510 at the output terminal 516. The example oscillator 518 can be implemented by a phase-locked loop oscillator. In other examples, the oscillator 518 is a capacitor (RC) oscillator, a ring oscillator, a crystal oscillator, or any other suitable oscillator for the application. The example oscillator 518 generates an oscillation signal. Figure 5 In the example embodiment, the oscillating signal may be a periodic and / or non-periodic signal generated to initiate sampling by the digital-to-analog converter 508. Furthermore, the example oscillator 518 includes functionality to be enabled and disabled.

[0107] exist Figure 5 In the example DAC 508, the voltage level of the voltage signal generated by the second voltage amplifier 506 is sampled at the frequency of the oscillator 518 (e.g., at the rising edge of the signal generated by the oscillator 518). Because the DAC 508 samples the voltage signal generated by the second voltage amplifier 506, the voltage level of the signal is generated by the DAC 508. Therefore, when the DAC 508 samples the signal generated by the second voltage amplifier 506, the voltage level at the second input 514 slowly increases to the voltage level of the signal generated by the second voltage amplifier 506 at the frequency of the oscillator 518. When the comparator 510 determines the voltage level at the first input 512 (e.g., V SET The voltage level of the signal) at the second input terminal 514 (eg, the first voltage signal V SOFT), the comparator 510 generates a control signal at the output 516 to disable the oscillator 518. In some examples, when the comparator 510 generates the control signal at the output 516, the comparator 510 additionally transmits the control signal to the switch, which converts the first voltage signal V SOFT The voltage level on the DAC 508 is switched from the voltage level at the output of the DAC 508 to V SET The voltage level of the signal.

[0108] Figure 6 It is an icon Figure 1 Example power converter system 100, Figure 2 Example power converter system 200 and / or Figure 3 6. A timing diagram 600 of the operation of an example power converter system 300 is shown. The timing diagram 600 includes an example first graph 602, an example second graph 604, an example third graph 606, an example fourth graph 608, an example first time 610 (T1), and an example second time 612 (T2). The example first graph 602 includes an example latch output graph 614. The example second graph 604 includes an example error amplifier output graph 616, and the example third graph 606 includes an example feedback voltage graph 618 and an example soft start graph 620. The example fourth graph 608 includes an example first non-inverting input graph 622, an example first inverting input graph 624, an example second non-inverting input graph 626, and an example second inverting input graph 628.

[0109] exist Figure 6 , a first graph 602 illustrates the output of an example latch 125 controlled by the output 124 of the example comparator 118 and / or the output 308 of the example flip-flop 302 versus time. In this example, a latch output graph 614 represents the analog voltage generated by the latch 125, which is controlled by the output 124 of the comparator 118 and / or the output 308 of the flip-flop 302. An example second graph 604 illustrates the output of the error amplifier 108 versus time. An example error amplifier output graph 616 illustrates the output of the error amplifier 108 controlled by the output 226 of the operational amplifier 218 and / or the output 308 of the example flip-flop 302. Figure 3 The voltage level at the output of the error amplifier 108 is dominated by the output 322 of the differential amplifier 312. The example third graph 606 shows the relationship between various voltages in the controller 102 and time. The example feedback voltage curve 618 shows the voltage level at the output of the error amplifier 108 at the output voltage node V of the power stage 104 by the error amplifier 108 via the voltage divider 117. O The feedback voltage signal V FB The example soft start curve 620 represents the first voltage signal V generated by the reference voltage generator 106. SOFTAn example first non-inverting input curve 622 represents the voltage level at the first non-inverting input 314 of the differential difference amplifier 312. An example first inverting input curve 624 represents the voltage level at the first inverting input 316 of the differential difference amplifier 312. An example second non-inverting input curve 626 represents the voltage level at the second non-inverting input 318 of the differential difference amplifier 312. An example second inverting input curve 628 represents the voltage level at the second inverting input 320 of the differential difference amplifier 312.

[0110] exist Figure 6 , the first time 610 represents the start-up of one or more of the power converter system 100, the power converter system 200, or the power converter system 300. For example, the first time 610 may represent that a power source is connected to the controller 102. In other examples, the first time 610 represents that the controller 102 receives an enable signal. At the first time 610, the value of the latch output curve 614 is 0 volts, the value of the error amplifier output curve 616 is 1.03 volts, the value of the feedback voltage curve 618 is 40 millivolts (mV), and the value of the soft start curve 620 is zero mV. Additionally, at the first time 610, the value of the first non-inverting input curve 622 is 40 mV, the value of the first inverting input curve 624 is 40 mV, the value of the second non-inverting input curve 626 is 20 mV, and the value of the second inverting input curve 628 is zero mV. Figure 1 At a first time 610, the comparator 118 opens the first switch 126, closes the second switch 128, opens the third switch 130, closes the fourth switch 132, and opens the fifth switch 134. Figure 2 At a first time 610, the comparator 118 opens the first switch 126, closes the second switch 128, opens the third switch 130, closes the fourth switch 132, and opens the fifth switch 134. Figure 3 In the embodiment of the present invention, at the first time 610, the trigger 302 closes the fourth switch 132, opens the fifth switch 134, and configures the eighth switch 310 so that the second terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. At the first time 610, the comparator 118 and / or the trigger 302 closes and / or opens one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, or the eighth switch 134 to configure the error amplifier 108 to adjust the voltage based on the trim voltage signal V TON In an alternative example, the comparator 118 closes and / or opens one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134 to configure the error amplifier 108 to adjust the voltage signal VTON The duration of each delay unit in the delay unit 110 is controlled. In addition, at the example first time 610, the example feed-forward voltage controller 116 controls the time of each delay unit in the delay unit 110 based on the first voltage signal V SOFT Divide by the input voltage signal V IN The output (e.g., PWM signal) of the delay unit 110 is set by multiplying the period of the oscillator 112. In addition, the example comparator 118 and / or the flip-flop 302 disables the PWM signal in the delay unit 110 by configuring one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, or the eighth switch 310.

[0111] exist Figure 6 In the process, between the first time 610 and the second time 612, the reference voltage generator 106 starts to convert the first voltage signal V SOFT Ramp up from zero to the output voltage node V corresponding to the power stage 104 O The desired voltage on the SET Between the first time 610 and the second time 612, the latch output curve 614 remains at zero volts, the error amplifier output curve 616 remains at 1.03 volts, the feedback voltage curve 618 remains at 40 mV, and the soft start curve 620 begins to rise to a value corresponding to the output voltage node V O Furthermore, between the first time 610 and the second time 612, the first non-inverting input curve 622 remains at a value of 40 mV, the first inverting input curve 624 remains at a value of 40 mV, the second non-inverting input curve 626 remains at a value of 20 mV, and the second inverting input curve 628 begins to rise to the voltage level at the second non-inverting input terminal 318 of the differential difference amplifier 312.

[0112] exist Figure 6 The second time 612 represents the feedback voltage signal V FB Equal to the first voltage signal V SOFT At the second time 612, the latch output curve 614 transitions from 0 volts to 4.6 volts, the error amplifier output curve 616 transitions from a constant voltage of 1.03 volts to a voltage that depends on the gain of the error amplifier feedback network of the error amplifier 108, the feedback voltage curve 618 is at a value of 40 mV, and the soft start curve 620 is at a value greater than or equal to 40 mV. In addition, at the second time 612, the value of the first non-inverting input curve 622 is 40 mV, the value of the first inverting input curve 624 is 40 mV, the value of the second non-inverting input curve 626 is 20 mV, and the value of the second inverting input curve 628 is 20 mV. Figure 1At the second time 612, the example comparator 118 closes the first switch 126, opens the second switch 128, closes the third switch 130, opens the fourth switch 132, and closes the fifth switch 134. Figure 2 At the second time 612, the example comparator 118 closes the first switch 126, opens the second switch 128, closes the third switch 130, opens the fourth switch 132, and closes the fifth switch 134. Figure 3 In the example, at the second time 612, the trigger 302 opens the fourth switch 132, closes the fifth switch 134, and switches the eighth switch 310 so that the first terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. At the second time 612, the comparator 118 and / or the trigger 302 closes and / or opens one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, or the eighth switch 310 to enable the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT In an alternative example, the comparator 118 closes and / or opens one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the fifth switch 134 to configure the error amplifier 108 to output the current based on the feedback voltage signal V FB and the first voltage signal V SOFT The duration of each delay cell in the delay cell 110 is controlled. Furthermore, the example comparator 118 and / or the example flip-flop 302 enable the PWM signal of the delay cell 110 by configuring one or more of the first switch 126 , the second switch 128 , the third switch 130 , the fourth switch 132 , and the fifth switch 134 .

[0113] exist Figure 6 In the example, after the second time 612, the example latch output curve 614 remains at 4.6 volts, the example error amplifier output curve 616 continues to depend on the gain of the error amplifier feedback network of the error amplifier 108, and the example feedback voltage curve 618 is about the first voltage signal V SOFT The voltage level of the power stage 104 changes slightly, and the example soft start curve 620 continues to ramp up to the output voltage node V corresponding to the power stage 104. O The desired voltage at SET In addition, after the second time 612, the first non-inverting input curve 622 is at the first voltage signal V SOFT The first inverting input curve 624 continues to ramp up to a voltage corresponding to the output voltage node V OThe desired voltage level at SET The second non-inverting input curve 626 is kept at a value of 20 mV, and the second inverting input curve 628 is kept at a value of 20 mV at the fine-tuning voltage signal V TON The voltage level of Figure 6 , a difference between the voltage levels of the first non-inverting input curve 622 and the first inverting input curve 624 is substantially similar to a difference between the voltage levels of the second non-inverting input curve 626 and the second inverting input curve 628 .

[0114] Figure 7 It is an icon Figure 1 Example power converter system 100, Figure 2 Example power converter system 200 and / or Figure 3 1 and 2. A timing diagram 700 is provided for additional operation of the example power converter system 300. The timing diagram 700 includes an example fifth graph 702, an example sixth graph 704, an example first time 610 (T1), and an example second time 612 (T2). The example fifth graph 702 includes an example output voltage curve 706. The example sixth graph 704 includes an example converter current curve 708.

[0115] exist Figure 7 , the fifth graph 702 illustrates the output voltage node V of the power stage 104. O In this example, the output voltage curve 706 represents the output voltage node V of the power stage 104. O The example sixth graph 704 illustrates the current I through the inductor 206. SW The example converter current curve 708 illustrates the relationship between the Figure 2 and 3 The current I of the inductor 206 SW In other examples, the example converter current curve 708 represents the current flowing through Figure 1 The current of the power stage 104.

[0116] exist Figure 7 , first time 610 represents the start-up of one or more of power converter system 100, power converter system 200, or power converter system 300. For example, first time 610 may represent the power source being connected to controller 102. In other examples, first time 610 represents controller 102 receiving an enable signal. At first time 610, output voltage curve 706 is at a value of 200 mV and converter current curve 708 is at a value of zero amperes. Figure 1At a first time 610, the comparator 118 opens the first switch 126, closes the second switch 128, opens the third switch 130, closes the fourth switch 132, and opens the fifth switch 134. Figure 2 At a first time 610, the comparator 118 opens the first switch 126, closes the second switch 128, opens the third switch 130, closes the fourth switch 132, and opens the fifth switch 134. Figure 3 In the embodiment of the present invention, at the first time 610, the comparator 118 closes the fourth switch 132, opens the fifth switch 134, and configures the eighth switch 310 so that the second terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. At the first time 610, the comparator 118 and / or the trigger 302 closes and / or opens one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, or the eighth switch 134 to configure the error amplifier 108 to respond to the trim voltage signal V TON The duration of each delay unit in the delay unit 110 is controlled. In addition, at the example first time 610, the example feed-forward voltage controller 116 sets the output (eg, PWM signal) of the delay unit 110 to track the voltage signal V divided by the input voltage signal V IN and multiplying the first voltage signal V by the period of the oscillator 112 SOFT Furthermore, the example comparator 118 and / or the example flip-flop 302 disables the PWM signal in the delay unit 110 by configuring one or more of the first switch 126 , the second switch 128 , the third switch 130 , the fourth switch 132 , the fifth switch 134 , or the eighth switch 310 .

[0117] exist Figure 7 In the process, between the first time 610 and the second time 612, the reference voltage generator 106 starts to convert the first voltage signal V SOFT Ramp up from zero to the output voltage node V corresponding to the power stage 104 O Between the first time 610 and the second time 612, the output voltage curve 706 remains at 200 mV and the converter current curve 708 remains at a value of zero amperes.

[0118] exist Figure 7 The second time 612 represents the feedback voltage signal V FB Equal to the first voltage signal V SOFT At the second time 612, the output voltage curve 706 changes with the output voltage node V of the power stage 104. O The output voltage level at starts to rise, and the converter current curve 708 starts to rise and then falls as the magnetic field of the inductor 206 charges and discharges. Figure 1At the second time 612, the example comparator 118 closes the first switch 126, opens the second switch 128, closes the third switch 130, opens the fourth switch 132, and closes the fifth switch 134. Figure 2 At the second time 612, the example comparator 118 closes the first switch 126, opens the second switch 128, closes the third switch 130, opens the fourth switch 132, and closes the fifth switch 134. Figure 3 In the example, at the second time 612, the trigger 302 opens the fourth switch 132, closes the fifth switch 134, and switches the eighth switch 310 so that the first terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. At the second time 612, the comparator 118 and / or the trigger 302 closes and / or opens one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, the fifth switch 134, or the eighth switch 310 to enable the error amplifier 108 to generate a voltage signal based on the feedback voltage signal V FB and the first voltage signal V SOFT The duration of each delay cell in the delay cell 110 is controlled. Furthermore, the example comparator 118 and / or the example flip-flop 302 enable the PWM signal of the delay cell 110 by configuring one or more of the first switch 126 , the second switch 128 , the third switch 130 , the fourth switch 132 , and the fifth switch 134 .

[0119] exist Figure 7 , after the second time 612 , the example output voltage curve 706 continues to rise and the example converter current curve 708 continues to rise and then falls while trending toward a higher current value.

[0120] Figure 8 It is an icon Figure 1 An example reference voltage generator 106, Figure 2 An example reference voltage generator 106 and / or Figure 3 8. The example timing diagram 800 illustrates an example seventh graph 802, an example eighth graph 804, an example ninth graph 806, an example tenth graph 808, an example eleventh graph 810, an example third time 812 (T3), and an example fourth time 814 (T4).

[0121] exist Figure 8 , the seventh graph 802 includes an example supply voltage curve 816 , the eighth graph 804 includes an example set voltage curve 818 , the ninth graph 806 includes an example soft start curve 820 , the tenth graph 808 includes an example oscillator curve 822 , and the eleventh graph 810 includes an example comparator output curve 824 .

[0122] exist Figure 8 , the seventh graph 802 illustrates the voltage supply signal V generated at the voltage supply node 408. DD The example power supply voltage curve 816 represents the voltage supply signal V DD The example eighth graph 804 illustrates the voltage level at the voltage input 140 versus time. The example set voltage graph 818 illustrates the voltage level at the voltage input 140 versus time. SET The example ninth graph 806 illustrates the voltage level of the digital-to-analog converter 508 versus time. The example soft start graph 820 illustrates the first voltage signal V generated by the digital-to-analog converter 508. SOFT Example tenth graph 808 illustrates the frequency of oscillator 518 versus time. Example oscillator graph 822 illustrates the oscillator signal generated by oscillator 518. Example eleventh graph 810 illustrates the logic value of output 516 of comparator 510 versus time. Example comparator output graph 824 illustrates the logic value generated at output 516.

[0123] exist Figure 8 In the embodiment, the third time 812 represents the start-up of one or more of the power converter system 100, the power converter system 200, or the power converter system 300. For example, the third time 812 may represent the start-up of the power supply connected to the controller 102 (e.g., the power supply voltage signal V DD At a third time 812, the value of the power supply voltage curve 816 is 3.3 V, the value of the set voltage curve 818 is 1.5 V, the value of the soft start curve 820 is 0 volts, the oscillator curve 822 is at a logic low value, and the comparator output curve 824 is at a logic low value.

[0124] exist Figure 8 In the process, between the third time 812 and the fourth time 814, the first voltage signal V SOFT Rising to V SET Between the third time 812 and the fourth time 814, the supply voltage curve 816 remains at a value of 3.3V, the set voltage curve 818 remains at a value of 1.5V, the soft start curve 820 begins to rise incrementally from zero volts to 1.5V (e.g., at the rising edge of the oscillator curve 822), the oscillator curve 822 begins to oscillate at the frequency of the oscillator 518, and the comparator output curve 824 remains at a logic low value.

[0125] exist Figure 8In the example, the fourth time 814 indicates that the soft start voltage level of one or more of the power converter system 100, the power converter system 200, or the power converter system 300 meets the preset or desired voltage level (eg, V SET At the fourth time 814, the value of the power supply voltage curve 816 is 3.3V, the value of the set voltage curve 818 is 1.5V, the value of the soft start curve 820 is 1.5V, the oscillator curve 822 is at a logic high value (e.g., a rising edge), and the comparator output curve 824 changes from a logic low value to a logic high value. Figure 5 , at a fourth time 814, the voltage level generated by the digital-to-analog converter 508 is substantially similar to the voltage level at the voltage input 140. At the fourth time 814, the example comparator 510 generates a logic high value at the output 516 to disable the oscillator 518.

[0126] exist Figure 8 , after the fourth time 814, the power supply voltage curve 816 remains at a value of 3.3V, the set voltage curve 818 remains at a value of 1.5V, the soft start curve 820 remains at a value of 1.5V, the oscillator curve 822 transitions from a logic high value to a logic low value and remains at a logic low value, and the comparator output curve 824 remains at a logic high value.

[0127] Although Figure 2 and Figure 3 The diagram shows the implementation Figure 1 Controller 102 example approach, but Figure 2 and Figure 3 One or more of the elements, processes, and / or devices illustrated in the examples may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. In addition, the example reference voltage generator 106, the example error amplifier 108, the example delay unit 110, the example oscillator 112, the example ADC 114, the example feed-forward voltage controller 116, the example comparator 118, and / or more generally, Figure 1 、 2The example controller 102 of FIG3 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the example reference voltage generator 106, the example error amplifier 108, the example delay unit 110, the example oscillator 112, the example ADC 114, the example feed-forward voltage controller 116, the example comparator 118, and / or more generally, the example controller 102 can be implemented by one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application specific integrated circuits (ASICs), one or more programmable logic devices (PLDs), and / or one or more field programmable logic devices (FPLDs). When any apparatus or system claims of this patent are read to encompass purely software and / or firmware implementations, at least one of the example reference voltage generator 106, the example error amplifier 108, the example delay unit 110, the example oscillator 112, the example ADC 114, the example feed-forward voltage controller 116, the example comparator 118, and / or the example controller 102 is expressly defined herein as including a non-transitory computer-readable storage device or storage disk, such as a memory, including software and / or firmware. Further, Figure 1 、 2 and 3. The example controller 102 may include Figure 9 One or more elements, processes and / or devices other than those shown in, or in place of Figure 9 The present invention relates to a method for communicating with a user, wherein the method comprises one or more of the elements, processes and / or devices shown in the embodiment of the present invention, and / or may include more than one or all of the elements, processes and devices shown. As used herein, the phrase "in communication" includes variations thereof, encompassing direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but rather includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0128] Figure 9 shows a representative for implementing Figure 1 、 2and 3, a flowchart of example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof for the controller 102. The machine-readable instructions may be one or more executable programs or portions of executable programs that are executed by a computer processor such as the controller 102. The programs may be implemented in software stored on a non-transitory computer-readable storage medium such as a non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), a volatile memory (e.g., synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), etc., and / or any other type of random access memory (RAM) device), or memory associated with the controller 102, but the entire program and / or portions thereof may alternatively be executed by a device other than the controller 102 and / or implemented in firmware or dedicated hardware. Furthermore, although reference is made to Figure 9 The flowchart shown in describes an example program, but many other methods of implementing the example controller 102 may be used instead. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0129] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a packaged format, and the like. The machine-readable instructions described herein may be stored as data (e.g., a portion of an instruction, code, a representation of code, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., a server). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, and the like in order to make them directly readable and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts that are separately compressed, encrypted, and stored on separate computing devices, wherein the parts, after decryption, decompression, and combination, form a set of executable instructions that implement a program such as described herein. In another example, before the machine-readable instructions and / or corresponding one or more programs can be executed in whole or in part, the machine-readable instructions may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.). Thus, the description of machine-readable instructions and / or corresponding program(s) encompasses such machine-readable instructions and / or program(s) regardless of the particular format or state of the machine-readable instructions and / or program(s) when stored or otherwise disposed of or in transit.

[0130] As mentioned above, Figure 9 The example processes of may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on a non-transitory computer and / or machine readable medium, such as a hard drive, flash memory, read-only memory, compact disc, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk that stores information for any duration (e.g., for an extended period of time, permanently, for transient instances, for temporary caching, and / or caching information). As used herein, the term "non-transitory computer readable medium" includes any type of computer readable storage device and / or storage disk and excludes propagating signals and excludes transmission media.

[0131] "Includes" and "comprising" (and all their forms and tenses) are open-ended terms. Thus, whenever a claim employs any form of "includes" or "comprising" (e.g., includes, contains, having, etc.) as a preamble or in any kind of claim recitation, other elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. The phrase is open-ended in at least the same way that the terms "includes" and "comprising" are open-ended. The terms "and / or" when used, for example, in a form such as A, B, and / or C refer to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, and (7) A, B, and C. The phrase at least one of A and B refers to embodiments that include (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.

[0132] Figure 9 Is a representation that can be executed to achieve Figure 1 、 2 3 and 4. The example machine readable instructions 900 begin at block 902, where the comparator 118 configures the error amplifier 108 to adjust the voltage signal V based on the trimmed voltage. TON To control the duration of the delay of the delay cell in the delay cell 110. More specifically, at block 902, the comparator 118 enables and / or disables one or more of the first switch 126, the second switch 128, the third switch 130, and the fourth switch 132. For example, in the power converter system 100, the comparator 118 disables the first switch 126, enables the second switch 128, disables the third switch 130, and enables the fourth switch 132. Furthermore, for example, in the power converter system 200, the comparator 118 disables the first switch 126, enables the second switch 128, disables the third switch 130, and enables the fourth switch 132. Alternatively, in the example power converter system 300, the example comparator 118 enables the fourth switch 132 and configures the eighth switch 310 such that the second terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310.

[0133] exist Figure 9 In the embodiment of the present invention, at block 904, the comparator 118 disables the delay unit 110. More specifically, the comparator 118 disables the fifth switch 134. At block 906, the feedforward voltage controller 116 sets the delay unit 110 so that the PWM signal tracks the first voltage signal V SOFT and the period of the oscillator 112 divided by the input voltage signal V IN At block 908, the comparator 118 monitors the first voltage signal V SOFT At block 910 , the comparator 118 determines the first voltage signal VSOFT Has it started to rise from zero volts? If the comparator 118 determines that the first voltage signal V SOFT has begun to rise (block 910: YES), the machine readable instructions 900 proceed to block 912. If the comparator 118 determines that the first voltage signal V SOFT If the ascent has not started (block 910 : NO), the machine readable instructions 900 proceed to block 908 .

[0134] exist Figure 9 At block 912, the comparator 118 monitors the feedback voltage signal V FB and the first voltage signal V SOFT At block 914, the comparator 118 determines the first voltage signal V SOFT Is the feedback voltage signal V FB If the comparator 118 determines that the first voltage signal V SOFT The feedback voltage signal V FB If the comparator 118 determines that the first voltage signal V SOFT No feedback voltage signal V FB , (block 914 : NO), the machine readable instructions 900 proceed to block 912 .

[0135] At block 916, in response to the first voltage signal V FB The feedback voltage signal V FB The comparator 118 configures the error amplifier 108 to respond to the feedback voltage signal V FB The duration of each delay cell in the delay cell 110 is controlled. More specifically, the comparator 118 enables and / or disables one or more of the first switch 126, the second switch 128, the third switch 130, the fourth switch 132, or the eighth switch 310. For example, in the power converter system 100, the comparator 118 enables the first switch 126, disables the second switch 128, enables the third switch 130, and disables the fourth switch 132. Also, for example, in the power converter system 200, the comparator 118 enables the first switch 126, disables the second switch 128, enables the third switch 130, and disables the fourth switch 132. Alternatively, in the example power converter system 300, the example comparator 118 disables the fourth switch 132 and configures the eighth switch 310 such that the first terminal of the eighth switch 310 is coupled to the third terminal of the eighth switch 310. Figure 9 In the example embodiment, at block 918 , the comparator 118 enables the delay unit 110 . More specifically, the comparator 118 enables the fifth switch 134 .

[0136] As can be understood from the above, example methods, apparatus, and articles have been described that prevent transients on the output of a power converter by smoothly transitioning the power converter from an off state to a state controlled to output a voltage level equal to or greater than a pre-bias voltage level at the output of the power converter. In addition, some examples prevent negative current and DCM operation by disabling the power converter until the soft start voltage corresponding to the power converter is equal to or greater than the voltage level corresponding to the pre-bias voltage. The described methods, apparatus, and articles improve the efficiency of using a computing device by reducing the power consumption of the device by preventing negative current flow and DCM operation of the power converter. The described methods, apparatus, and articles improve the output signal of the power converter by reducing transients, thereby improving the functionality of one or more circuits and / or devices coupled to the power converter. The described methods, apparatus, and articles accordingly make one or more improvements to the functionality of a computer.

[0137] Although certain example methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

1. A device for a power converter, comprising: an error amplifier, the error amplifier comprising a feedback network and a differential difference amplifier (DDA), the DDA comprising a first input, a second input, a third input, a fourth input, and an output, the second input of the DDA being coupled to a power converter output, the third input of the DDA being coupled to a voltage generator first output, and the feedback network being coupled to the third input of the DDA, the fourth input of the DDA, and the output of the DDA; a multiplexer comprising a control terminal, the multiplexer coupled to the second output of the voltage generator, the multiplexer coupled to the second input of the DDA and the first input of the DDA; a first switch, the first switch including a control terminal, the first switch coupled in parallel with the feedback network; a second switch including a control terminal, the second switch being coupled to the delay unit input and the oscillator output; as well as A trigger comprising an output terminal, the trigger being coupled to the second output terminal of the voltage generator and the output terminal of the power converter, and the output terminal of the trigger being coupled to the control terminal of the multiplexer, the control terminal of the first switch, and the control terminal of the second switch.

2. The device according to claim 1, wherein The multiplexer includes a first current terminal, a second current terminal, and a third current terminal, the first current terminal of the multiplexer is configured to be coupled to the second output of the voltage generator, the second current terminal of the multiplexer is coupled to the second input of the DDA, and the third current terminal of the multiplexer is coupled to the first input of the DDA, and wherein the trigger includes a first input and a second input, the first input of the trigger is configured to be coupled to the second output of the voltage generator and the second input of the trigger is configured to be coupled to the output of the power converter.

3. The apparatus of claim 1 , further comprising a latch and an inverter, the latch being coupled to the output of the flip-flop and the control terminal of the multiplexer, the control terminal of the first switch, and the inverter being coupled to the control terminal of the second switch.

4. The apparatus according to claim 1, wherein The trigger is configured to configure the first switch, the second switch, and the multiplexer to enable the error amplifier to control the power converter based on the output voltage level and the first voltage level in response to a first voltage level being within a threshold difference of an output voltage level at the output terminal of the power converter.

5. The device according to claim 4, wherein The delay cell is configured such that a duration of the delay cell is adjustable based on a second voltage level at the output of the DDA.

6. The device according to claim 5, wherein The first voltage level is a reference voltage level corresponding to a soft start of the power converter, the second voltage level is a reference voltage level corresponding to the duration of the delay unit, and the output voltage level corresponds to a pre-bias voltage level at a load of the power converter.

7. The apparatus of claim 1 , further comprising a delay-based pulse width modulator, wherein The delay-based pulse width modulator comprises a plurality of delay cells including the delay cell, wherein a duration of a pulse generated by the delay-based pulse width modulator corresponds to a subset of the plurality of delay cells that are activated.

8. The apparatus of claim 1, comprising a power converter circuit having the power converter output.

9. The apparatus of claim 1, comprising a voltage generator circuit having the voltage generator first output and the voltage generator second output.

10. The apparatus of claim 1, comprising a delay cell circuit having the delay cell input.

11. The apparatus of claim 1 , comprising an oscillator circuit having the oscillator output.

12. The apparatus of claim 1, wherein the first input of the DDA is a non-inverting input.

13. The apparatus of claim 1, wherein the second input of the DDA is an inverting input.

14. The apparatus of claim 1, wherein the third input of the DDA is a non-inverting input.

15. The apparatus of claim 1, wherein the fourth input of the DDA is an inverting input.

16. A device for a power converter, comprising: a differential difference amplifier that controls a duration of the delay cell based on a first voltage level at a first output of the voltage generator; a first switch coupled to the differential difference amplifier; a multiplexer coupled to the differential amplifier, the first switch and the multiplexer being used to configure the differential amplifier; a second switch coupled to the delay unit to enable the delay unit; as well as a trigger coupled to a second voltage node, an output terminal of the power converter, the differential difference amplifier, the first switch, and the second switch, the trigger configuring the first switch, the multiplexer, and the second switch to enable the differential difference amplifier to control the power converter based on the output voltage level and the second voltage level in response to a second voltage level at the second output terminal of the voltage generator being within a threshold difference of an output voltage level at the output terminal of the power converter.

17. The apparatus of claim 16, further comprising a delay-based pulse width modulator, wherein The delay-based pulse width modulator comprises a plurality of delay cells including the delay cell, wherein a duration of a pulse generated by the delay-based pulse width modulator corresponds to a subset of the plurality of delay cells that are activated.

18. The apparatus according to claim 16, wherein The first voltage level is a reference voltage level corresponding to the duration of the delay unit, the second voltage level is a reference voltage level corresponding to a soft start of the power converter, and wherein the output voltage level corresponds to a pre-bias voltage level at a load of the power converter.

19. The apparatus of claim 16, further comprising a first resistor, a second resistor, and a capacitor.

20. The apparatus according to claim 19, wherein The first switch is coupled in parallel with the capacitor, the second switch is coupled with an oscillator and the delay unit, and the multiplexer is coupled with the second output of the voltage generator, the output of the power converter, and the first input of the differential difference amplifier; wherein the second input of the differential difference amplifier is coupled to the output of the power converter; and wherein the third and fourth inputs of the differential difference amplifier are coupled to the first output of the voltage generator.

21. The apparatus according to claim 20, wherein The first switch, the second switch, and the multiplexer are configured such that the first switch is closed and the second switch is open, and the multiplexer is configured such that the output terminal of the power converter is coupled to the first input terminal of the differential difference amplifier, and wherein, when the trigger is to configure the first switch, the second switch, and the multiplexer, the trigger is to open the first switch, close the second switch, and configure the multiplexer such that the second output terminal of the voltage generator is coupled to the first input terminal of the differential difference amplifier.

22. The apparatus of claim 16, further comprising a latch and an inverter, the latch coupled to the output of the flip-flop, the multiplexer, the first switch, and the inverter, the inverter coupled to the second switch.

23. A system for a power converter, comprising: load; A power converter comprising an input terminal and an output terminal, wherein the output terminal of the power converter is coupled to the load and comprises: an error amplifier, the error amplifier comprising a feedback network and a differential difference amplifier (DDA), the DDA comprising a first input, a second input, a third input, a fourth input, and an output, the second input of the DDA being coupled to a power converter output, the third input of the DDA being coupled to a voltage generator first output, and the feedback network being coupled to the third input of the DDA, the fourth input of the DDA, and the output of the DDA; a multiplexer comprising a control terminal, the multiplexer coupled to the second output of the voltage generator, the multiplexer coupled to the second input of the DDA and the first input of the DDA; a first switch, the first switch including a control terminal, the first switch coupled in parallel with the feedback network; a second switch including a control terminal, the second switch coupled to the delay cell input and the oscillator output; and a controller configured to drive the power converter when a pre-bias voltage is present at the output terminal of the power converter, the controller being configured to be coupled to the input terminal of the power converter, the controller being configured to: controlling a duration of the delay unit based on a first voltage level at a first output of the voltage generator; and In response to a second voltage level at a second output terminal of the voltage generator being within a threshold difference of an output voltage level at the output terminal of the power converter, configuring the first switch and the multiplexer to enable the controller to control the power converter based on the output voltage level and the second voltage level, and configuring the second switch to enable the delay unit to drive the power converter via the controller.

24. The system of claim 23, further comprising a delay-based pulse width modulator, wherein The delay-based pulse width modulator comprises a plurality of delay cells including the delay cell, wherein a duration of a pulse generated by the delay-based pulse width modulator corresponds to a subset of the plurality of delay cells that are activated.

25. The system of claim 23, wherein: The first voltage level is a reference voltage level corresponding to the duration of the delay unit, the second voltage level is a reference voltage level corresponding to a soft start of the power converter, and the output voltage level corresponds to a pre-bias voltage level at the load.

26. The system of claim 23, wherein: The controller includes a differential difference amplifier, the first switch, the second switch, the multiplexer, a first resistor, a second resistor, and a capacitor.

27. The system of claim 26, wherein: The first switch is coupled in parallel with the capacitor, the second switch is coupled with an oscillator and the delay unit, and the multiplexer is coupled with the second output of the voltage generator, the output of the power converter, and the first input of the differential difference amplifier; wherein the second input of the differential difference amplifier is coupled to the output of the power converter; and wherein the third and fourth inputs of the differential difference amplifier are coupled to the first output of the voltage generator.

28. The system of claim 27, wherein: The first switch, the second switch, and the multiplexer are configured such that the first switch is closed and the second switch is open, and the multiplexer is configured such that the output terminal of the power converter is coupled to the first input terminal of the differential difference amplifier, and wherein, when the controller is to configure the first switch, the second switch, and the multiplexer, the controller is to open the first switch, close the second switch, and configure the multiplexer such that the second output terminal of the voltage generator is coupled to the first input terminal of the differential difference amplifier.

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