Multi-channel multi-carrier transceiver

Abstract

A multi-channel, multi-carrier transceiver includes: a first channel for transmitting a first carrier; a second channel for transmitting a second carrier; a first ADPLL coupled to the first channel for providing a local oscillator signal for the first channel; a second ADPLL coupled to the second channel for providing a local oscillator signal for the second channel; and a configuration circuit coupled to the first ADPLL and the second ADPLL, respectively, for configuring the first ADPLL or the second ADPLL based on combined information of the first and second carriers. By configuring the phase-locked loops based on the combined information of multiple carriers, the phase-locked loops can eliminate spurious signals caused by frequency pulling of the multiple carriers, thereby improving the reliability of multi-channel, multi-carrier communications. Multiple phase-locked loops can be placed side by side in parallel on a layout, without being limited by the loop bandwidth of the phase-locked loops, and can save area overhead while incurring minimal area penalty.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a multi-channel multi-carrier transceiver. Background Art

[0002] In wireless radio frequency chips, phase-locked loops are used to provide stable local oscillator (LO) signals to transmitters and receivers. Figure 1 The structure diagram of the all digital phase-locked loop (ADPLL) in the RF transceiver shown in the figure is that compared with the traditional phase-locked loop, the area of ​​the ADPLL can be more flexibly reduced as the process size decreases, so it is increasingly widely used. ADPLL generally includes a time-digital converter (TDC), a digital filter, a digital-controlled oscillator (DCO) and a feedback divider (Ndivider). The principle of the phase-locked loop is to use a high-precision clock as a reference source to generate a high-frequency signal with several times its frequency, and pass it through a divider (such as Figure 1 The LO Div in the transmitter generates the actual LO signal, which is then passed through an up-conversion mixer (such as Figure 1 The baseband signal is transmitted after passing through the up-converter) and power amplifier (PA) in the receiver, or the RF signal received by the low noise amplifier (LNA) is converted into a baseband signal after passing through a down-conversion mixer (mixer) in the receiver.

[0003] When multiple phase-locked loops (PLLs) operate simultaneously on a chip, such as in non-contiguous carrier aggregation scenarios, frequency pulling between multiple DCOs can cause spurious signals or interference. These spurious signals can cause the PLL output signal to exceed the spectral mask defined by the transmit system at the corresponding frequency offset, degrading the noise figure in blocking scenarios defined by the receive system or directly degrading the PLL's noise. Because multiple local oscillator frequencies and clocks coexist in the system and interference channels are numerous, spurious signals become the most critical metric in PLL engineering design.

[0004] An existing method to reduce spurious signals or interference is to use the low-pass characteristics of the filter in the phase-locked loop to filter out spurious signals. For low-order modulation systems with low noise requirements, reducing the loop bandwidth can effectively suppress out-of-band spurious signals. Figure 2 The bandwidth suppression diagram shown in the figure shows that after the loop bandwidth is reduced from 150kHz to about 70kHz, the spur is reduced by about 12dB.

[0005] However, as systems place increasingly stringent demands on the integrated phase noise of phase-locked loops (PLLs), using a narrow bandwidth cannot meet these requirements. Increasing the bandwidth degrades the loop's ability to suppress spurious signals, and even eliminates them completely when they fall within the loop bandwidth. In this case, optimizing the bandwidth to simultaneously meet both low noise and low spurious requirements is no longer feasible. Furthermore, since the minimum raster in 5G applications is 15kHz, theoretically, spurs of 15kHz and its harmonics can be generated. However, the typical bandwidth of a PLL is much greater than 15kHz, making it impossible to suppress spurious signals by reducing the bandwidth.

[0006] In addition to optimizing bandwidth, another way to reduce spurious or interference is to Figure 3 The schematic diagram of the interference source and interfered source isolation solution shown in the figure shows that careful layout and routing can improve the isolation between various interference sources (such as DCO / PA / power supply, etc.) and interfered sources (clock traces / DCO / power supply, etc.), which can also improve better spurious performance. For example, if the distance between the inductors of two DCOs is 100um, the spur caused by pulling is -40dBc. If the distance is increased to 200um, the spur can be reduced to -50dBc, reducing the impact on integrated phase noise. Alternatively, if the distance between the clock trace and the DCO inductor is 100um, the fractional spur in the output spectrum is -60dBc, which does not meet the transmitter's spectrum mask requirements. If the distance is increased to 200um, the spur is reduced to -70dBc, meeting the requirements.

[0007] However, increasing isolation between the interferer and the victim often requires increasing the distance between the interferer and the victim, implementing guard rings / guard bands, or using different power supplies for modules operating at different frequencies to achieve sufficient isolation. These methods all increase chip area. Furthermore, as communication systems become increasingly complex and incorporate more on-chip subsystems, the number of interference sources and pathways increases significantly. Improving spurious performance by simply increasing isolation is becoming increasingly difficult and costly. Summary of the Invention

[0008] The embodiments of the present application provide a multi-channel multi-carrier transceiver to improve the reliability of multi-channel multi-carrier communications.

[0009] In a first aspect, a multi-channel multi-carrier transceiver is provided, comprising: a first channel for transmitting a first carrier; a second channel for transmitting a second carrier; a first all-digital phase-locked loop (ADPLL) coupled to the first channel for providing a local oscillator signal for the first channel; a second ADPLL coupled to the second channel for providing a local oscillator signal for the second channel; and a configuration circuit, coupled to the first ADPLL and the second ADPLL, respectively, for configuring the first ADPLL or the second ADPLL based on combined information of the first carrier and the second carrier. In this aspect, by configuring the phase-locked loop based on the combined information of multiple carriers, the phase-locked loop can eliminate spurious signals caused by frequency pulling of the multiple carriers, thereby improving the reliability of multi-channel multi-carrier communication.

[0010] In one implementation, the first ADPLL or the second ADPLL further includes a signal generating circuit coupled to the configuration circuit, the signal generating circuit configured to eliminate spurious signals based on the spurious signal frequencies configured by the configuration circuit. In this implementation, the signal generating circuit can accurately eliminate spurious signals caused by frequency pulling of multiple carriers based on the spurious signal frequencies configured by the configuration circuit.

[0011] In yet another implementation, the configuration circuit is specifically configured to configure the spurious frequency to be the absolute value of the difference between a first frequency and a second frequency, where the first frequency is the frequency of the first carrier and the second frequency is the frequency of the second carrier. In this implementation, configuring the spurious frequency to be the absolute value of the difference between the frequencies of the first carrier and the second carrier allows accurate determination of the spurious frequency.

[0012] In another implementation, the configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A-Flo_B*Div_B), where Flo_A is the frequency of the first carrier, Div_A is the division rate of the local oscillator connected to the first ADPLL, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the second frequency. In this implementation, the spurious frequency is related to the frequency of each carrier and the division rate of the local oscillator.

[0013] In another implementation, the signal generating circuit includes a single-tone complex signal generating circuit, an adaptive algorithm circuit, a loop phase compensation circuit, a cancellation signal generating circuit and a spurious cancellation circuit that are interconnected; the single-tone complex signal generating circuit is coupled to the configuration circuit; the single-tone complex signal generating circuit is used to generate a single-tone complex signal according to the frequency of the spurious configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious; the adaptive algorithm circuit is used to adaptively converge the spurious according to the single-tone complex signal to obtain a converged signal; the loop phase compensation circuit is used to perform phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal; the cancellation signal generating circuit is used to generate the spurious cancellation signal according to the converged signal and the compensated signal; and the spurious cancellation circuit is used to use the spurious cancellation signal to cancel the spurious in the signal. In this implementation, the frequency of the spurious cancellation signal generated by the signal generation circuit is the same as the frequency of the spurious signal. The amplitude and phase of the spurious cancellation signal are converged through an adaptive algorithm, so that the spurious amplitude in the DCO signal is reduced to meet the system requirements. In this way, the spurious signal caused by frequency pulling between multiple DCOs can be eliminated in a fully digital manner.

[0014] In yet another implementation, the configuration circuit is configured to configure multiple spurious frequencies, and the configuration circuit is connected in parallel to multiple signal generating circuits; the multiple parallel-connected signal generating circuits are configured to simultaneously eliminate multiple spurious signals based on the single-tone complex signals generated by the single-tone complex signal generating circuit in each signal generating circuit. In this implementation, the configuration circuit can simultaneously configure multiple spurious frequencies for multiple signal generating circuits, allowing the multiple signal generating circuits to eliminate multiple spurious signals, while improving configuration efficiency.

[0015] In yet another implementation, the configuration circuit is configured to configure multiple spurious frequencies, and the configuration circuit is serially connected to multiple signal generating circuits; the multiple serially connected signal generating circuits are configured to sequentially eliminate the multiple spurious signals based on the single-tone complex signals generated by the single-tone complex signal generating circuit in each signal generating circuit. In this implementation, the configuration circuit can sequentially configure the multiple spurious frequencies for the multiple signal generating circuits, so that the multiple signal generating circuits can eliminate the multiple spurious signals.

[0016] In a second aspect, a multi-channel, multi-carrier transceiver is provided, comprising: a first channel for transmitting a first carrier; a second channel for transmitting a second carrier; a first all-digital phase-locked loop (ADPLL) coupled to the first channel for providing a local oscillator signal for the first channel; and a second ADPLL coupled to the second channel for providing a local oscillator signal for the second channel; the first and second ADPLLs being placed side by side and in parallel on a circuit board. In this aspect, multiple phase-locked loops can be placed side by side and in parallel on the circuit board, without being limited by the loop bandwidth of the phase-locked loops. This also saves area overhead caused by isolation limitations or power supply splitting, while the area cost introduced by the circuit board itself is minimal.

[0017] In one implementation, the inductor of the first ADPLL is adjacent to the inductor of the second ADPLL.

[0018] In yet another implementation, the transceiver further includes a configuration circuit, coupled to the first ADPLL and the second ADPLL, respectively, for configuring the first ADPLL or the second ADPLL according to the combination information of the first carrier and the second carrier.

[0019] In yet another implementation, the first ADPLL or the second ADPLL further includes a signal generating circuit, which is coupled to the configuration circuit and configured to eliminate the spurious signal according to the frequency of the spurious signal configured by the configuration circuit.

[0020] In another implementation, the configuration circuit is specifically configured to configure the spurious frequency to be the absolute value of the difference between a first frequency and a second frequency, wherein the first frequency is the frequency of the first carrier and the second frequency is the frequency of the second carrier.

[0021] In another implementation, the configured spurious frequency Fspur_A_B = Abs(Flo_A*Div_A-Flo_B*Div_B), wherein Flo_A is the frequency of the first carrier, Div_A is the division rate of the local oscillator connected to the first ADPLL, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the second frequency.

[0022] In another implementation, the signal generating circuit includes a single-tone complex signal generating circuit, an adaptive algorithm circuit, a loop phase compensation circuit, a cancellation signal generating circuit and a spurious cancellation circuit that are interconnected; the single-tone complex signal generating circuit is coupled to the configuration circuit; the single-tone complex signal generating circuit is used to generate a single-tone complex signal according to the frequency of the spurious configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious; the adaptive algorithm circuit is used to adaptively converge the spurious according to the single-tone complex signal to obtain a converged signal; the loop phase compensation circuit is used to perform phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal; the cancellation signal generating circuit is used to generate the spurious cancellation signal according to the converged signal and the compensated signal; and the spurious cancellation circuit is used to use the spurious cancellation signal to cancel the spurious in the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of a fully digital phase-locked loop in a radio frequency transceiver;

[0024] Figure 2 Schematic diagram of bandwidth suppression on spurious signals;

[0025] Figure 3 Schematic diagram of the scheme for isolating the interference source and the interfered source;

[0026] Figure 4 A schematic structural diagram of a multi-channel multi-carrier transceiver is shown as an example;

[0027] Figure 5 A schematic structural diagram of a multi-channel multi-carrier transceiver provided in an embodiment of the present application;

[0028] Figure 6a A schematic diagram of the internal structure of a phase-locked loop provided in an embodiment of the present application;

[0029] Figure 6b A schematic diagram of the internal structure of another phase-locked loop provided in an embodiment of the present application;

[0030] Figure 7a for Figure 6a A detailed structural diagram of the signal generating circuit 25a in the illustrated embodiment;

[0031] Figure 7b for Figure 6b A detailed structural diagram of the signal generating circuit 25b in the illustrated embodiment;

[0032] Figure 8 A schematic diagram of the structure of parallel spurious elimination provided in an embodiment of the present application;

[0033] Figure 9 The diagram below shows the layout of two phase-locked loops. DETAILED DESCRIPTION

[0034] The technical solution of this application is described below in conjunction with the above-mentioned drawings.

[0035] See also Figure 4 , is a structural diagram of an example multi-channel multi-carrier transceiver. Figure 4 The fifth generation (5 th The carrier aggregation (CA) combination Band 28 and Band 79 used in the 5G generation mobile communication receiving system is shown as an example. The two carrier frequencies are: Fsig1 = 800MHz, Fsig2 = 4800.2MHz; the two receiving channel local oscillator frequencies are: Flo1 = 800MHz, Flo2 = 4800.2MHz; the division ratios of LO1 and LO2 are selected as 12 and 2 respectively, then the DCO frequencies of the two frequency synthesizer outputs are Fdco1 = 9600MHz, Fdco2 = 9600.4MHz respectively. The mutual pulling of the two DCOs will generate a spur of Fspur = 0.4MHz, which is called frequency pulling spur. If the isolation between the two DCOs is insufficient, the generated spur will seriously deteriorate the integrated noise of the phase-locked loop.

[0036] Related scenarios also include situations where multiple DCOs operate simultaneously, such as inter-band carrier aggregation (inter-band CA) and intra-band non-contiguous carrier aggregation (intra-band NC-CA) in the transmitting or receiving system, and dual-SIM dual standby (DSDS). Because 5G applications have a wide variety of CA combinations, there are many scenarios where DCO frequencies are similar.

[0037] In view of this, the present application provides a multi-channel multi-carrier transceiver, which configures the phase-locked loop according to the combination information of multiple carriers, so that the phase-locked loop can eliminate the spurious caused by the frequency pulling of multiple carriers, thereby improving the reliability of multi-channel multi-carrier communication; multiple phase-locked loops can be placed side by side in parallel on the layout, without being limited by the loop bandwidth of the phase-locked loop, and can save area overhead, while the area cost introduced by itself is very small.

[0038] See also Figure 5 , Figure 5A structural schematic diagram of a multi-channel multi-carrier transceiver provided in an embodiment of the present application, the transceiver includes a first channel (not shown in the figure) for transmitting a first carrier; a second channel (not shown in the figure) for transmitting a second carrier; a first ADPLL11, coupled to the first channel, for providing a local oscillator signal for the first channel; a second ADPLL12, coupled to the second channel, for providing a local oscillator signal for the second channel; and a configuration circuit 13, coupled to the first ADPLL11 and the second ADPLL12, respectively, for configuring the first ADPLL11 or the second ADPLL12 according to the combination information of the first carrier and the second carrier.

[0039] Specifically, the configuration circuit is used to configure the frequency of spurious signals, which are caused by the frequency pulling of two carriers, specifically the frequency pulling of DCOs of two phase-locked loops.

[0040] Specifically, the configuration circuit is used to configure the spurious frequency to be the absolute value of the difference between a first frequency and a second frequency, wherein the first frequency is the frequency of the first carrier and the second frequency is the frequency of the second carrier.

[0041] As shown in Table 1, assuming that phase-locked loop 1 operates in frequency band A and phase-locked loop 2 operates in frequency band B, the frequency of the configured pulling spur is Fspur_A_B = Abs(Flo_A*Div_A-Flo_B*Div_B). Flo_A is the frequency of the first carrier, that is, the frequency at which phase-locked loop 1 operates; Div_A is the division rate of the local oscillator connected to the first ADPLL; Flo_A*Div_A is the first frequency, that is, the DCO frequency of phase-locked loop 1. Flo_B is the frequency of the second carrier, that is, the frequency at which phase-locked loop 2 operates; Div_B is the division rate of the local oscillator connected to the second ADPLL; Flo_B*Div_B is the second frequency, that is, the DCO frequency of phase-locked loop 2.

[0042] Assuming that PLL 1 operates in frequency band C and PLL 2 operates in frequency band D, the frequency of the configured pull-in spurious signal is Fspur_C_D = Abs(Flo_C*Div_C-Flo_D*Div_D). Here, Flo_C is the frequency of the first carrier, Div_C is the division rate of the local oscillator connected to the first ADPLL, and Flo_C*Div_C is the first frequency, i.e., the DCO frequency of PLL 1. Flo_D is the frequency of the second carrier, Div_D is the division rate of the local oscillator connected to the second ADPLL, and Flo_D*Div_D is the second frequency, i.e., the DCO frequency of PLL 2.

[0043] Of course, here the phase-locked loop 1 operates in frequency band A or frequency band C, and the phase-locked loop 2 operates in frequency band B or frequency band D is only an example, and this application does not limit this.

[0044] The parameters in Table 1 may be preconfigured. When the operating frequency bands of the first ADPLL and the second ADPLL are determined, the spurious frequencies to be configured may be determined.

[0045] Table 1

[0046]

[0047] Table 2 shows examples of specific PLL operating frequency bands, frequency points, LO division rates, and DCO frequencies. These parameters can be substituted into the above formula for configuring the pull-in spurious frequency to calculate the specific pull-in spurious frequency. For example, assuming PLL 1 operates in frequency band B3 and PLL 2 operates in frequency band B8, then Fspur = Abs(1875*4-937.6*8) = Abs(7500-7500.8) = 0.8.

[0048] Table 2

[0049]

[0050] As shown in Table 3, assuming the LO division rate is fixed or only the frequency point is preconfigured, the pulling spurious frequency can also be obtained based on the frequency band of the phase-locked loop, the fixed LO division rate, and the preconfigured frequency point.

[0051] Table 3

[0052]

[0053] Table 4 shows examples of specific frequency bands and frequency points for phase-locked loop operation. Assuming that the LO division ratio for phase-locked loop 1 is 4 and the LO division ratio for phase-locked loop 2 is 8, the values ​​of these parameters can be substituted into the above formula for the pull-in spurious frequency configuration to calculate the specific pull-in spurious frequency value. For example, assuming that phase-locked loop 1 operates in frequency band B3 and phase-locked loop 2 operates in frequency band B8, then Fspur = Abs(1875*4-937.6*8) = Abs(7500-7500.8) = 0.8.

[0054] Table 4

[0055]

[0056] The configuration method (configured PLL, operating frequency band, and operating frequency) must be listed in the user manual, as shown in Tables 1 to 4. Table 1 is for designers only and does not need to be included in the user manual. Only the information in Table 3 is required.

[0057] Furthermore, if Figure 6a and Figure 6b As shown in the internal structure diagram of the phase-locked loop, an ADPLL (including the first ADPLL 11 and the second ADPLL 12) includes a time-to-digital converter 21, a digital filter 22, a digitally controlled oscillator 23 and a feedback divider 24 coupled in sequence. In this embodiment, the ADPLL may also include a signal generating circuit. Figure 6a In the embodiment, the signal generating circuit 25 is connected between the TDC 21 and the DCO 23; Figure 6b In the embodiment, the signal generating circuit 25 is connected between the TDC 21 and the digital filter 22. The signal generating circuit is also coupled to the configuration circuit. The signal generating circuit is used to eliminate spurious signals according to the spurious signal frequencies configured by the configuration circuit.

[0058] Among them, the output TDC_OUT of TDC21 includes an amplitude of A spur , frequency f spur , the phase is φ spur The signal generating circuit 25 is used to generate a single-tone complex signal with the same frequency as the spurious signal, and generate a spurious cancellation signal based on the amplitude and phase of the spurious signal in the TDC output. The amplitude of the spurious cancellation signal is converged and the phase of the spurious cancellation signal is compensated through an adaptive algorithm, so that the spurious amplitude in the signal output by the TDC is reduced to meet the system requirements, thereby ultimately reducing the spurious energy of the phase-locked loop output signal.

[0059] Specifically, see Figure 7a ,for Figure 6a Detailed structural diagram of the signal generating circuit 25 shown in FIG. Figure 7a As shown, the signal generating circuit 25 may include a single-tone complex signal generating circuit 251, an adaptive algorithm circuit 252, a loop phase compensation circuit 253, a cancellation signal generating circuit 254, and a spurious cancellation circuit 255, which are coupled to each other. The signal generating circuit 25 is coupled to the configuration circuit 13, which is connected to the single-tone complex signal generating circuit 251. The output of the TDC 21 includes a signal and pulling spurs, wherein the pulling spurs are time-varying signals. The signal and pulling spurs output by the TDC 21 are passed through a digital filter 22. The digital filter 22 outputs a filtered signal (referred to as "signal_filtered") and filtered pulling spurs (referred to as "pulling spurs_filtered"), wherein the pulling spurs_filtered signal is also a time-varying signal. The signal generating circuit 25 uses the generated pulling spurious cancellation signal to cancel the pulling spurs_filtered signal output by the digital filter 22, thereby obtaining a filtered signal.

[0060] Figure 7b for Figure 6bThe detailed structural diagram of the signal generating circuit 25 is shown in FIG. Figure 7a The internal structure of the signal generating circuit 25 shown is the same, except that the signal generating circuit 25 is connected between the TDC 21 and the digital filter 22 .

[0061] Different from the open-loop calibration method of fractional spurious, the pulling spurious elimination is a closed-loop calibration method of real-time monitoring, calculation and elimination. Therefore, the pulling spurious is a time-varying signal. In this embodiment, the single-tone complex signal generating circuit 251 generates a frequency of f spur The single-tone complex signal d j2πFspur*t , the frequency of the single-tone complex signal is the same as the spurious frequency f spur same.

[0062] ADPLL cannot directly obtain the frequency information of the pulled spurious, but the software responsible for configuring the ADPLL operating frequency can know the frequency information of the pulled spurious based on the working scenario, that is, the CA combination information, so the frequency of the spurious can be configured by the above-mentioned configuration circuit 13. When the frequencies of the interference source DCO (Aggressor) and the victim DCO (victim) are known, the configuration circuit 13 can obtain the frequency of the spurious. Specifically, the configuration circuit 13 configures the frequency of the spurious to be the absolute value of the difference between the first frequency and the second frequency, where the first frequency is the frequency of the signal output by the DCO of the interference source, and the second frequency is the frequency of the signal output by the DCO of the victim. For example, Figure 4 As shown, subsystem 1 is locked at f dco1 , open the work to be done in f dco2 After configuring subsystem 2, the spurious frequency to be eliminated can be configured as f spur =|f dco1 -f dco2 |.

[0063] Frequency pulling between multiple DCOs will generate spurious signals. The output of TDC21 includes such spurious signals. The adaptive algorithm circuit 252 detects the amplitude Acl and phase φ of the pulling spurious signals corresponding to the frequency in the output of TDC251 according to the frequency of the single-tone complex signal. c1 , and adaptively converge to obtain the converged signal

[0064] Since both the adaptive algorithm circuit 252 and the cancellation signal generating circuit 254 need to use the above-mentioned single-tone complex signal, and there is a phase shift between the adaptive algorithm circuit 252 and the cancellation signal generating circuit 254 due to the phase-locked loop pulling spurious, the loop phase compensation circuit 253 performs phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal.

[0065] The cancellation signal generating circuit 254 combines the converged signal output by the adaptive algorithm circuit 252 and the compensated signal output by the loop phase compensation circuit 253 to generate a spurious cancellation signal A. c1 *sin(2πf spur *t+φ comp +φ c1 ).

[0066] Since the frequency of the spurious cancellation signal is the same as that of the spurious frequency, the amplitude and phase of the spurious cancellation signal have been converged through the adaptive algorithm, and the spurious amplitude in the signal output by the digital filter is reduced to meet the system requirements. Therefore, the spurious in the signal is basically eliminated.

[0067] The aggressor DCO (aggressor) directly interferes with the victim DCO (victim), generating a pulling spur with a frequency of fspur = |fdco_victim - fdco_aggressor|. Since the TDC output directly reflects the spurious signals modulated by the DCO, the TDC output consists of both the signal and the pulling spur. A pulling spur cancellation signal with a frequency of fspur, an amplitude of Acal, and a phase of φcal is injected into the input or output of the digital filter. The amplitude Acal and the phase φcal are calculated by detecting the TDC output using an adaptive algorithm. Acal and φcal are time-varying signals during the convergence of the adaptive algorithm. Ideally, after convergence, the pulling spur component with a frequency of fspur disappears from the TDC output signal. Therefore, the output of the spurious cancellation circuit consists of only the signal and the pulling spur cancellation signal. In practice, due to the limited accuracy of the cancellation signal, the pulling spur component will not be completely eliminated, but it can still be reduced to within an acceptable range for the system.

[0068] In the above embodiment, further, in one implementation, taking the example of multiple signal generating circuits connected between the TDC and the digital filter (the solution of connecting the signal generating circuits to the TDC and the DCO can also adopt this implementation), if the output of the TDC includes spurious signals of multiple frequencies, then Figure 8 The schematic diagram of the parallel spurious elimination structure shown in the figure shows that the configuration circuit can be connected in parallel with multiple signal generating circuits. The configuration circuit can be used to configure the frequencies of multiple spurious signals. The multiple parallel connected signal generating circuits are used to simultaneously eliminate multiple spurious signals based on the single-tone complex signal generated by the single-tone complex signal generating circuit in each signal generating circuit. Specifically, the output of the TDC is a signal Then, multiple signal generating circuits can be connected in parallel in the TDC and digital filter: spurious 1 signal generating circuit, spurious 2 signal generating circuit, ... spurious k signal generating circuit. Among them, the spurious 1 signal generating circuit generates the spurious cancellation signal To cancel spur_1; similarly, the spurious 2 signal generation circuit generates a spurious cancellation signal To cancel spur_2, the spurious k signal generation circuit generates a spurious cancellation signal To cancel out spur_k. The multiple signal generating circuits can operate simultaneously. Thus, the multiple parallel signal generating circuits can ultimately eliminate all spurs in the TDC output. Specifically, the signal generating circuits operating in parallel means that the aforementioned circuits included in each signal generating circuit are connected in parallel as a whole.

[0069] In another implementation, if the TDC output includes spurious signals of multiple frequencies, a configuration circuit is used to configure the frequencies of the multiple spurious signals. The configuration circuit is serially connected to multiple signal generating circuits. The multiple serially connected signal generating circuits are used to sequentially eliminate the multiple spurious signals based on the single-tone complex signals generated by the single-tone complex signal generating circuit in each signal generating circuit. Specifically, the adaptive algorithm circuits in the multiple signal generating circuits are serially connected to extract the amplitude and phase of the spurious signals of each frequency, respectively. The other circuits of the signal generating circuit are connected in parallel to the corresponding adaptive algorithm circuits as a whole.

[0070] According to a multi-channel multi-carrier transceiver provided by an embodiment of the present application, a phase-locked loop is configured according to the combination information of multiple carriers, so that the phase-locked loop can eliminate the spurious caused by the frequency pulling of multiple carriers, thereby improving the reliability of multi-channel multi-carrier communication.

[0071] An embodiment of the present application further provides a multi-channel, multi-carrier transceiver, comprising: a first channel for transmitting a first carrier; a second channel for transmitting a second carrier; a first ADPLL coupled to the first channel for providing a local oscillator signal for the first channel; and a second ADPLL coupled to the second channel for providing a local oscillator signal for the second channel. The first ADPLL and the second ADPLL are placed side by side and in parallel on a layout. Optionally, the inductor of the first ADPLL is adjacent to the inductor of the second ADPLL.

[0072] like Figure 9 The schematic diagram of the layout of two phase-locked loops shown in FIG. 1 illustrates the layout of N phase-locked loops, where each phase-locked loop is placed side by side in parallel on the layout, and the inductors of each phase-locked loop are adjacent.

[0073] Multiple phase-locked loops can be placed side by side in parallel on the layout, without being limited by the loop bandwidth of the phase-locked loop, and can save area overhead, while the area cost introduced by itself is very small.

[0074] Furthermore, the transceiver further includes a configuration circuit, coupled to the first ADPLL and the second ADPLL, respectively, for configuring the first ADPLL or the second ADPLL according to the combination information of the first carrier and the second carrier. Regarding the configuration of the spurious frequency, reference can be made to the above embodiment.

[0075] Furthermore, the first ADPLL or the second ADPLL further includes a signal generating circuit, coupled to the configuration circuit, configured to eliminate spurious signals according to the configured spurious signal frequency of the configuration circuit. For details on how the signal generating circuit eliminates spurious signals, reference can be made to the above embodiments.

[0076] After applying the above signal generation circuit, on-chip DCOs can be placed side by side in parallel with a spacing of less than 1mm, or other circuits can be optimized first during layout and routing on the top layer of the chip without being restricted by the pulling spurious between DCOs, making the top layer layout of the chip more flexible.

[0077] The present application provides a multi-channel multi-carrier transceiver, in which multiple phase-locked loops can be placed side by side in parallel on the layout, are not limited by the loop bandwidth of the phase-locked loop, and can save area overhead, while the area cost introduced by itself is very small.

[0078] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The mutual coupling, direct coupling, or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, and can be electrical, mechanical or other forms.

[0080] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0081] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic medium such as a floppy disk, a hard disk, a tape, a magnetic disk, or an optical medium such as a digital versatile disc (DVD), or a semiconductor medium such as a solid state disk (SSD).

Claims

1. A multi-channel multi-carrier transceiver, characterized in that: include: A first channel is used to transmit a first carrier; A second channel is used to transmit a second carrier; a first ADPLL, coupled to the first mixer in the first channel, for providing a local oscillator signal to the first mixer; a second ADPLL, coupled to the second mixer in the second channel, for providing a local oscillator signal to the second mixer; a configuration circuit, coupled to the first ADPLL and the second ADPLL, respectively, configured to configure a spurious frequency of the first ADPLL or the second ADPLL according to carrier aggregation combination information of the first carrier and the second carrier, where the spurious frequency is caused by frequency pulling of the first carrier and the second carrier; The first ADPLL or the second ADPLL further includes a signal generating circuit, the signal generating circuit being coupled to the configuration circuit, the signal generating circuit being configured to eliminate the spurious signal according to the spurious frequency; The signal generating circuit includes a single-tone complex signal generating circuit, an adaptive algorithm circuit, a loop phase compensation circuit, a cancellation signal generating circuit and a spurious cancellation circuit that are interconnected; the single-tone complex signal generating circuit is coupled to the configuration circuit; The single-tone complex signal generating circuit is used to generate a single-tone complex signal according to the frequency of the spurious signal configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious signal; The adaptive algorithm circuit is used to adaptively converge the spurious signal according to the single-tone complex signal to obtain a converged signal; The loop phase compensation circuit is used to perform phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal; The cancellation signal generating circuit is used to generate a spurious cancellation signal according to the converged signal and the compensated signal; The spurious cancellation circuit is used to cancel the spurious in the signal using the spurious cancellation signal.

2. The multi-channel multi-carrier transceiver according to claim 1, wherein: The configuration circuit is specifically used to configure the spurious frequency to be the absolute value of the difference between a first frequency and a second frequency, wherein the first frequency is the frequency of the first carrier, and the second frequency is the frequency of the second carrier.

3. The multi-channel multi-carrier transceiver according to claim 2, wherein: The configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A- Flo_B*Div_B), wherein Flo_A is the frequency of the first carrier, Div_A is the division rate of the local oscillator connected to the first ADPLL, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the second frequency.

4. The multi-channel multi-carrier transceiver according to claim 1, wherein: The configuration circuit is used to configure multiple stray frequencies, and the configuration circuit is connected in parallel with multiple signal generating circuits; The plurality of signal generating circuits connected in parallel are used for simultaneously eliminating a plurality of spurious signals according to the single-tone complex signal generated by the single-tone complex signal generating circuit in each signal generating circuit.

5. The multi-channel multi-carrier transceiver according to any one of claims 1 to 3, characterized in that: The configuration circuit is used to configure multiple stray frequencies, and the configuration circuit is serially connected to multiple signal generating circuits; The plurality of serially connected signal generating circuits are used to sequentially eliminate the plurality of spurious signals according to the single-tone complex signal generated by the single-tone complex signal generating circuit in each signal generating circuit.

6. A multi-channel multi-carrier transceiver, characterized in that: include: A first channel is used to transmit a first carrier; A second channel is used to transmit a second carrier; a first ADPLL, coupled to the first mixer in the first channel, for providing a local oscillator signal to the first mixer; a second ADPLL, coupled to the second mixer in the second channel, for providing a local oscillator signal to the second mixer; a configuration circuit, coupled to the first ADPLL and the second ADPLL, respectively, configured to configure a spurious frequency of the first ADPLL or the second ADPLL according to carrier aggregation combination information of the first carrier and the second carrier, where the spurious frequency is caused by frequency pulling of the first carrier and the second carrier; The first ADPLL or the second ADPLL further includes a signal generating circuit, the signal generating circuit being coupled to the configuration circuit, the signal generating circuit being configured to eliminate the spurious signal according to the spurious frequency; The first ADPLL and the second ADPLL are placed side by side and in parallel on the layout; The signal generating circuit includes a single-tone complex signal generating circuit, an adaptive algorithm circuit, a loop phase compensation circuit, a cancellation signal generating circuit and a spurious cancellation circuit that are interconnected; the single-tone complex signal generating circuit is coupled to the configuration circuit; The single-tone complex signal generating circuit is used to generate a single-tone complex signal according to the frequency of the spurious signal configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious signal; The adaptive algorithm circuit is used to adaptively converge the spurious signal according to the single-tone complex signal to obtain a converged signal; The loop phase compensation circuit is used to perform phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal; The cancellation signal generating circuit is used to generate a spurious cancellation signal according to the converged signal and the compensated signal; The spurious cancellation circuit is used to cancel the spurious in the signal using the spurious cancellation signal.

7. The multi-channel multi-carrier transceiver according to claim 6, characterized in that: The inductor of the first ADPLL is adjacent to the inductor of the second ADPLL.

8. The multi-channel multi-carrier transceiver according to claim 6, characterized in that: The configuration circuit is specifically used to configure the spurious frequency to be the absolute value of the difference between a first frequency and a second frequency, wherein the first frequency is the frequency of the first carrier, and the second frequency is the frequency of the second carrier.

9. The multi-channel multi-carrier transceiver according to claim 8, characterized in that: The configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A- Flo_B*Div_B), wherein Flo_A is the frequency of the first carrier, Div_A is the division rate of the local oscillator connected to the first ADPLL, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the second frequency.

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