Microprocessor and branch prediction control method

Abstract

This invention provides a microprocessor and a branch prediction control method. In one embodiment, a microprocessor includes: a table including a plurality of edges, wherein at least a first edge includes a first conditional branch predictor having a first set of prediction tables, wherein at least a second edge includes a second conditional branch predictor having a second set of prediction tables, wherein the second conditional branch predictor is configured to provide a first prediction based on a prediction table hit for a branch instruction including information in the second edge, and wherein the first conditional branch predictor has higher complexity than the second conditional branch predictor; and control logic, wherein, based on receiving an indication of an incorrect prediction corresponding to the first prediction for the branch instruction, the control logic is configured to write information for the branch instruction into one of the first set of prediction tables of the first edge.

Description

Technical Field

[0001] This invention generally relates to microprocessors, and more particularly to branch prediction in microprocessors. Background Technology

[0002] Modern microprocessors operate using a pipelined processing scheme, where programming instructions are broken down into steps that are executed concurrently across multiple stages of the pipeline. Instructions typically (e.g., 10-20% of the programming code) include branch instructions, or simply branches, which include unconditional branches (e.g., branches that are always taken) and conditional branches (e.g., branches that are taken or not taken based on the evaluation of a specified condition). It is generally not known precisely whether a conditional jump will be taken or not until the condition has been evaluated and the conditional jump has passed through an execution stage in the instruction pipeline, which can lead to delays in fetching the next instruction. A branch predictor has been developed that attempts to guess at the front end of the pipeline which direction (taken or not taken) the conditional branch will proceed and to which target address, thereby improving the instruction flow through the pipeline.

[0003] One common branch predictor used in microprocessors is called the Branch Target Address Cache (BTAC). A BTAC includes hardware logic that may include a global history pattern of past branch instruction behavior to predict the target address of a fetched branch instruction. Generally, a branch predictor for a BTAC may include multiple predictor tables used in conjunction with multiple, often alphabetically represented, associated caches or sides (such as sides A and B in the case of two caches in a BTAC). Each side may include multiple paths (e.g., 2-way, 4-way, etc.). Information for some example BTAC arrays can be found in U.S. Patent Nos. 8,832,418 and 7,707,397, which are incorporated herein by reference to the extent consistent with the present disclosure. For a given cache fetch (e.g., a sixteen (16)-byte fetch of a cache line in the instruction cache), there may be more than a single branch instruction. For a BTAC with edges A and B, and a cache fetch containing two branch instructions, information for those two branch instructions (e.g., target address, direction, etc.) can be found in edges A and B, respectively. However, although infrequent, there may be more than two (e.g., three) branch instructions in a given cache fetch, and the microprocessor's prediction logic should be able to efficiently handle these multiple branch instructions encountered in a single cache line fetch without inappropriate latency and regardless of the complexity of the branch instructions. Summary of the Invention

[0004] In one embodiment, a microprocessor includes: a table comprising a plurality of edges, wherein at least a first edge includes a first conditional branch predictor having a first set of prediction tables, wherein at least a second edge includes a second conditional branch predictor having a second set of prediction tables, wherein the second conditional branch predictor is configured to provide a first prediction based on a prediction table hit for a branch instruction including information in the second edge, and wherein the first conditional branch predictor has higher complexity than the second conditional branch predictor; and control logic, wherein, based on receiving an indication of an incorrect prediction corresponding to the first prediction for the branch instruction, the control logic is configured to write information for the branch instruction into one of the first set of prediction tables of the first edge.

[0005] Other systems, methods, features, and advantages of the present invention will be apparent to those skilled in the art upon review of the following drawings and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of the invention, and protected by the appended claims. Attached Figure Description

[0006] The various aspects of the invention can be better understood by referring to the following accompanying drawings. The components in the drawings are not necessarily drawn to scale; rather, the focus is on clearly illustrating the principles of the invention. Furthermore, in the drawings, the same reference numerals denote corresponding parts in multiple views.

[0007] Figure 1A This is a block diagram illustrating an example branch unit pipeline used by a microprocessor to implement an embodiment of a branch predictive control system.

[0008] Figure 1B It is shown Figure 1A The diagram shows an example front end of a branch unit pipeline.

[0009] Figure 2A This is a schematic diagram illustrating an embodiment of an example branch predictive control system.

[0010] Figure 2B It is shown in Figure 2A A schematic diagram of an example escape logic implementation used in a branch predictive control system.

[0011] Figure 3 This is a flowchart illustrating an embodiment of the branch predictive control method.

[0012] Figure 4 This is a flowchart illustrating an embodiment of an example branch predictive control method.

[0013] Figure 5 This is a flowchart illustrating an embodiment of another example branch predictive control method. Detailed Implementation

[0014] Some embodiments of a branch prediction control system and method are disclosed, comprising a table with three cache memory edges, said three cache memory edges using two types of conditional branch predictors of different complexities to efficiently handle cases where three branch instructions in a single cache line fetch and / or more complex branch instructions are located on an edge with a smaller prediction table. In one embodiment, the branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache edge using a lower-complexity conditional branch predictor to one of two larger cache edges using a higher-complexity conditional branch predictor. The move (write) is implemented based on a configurable probability or likelihood to avoid recurrence of misprediction, and the result is a reduction in the amount of misprediction for a given branch instruction.

[0015] To digress slightly, traditional branch prediction schemes use branch prediction logic that includes a prediction logic table with multiple edges (e.g., a branch target address cache or BTAC). Although rare, cached line fetching with three branch instructions can result in prediction table hits in each of the three edges. In a BTAC, branch instructions are generally assigned in the order they appear in the programming code (e.g., first branch instruction to edge 1 or edge A, second branch instruction to edge 2 or edge B, and third branch instruction to edge 3 or edge C). However, the occurrence of three branch instructions is uncommon, and therefore, in most cases, it is unfounded to require these three edges to have equal sizes and / or equal prediction logic complexities. However, reducing the size and prediction complexity of one of these edges (e.g., edge C), while achieving the benefits of reduced complexity and increased operation speed, can lead to performance compromises when (e.g., compared to the other two branch instructions fetched from the cached line) a branch instruction requiring more precise branch prediction is located on a lower complexity edge (e.g., edge C). Some embodiments of the branch prediction control system detect a situation where an offending branch instruction is located on edge C, and therefore provide the option to remove or move the offending branch instruction from edge C (lower complexity) to either edge A or B (higher complexity) based on a configurable possibility representing one of several different predefined ratios (e.g., 1 / 128, 1 / 32, 1 / 8). By using a branch prediction microarchitecture with lower branch prediction complexity, performance improvements are achieved (e.g., compared to three edges using prediction functionality of the same complexity), while enabling small branch predictor removals (e.g., moving to an edge with a larger table of branch predictors using a more sophisticated branch prediction algorithm) when an offending branch instruction is mispredicted on edge C.

[0016] Having summarized certain features of the branch prediction control system of the present invention, detailed reference will now be made to the description of the branch prediction control system illustrated in the accompanying drawings. While the branch prediction control system will be described in conjunction with these drawings, it is not intended to limit it to the embodiments disclosed herein. That is, while the invention is readily adaptable to various modifications and alternatives, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein in a manner sufficient for those skilled in the art to understand. For example, although the focus below is on prediction logic having a conditional branch predictor table comprising three edges, those skilled in the art will understand in the context of the invention that tables having more than three edges or only two edges may also be used, and are therefore contemplated within the scope of the invention. Furthermore, although specific embodiments of a tagged geometric predictor having multiple tables of varying complexity in each of edges A and B and a gshare predictor having a single predictor table in edge C are described, in some embodiments, different types of conditional branch predictors may be used, and are therefore contemplated within the scope of the invention. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to the specific forms disclosed. Rather, it is intended to cover all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention as defined by the appended claims. As used herein, the word “may” is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Similarly, the word “comprising” means including, but not limited to, other than.

[0017] Various units, modules, circuits, logic, or other components can be described as being "configured" to perform one or more tasks. In this context, "configured" is a broad description of the structure, generally meaning "having a circuit or other physical structure that performs or is capable of performing one or more tasks during operation." A circuit can be a dedicated circuit or a more general processing circuit operating under the control of coded instructions. That is, terms such as "unit," "module," "circuit," "logic," and "component" are used herein when describing certain aspects or features of various implementations of the invention. Those skilled in the art will understand that the corresponding features are implemented using circuits, whether the circuit is a dedicated circuit or a more general circuit operating under the control of microcoded instructions.

[0018] Furthermore, units / modules / circuits / logic / components can be configured to perform tasks even when the unit / module / circuit / logic / component is not currently in operation. The description of units / modules / circuits / logic / components configured to perform one or more tasks is explicitly not intended to functionally limit the unit / module / circuit / logic / component. In this regard, those skilled in the art will understand that the specific structure or interconnection of circuit elements will generally be determined by the compiler of design automation tools, such as a register-transfer language (RTL) compiler. An RTL compiler runs on a script that is very similar to assembly language code to compile that script into a form for the layout or fabrication of the final circuit.

[0019] In other words, more advanced software tools are used to design integrated circuits (such as those of this invention) to model the desired functional operation of the circuit. Electronic Design Automation (or EDA) is a class of software tools used to design electronic systems such as integrated circuits. EDA tools are also used to program design functions into field-programmable gate arrays (FPGAs). Hardware descriptor languages ​​(HDLs) such as Verilog and Very High Speed ​​Integrated Circuits (VHDL) are used to create a high-level representation of the circuit, from which lower-level representations and the final actual wiring can be inferred. In practice, EDA tools are considered essential for the design of modern semiconductor chips, which can contain billions of components. In practice, circuit designers use programming languages ​​such as C / C++ to specify operational functions. EDA software tools translate this specified function into RTL. A hardware descriptor language (e.g., Verilog) then translates the RTL into a discrete netlist of gates. This netlist defines the actual circuit produced by, for example, a foundry. These tools are well-known and understood for their role and use in facilitating the design process of electronic and digital systems, and therefore need not be described here.

[0020] Figure 1A An embodiment of an example branch unit pipeline used by microprocessor 10 is shown. It should be understood that certain known components of microprocessor 10 are omitted herein for brevity and ease of explanation and illustration. As is well known, pipelined architectures provide multiple instructions that overlap during execution, where each level is called a pipeline level. The blocks shown in the branch unit pipeline can each be implemented according to one or more levels, which are shown to the left of the block and, in the depicted embodiment, are represented by the uppercase letters C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, which proceed sequentially from top to bottom and are redirected (as indicated by arrows). Those skilled in the art will understand that... Figure 1AThe number and / or arrangement of stages depicted herein are merely illustrative of one example embodiment, and in some embodiments, different numbers and / or arrangements of stages may be implemented, and are therefore contemplated within the scope of the invention. Those skilled in the art will also understand that these blocks provide a general description of the functionality of the branch pipeline, and for brevity, related logic or circuitry known to those skilled in the art is omitted herein. For example, those skilled in the art will understand that, as is known, each stage of a pipeline can be separated by a clock pipeline register or latch. As another example, although in Figure 1A Although not explicitly shown, those skilled in the art should understand that operations at the front end involve data exchange or interaction with the instruction cache.

[0021] An instruction cache is a random access memory device within a microprocessor in which the microprocessor places instructions (such as x86 ISA machine language instructions) that have recently been fetched and / or pre-fetched (e.g., fetched and / or pre-fetched from DRAM by a bus interface unit) from a larger cache (e.g., L2 cache, L3 cache) or system memory and executed by the microprocessor during the execution of an ISA machine language program. An ISA defines an instruction address register (defined by x86 ISA as the instruction pointer (IP), but sometimes called the program counter (PC)) to hold the memory address of the next ISA instruction to be executed, and the microprocessor updates the contents of the instruction address register as it executes the machine language program to control program flow. To subsequently execute ISA instructions based on the contents of the instruction address register, which allows for faster fetching of ISA instructions from the instruction cache rather than from system memory, the ISA instructions are cached such that the register holds the memory address of the ISA instructions present in the instruction cache. Specifically, the instruction cache is accessed based on the memory address held in the instruction address register (e.g., IP), rather than exclusively based on the memory address specified by the load or store instruction. Therefore, a dedicated data cache that holds ISA instructions as data (such as those that may reside in the hardware portion of a system employing a software translator) and accesses that data exclusively based on the load / store address rather than through the instruction address register value is not an instruction cache. Furthermore, for the purposes of this invention, a unified cache that caches both instructions and data (i.e., accessed based on both the instruction address register value and the load / store address, rather than exclusively based on the load / store address) is intended to be included in the definition of an instruction cache.

[0022] Special attention Figure 1AThe microprocessor 10 includes a branch unit pipeline, wherein the microprocessor 10 comprises a pipelined microprocessor, and in one embodiment, the instruction set of the pipelined microprocessor substantially conforms to the x86 architecture instruction set. Based on the description provided herein, those skilled in the art will understand that the present invention can be implemented in a variety of different circuit structures and architectures, and Figure 1A The architecture shown is just one of many suitable architectures. Example microprocessor 10 includes a fast predictor 12, a branch target address cache (BTAC) 14, an instruction byte queue (XIB) 16, a branch decoder 18, a formatted instruction queue (FIQ) / circular queue 20, an instruction translator 22, a register alias table (RAT) / reservation station (RS) 24, functional units (e.g., integer units, floating-point units, etc.) 26, and a branch table updater 28. The digitally labeled blocks of microprocessor 10 each correspond to logic implemented on corresponding multiple stages C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, where the pipelined architecture implements a different set of instructions at each stage. In one embodiment, four or more instructions can be executed at each stage, where control signals label each stage along the pipeline. The stages associated with the fast predictor 12, BTAC 14, and XIB 16 relate to the instruction cache (I cache, Figure 1A Access (not shown in the image).

[0023] The fast predictor 12 includes a single-cycle branch predictor that provides single-cycle prediction (e.g., taking one cycle to generate the target address, a prediction provided at level I in one embodiment). In one embodiment, the fast predictor 12 includes a table (also referred to herein as an array or target array) storing the branch target addresses of previously executed branch instructions, which enables branch prediction when the stored branch instructions are subsequently encountered. In one embodiment, the table includes 128 entries, but in some embodiments other sizes (e.g., 64 entries, 32 entries, etc.) may be used. The table is organized as an n-way (e.g., n is an integer greater than 1) set-associative cache. Generally, an n-way set-associative cache is also referred to herein as a multi-set-associative cache. In one embodiment, each entry stores eight (8) 3-bit counters and the current local branch mode, which is selected by the 3-bit local branch mode. The fast predictor 12 also includes a conditional branch predictor that is accessed in parallel with the table and provides take / not take direction for conditional branches. The fast predictor also includes a return stack that can provide targets instead of the table. In one embodiment, the return stack comprises four (4) entries and provides a target for the return instruction. Note that the specifications listed above are merely illustrative, and some embodiments may be implemented under different specifications, and are therefore contemplated within the scope of the invention. The fast predictor 12 is configured to deliver the predicted branch target immediately (within a single cycle) without imposing branch penalties. In some embodiments, the fast predictor 12 may operate according to other specifications of its prediction mechanism and / or table configuration, or in some embodiments, may be omitted. Most branches are correctly predicted by the fast predictor 12. In some embodiments, where the fast predictor 12 provides a branch prediction that differs from the branch prediction of BTAC 14 (e.g., different in direction and / or target) based on the same picked-up branch instruction, BTAC 14 utilizes the branch prediction information provided by BTAC 14 (e.g., direction, target address, branch prediction type) to overwrite the branch prediction of the fast predictor 12 and update the fast predictor table within a set of levels of BTAC 14 (e.g., at level U).

[0024] Level I and / or Level B correspond to various tables in the access branch unit pipeline (including I cache, tag array, translation back buffer (TLB) array, BTAC array, return stack array, etc.), (e.g., tag-based) providing direction or path through multiplexing, and reading instructions.

[0025] BTAC 14 maintains information about previously executed branch instructions used to predict the target address, direction, and type during subsequent execution. BTAC 14 includes one or more tables much larger than those of the fast predictor 12. In one embodiment, BTAC 14 includes a 4k-entry, m-way group association table (also referred to herein as an array or target array), where m is an integer greater than 1. Each entry in BTAC 14 includes a valid bit, a branch target address prediction, a direction prediction, and a branch type. The branch type specifies whether the branch instruction is a call / return, an indirect branch, a conditional relative branch, or an unconditional relative branch. In one embodiment, BTAC 14 includes or cooperates with a conditional relative branch predictor (or simply a conditional branch predictor), wherein the conditional branch predictor has a multi-entry (e.g., 12k) tag geometry (TAGE)-based conditional branch predictor, multiple tables, multiple bits (e.g., 3 bits), a take / not take (T / NT) counter, and a multi-bit global branch history. That is, the TAGE conditional branch predictor includes a tag table with a geometrically increased branch history length, as is well known. As another example, indirect prediction includes a multi-entry (e.g., 1.5k) TAGE predictor and uses table entries for static indirect branching. In one embodiment, two TAGE conditional branch predictors are used, one for edge A of the table and one for edge B of the table. The TAGE conditional branch predictor may be part of or used in conjunction with BTAC 14. In one embodiment, BTAC 14 includes or collaborates with a second type of conditional branch predictor (e.g., a gshare predictor associated with edge C of the table) that has lower complexity than the TAGE conditional branch predictor. The gshare conditional branch predictor may be part of or used in conjunction with BTAC 14. The gshare conditional branch predictor has a complexity between that of the fast predictor 12 and that of the TAGE conditional branch predictor (e.g., approximately 1 / 10 the size of the TAGE conditional branch predictor). In one embodiment, the gshare conditional branch predictor includes a single table (e.g., an m-bit global history register containing the branch patterns of the last m executed branch instructions, where m is typically 10-12 bits, but is not limited to that number). The gshare conditional branch predictor uses the global branch history and the location of the branch instruction (e.g., IP) to create an index (via XOR logical operation) into a table of counters (e.g., a 2-bit counter), where the result of the index is used for prediction of the current branch. Since conditional branch predictors of the TAGE and gshare types are known in the art, further description thereof is omitted here for brevity. Note that in some embodiments, other types of prediction mechanisms may be used, including correlation-based prediction mechanisms, conditional branch predictors using a combination of global and local branch histories, etc.Furthermore, although edges A, B, and C are emphasized here, fewer or more edges may be used in some embodiments. For each portion of a cache line of the instruction cache or each fetch unit (e.g., 16 bytes), BTAC 14 may maintain three entries (e.g., edges A, B, and C, although fewer edges may be used in some embodiments to store prediction information for fewer branch instructions), which may hold prediction information for up to three branch instructions that may exist in a portion of the cache line. BTAC 14 includes operation through a set of levels (e.g., level I, level B, and level U). In practice, level U of the branch instruction is used as level C of the target (e.g., the arrow from level B to level C reflects the branch instruction at level B, and the next clock is level C of the target, or here also a cache address), resulting in a two-clock delay for BTAC prediction.

[0026] BTAC 14 features a two-clock taken penalty, which also reveals the benefit of the fast predictor 12 in providing fast branch prediction (without taken penalty) by immediately bootstrapping a new cache address as the target. In one embodiment, BTAC 14 (larger than the fast predictor 12 and with a more sophisticated branch prediction mechanism) is configured to overwrite the branch prediction of the fast predictor 12 when there is a divergence in branch prediction (e.g., the branch prediction determined by BTAC 14 differs from the take decision and / or branch target address determined by the fast predictor 12) (e.g., always). In some embodiments, BTAC 14 is configured to update the fast predictor 12 during one of the BTAC levels (e.g., level U) by writing branch prediction information to the table of the fast predictor 12 (and also to the table of BTAC 14). In some embodiments, updates to BTAC 14 are deferred until the branch is executed or exited, wherein updates to BTAC 14 involve writing to the predictor table of BTAC 14. In one embodiment, the update involves target information and / or counter updates. The update includes writing incorrectly predicted conditional branch information from edge C of BTAC 14 to either edge A or edge B and / or the conditional branch predictor array (depending on the cache replacement scheme) based on configurable probabilities or likelihoods, and writing conditional branch information from edge A or edge B to edge C. However, updates to the fast predictor 12 do not wait that long; they occur during the BTAC stage. Note that branches not in the fast predictor 12 are written to the fast predictor 12 two cycles later at a time corresponding to the BTAC stage (e.g., during the BTAC stage).

[0027] XIB 16 is an entry queue where each entry holds 16 bytes of data from the instruction cache. For example, cached data from XIB 16 is simply a stream of instruction bytes in 16-byte blocks, and in the case of a given instruction having a variable length, it is unknown where a given x86 instruction begins or ends within the stream or within a given block. XIB 16 includes known logic for determining and marking the start and end bytes of each instruction within the stream, thereby breaking the byte stream into a stream of x86 instructions, which is provided to and stored in FIQ / circular queue 20 for processing by the rest of the microprocessor pipeline. At the L (length) level, XIB 16 determines the instruction length. In one embodiment, the pre-decoder ( Figure 1A (Not shown) Implemented at level U, and configured to detect potential branch instructions for each instruction byte in the queue and mark them as potential branch instructions. It is worth noting that at this level, there is ambiguity regarding whether a given byte is the start of an instruction. If the byte is the opcode byte of a branch instruction determined later (at level M), the instruction is confirmed as a branch instruction. For example, branch decoder 18 includes an instruction multiplexer (not shown) for multiplexing instructions in a multiplexer or at level M, where branch instructions are thus confirmed.

[0028] At level F, instructions are formatted. In one embodiment, the formatting instructions include instructions that substantially conform to the x86 architecture instruction set. Additionally, at level M, it is determined whether a given instruction (which may have been pre-marked by a pre-decoder) is indeed a branch. For example, in the event of a miss at fast predictor 12 or BTAC 14 (e.g., at initial startup), branch decoder 18 (e.g., an instruction multiplexer) determines that the current instruction is a branch and redirects the cache address to the new target at level G, and updates the tables in the front end of microprocessor 10. In effect, branch decoder 18 provides branch prediction in the event of a miss at fast predictor 12 or BTAC 14, where the branch instruction is redirected to the target at level C. In some cases, such as when there are more than a finite or predetermined maximum number of branches for each fetch at BTAC 14 (e.g., more than three branches for each 16-byte fetch), branch prediction for the additional branches is delayed until the decoding time.

[0029] FIQ / Circular Queue 20 receives and buffers formatting instructions until they can be translated into microinstructions. FIQ / Circular Queue 20 also provides preliminary decoding and fast looping functionality (e.g., on a BTAC loop branch, activating the circular queue and repeatedly sending loop instructions), the latter indicated by the arrow on the right side of Block 20.

[0030] The W class offers an optional additional timing clock.

[0031] At level X, instruction translator 22 (at level X or translation level) translates the formatted instructions stored in FIQ / circular queue 20 into microinstructions.

[0032] Instructions are provided to the Register Alias ​​Table / Reservation Table (RAT / RS) 24 in program order. The RAT function of RAT / RS 24 maintains and generates dependency information for each instruction. The RAT function of RAT / RS 24 renames the source and destination of instructions to internal registers and dispatches instructions to the reservation stations of RAT / RS 24, which (possibly out of program order) issue instructions to function unit 26. Function or execution unit 26, including integer units, executes branch instructions at level E (execution). Here, execution unit, branch unit, and integer unit are interchangeable terms. In one embodiment, execution unit 26 (e.g., two execution units) executes two branches in a single clock cycle. Execution unit 26 also indicates to BTAC 14 whether the branch instructions have been correctly predicted.

[0033] In one embodiment, the results of execution are provided to a reordering cache (not shown), which includes information related to the instructions that have been executed. It is well known that reordering caches maintain the original program order of instructions after they are issued and allow serialization of results during the retire stage. In one embodiment, some information about the reordering cache may be stored elsewhere in the pipeline, such as at decoder 18. The information stored in the reordering cache may include branch information, such as the type of branch, branch pattern, target, tables used in prediction, and cache replacement policy information (e.g., Least Recently Used or LRU).

[0034] Branch table update 28 includes levels S, W, Y, and Z, and is configured to update various tables (e.g., BTAC, TAGE) at the front end using information from fully decoded and executed branch instructions (e.g., the final result of the branch) (e.g., at level S). At levels S, W, Y, and Z, updates may involve table reads, target address writes, and counter increments or decrements, which may involve some latency. In one embodiment, branch table update 28 provides an indication of error prediction for a given conditional branch instruction and the edge (e.g., A, B, or C) where that conditional branch instruction is cached.

[0035] Now continuing to refer to Figure 1A In case of reference Figure 1B Example fast predictor 12 is shown, and it is used for... Figure 1AOther example sources are used at the front end 30 of the branch unit pipeline shown in the microprocessor 10. The front end 30 includes a pickup unit 32 (e.g., including a multiplexer and a clock register), a translation back buffer (TLB) 34, an instruction cache (I cache data) 36, I cache tags 38 (or a tag array), a BTAC 14, and a fast predictor 12. The pickup unit 32 receives multiple cached instruction address sources, including (e.g., from I level) sequential instruction addresses, (e.g., from S level) corrected instruction addresses, (e.g., from G level) decode-time instruction addresses, and addresses from the BTAC 14 and the fast predictor 12. The output of the pickup unit 32 is provided as input to the TLB 34, I cache data 36, ​​I cache tags 38, BTAC 14, and the fast predictor 12 for accessing the cache address of the next instruction for I cache data 36.

[0036] Under the management of a memory management unit (not shown), TLB 34 provides virtual-to-physical page address translation as is known. That is, TLB 34 stores the physical address of the most recently used virtual address. TLB 34 receives a linear address from a segmentation unit (which translates logical addresses from a program into linear addresses), and a portion of that linear address is compared with entries in TLB 34 to find a match. If a match is found, the physical address is calculated based on the TLB entry. If no match is found, a page table entry from memory is fetched and placed into TLB 34.

[0037] I cache data 36 includes a Level 1 cache of instructions fetched or pre-fetched from L2, L3, or main memory. I cache data 36 includes multiple clock registers.

[0038] I cache tag 38 includes an array of tags corresponding to instructions in I cache data 36, ​​and includes multiple clock registers for determining the match between information associated with a picked-up cache instruction (e.g., a tag or portion of a cache address) and I cache data 36 and BTAC 14.

[0039] The above combination Figure 1ALet's explain BTAC 14, which has multiple clock registers and a two (2) clock take penalty. Also as explained above, the fast predictor 12 has a zero (0) clock take penalty. For example, suppose fetching along the I cache at 16 bytes per cycle, and suppose a branch instruction from cache address 20 to cache address 95. Note that the address descriptions in this example imply hexadecimal notation (e.g., 0x0, 0x10, 0x20, etc.). Thus, fetching occurs at cache address 0, cache address 10, cache address 20 (branch instruction, but not yet resolved due to BTAC 14's multi-cycle read and multiplexing, where in some embodiments these multi-cycles are the same timing as the I cache), cache address 30 (relative clock 1), cache address 40 (relative clock 2), and then on the third clock (relative clock 3), the cache instruction fetch is redirected to cache address 95. Therefore, in this example, the branch penalty takes two clock cycles because cache addresses 30 and 40 occur after the branch. In other words, without the fast predictor 12, the branch penalty for this particular design example would always be two clock cycles. With the smaller and faster fast predictor 12, in the example above, cache addresses include 0, 10, 20, and 95, and there is no latency on the cache addresses and the penalty is zero. As mentioned above, in some embodiments, the fast predictor 12 can be omitted.

[0040] Now let's turn our attention to... Figure 2A This illustrates an embodiment of an example branch prediction control system 40. In one embodiment, the branch prediction control system 40 includes: BTAC 14, branch table update 28, control logic 44, deselection logic 46, and cache entry replacement logic 48, which are included in or coupled to a conditional branch table 42 (hereinafter simply referred to as the table). Note that for brevity, other parts of the pipeline are omitted here; however, it should be understood that the pipeline, as described above, is similar to... Figure 1A-1BIt functions as described in the associated description. In some embodiments, the predictive control system 40 may be considered to include fewer or more components. In one embodiment, table 42 includes a first edge (A), a second edge (B), and a third edge (C), the first edge A and the second edge B each including a first condition predictor (or more specifically, for this embodiment, a TAGE conditional branch predictor (one for edge A and one for edge B)) having multiple sets of association tables (e.g., multiple tables with global branch patterns of different complexities, not shown), and the third edge including a conditional branch predictor having a single predictor table (e.g., a gshare conditional branch predictor). As explained above, each TAGE conditional branch predictor has higher complexity than the gshare conditional branch predictor. Although depicted as a single table 42, those skilled in the art will understand that both BTAC 14 and the conditional branch predictors (TAGE, gshare) have tables with multiple edges (each with edges A, B, and C). For example, if a branch exists on edge B of BTAC 14, it also exists on edge B of the conditional predictor. Figure 2A As shown in Table 42, edges A and B each have their own TAGE condition predictors, while edge C has a gshare condition branch predictor.

[0041] In short, the gshare conditional branch predictor is used for edge C because two or more branches in a single cache line fetch are rare. Two TAGE conditional branch predictors are used for edges A and B, respectively, in conditional branch predictor table 42. Generally, the first branch (and the second branch) is assigned to edges A and B according to cache entry replacement logic 48 (such as Least Recently Used (LRU)). Edges A and B are independent and typically contain branches from different cache fetches. However, there are cases where the gshare conditional branch predictor is used to handle branch instructions that are more difficult to predict than other branch instructions. For example, the branch instruction for edge C might have a more complex directional pattern that is taken once every 27 times, or it might have a directional pattern that repeats after four takes and seven not takes. Other examples of more complex branch directional patterns can be considered by those skilled in the art. Such conditional branch instructions may also be performance-critical (e.g., performance-critical tight loops), thus further compromising microprocessor performance due to the increased risk of misprediction in these cases when using the gshare conditional branch predictor. Without correction, erroneous predictions may recur over millions or billions of cycles, resulting in a corresponding overall performance degradation (e.g., up to approximately 20%). The branch prediction control system 40 addresses at least these cases by using control logic 44 to decouple the conditional branch prediction from edge C based on a given probability or likelihood and write the problematic branch instruction to edge A or edge B, where the TAGE conditional branch predictor is better suited to handling more complex branch instructions.

[0042] like Figure 2A As shown, branch table update 28 provides information to control logic 44, including whether a given conditional branch instruction was mispredicted and whether the problematic (mispredicted) conditional branch instruction is on edge C. Control logic 44 collaborates with detour logic 46 and cache entry replacement logic 48 to write the branch instruction to edge A, B, or C. In one embodiment, the following... Figure 2BThe detachment logic 46, described further in association, includes a pseudo-random generator for providing a detachment trigger to control logic 44 to write mispredicted branch instruction entries (at a certain percentage of times) to edge A or B. Cache entry replacement logic 48 includes an array utilizing one of several known cache replacement schemes. For example, in one embodiment, the Least Recently Used (LRU) replacement algorithm is used. Control logic 44 controls an address multiplexer (not shown) to select the update address when a conditional branch in table 42 (e.g., at edge C) is being written to edge A or B, and when a conditional branch in edge A or B is being written to edge C. Cache entry replacement logic 48 stores replacement information for edges A, B, and C. Therefore, cache entry replacement logic 48 is a global resource shared among the edges of table 42. In one embodiment, the replacement information includes bits indicating which edge and which path of each edge is least recently used, which control logic 44 uses to perform writes to table 42. Control logic 44 also controls updates to the LRU array of cache entry replacement logic 48.

[0043] Continue to refer to Figure 2A Turn attention to Figure 2B This illustrates an embodiment detached from logic 46. Those skilled in the art will understand from the present invention that... Figure 2BThe example detach logic 46 shown is an illustrative example, and in some embodiments, different circuitry may be used to perform similar functionality. Detach logic 46 is generally configured to generate pseudo-random detach triggers, i.e., configurable time percentages. In one embodiment, detach logic 46 includes a linear feedback shift register (LFSR) 50, processing logic 52, and a feature control register (FCR) 54. In one embodiment, LFSR 50 includes seven (7) bits fed to processing logic 52, which in one embodiment includes an inverter. Note that the use of 7 bits is merely illustrative of an example, and in some embodiments, registers of other sizes may be used. In practice, LFSR 50 and processing logic 52 generate each possible value for the 7 bits (e.g., cycling through all 2^7 states in a pseudo-random order, except for all zero states). A subset of bits (e.g., a 5-bit sample, though not limited thereto) is provided to FCR 54, which selects one of several possible or probabilities of a detach or write from edge C to edge A or B (e.g., depending on the LRU scheme) being triggered. In one embodiment, FCR 54 may be configured (e.g., by physical or software / microcode adjustment) to make the probability or likelihood of detachment triggering 1 / 128, 1 / 32, 1 / 8, or even zero (off). Note that in some embodiments, all or some of these values ​​or ratios, and / or other values ​​or ratios, may be used. For example, when set to 1 / 32, there is a detachment trigger (provided to control logic 44) that allows edge C to detach randomly in approximately 3% of the time. This random mechanism is the opposite of a simple counter that triggers every 32 cycles, because the detachment logic 46 provides the trigger in a random manner (which avoids possible symmetry with programming code that always prevents detachment from occurring).

[0044] Based on the above description, those skilled in the art should understand that a branch predictive control method (in...) Figure 3 The method (represented as method 56, and implemented by control logic 44 in one embodiment) includes receiving an indication of an erroneous prediction of a branch instruction (58). Method 56 determines whether the erroneously predicted branch instruction is an entry in edge C (60). If "no" (60 is "no"), method 56 continues to monitor the erroneously predicted branch instruction. If "yes" (60 is "yes"), method 56 determines whether the problematic branch instruction is a conditional branch instruction (62), and if "no" (62 is "no"), returns to 58, while if "yes" (62 is "yes"), the above is used. Figure 2B The associated detachment logic 46 is used to detach edge C. It should be understood that in some embodiments, the steps of method 56 may be switched in sequence or performed in parallel.

[0045] The branch predictive control system 40 has been described. Figure 2A) and method 56 ( Figure 3 In some embodiments, it should be understood that the branch predictive control method is implemented in the microprocessor. Figure 4 In one embodiment of method 64, the microprocessor has a table comprising a plurality of edges, wherein at least a first edge of the plurality of edges includes a first conditional branch predictor having a first set of prediction tables, wherein at least a second edge of the plurality of edges includes a second conditional branch predictor having a second set of prediction tables, wherein the first conditional branch predictor has higher complexity than the second conditional branch predictor. Branch prediction control method 64 includes receiving an indication (66) of an erroneous prediction corresponding to a first prediction for a branch instruction including information in the second edge; and writing information for the branch instruction into the first edge (68) based on the received erroneous prediction indication.

[0046] Based on the above description, it should be understood that the branch predictive control method is implemented in the microprocessor (in... Figure 5 In another embodiment of method 70), the microprocessor has a table including a first side, a second side, and a third side, each of the first and second sides including a first conditional branch predictor having a group of multiple sets of associated tables, and a third side including a second conditional branch predictor having a single table, wherein each of the first conditional branch predictors has higher complexity than the second conditional branch predictor. The branch prediction control method includes: providing a first prediction (72) based on a prediction table hit for a branch instruction including information in the third side; receiving an indication of an incorrect prediction corresponding to the first prediction for the branch instruction (74); writing information for the branch instruction to one of the first side or the second side (76); and providing a second prediction based on a prediction table hit for a branch instruction including information in one of the first and second sides, wherein the amount of incorrect predictions for subsequent prediction table hits of the branch instruction is reduced based on the writing to one of the first and second sides (78).

[0047] Any process description or block in the flowchart should be understood as representing a module, segment, logic, or portion of code (which includes one or more executable instructions for implementing a particular logical function or step in the process), and alternative implementations are included within the scope of the embodiments, wherein, as those skilled in the art will understand, functions may be performed in a different order than shown or discussed (including substantially simultaneously or in a different order), depending on the functions involved.

[0048] Although the invention has been shown and described in detail in the accompanying drawings and the foregoing description, such drawings and descriptions should be considered illustrative or exemplary, not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention upon study of the drawings, the disclosure, and the appended claims.

[0049] Note that various combinations of the disclosed embodiments can be used, therefore referring to an embodiment or one embodiment does not imply that the features of that embodiment are excluded from use in other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.

Claims

1. A microprocessor, comprising: A table comprising multiple edges, wherein at least a first edge includes a first conditional branch predictor having a first set of prediction tables, and wherein at least a second edge includes a second conditional branch predictor having a second set of prediction tables. Wherein, for a given cache line fetch including at least a first branch instruction and a second branch instruction, the second conditional branch predictor is configured to provide a first branch prediction for the first branch instruction, and The first conditional branch predictor has higher complexity than the second conditional branch predictor; and Hardware control logic, wherein, based on receiving an indication of an erroneous prediction corresponding to a first branch prediction for the first branch instruction, the hardware control logic is configured to write a branch prediction entry for the first branch prediction to the first side.

2. The microprocessor of claim 1 further includes pseudo-random generator logic configured to provide a trigger signal for prompting a write operation via the hardware control logic, the trigger signal being provided according to a configurable probability.

3. The microprocessor according to claim 2, wherein, The configurable probability includes one of several possible ratios.

4. The microprocessor according to claim 1, wherein, The first conditional branch predictor is configured to provide a second branch prediction for the second branch instruction.

5. The microprocessor according to claim 4, wherein, Based on the writing to the first side, the amount of incorrect predictions for subsequent instances of the first branch instruction is reduced.

6. The microprocessor according to claim 1, wherein, The second conditional branch predictor includes a single prediction table and includes a gshare predictor.

7. The microprocessor according to claim 1, wherein, The first conditional branch predictor includes multiple branch predictor tables with different branch history lengths, and the first conditional branch predictor includes a label geometry predictor, namely a TAGE predictor.

8. The microprocessor of claim 7 further includes a second TAGE predictor for a third edge of the plurality of edges.

9. The microprocessor according to claim 1, wherein, The hardware control logic is further configured to write branch prediction entries corresponding to other branch instructions to the second side at the time corresponding to writing the first side.

10. The microprocessor according to claim 9, wherein, The selection of the branch prediction entry to be written to the second side corresponding to the other branch instructions is based on one of several different cache entry replacement schemes.

11. A branch prediction control method implemented in a microprocessor, the microprocessor having a table including multiple edges, wherein, At least a first edge of the plurality of edges includes a first conditional branch predictor having a first set of prediction tables, wherein at least a second edge of the plurality of edges includes a second conditional branch predictor having a second set of prediction tables, wherein the first conditional branch predictor has higher complexity than the second conditional branch predictor, and the branch prediction control method includes: Receive an indication of an erroneous prediction corresponding to the first branch prediction for the first branch instruction; and Based on the received instruction regarding the incorrect prediction, the branch prediction entry for the first branch instruction is written into the first side.

12. The branch prediction control method according to claim 11, wherein, The write operation is also based on receiving a trigger signal from a pseudo-random generator, provided according to a configurable probability.

13. The branch prediction control method according to claim 12, wherein, The configurable probability includes one of several possible ratios.

14. The branch prediction control method according to claim 11, further comprising: At the time corresponding to writing the first side, the branch prediction entries corresponding to other branch instructions are written to the second side.

15. The branch prediction control method according to claim 14, wherein, The selection of the branch prediction entry to be written to the second side corresponding to the other branch instructions is based on one of several different cache entry replacement schemes.

16. A branch prediction control method implemented in a microprocessor, the microprocessor having a table including a first side, a second side, and a third side, the first side and the second side each including a first conditional branch predictor having a group of multiple sets of association tables, the third side including a second conditional branch predictor having a single table, wherein, The first conditional branch predictor has a higher complexity than the second conditional branch predictor, and the branch prediction control method includes: For a given cache line fetch including first branch instructions, second branch instructions, and third branch instructions: The second conditional branch predictor is used to provide a first branch prediction for the first branch instruction; Receive an indication of an incorrect prediction corresponding to the first branch prediction; Write the branch prediction entry for the first branch instruction into one of the first edge and the second edge; and A first conditional branch predictor, using one of the first and second edges, is used to provide a second branch prediction for subsequent instances of the first branch instruction.

17. The branch prediction control method according to claim 16, wherein, The second conditional branch predictor includes the gshare predictor.

18. The branch prediction control method according to claim 16, wherein, Each of the first conditional branch predictors includes a label geometry predictor, i.e., a TAGE predictor.

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