Semiconductor package including embedded solder connection structure and method of manufacturing the same

Abstract

The present application relates to a semiconductor package including an embedded solder connection structure and a method for manufacturing the same. A semiconductor package includes: a first semiconductor chip including a first chip main body and a first chip rear bump arranged in a region recessed into the first chip main body; and a second semiconductor chip stacked on the first semiconductor chip and including a second chip main body and a second chip front bump protruding from the second chip main body. The first chip rear bump includes a lower metal layer and a solder layer arranged on the lower metal layer. The second chip front bump is bonded to the solder layer. The second chip front bump is arranged to cover at least the solder layer on the bonding surface of the second chip front bump and the solder layer.

Description

Technical Field

[0001] The present disclosure relates generally to a semiconductor package, and more particularly, to a semiconductor package including an embedded solder connection structure. Background Art

[0002] The semiconductor industry has been moving toward manufacturing semiconductor products with low weight, small size, high speed, multi-function, high performance and high reliability at low cost, and one of the important technologies for realizing such products is semiconductor packaging technology. Semiconductor packaging technology is a technology for mounting a semiconductor chip having a circuit portion formed on a packaging substrate through a wafer process, a technology for ensuring electrical connection between a semiconductor chip and an external electronic device through a packaging substrate, and a technology for protecting the semiconductor chip from the external environment.

[0003] Recently, in response to demands for lighter and shorter package products, research on structural stability and electrical connection stability of a package substrate and a semiconductor chip stacked on the package substrate has been continuously conducted. Summary of the invention

[0004] A semiconductor package according to one aspect of the present disclosure may include: a first semiconductor chip including a first chip body and a first chip back bump disposed in a region recessed in the first chip body; and a second semiconductor chip stacked on the first semiconductor chip and including a second chip body and a second chip front bump protruding from the second chip body. The first chip back bump may include a lower metal layer and a soldering layer disposed on the lower metal layer. The second chip front bump may be bonded to the soldering layer. The second chip front bump may be disposed to at least cover the soldering layer on a bonding surface of the second chip front bump and the soldering layer.

[0005] A semiconductor package according to another aspect of the present disclosure may include: a base member; a first semiconductor chip disposed on the base member; and a second semiconductor chip disposed on the first semiconductor chip. The first semiconductor chip may include: a first chip main body portion including a front surface and a rear surface; and a first chip rear bump disposed in an area recessed from the rear surface into the first chip main body portion. The second semiconductor chip may include: a second chip main body portion including a front surface and a rear surface; and a second chip front bump protruding from the front surface of the second chip main body portion. The first chip rear bump may include a lower metal layer and a soldering layer disposed on the lower metal layer. The soldering layer of the first semiconductor chip and the second chip front bump of the second semiconductor chip may be bonded to each other. The second chip front bump may be disposed to at least cover the soldering layer on the bonding surface of the second chip front bump and the soldering layer.

[0006] A method for manufacturing a semiconductor package according to another aspect of the present disclosure is disclosed. In the method, a first semiconductor chip can be prepared, which includes a first chip main body and a first chip back bump arranged in a region recessed in the first chip main body, wherein the first chip back bump may include a lower metal layer and a welding material layer arranged on the lower metal layer. A second semiconductor chip can be prepared, which includes a second chip main body and a second chip front bump protruding from the second chip main body. The welding material layer of the first semiconductor chip and the second chip front bump of the second semiconductor chip can be joined to form a welding layer. When joining the welding material layer and the second chip front bump, the second chip front bump and the welding layer can be joined to each other so that the second chip front bump at least covers the welding layer on the joining surface of the second chip front bump and the welding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view showing a semiconductor package according to one embodiment of the present disclosure.

[0008] Figure 2 is with Figure 1 An enlarged view of a region “A” related to a connection structure between semiconductor chips in a semiconductor package.

[0009] Figure 3 , Figure 4A , Figure 4B , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figures 8 to 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of these terms may be interpreted differently according to the common techniques in the field to which the embodiments belong. If a detailed definition is made, the term may be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as those commonly understood by those of ordinary skill in the field to which the embodiments belong.

[0011] In the description of the embodiments of the present disclosure, descriptions such as “first” and “second”, “upper” and “lower”, and “left” and “right” are used to distinguish components rather than to limit the components themselves or to indicate a specific order.

[0012] Throughout the specification, the same reference numerals denote the same elements. Even if a reference numeral is not mentioned or described with reference to one figure, it may be mentioned or described with reference to another figure. In addition, even if a reference numeral is not shown in one figure, it may be mentioned or described with reference to another figure.

[0013] In the accompanying drawings, the size (e.g., width or thickness) of an element (e.g., layer or region) may be magnified for clarity of illustration. In addition, the elements may be simplified to clearly illustrate their operation, their state, and the relationship therebetween in the accompanying drawings. In the specification, the description of the accompanying drawings is based on the viewpoint of the observer. It should be understood that when an element is referred to as being "on" another element, it may be directly "on" the other element, or there may be an intermediate element. In the accompanying drawings, the same reference numerals always represent the same elements. It should also be noted that in this specification, "connection / coupling" means that a component is not only directly connected to another component, but also indirectly connected to another component through an intermediate component. In addition, as long as there is no special mention, the singular form may include the plural form, and vice versa.

[0014] Figure 1 is a cross-sectional view showing a semiconductor package 1 according to one embodiment of the present disclosure. Figure 2 is with Figure 1 FIG. 1 is an enlarged view of a region “A” related to a connection structure between semiconductor chips in the semiconductor package 1. FIG.

[0015] Reference Figure 1 and Figure 2 The semiconductor package 1 may include a base member 10, a first semiconductor chip 20 disposed on the base member 10, and a second semiconductor chip 30 disposed on the first semiconductor chip 20. In addition, the semiconductor package 1 may further include a third semiconductor chip 40 disposed on the second semiconductor chip 30. Figure 1 and Figure 2 In the embodiment, one semiconductor chip is stacked on the second semiconductor chip 30, but is not necessarily limited thereto. In some embodiments, two or more semiconductor chips may be stacked on the second semiconductor chip 30. In addition, the semiconductor package 1 may further include a molding layer 710 surrounding the first to third semiconductor chips 20, 30, and 40 on the base member 10.

[0016] The base member 10 may electrically connect the first to third semiconductor chips 20, 30, and 40 to an external system. The base member 10 may be, for example, an interposer or a printed circuit board (PCB).

[0017] The base member 10 may include a base body 110. In one embodiment, the base body 110 may include a semiconductor material, such as silicon (Si). In another embodiment, the base body 110 may include a ceramic material, such as silicon oxide or glass. In another embodiment, the base body 110 may include a polymer material, such as a resin.

[0018] The base body 110 may include a first surface 110S1 and a second surface 110S2. The first surface 110S1 may be a surface facing the first semiconductor chip 20. The second surface 110S2 may be a surface opposite to the first surface 110S1 based on the base body 110.

[0019] The chip connection pad 120 for electrically connecting to the first semiconductor chip 20 may be provided on the first surface 110S1 of the base body 110. The chip connection pad 120 may be connected to the solder layer 220b of the first chip front bump 220 so that the base member 10 and the first semiconductor chip 20 may be electrically connected to each other. The bump pad 140 may be located on the second surface 110S2 of the base body 110. In one embodiment, the bump pad 140 may be embedded in the base body 110 except for the lower surface of the bump pad 140 which is located on the same plane as the second surface 110S2. In some embodiments, the bump pad 140 may be arranged to protrude outward from the second surface 110S2.

[0020] The connection structure 510 may be disposed on the lower surface of the bump pad 140. The connection structure 510 may be, for example, a solder bump or a solder ball. The connection structure 510 is connected to another printed circuit board or an external system so that the printed circuit board or the external system can be electrically connected to the base member 10. Depending on the function performed, the connection structure 510 may be classified as a power pin structure, a ground pin structure, or an input / output pin structure. A plurality of connection structures 510 may be spaced apart from each other on the second surface 110S2.

[0021] Although not shown, the base member 10 may include internal wiring. The internal wiring may include a plurality of circuit pattern layers and through holes electrically connecting the plurality of circuit pattern layers. The internal wiring may electrically connect the chip connection pad 120 to the bump pad 140. Therefore, an electrical signal input to the bump pad 140 from another printed circuit board or an external system through the connection structure 510 may reach the chip connection pad 120 via the internal wiring.

[0022] Reference Figure 1 and Figure 2, the first semiconductor chip 20 may be disposed on the base member 10. The first semiconductor chip 20 may include a first chip body 210. The first chip body 210 may be made of silicon (Si). The first semiconductor chip 20 may be a chip manufactured by a silicon integration process. The first chip body 210 may include a front surface 210S1 and a rear surface 210S2. Here, the front surface 210S1 may be a surface adjacent to an area where integrated circuits are densely distributed inside the first semiconductor chip 20. That is, active elements such as transistors and passive elements such as capacitors or resistors may be integrated in an inner region adjacent to the front surface 210S1 of the first chip body 210. In addition, a plurality of wiring pattern layers electrically connected to the active elements and the passive elements may be disposed in an inner region adjacent to the front surface 210S1 of the first chip body 210. The rear surface 210S2 may be an opposite surface of the front surface 210S1 based on the first chip body 210. In an inner region of the first chip body part 210 adjacent to the rear surface 210S2 , the integrated circuits may not exist or may be distributed at a relatively lower density compared to the first chip body part 210 adjacent to the front surface 210S1 .

[0023] The first chip front bump 220 can be arranged on the front surface 210S1 of the first chip main body 210. The first chip front bump 220 can be arranged to correspond to the chip connection pad 120 of the base member 10. Each first chip front bump 220 may include a bump body 220a and a welding layer 220b. The bump body 220a may include copper (Cu) or nickel (Ni), for example. The welding layer 220b may include a solder material containing tin (Sn) and silver (Ag). By bonding the welding layer 220b of the first chip front bump 220 to the chip connection pad 120, the base member 10 can be electrically connected to the first semiconductor chip 20.

[0024] The first chip front bump 220 may be electrically connected to the first chip through the through hole 240. Figure 1 , the first chip front bump 220 may be arranged to contact the first chip through via 240 in the z direction, or may be arranged not to contact the first chip through via 240 in the z direction. When the first chip front bump 220 does not contact the first chip through via 240 in the z direction, the first chip front bump 220 may be electrically connected to the end of the first chip through via 240 through a redistribution line (not shown) provided in the first chip body part 210.

[0025] In addition, the first chip rear connection structure 230 may be disposed in an area adjacent to the rear surface 210S2 of the first chip body portion 210. The first chip rear connection structure 230 may contact the front bump 320 of the second semiconductor chip 30. Thus, the first semiconductor chip 20 can be electrically connected to the second semiconductor chip 30. In addition, the first chip through-hole 240 is disposed inside the first chip body portion 210 to electrically connect the first chip front bump 220 to the first chip rear connection structure 230. Through the first chip through-hole 240, an electrical signal input from the base member 10 to the first semiconductor chip 20 can be transmitted toward the second semiconductor chip 30.

[0026] In some embodiments not shown, a gold (Au) layer may be additionally disposed on the surface of the bump body 220a of each first chip front bump 220. A soldering layer 220b may be disposed on the gold (Au) layer. The gold (Au) layer may be used as an anti-oxidation layer for the bump body 220a. In addition, when the soldering layer 220b engages the bump body 220a and the chip connection pad 120, the gold (Au) layer may be used to promote the formation of an intermetallic compound in the soldering layer 220b, or may be directly combined with the soldering material in the soldering layer 220b to be converted into an intermetallic compound. As described below, when the soldering material includes tin (Sn), the intermetallic compound may include gold-tin (AuSn4).

[0027] The first chip body 210 may include a first chip passivation layer 210a disposed in an area adjacent to the rear surface 210S2. For example, the first chip passivation layer 210a may be arranged to have a predetermined thickness in the inward direction of the first chip body 210 from the rear surface 210S2 of the first chip body 210. The first chip passivation layer 210a may include an inorganic material. For example, the first chip passivation layer 210a may include silicon oxide, silicon nitride, or silicon oxynitride. The word "predetermined" used herein with respect to a parameter (e.g., a predetermined thickness, a predetermined voltage, or a predetermined spacing) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0028] Reference Figure 1 and Figure 2 , the first chip rear connection structure 230 may be disposed adjacent to the rear surface 210S2 of the first chip body part 210. The first chip rear connection structure 230 may be disposed in a region recessed from the rear surface 210S2 of the first chip body part 210 into the first chip body part 210. In one embodiment, referring to Figure 2, a groove pattern 212 may be formed in a region of the first chip passivation layer 210a recessed in the first chip body portion 210. The first chip rear connection structures 230 may be respectively disposed in the respective groove patterns 212. The first chip rear connection structures 230 may be electrically connected to the first chip through the through-holes 240. Meanwhile, as shown in the figure, the first chip passivation layer 210a may be disposed to surround a portion of each first chip rear connection structure 230 and a portion of each first chip through-hole 240.

[0029] Each of the first chip back connection structures 230 may include a barrier layer 231 and a first chip back bump 232. The first chip back bump 232 may include a lower metal layer 232a and a solder layer 232b disposed on the lower metal layer 232a.

[0030] The barrier layer 231 may be arranged along the inner surface of the groove pattern 212. The barrier layer 231 may be arranged to surround the first chip back bump 232. The barrier layer 231 can isolate the first chip back bump 232 from the first chip passivation layer 210a. The barrier layer 231 can prevent the diffusion of materials between the first chip back bump 232 and the first chip passivation layer 210a. In addition, the barrier layer 231 may be electrically connected to the first chip through the through hole 240. For example, the barrier layer 231 may include tantalum (Ta). In one embodiment, the barrier layer 231 may be a tantalum (Ta) layer. In another embodiment, the barrier layer 231 may be formed as a two-layer structure of a tantalum layer and a cobalt (Co) layer. At this time, the tantalum (Ta) layer may be arranged to contact the first chip passivation layer 210a and the first chip through hole 240, and the cobalt (Co) layer may be arranged on the tantalum (Ta) layer.

[0031] The lower metal layer 232a may be disposed at a predetermined thickness on a portion of the barrier layer 231 corresponding to the bottom of the groove pattern 212. The lower metal layer 232a may provide a metal constituting an intermetallic compound generated inside the solder layer 232b in a process of forming the solder layer 232b, which will be described later. Fig. 7A and Figure 7B In addition, the lower metal layer 232a may be used to prevent copper (Cu) constituting the first chip through via 240 from diffusing into the solder layer 232b. For example, the lower metal layer 232a may include nickel (Ni).

[0032] The solder layer 232b may be disposed on the lower metal layer 232a in a direction perpendicular to the bottom of the groove pattern 212. The solder layer 232b may be bonded to the second chip front bump 320 of the second semiconductor chip 30. As a result, the first chip back bump 232 may be electrically connected to the second chip front bump 320.

[0033] The solder layer 232b may include solder material and intermetallic compounds. The solder material may include tin (Sn) or silver (Ag), etc. As described below, Fig. 7A and Figure 7B As shown, when using Figure 4B When the soldering material layer 232c of the first chip rear bump 232 of the first semiconductor chip 20 shown joins the lower metal layer 232a of the first semiconductor chip 20 and the second chip front bump 320 of the second semiconductor chip 30, the soldering material layer 232c may be transformed into a soldering layer 232b including an intermetallic compound. The intermetallic compound may be formed by at least one of a chemical reaction between the soldering material layer 232c and the lower metal layer 232a and a chemical reaction between the soldering material layer 232c and the second chip front bump 320.

[0034] In one embodiment, when each of the lower metal layer 232a and the second chip front bump 320 includes nickel (Ni), the intermetallic compound may include, for example, nickel-tin (Ni3Sn4). In some embodiments, a gold (Au) layer may be additionally provided on the surface of the second chip front bump 320 to prevent oxidation of the second chip front bump 320. In this case, for example, the intermetallic compound may also include gold-tin (AuSn4).

[0035] Each of the first chip back bumps 232 may be disposed to have a predetermined pitch Pb with other first chip back bumps in a lateral direction (ie, x direction). For example, the pitch Pb may be 10 μm or less.

[0036] The filling material layer 610 may be disposed in a region where the base member 10 and the first semiconductor chip 20 overlap in the z direction. The filling material layer 610 may include an organic material. For example, the filling material layer 610 may include an underfill. In some embodiments, the filling material layer 610 may include the same material as the molding layer 710. That is, when the molding layer 710 is formed, the region where the base member 10 and the first semiconductor chip 20 overlap in the z direction may be filled with molding material without the need for a separate process for forming the filling material layer 610.

[0037] Reference Figure 1 and Figure 2, the second semiconductor chip 30 may be disposed on the first semiconductor chip 20. The second semiconductor chip 30 may include a second chip body 310. The second chip body 310 may be formed of silicon (Si). The second semiconductor chip 30 may be a chip manufactured by a silicon (Si) integration process. The second chip body 310 may include a front surface 310S1 and a rear surface 310S2. Here, the front surface 310S1 may be a surface of an area where integrated circuits are densely distributed adjacent to the inside of the second semiconductor chip 30. The rear surface 310S2 may be a surface opposite to the front surface 310S1 based on the second chip body 310. In the inner area adjacent to the rear surface 310S2 of the second chip body 310, the integrated circuit may not exist or may exist at a relatively low density compared to the second chip body 310 adjacent to the front surface 310S1.

[0038] The second chip front bump 320 may be disposed on the front surface 310S1 of the second chip body portion 310. The second chip front bump 320 may be disposed to protrude from the second chip body portion 310. Figure 2 As shown, the second chip front bump 320 may be bonded to the solder layer 232b of the first chip back bump 232. The second chip front bump 320 may include, for example, nickel (Ni).

[0039] The second chip rear connection structure 330 may be disposed on the rear surface 310S2 of the second chip body part 310. The second chip rear connection structure 330 may be electrically connected to the front bump 420 of the third semiconductor chip 40. In addition, a second chip through via 340 electrically connecting the second chip front bump 320 and the second chip rear connection structure 330 may be disposed inside the second chip body part 310.

[0040] Reference Figure 2 , the second chip front bump 320 can be arranged to correspond to the first chip rear bump 232 of the first chip main body 210. On the bonding surface (i.e., rear surface 210S2) of the solder layer 232b in the second chip front bump 320 and the first chip rear bump 232, each second chip front bump 320 can be arranged to have a predetermined spacing Pb with the adjacent second chip front bump. At this time, the spacing Pb between the second chip front bumps 320 can be substantially the same as the spacing Pb between the first chip rear bumps 232.

[0041] The second chip front bump 320 can be arranged to at least cover the soldering layer 232b at the bonding surface of the second chip front bump 320 and the soldering layer 232b. In other words, each second chip front bump 320 can be arranged to cover the entirety of the soldering layer 232b. In addition, each second chip front bump 320 can be arranged to additionally cover the barrier layer 231 at the bonding surface.

[0042] The second chip front bump 320 may be surrounded by the first polymer bonding layer 620 on the front surface 310S1 of the second chip main body 310. For example, the side of the second chip front bump 320 may be buried by the first polymer bonding layer 620. The first polymer bonding layer 620 may include, for example, a polymer material. The first polymer bonding layer 620 may include, for example, a non-conductive film (NCF). The first polymer bonding layer 620 may be bonded to the first chip passivation layer 210a of the first chip main body 210. The bonding surface of the first polymer bonding layer 620 and the first chip passivation layer 210a may be substantially the same plane as the bonding surface of the second chip front bump 320 and the solder layer 232b.

[0043] In one embodiment, the second chip front bump 320 can be arranged to cover the entirety of the solder layer 232b at the bonding surface of the second chip front bump 320 and the solder layer 232b. In addition, the solder layer 232b can be separated from the first chip passivation layer 210a by the barrier layer 231. The barrier layer 231 is separated from the first polymer adhesive layer 620, and the first chip passivation layer 210a is therebetween, so that the solder layer 232b can be isolated from the first polymer adhesive layer 620 by the second chip front bump 320 and the barrier layer 231. That is, the solder layer 232b can be configured not to contact the first polymer adhesive layer 620.

[0044] At the same time, refer again Figure 1 , the second chip body part 310 may include a second chip passivation layer 310a disposed in a region adjacent to the rear surface 310S2. For example, the second chip passivation layer 310a may be disposed to have a predetermined thickness in an inward direction of the second chip body part 310 from the rear surface 310S2 of the second chip body part 310. The second chip passivation layer 310a may include an inorganic material. For example, the second chip passivation layer 310a may include silicon oxide, silicon nitride, or silicon oxynitride.

[0045] Reference Figure 1, the second chip rear connection structure 330 may be arranged adjacent to the rear surface 310S2 of the second chip main body 310. The second chip rear connection structure 330 may be arranged in a region recessed from the rear surface 310S2 of the second chip main body 310 into the second chip main body 310. The configuration of the second chip rear connection structure 330 may be substantially the same as the configuration of the first chip rear connection structure 230 of the first semiconductor chip 20. Therefore, the description of the configuration of the second chip rear connection structure 300 is omitted. Although not shown, each second chip rear connection structure 330 may include a barrier layer, a second chip rear bump, and a second welding layer corresponding to the barrier layer 231, the first chip rear bump 232, and the first welding layer 232b of the first chip rear connection structure 230. The barrier layer, the second chip rear bump, and the second welding layer of the second chip rear connection structure 330 may be formed inside the groove pattern formed in the second chip passivation layer 310a. That is, the second chip passivation layer 310a may be arranged to surround the second chip rear connection structure 330. In addition, the second chip passivation layer 310 a may be provided to also surround a portion of the second chip through via 340 .

[0046] The second chip rear connection structure 330 may be bonded to the third chip front bump 420 of the third semiconductor chip 40. The bonding structure between the second chip rear connection structure 330 and the third chip front bump 420 may be substantially the same as the bonding structure of the first chip rear connection structure 230 and the second chip front bump 320 described above.

[0047] Refer again Figure 1 , the third semiconductor chip 40 may be disposed on the second semiconductor chip 30. The third semiconductor chip 40 may include a third chip body portion 410, which includes a front surface 410S1 and a rear surface 410S2. The third semiconductor chip 40 may include a third chip front bump 420 disposed on the front surface 410S1 of the third chip body portion 410. At this time, the third chip front bump 420 on the front surface 410S1 of the third chip body portion 410 may be surrounded by the second polymer adhesive layer 630.

[0048] The third semiconductor chip 40 may include a third chip passivation layer 410a disposed in a region adjacent to the rear surface 410S2 of the third chip body portion 410. In addition, the third semiconductor chip 40 may include a third chip rear connection structure 430 disposed adjacent to the rear surface 410S2 of the third chip body portion 410. The third semiconductor chip 40 may include a third chip through-hole 440 connecting the third chip front bump 420 and the third chip rear connection structure 430.

[0049] Meanwhile, the configuration of the third semiconductor chip 40 may be substantially the same as that of the second semiconductor chip 30. For example, the configuration of the third chip body 410, the third chip passivation layer 410a, the third chip front bump 420, the third chip rear connection structure 430, and the third chip through-hole 440 may be substantially the same as that of the second chip body 310, the second chip passivation layer 310a, the second chip front bump 320, the second chip rear connection structure 330, and the second chip through-hole 340. In addition, the configuration of the second polymer adhesive layer 630 may be substantially the same as that of the first polymer adhesive layer 620.

[0050] In some embodiments, when a plurality of semiconductor chips are stacked on the base member 10, the uppermost semiconductor chip among the plurality of semiconductor chips may not include a chip through via and a chip post connection structure. Figure 1 In the embodiment, when the first to third semiconductor chips 20 , 30 , and 40 are stacked on the base member 10 , the uppermost third semiconductor chip 40 may not include the third chip back connection structure 430 and the third chip through via 440 .

[0051] Refer again Figure 1 A mold layer 710 surrounding the first to third semiconductor chips 20, 30, and 40 may be disposed on the base member 10. The mold layer 710 may include, for example, epoxy molding compound (EMC). The mold layer 710 may be used to physically or chemically protect the first to third semiconductor chips 20, 30, and 40 from the external environment.

[0052] As described above, the chip through holes 240, 340 and 440 can be used in the semiconductor chips 20, 30 and 40, respectively, to exchange electrical signals between the base member 10 and the semiconductor chips 20, 30 and 40 stacked on the base member 10. According to various embodiments of the present disclosure, the solder layer 232b electrically connecting the first semiconductor chip 20 and the second semiconductor chip 30 can be isolated from the first polymer adhesive layer 620 by the second chip front bump 320, the barrier layer 231 and the first chip passivation layer 210a. This physical isolation can prevent defects caused by electrochemical reactions such as the conductive anodic filament generation phenomenon. The conductive anodic filament generation phenomenon can be such an electrochemical reaction: in a structure where the anode and the cathode are arranged to contact the polymer layer, when an electric field is applied between the anode and the cathode, filaments made of the anode material are generated in the polymer layer. When a high electric field is applied between the anode and the cathode in a high temperature and high humidity environment, an electrochemical reaction may occur in a state where the polymer layer absorbs moisture and the insulation of the polymer layer is deteriorated.

[0053] More specifically, when a high electric field is applied in the environment, after the conductive chemical in the anode is oxidized, the oxidized conductive chemical may be released into the polymer layer in the form of ions. The released ions of the conductive chemical may move toward the cathode along the electric field and be reduced by gaining electrons, thereby forming conductive filaments within the polymer layer. When the conductive chemical forms conductive filaments, defects such as electrical short circuits may occur between the anode and the cathode.

[0054] Refer again Figure 2 , the signal exchange between the first semiconductor chip 20 and the second semiconductor chip 30 can be performed through the first electrical path P1 and the second electrical path P2. Here, the first electrical path P1 represents the signal exchange between the first semiconductor chip 20 and the second semiconductor chip 30. Figure 2 The electrical signal flow of the first chip through hole 240, the first chip rear connection structure 230, the second chip front bump 320 and the second chip through hole 340 on the left side. The second electrical path P2 represents the electrical signal flow through the first chip rear connection structure 230, the second chip front bump 320 and the second chip through hole 340. Figure 2 The electrical signal flows of the first chip through via 240, the first chip back connection structure 230, the second chip front bump 320, and the second chip through via 340 on the right side. Here, in order to generate the electrical signal flows along the first electrical path P1 and the second electrical path P2, predetermined voltages may be applied to the first electrical path P1 and the second electrical path P2, respectively.

[0055] If with Figure 2 Unlike the current embodiment of the present disclosure shown, the welding layer 232b (ie, Figure 2 The solder layer 232b shown on the left in the figure and the solder layer 232b located in the second electrical path P2 (ie, Figure 2 If the welding layer 323b shown on the right side of the figure directly contacts the first polymer bonding layer 620, electrical defects such as the above-mentioned conductive anode filaments may occur. That is, in an environment of high temperature and high humidity, when the voltage applied to the first electrical path P1 and the voltage applied to the second electrical path P2 produce a voltage difference on the first polymer bonding layer 620, one of the welding layers 232b in the first electrical path P1 and the second electrical path P2 can be used as an anode, and the other as a cathode. Therefore, the tin (Sn) in the welding layer 232b used as the anode can be oxidized to produce tin (Sn) ions, and the tin (Sn) ions can move toward the cathode inside the first polymer bonding layer 620. In addition, the tin (Sn) ions can be reduced inside the first polymer bonding layer 620 to form tin (Sn) filaments. The tin (Sn) filaments may cause an electrical short circuit between the anode and the cathode.

[0056] At the same time, refer again Figure 2According to one embodiment of the present disclosure, the second chip front bump 320, the barrier layer 231, and the first chip passivation layer 210a can allow the solder layer 232b and the first polymer adhesive layer 620 to be separated from each other. Therefore, when a predetermined voltage is applied along the first electrical path P1 and the second electrical path P2, respectively, the phenomenon that tin (Sn) inside the solder layer 323b moves into the first polymer adhesive layer 620 due to the above-mentioned electrochemical reaction can be prevented. As a result, according to one embodiment of the present disclosure, the solder layer 232b is structurally stable, thereby being able to ensure the electrical reliability of the solder joint between the first semiconductor chip and the second semiconductor chip.

[0057] Meanwhile, the electrical connection structure between the second semiconductor chip 30 and the third semiconductor chip 40 may be substantially the same as the electrical connection structure between the first semiconductor chip 20 and the second semiconductor chip 30. Therefore, the electrical reliability of the solder joint between the second semiconductor chip 30 and the third semiconductor chip 40 can be ensured in the same manner.

[0058] Figure 3 , Figure 4A , Figure 4B , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figures 8 to 10 is a cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. Here, Figure 4B yes Figure 4A Magnified view of area "B". Figure 6B yes Fig. 6A The enlarged view of area "C" is shown in Figure 2. Figure 6C yes Fig. 6A Magnified view of area "D". Figure 7B yes Fig. 7A Magnified view of area "E".

[0059] Reference Figure 3 , a base member 10 may be provided. The base member 10 may include a base body 110 having a first surface 110S1 and a second surface 110S2. A chip connection pad 120 may be provided on the first surface 110S1 of the base body 110.

[0060] The bump pads 140 may be exposed to the second surface 110S2 of the base body 110. In one embodiment, each bump pad 140 may be buried inside the base body 110 except for the lower surface of the bump pad 140 located on the same plane as the second surface 110S2. In some embodiments, the bump pads 140 may be configured to protrude outward from the second surface 110S2.

[0061] Although not shown, the base member 10 may include internal wiring. The internal wiring may include a plurality of circuit pattern layers and through holes electrically connecting the plurality of circuit pattern layers. The internal wiring may electrically connect the chip connection pad 120 to the bump pad 140.

[0062] Reference Figure 4A and Figure 4B , a first semiconductor chip 20 may be provided. The first semiconductor chip 20 may include a first chip body 210. The first chip body 210 may be made of silicon (Si). A plurality of integrated circuit layers manufactured by a silicon process and a plurality of insulating layers insulating the plurality of integrated circuit layers may be provided in the first chip body 210. The first chip body 210 may include a front surface 210S1 and a rear surface 210S2.

[0063] A bump body 220a may be formed on the front surface 210S1 of the first chip body 210. Each bump body 220a may include, for example, nickel (Ni). A soldering material layer 220c may be formed on each bump body 220a. The soldering material layer 220c may include, for example, tin (Sn) or silver (Ag). The bump body 220a and the soldering material layer 220c may be formed by an electroplating process.

[0064] The first chip body 210 may include a first chip passivation layer 210a. The first chip passivation layer 210a may be formed to have a predetermined thickness in an inward direction of the first chip body 210 from a rear surface 210S2 of the first chip body 210. The first chip passivation layer 210a may include an inorganic material. For example, the first chip passivation layer 210a may include silicon oxide, silicon nitride, or silicon oxynitride. The first chip passivation layer 210a may be formed in the first chip body 210 by a semiconductor thin film deposition process such as chemical vapor deposition or physical vapor deposition.

[0065] The first chip rear connection structure 230 may be formed adjacent to the rear surface 210S2 of the first chip body part 210. Figure 4A and Figure 4B , the process of forming the first chip rear connection structure 230 may be performed as follows. First, a groove pattern 212 may be formed from the rear surface 210S2 to the inside of the first chip body 210. For example, the groove pattern 212 may be formed inside the first chip passivation layer 210a of the first chip body 210. For the process of forming the groove pattern 212, a semiconductor photolithography process and an etching process may be applied.

[0066] Subsequently, a barrier layer 231 may be formed along the inner surface of the groove pattern 212. For example, each barrier layer 231 may include tantalum (Ta). In one embodiment, the barrier layer 231 may be a tantalum (Ta) layer. In another embodiment, the barrier layer 231 may be formed as a two-layer structure of a tantalum (Ta) layer and a cobalt (Co) layer. In this case, the tantalum (Ta) layer may be arranged to contact the first chip passivation layer 210a and the first chip through hole 240, and the cobalt (Co) layer may be arranged on the tantalum (Ta) layer. For example, a semiconductor thin film deposition process such as sputtering may be used to perform the process of forming the barrier layer 231.

[0067] Subsequently, a lower metal layer 232a of a predetermined thickness may be formed on a portion of the barrier layer 231 corresponding to the bottom surface of the groove pattern 212. For example, each lower metal layer 232a may include nickel (Ni). The lower metal layer 232a may be formed, for example, by an electroplating method. In one embodiment, a plating seed layer (not shown) may be formed on the barrier layer 231, and the lower metal layer 232a may be formed by an electrolytic plating method using the plating seed layer.

[0068] Subsequently, a solder material layer 232c of a predetermined thickness may be formed on the lower metal layer 232a. The solder material layer 232c may be formed, for example, using an electroplating method. The solder material layer 232c may include, for example, a solder material such as tin (Sn) or silver (Ag). Here, the upper surface of the solder material layer 232c may be controlled so that it is located at substantially the same level as the rear surface 210S2 of the first chip body portion 210.

[0069] In one embodiment, each groove pattern 212 may be formed to have a predetermined interval with an adjacent groove pattern. Therefore, each first chip back connection structure 230 formed inside the groove pattern 212 may have a predetermined pitch Pb with other first chip back connection structures adjacent in the lateral direction (i.e., x direction). The pitch Pb may be, for example, 10 μm or less.

[0070] Reference Figure 4A , a first through chip via 240 electrically connecting the first chip front bump 220 to the first chip rear connection structure 230 may be formed in the first chip body part 210. The first through chip via 240 may be formed by an electroplating process.

[0071] Reference Figure 5 , the first semiconductor chip 20 may be stacked on the base member 10. For example, the bump body 220a and the chip connection pad 120 may be formed using Figure 4A The solder material layer 220c formed on the bump body 220a is shown to be bonded to each other. Therefore, the base member 10 and the first semiconductor chip 20 can be electrically connected to each other.

[0072] In the bonding process, Figure 4A The solder material layer 220c of the first semiconductor chip 20 shown may be placed Figure 3 The solder material layer 220c is formed by applying heat to the corresponding chip connection pad 120 of the base member 10 shown. The solder of the solder material layer 220c flows by the heat so that the chip connection pad 120 and the bump body 220a can be bonded to each other. Thereafter, the solder can be cooled and the solder material layer 232c can be transformed into Figure 5 Solder layer 220b is shown.

[0073] The solder layer 220b may also include an intermetallic compound generated by a solder component and a chemical reaction derived from the solder material layer 220c. The chemical reaction may include at least one of a chemical reaction between the solder material layer 220c and the bump body 220a and a chemical reaction between the solder material layer 220c and the chip connection pad 120. The intermetallic compound may include, for example, nickel-tin (Ni3Sn4) or copper-tin (Cu-Sn).

[0074] Subsequently, a filling material layer 610 may be formed in an area where the base body 110 and the first chip body part 210 overlap in the z direction. The filling material layer 610 may include a polymer material. For example, the filling material layer 610 may be formed by an underfill process using an underfill. In some embodiments, the process of forming the filling material layer 610 may be omitted. Fig. 9 In the described process of forming the mold layer 710 , a process of filling the overlapping region of the base body 110 and the first chip body part 210 with a molding material may be performed together.

[0075] Reference FIG. 6A to FIG. 6C , a second semiconductor chip 30 may be provided. The second semiconductor chip 30 may include a second chip body part 310. The second chip body part 310 may include a front surface 310S1 and a rear surface 310S2.

[0076] A second chip front bump 320 may be formed on the front surface 310S1 of the second chip body part 310. A second chip rear connection structure 330 may be formed in a region adjacent to the rear surface 310S2 of the second chip body part 310. In addition, in the second chip body part 310, a second chip passivation layer 310a may be formed in an inner region adjacent to the rear surface 310S2. Figure 6C , a second chip back connection structure 330 may be formed in the groove pattern 312 formed inside the second chip passivation layer 310a. Each second chip back connection structure 330 may include a barrier layer 331, a lower metal layer 332a, and a solder material layer 332c. In addition, referring again to Fig. 6A In the second chip body part 310 , a second chip through via 340 electrically connecting the second chip front bump 320 to the second chip rear connection structure 330 may be formed.

[0077] In one embodiment, in addition to the second chip front bump 320, FIG. 6A to FIG. 6C The configuration of the second semiconductor chip 30 shown in FIG. Figure 4A and Figure 4B The configuration of the first semiconductor chip 20 described is substantially the same. That is, the configuration of the second chip body 310, the second chip passivation layer 310a, the second chip back connection structure 330 and the second chip through-hole 340 of the second semiconductor chip 30 may be substantially the same as the configuration of the first chip body 210, the first chip passivation layer 210a, the first chip back connection structure 230 and the first chip through-hole 240 of the first semiconductor chip 20.

[0078] Reference FIG. 6A to FIG. 6C The area of ​​each second chip front bump 320 located on the front surface 310S1 of the second semiconductor chip 30 may be larger than Figure 4B The area of ​​each solder material layer 232c located on the rear surface 210S2 of the first semiconductor chip 20 is shown. Fig. 7A and Figure 7B When the corresponding second chip front bumps 320 and the solder material layer 232c are respectively bonded, each second chip front bump 320 can cover the entirety of each solder material layer 232c at the bonding interface. In this case, the bonding interface can be substantially the same plane as the rear surface 210S2 of the first chip main body 210.

[0079] Reference Fig. 6A and Figure 6B Each second chip front bump 320 may have a second pitch size of pitch Pb with the second chip front bump 320 adjacent in the lateral direction (ie, x direction) on the front surface 310S1. The pitch Pb of the second chip front bump 320 may correspond to Figure 4A The pitch Pb of the first chip back connection structure 230 of the first semiconductor chip 20 is shown. Fig. 6A and Figure 6C The second chip back connection structure 330 may have a predetermined interval Pb with other second back connection structures adjacent to the second chip back connection structure in the lateral direction (ie, the x direction).

[0080] Reference Fig. 6A and Figure 6B, a first polymer adhesive layer 620 surrounding the second chip front bump 320 may be formed on the front surface 310S1 of the second chip body part 310. The first polymer adhesive layer 620 may include, for example, a polymer material such as a resin. For example, the first polymer adhesive layer 620 may include a non-conductive film (NCF).

[0081] The method of forming the first polymer adhesive layer 620 can be performed using the following various embodiments. In one embodiment, an adhesive film of a polymer component can be prepared. The adhesive film can be attached by applying pressure on the front surface 310S1 of the second chip body 310. Thus, the adhesive film can cover the second chip front bump 320. At this time, the adhesive film can be selectively removed so that the adhesive film is not applied to a surface 320S of the second chip front bump 320. In another embodiment, a liquid polymer adhesive with a predetermined viscosity can be prepared. For example, by applying a coating method, a polymer adhesive can be coated on the front surface 310S1 of the second chip body 310. Then, the coated polymer adhesive may not be completely cured, so that the incompletely cured adhesive can cover the second chip front bump 320. At this time, the polymer adhesive that is not completely cured can be selectively removed so that the polymer adhesive is not applied to a surface 320S of the second chip front bump 320. In another embodiment, a photosensitive polymer adhesive can be prepared. A photosensitive polymer adhesive may be applied to the front surface 310S1 of the second chip body portion 310 so that the photosensitive polymer adhesive may cover the second chip front bumps 320. Thereafter, the photosensitive polymer adhesive may be selectively exposed and developed to selectively remove the polymer adhesive applied to one surface 320S of each second chip front bump 320. By applying the methods of the various embodiments described above, a first polymer adhesive layer 620 surrounding the second chip front bumps 320 may be formed on the front surface 310S1. As a result of forming the first polymer adhesive layer 620 by the various methods described above, as shown in FIG. Figure 6B As shown, one surface 320S of each second chip front bump 320 and one surface 620S of the first polymer adhesive layer 620 may be disposed on substantially the same plane.

[0082] Reference Fig. 7A and Figure 7B , the second semiconductor chip 30 may be stacked on the first semiconductor chip 20. For example, by applying heat and pressure, Figure 4B The solder material layer 232c in the first chip back connection structure 230 of the first chip body part 210 shown in FIG. Fig. 6A and Figure 6BThe second chip front bump 320 of the second chip body 310 is shown. During the bonding process, the solder material layer 232c may be transformed into the solder layer 232b. In addition, in the z direction, the space between the first chip body 210 and the second chip body 310 may be filled with the first polymer adhesive layer 620.

[0083] As mentioned above Fig. 6A and Figure 6B The area of ​​each second chip front bump 320 located on the front surface 310S1 of the second chip main body 310 may be larger than that of the above reference Figure 4B The area of ​​the soldering material layer 232c located on the rear surface 210S2 of the first chip main body 210. Therefore, as a result of bonding the second chip front bumps 320 and the soldering material layer 232c corresponding to each other, at the bonding interface, each second chip front bump 320 can each cover the entirety of the soldering layer 232b. The bonding interface and the rear surface 210S2 of the first chip main body 210 can be substantially the same plane.

[0084] Reference Figure 8 , the third semiconductor chip 40 may be stacked on the second semiconductor chip 30. The third semiconductor chip 40 may include a third chip body part 410. The third chip body part 410 may include a front surface 410S1 and a rear surface 410S2.

[0085] A third chip front bump 420 may be formed on the front surface 410S1 of the third chip body 410. A third chip rear connection structure 430 may be formed in an area adjacent to the rear surface 410S2 of the third chip body 410. In addition, the third chip body 410 may include a third chip passivation layer 410a formed in an inner area adjacent to the rear surface 410S2. A third chip through-hole 440 connecting the third chip front bump 420 to the third chip rear connection structure 430 may be formed inside the third chip body 410.

[0086] The configuration of the third semiconductor chip 40 may be substantially the same as that of the second semiconductor chip 30. That is, the configuration of the third chip body 410, the third chip passivation layer 410a, the third chip front bump 420, the third chip rear connection structure 430, and the third chip through-hole 440 may be substantially the same as that of the second chip body 310, the second chip passivation layer 310a, the second chip front bump 320, the second chip rear connection structure 330, and the second chip through-hole 340.

[0087] In some embodiments, the uppermost semiconductor chip among the plurality of semiconductor chips sequentially stacked on the base member 10 of the semiconductor package may not include a through chip via and a chip post connection structure. Figure 8, unlike what is shown, the third semiconductor chip 40 provided as a top layer on the base member 10 may not include the third chip back connection structure 430 and the third chip through via 440 .

[0088] Meanwhile, the method of stacking the third semiconductor chip 40 on the second semiconductor chip 30 may be the same as that described above with reference to Fig. 7A and Figure 7B The described method of stacking the second semiconductor chip 30 on the first semiconductor chip 20 is substantially the same.

[0089] Reference Fig. 9 , a molding layer 710 may be formed to cover the first to third semiconductor chips 20, 30, and 40 on the base member 10. In the method of forming the molding layer 710, for example, an epoxy molding compound (EMC) may be provided on the base member 10 to bury the first to third semiconductor chips 20, 30, and 40. In some embodiments, in reference to Figure 5 In the bonding process of the base member 10 and the first semiconductor chip 20 described above, when the process of forming the filling material layer 610 in the region where the base body 110 and the first chip body 210 overlap in the z direction is omitted, Fig. 9 The process of filling the epoxy molding material in the region where the base body 110 and the first chip body part 210 overlap in the z direction is performed in the forming operation of the molding layer 710 .

[0090] Reference Fig.10 , a connection structure 510 may be formed on the second surface 110S2 of the base body 110. The connection structures 510 may be formed on each of the bump pads 140. Each of the connection structures 510 may be a solder bump or a solder ball.

[0091] Through the above-mentioned processes, the semiconductor package according to one embodiment of the present disclosure can be manufactured.

[0092] The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure and the accompanying claims.

[0093] CROSS-REFERENCE TO RELATED APPLICATIONS

[0094] This application claims priority from Korean Application No. 10-2020-0043654, filed on Apr. 9, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: a first semiconductor chip including a first chip body portion and a first chip back bump disposed in a recessed region recessed into the first chip body portion; as well as a second semiconductor chip, the second semiconductor chip being stacked on the first semiconductor chip and comprising a second chip main body portion and a second chip front bump protruding from the second chip main body portion, Wherein, the first chip back bump includes a lower metal layer and a welding layer arranged on the lower metal layer, The second chip front bump is bonded to the solder layer, and The second chip front bump is arranged to cover at least the solder layer on a bonding surface between the second chip front bump and the solder layer. The semiconductor package further comprises a polymer adhesive layer, wherein the polymer adhesive layer is located between the first chip main body portion and the second chip main body portion, and Wherein, the welding layer is isolated from the polymer adhesive layer.

2. The semiconductor package according to claim 1, in, The solder layer is isolated from the polymer adhesive layer by the second chip front bump and the first chip body portion.

3. The semiconductor package according to claim 1, wherein: The first semiconductor chip further includes: a groove pattern formed in the recessed area; and a barrier layer disposed along an inner surface of the groove pattern, wherein the lower metal layer is disposed on a portion of the barrier layer corresponding to the bottom of the groove pattern, and The welding layer is disposed on the lower metal layer.

4. The semiconductor package according to claim 3, in, The solder layer is isolated from the polymer adhesive layer by at least one of the second chip front bump, the first chip body portion, and the barrier layer.

5. The semiconductor package according to claim 1, in, The first semiconductor chip includes a first through chip via, and the second semiconductor chip includes a second through chip via, wherein the first chip through hole penetrates the first chip main body to be electrically connected to the first chip rear bump, and The second chip through via penetrates the second chip body portion to be electrically connected to the second chip front bump.

6. The semiconductor package according to claim 1, further comprising a first chip passivation layer, the first chip passivation layer being disposed in the first chip body portion and surrounding the first chip back bump, in, The first chip passivation layer includes an inorganic material.

7. The semiconductor package according to claim 6, wherein: The polymer adhesive layer surrounds the second chip front bump, The bonding surface between the second chip front bump and the welding layer and the bonding surface between the polymer adhesive layer and the first chip passivation layer are in the same plane.

8. The semiconductor package according to claim 6, wherein: The first chip passivation layer includes any one selected from silicon oxide, silicon nitride and silicon oxynitride.

9. The semiconductor package according to claim 1, wherein: The polymer adhesive layer includes a non-conductive film.

10. A semiconductor package, comprising: base member; a first semiconductor chip disposed on the base member; as well as a second semiconductor chip, the second semiconductor chip being disposed on the first semiconductor chip, Wherein, the first semiconductor chip comprises: a first chip body portion, the first chip body portion including a front surface and a rear surface; and a first chip rear bump, the first chip rear bump being disposed in a recessed area recessed from the rear surface into the first chip main body portion, Wherein, the second semiconductor chip comprises: a second chip body portion, the second chip body portion including a front surface and a rear surface; and a second chip front bump, the second chip front bump protruding from the front surface of the second chip main body, Wherein, the first chip back bump includes a lower metal layer and a welding layer arranged on the lower metal layer, The solder layer of the first semiconductor chip and the second chip front bump of the second semiconductor chip are bonded to each other, and The second chip front bump is arranged to cover at least the solder layer on a bonding surface between the second chip front bump and the solder layer. The semiconductor package further comprises a polymer adhesive layer, the polymer adhesive layer being arranged between the rear surface of the first chip body portion and the front surface of the second chip body portion, and Wherein, the welding layer is isolated from the polymer adhesive layer.

11. The semiconductor package according to claim 10, wherein: The first semiconductor chip further includes: a groove pattern formed in the recessed area; and a barrier layer disposed along an inner surface of the groove pattern, wherein the lower metal layer is disposed on a portion of the barrier layer corresponding to the bottom of the groove pattern, and The welding layer is disposed on the lower metal layer.

12. The semiconductor package according to claim 10, wherein: The base member includes one of an insert and a printed circuit board.

13. The semiconductor package according to claim 10, wherein: The polymer adhesive layer surrounds the second chip front bump.

14. The semiconductor package according to claim 13, wherein: The polymer adhesive layer includes a non-conductive film.

15. The semiconductor package according to claim 10, further comprising a first chip passivation layer, the first chip passivation layer being disposed in the first chip body portion and surrounding the first chip back bump, in, The first chip passivation layer includes an inorganic material.

16. The semiconductor package according to claim 15, wherein: The first chip passivation layer includes any one selected from silicon oxide, silicon nitride and silicon oxynitride.

17. The semiconductor package according to claim 15, wherein: The bonding surface of the second chip front bump and the solder layer is in the same plane as the bonding surface of the polymer adhesive layer and the first chip passivation layer.

18. The semiconductor package according to claim 10, further comprising: a first chip through hole penetrating the first chip main body to be electrically connected to the first chip back bump, and A second through chip via penetrates the second chip body portion to be electrically connected to the second chip front bump.

19. A method for manufacturing a semiconductor package, the method comprising the following steps: Prepare a first semiconductor chip, the first semiconductor chip comprising a first chip main body and a first chip rear bump disposed in a recessed region recessed into the first chip main body, the first chip rear bump comprising a lower metal layer and a solder material layer disposed on the lower metal layer; preparing a second semiconductor chip, the second semiconductor chip comprising a second chip main body and a second chip front bump protruding from the second chip main body; as well as bonding the solder material layer of the first semiconductor chip and the second chip front bump of the second semiconductor chip to form a solder layer, wherein the second chip front bump and the soldering layer are bonded to each other so that the second chip front bump at least covers the soldering layer on a bonding surface of the second chip front bump and the soldering layer, The method further comprises the following steps: forming a polymer adhesive layer between the rear surface of the first chip main body and the front surface of the second chip main body and on the second chip main body; The second chip front bump and the soldering layer are bonded to each other, so that the soldering layer and the polymer adhesive layer are separated from each other.

20. The method according to claim 19, in, The polymer adhesive layer surrounds the side surface of the second chip front bump.

21. The method according to claim 19, further comprising the steps of: preparing a base member including a base body, the base member including a chip connection pad disposed on a surface of the base body; as well as The first semiconductor chip is stacked on the surface of the base body, the chip connection pad is electrically connected to the first chip front bump of the first chip body, The first chip front bump of the first chip main body is located on an opposite side of the first chip rear bump relative to the first chip main body.

22. The method according to claim 19, wherein: The step of preparing the first semiconductor chip comprises the following steps: forming a groove pattern in the recessed area of ​​the first chip body portion; forming a barrier layer along the inner surface of the groove pattern; forming the lower metal layer on a portion of the barrier layer corresponding to a bottom of the groove pattern; and The solder material layer is formed on the lower metal layer.

23. The method according to claim 22, wherein: The step of preparing the first semiconductor chip further includes the steps of: forming a first chip passivation layer having a predetermined thickness in an inward direction of the first chip body portion from a rear surface of the first chip body portion, and Wherein, the first chip passivation layer is formed to cover the barrier layer.

24. The method according to claim 23, in, The step of bonding the welding material layer and the second chip front bump includes the following steps: bonding the welding material layer and the second chip front bump so that the bonding surface of the welding material layer and the second chip front bump becomes the same plane as the bonding surface of the polymer adhesive layer and the first chip passivation layer.

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