Integrated circuit and method of forming the same

Abstract

A semiconductor process system etches a gate metal located on a semiconductor wafer. The semiconductor process system includes an analysis model based on machine learning. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process condition data for a next etching process. Embodiments of the present application provide integrated circuits and methods for forming the same.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing. More specifically, the present invention relates to etching processes used in semiconductor manufacturing. Background Art

[0002] There has been a continuing demand to increase the computing power of electronic devices, including smartphones, tablet computers, desktop computers, laptop computers, and many other types of electronic devices. Integrated circuits provide the computing power for these electronic devices. One way to increase computing power in integrated circuits is to increase the number of transistors and other integrated circuit components that can be included in a given area of ​​a semiconductor substrate.

[0003] In order to continue to reduce the size of components in integrated circuits, various thin film deposition techniques, etching techniques and other processing techniques have been implemented. These techniques can form very small components. However, these techniques also face serious difficulties in ensuring that the components are properly formed. Summary of the invention

[0004] An embodiment of the present application provides an integrated circuit, comprising: an interlayer dielectric layer; a first transistor, wherein the first transistor comprises: a first trench formed in the interlayer dielectric layer; a gate dielectric disposed on the bottom of the first trench, a gate electrode, the gate electrode comprising: a first gate metal disposed on the gate dielectric at the bottom of the first trench, a silicide disposed in the first trench above the first gate metal; a conductive gate filling material disposed above the first gate metal and the silicide in the first trench; wherein the conductive gate filling material extends to a higher vertical level within the first trench than the first gate metal.

[0005] An embodiment of the present application provides a method, comprising: forming a first trench in an interlayer dielectric layer above a plurality of first semiconductor nanosheets corresponding to a channel region of a first transistor; depositing a gate dielectric on a bottom of the first trench; depositing a first gate metal of the first transistor in the first trench on the gate dielectric; forming a silicide on top of the first gate metal in the first trench; filling the first trench above the first gate metal and the silicide with a conductive gate filling material, wherein the conductive gate filling material extends to a higher vertical level within the first trench than the first gate metal.

[0006] An embodiment of the present application also provides a method, comprising: training an analysis model with a machine learning process to select parameters for an atomic layer etching process; depositing a gate metal of a transistor in a trench in an interlayer dielectric layer of an integrated circuit; selecting etching parameters for etching the gate metal with the analysis model; and etching the gate metal with the atomic layer etching process based on the selected etching parameters; and forming a silicide above the gate metal in the trench.

[0007] Embodiments of the present application provide a semiconductor device having a silicide gate filling structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1N are cross-sectional views of an integrated circuit at various stages of processing according to one embodiment.

[0009] Figure 1O to Figure 1Q are cross-sectional views of an integrated circuit at various stages of processing in accordance with an alternative embodiment.

[0010] Figure 2A is an illustration of a semiconductor processing system according to one embodiment.

[0011] Figure 2B is a graph showing fluid flow during a cycle of an atomic layer etch process.

[0012] Figure 3A It is a block diagram of the control system of a semiconductor process system.

[0013] Figure 3B is a block diagram of an analysis model according to one embodiment.

[0014] Figure 4 is a flow chart of a process for training an analytical model of a control system according to one embodiment.

[0015] Figure 5 is a flow chart of a process for performing a thin film deposition process in conjunction with an analytical model according to one embodiment. DETAILED DESCRIPTION

[0016] In the following description, many thicknesses and materials for various layers and structures within the integrated circuit die are described. For various embodiments, specific dimensions and materials are given in an exemplary manner. According to the present invention, those skilled in the art will recognize that other dimensions and materials can be used in many cases without departing from the scope of the present invention.

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include an embodiment in which the first and second features are directly contacted to form, and may also include an embodiment in which additional features are formed between the first feature and the second feature. The first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Further, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to easily describe the relationship of one element or component to another element or component as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present invention. However, those skilled in the art will appreciate that the present invention can be practiced without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present invention.

[0020] Unless the context requires otherwise, throughout the specification and the claims that follow, the word "comprise" and variations such as "consisting of" and "composed of" are to be interpreted in an open, inclusive sense, ie, "including, but not limited to."

[0021] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of sequential hierarchy but may simply distinguish multiple instances of an action or structure.

[0022] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular component, structure, or feature described in conjunction with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily all refer to the same embodiment. Furthermore, in one or more embodiments, particular components, structures, or features may be combined in any suitable manner.

[0023] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise.

[0024] Embodiments of the present invention provide a full-ring gate nanosheet transistor with a low-resistance gate electrode. Embodiments of the present invention can provide multiple types of full-ring gate transistors with different threshold voltages while still providing a low-resistance gate electrode. Different threshold voltages are obtained by selectively including or excluding individual thin gate metal layers in the gate structure. The threshold voltage of the transistor is based in part on the presence or absence of a thin gate metal layer in the gate structure. Low resistance is obtained by ensuring that the thin gate metal layer does not extend very high within the gate trench, so that the low-resistance gate fill material can fill more of the trench. The individual thin gate metal layers are carefully etched using a controlled etching process using machine learning techniques.

[0025] Embodiments of the present invention utilize machine learning techniques to adjust etching process parameters for etching thin gate metal layers between etching processes or even during etching processes. Embodiments of the present invention utilize machine learning techniques to train analytical models to determine process parameters that should be implemented for the next etching process or even for the next stage of the current etching process. As a result, the thin film etching process produces a thin film with a residual thickness and composition that reliably falls within the target specifications. If the thin gate metal layer is not formed correctly, the integrated circuit containing the thin gate metal layer will not have performance problems that may cause. In addition, a batch of semiconductor wafers will have an improved yield and fewer scrapped wafers.

[0026] Figure 1A 24 are cross-sectional views of integrated circuit 100 at successive intermediate processing stages according to one embodiment. Figure 1A 24 show an exemplary process for producing an integrated circuit including multiple types of transistors. Each type of transistor has a threshold voltage different from that of other types of transistors. Figure 1A FIG. 24 shows how to form all these types of transistors in a simple and efficient process according to the principles of the present invention. Other process steps and combinations of process steps may be utilized without departing from the scope of the present invention. Figure 1A FIG. 24 shows a process for forming an N-channel transistor of an ultra-low threshold voltage type, a low threshold voltage type, and a standard threshold voltage type. The process for forming these types of P-channel transistors is substantially the same as the process for forming an N-channel transistor, except that for the N-channel process, the process for a specific ultra-low threshold voltage transistor and a standard threshold voltage transistor is opposite to the P-channel process. This will be further elaborated below.

[0027] Figure 1A is a cross-sectional view of an integrated circuit 100 at an intermediate processing stage according to one embodiment. Figure 1A The view of FIG. 1 shows transistor 102, transistor 104, and transistor 106. Each of transistors 102, 104, and 106 is formed in the same integrated circuit 100. Transistors 102, 104, and 106 all have different threshold voltages. Figure 1A In the process stage shown in FIG. , transistors 102, 104 and 106 have the same structure. Figure 1A , the reference numbers applied to transistor 102 are applied to similar structures in transistors 104 and 106. Transistor 102 corresponds to an ultra-low threshold voltage transistor. Transistor 104 corresponds to a low threshold voltage transistor. Transistor 106 corresponds to a standard threshold voltage transistor. In other words, the threshold voltage of transistor 106 is greater than the threshold voltage of transistor 104. The threshold voltage of transistor 104 is greater than the threshold voltage of transistor 102.

[0028] Transistors 102, 104, and 106 are all-around gate (GAA) transistors. The all-around gate transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, spacings smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0029] Integrated circuit 100 includes semiconductor substrate 102. In one embodiment, substrate 102 includes a single crystal semiconductor layer located on at least a surface portion. Substrate 102 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In this embodiment, substrate 102 is made of Si. Substrate 102 may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain region. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material, such as but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a specific embodiment, substrate 102 includes a silicon germanium (SiGe) buffer layer epitaxially grown on silicon substrate 102. The germanium concentration of the SiGe buffer layer can be increased from 30 atomic % germanium for the bottommost buffer layer to 70 atomic % germanium for the topmost buffer layer. The substrate 102 may include various regions that have been appropriately doped with a dopant (e.g., p-type or n-type conductivity). The dopant is, for example, boron (BF) for n-type transistors. 2 ) and phosphorus for p-type transistors.

[0030] The integrated circuit 100 includes a shallow trench isolation 108. The shallow trench isolation 108 can be used to separate groups of transistor structures formed in combination with the semiconductor substrate 110. The shallow trench isolation 108 may include a dielectric material. The dielectric material used for the shallow trench isolation 108 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG) or low-K dielectric materials formed by LPCVD (low pressure chemical vapor deposition), plasma CVD or flowable CVD. Without departing from the scope of the present invention, other materials and structures can be used for the shallow trench isolation 108.

[0031] Integrated circuit 100 includes a plurality of semiconductor nanosheets 111 or nanowires. Semiconductor nanosheets 111 are layers of semiconductor material. Semiconductor nanosheets 111 correspond to channel regions of transistors 102, 104, and 106. Stacked semiconductor nanosheets 111 are formed over substrate 102. Semiconductor nanosheets 111 may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In one embodiment, semiconductor nanosheets 111 are the same semiconductor material as substrate 110. Other semiconductor materials may be used for semiconductor nanosheets 111 without departing from the scope of the present invention.

[0032] exist Figure 1A , each transistor 102, 104, and 106 has three semiconductor nanosheets 111. However, in practice, each transistor 102, 104, and 106 may have more than three semiconductor nanosheets 111. For example, each transistor 102 may include between 8 and 20 semiconductor nanosheets 111. Other numbers of semiconductor nanosheets 111 may be utilized without departing from the scope of the present invention.

[0033] The semiconductor nanosheet 111 may have a thickness between 2 nm and 50 nm. In one embodiment, the semiconductor nanosheet 111 has a thickness between 5 nm and 20 nm. In one embodiment, each nanosheet 111 is thicker than the nanosheet 111 above it. In one embodiment, each nanosheet 111 is shorter than the nanosheet above it. The semiconductor nanosheet 111 may have other thicknesses without departing from the scope of the present invention.

[0034] Integrated circuit 100 includes gate structure 114. Gate structure 114 is disposed between semiconductor nanosheets 111. In practice, gate structure 114 surrounds nanosheets 111 except where nanosheets 111 meet source and drain regions 112. Figure 1A At the processing stage shown, each gate structure 114 includes a high-K dielectric layer 120, an interfacial dielectric layer 122, a first gate metal 118, and a void 116. The high-K dielectric layer 120 and the interfacial dielectric layer 122 collectively form the gate dielectric of the transistors 102, 104, and 106. The high-K dielectric layer 120 and the interfacial dielectric layer 122 physically separate the semiconductor nanosheet 111 from the metal or metals of the gate structure 114. Figure 1A At the processing stage shown, only the first gate metal 118 is present. However, after further processing stages, other gate metals will be present in the gate structure 114. The high-K dielectric layer 120 and the interfacial dielectric layer 122 isolate these gate metals from the semiconductor nanosheet 111 corresponding to the channel region of the transistor.

[0035] In order to create a good interface between the semiconductor nanosheet 111 and the gate structure 114 and to suppress the reduction in the mobility of the channel carriers of the semiconductor device, an interface layer can be used. The interface dielectric layer 122 may include a dielectric material, such as silicon oxide, silicon nitride or other suitable dielectric materials. The interface dielectric layer 122 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The interface dielectric layer 122 may have a thickness between 0.5 nm and 3 nm. On the lower nanosheet 111, the thickness of the interface dielectric layer 122 may be greater. Without departing from the scope of the present invention, other materials, deposition processes and thicknesses may be used for the interface dielectric layer 122.

[0036] The high-K dielectric layer 120 includes one or more layers of dielectric materials such as silicon oxide, silicon nitride, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloys, other suitable high-K dielectric materials and / or combinations thereof. The high-K dielectric layer 120 can be formed by CVD, ALD or any suitable method. In one embodiment, in order to ensure that a gate dielectric layer with uniform thickness is formed around each semiconductor nanosheet 111, a high conformal deposition process such as ALD is used to form the high-K dielectric layer 120. In one embodiment, the thickness of the high-K dielectric is in the range of about 1 nm to about 6 nm. Without departing from the scope of the present invention, other thicknesses, deposition processes and materials may be used for the high-K dielectric layer 120. The high-K dielectric layer 120 may include a first layer and a second layer, the first layer including HfO having a dipole doping containing La and Mg. 2 The second layer includes a ZrO layer having a crystallized high-k. The high-k dielectric layer may be patterned using a controlled ALE process, as will be described in further detail below. The peak intensity of oxygen in the high-k dielectric layer of transistor 106 may be higher than that of transistors 102 and 104.

[0037] In one embodiment, the first gate metal 118 includes titanium nitride. Physical vapor deposition (PVD), atomic layer deposition, chemical vapor deposition or other suitable deposition processes can be used to deposit the first gate metal 118. The first gate metal 118 can have a thickness between 1nm and 5nm. The gate metal 118 can include metals such as Ti, Ta, W, Mo and compounds of oxygen and nitrogen. Accordingly, the gate metal can include TaN, WN and MoN. Without departing from the scope of the present invention, other materials, deposition processes and thicknesses can be used for the first gate metal 118.

[0038] The gate structure 114 may also include a sidewall spacer 124. The sidewall spacer 124 may include a multilayer dielectric material. The multilayer dielectric material may include silicon nitride, SiON, SiOCN, SiCN, silicon oxide, or other dielectric materials. Other dielectric materials may be used for the sidewall spacer 124 without departing from the scope of the present invention.

[0039] The source and drain regions 112 include semiconductor materials. The source and drain regions 112 may be epitaxially grown from the semiconductor nanosheet 111. The source and drain regions 112 may be epitaxially grown from the semiconductor nanosheet 111 and other semiconductor layers at the location previously occupied by the gate structure 114. In the case of an N-type transistor, the source and drain regions 112 may be doped with an N-type dopant species. In the case of a P-type transistor, the source and drain regions 112 may be doped with a P-type dopant species.

[0040] The integrated circuit 100 includes an interlayer dielectric layer 128 disposed on the source and drain regions 112. The interlayer dielectric layer 128 may include one or more of silicon oxide, silicon nitride, SICOH, SiOC, or an organic polymer. Other types of dielectric materials may be used for the interlayer dielectric layer 128 without departing from the scope of the present invention.

[0041] The integrated circuit 100 includes a trench 138 formed in the interlayer dielectric layer 128. The trench 138 corresponds to the future metal gate region of the transistors 102, 104 and 106. The trench 138 is defined by a first sidewall spacer 134. The first sidewall spacer 134 is the same material as the sidewall spacer 124 of the gate structure 114 and can be formed in the same deposition process. The bottom of the trench 138 includes an interfacial dielectric layer 122. The portion of the interfacial dielectric layer 122 formed on the top surface of the uppermost semiconductor nanosheet 111 at the bottom of the trench 138 is formed in the same process as the interfacial dielectric layer 122 of the gate structure 114. The high-K dielectric layer 120 is formed on the top surface of the interlayer dielectric layer 128, on the sidewalls of the trench 138, and on top of the portion of the interfacial dielectric layer 122 at the bottom of the trench 138. The first gate metal 118 is formed on the high-K dielectric layer 122 in the trench and on the top of the interlayer dielectric layer 128. The bottom of each trench 138 corresponds to the top surface of the uppermost semiconductor nanosheet 111.

[0042] As mentioned earlier, in Figure 1A At the processing point shown, transistor 102, transistor 104, and transistor 106 have identical structures. In subsequent processing steps, differentiation will be made in the gate metal that forms each transistor 102, 104, and 106.

[0043] The bottom of each trench 138 corresponds to the top surface of the uppermost semiconductor nanosheet 111 .

[0044] exist Figure 1B , mask 140 has been formed on first gate metal layer 118 of transistor 106. The mask fills trench 138 of transistor 106. Mask 140 is patterned so that the mask is not present on first gate metal layer 118 of transistor 102 and transistor 104. Accordingly, first gate metal 118 for transistor 102 and transistor 104 is exposed. Mask 140 may include patterned photoresist. Patterned photoresist may be implemented using standard photolithography processes.

[0045] exist Figure 1C , the first gate metal 118 has been removed at the transistor 102 and the transistor 104. Notably, the first gate metal 118 is removed from the trench 138 and from both the gate structures 114 of the transistor 102 and the transistor 104. One result is that the void 116 of the gate structures 114 of the transistor 102 and the transistor 104 is larger than the void 116 of the gate structure 114 of the transistor 106 where the first gate metal 118 is still present. The first gate metal 118 may be removed by wet etching, dry etching, or any other suitable etching process.

[0046] exist Figure 1D , the photoresist mask 140 has been removed from the transistor 106. Accordingly, the first gate metal 118 is exposed at the transistor 106. The photoresist mask 140 may be removed by any standard photoresist removal process.

[0047] exist Figure 1E , the first gate metal 118 has been etched back within the trench 138 of the transistor 106. The first gate metal 118 has not been completely removed from the trench 138 of the transistor 106. Instead, the first gate metal 118 has been etched back using a controlled etch that is selected to leave a remaining portion 142 of the first gate metal 118 on the high-K dielectric layer 120 at the bottom of the trench 138 of the transistor 106 while removing the first gate metal 118 from the high-K dielectric layer 120 on the sidewalls of the trench 138. Accordingly, in one example, the first gate metal 118 is removed from the sidewalls of the trench 138 while leaving a remaining portion 142 at the bottom of the trench 138.

[0048] In one embodiment, the controlled etching process used to etch back the first gate metal 118 is an atomic layer etching (ALE) process. In one embodiment, the ALE process is used to etch the titanium nitride first gate metal 118 to produce Figure 1EThe structure shown in transistor 106 of FIG. The ALE process is similar to the atomic layer deposition process (ALD). In the atomic layer etching process, different gases, fluids or materials are flowed into the process chamber for selected time periods. Each cycle of the ALE process includes flowing multiple materials at different stages. Each cycle can cause the removal of an atomic or molecular layer of the titanium nitride first gate metal 118.

[0049] In one example, the ALE cycle includes flowing WCI5 into the process chamber for a selected period of time, such as between 1 s and 10 s. The ALE cycle then includes a purge phase in which argon gas is flowed into the process chamber for a selected period of time, such as between 6 s and 15 s. The ALE cycle then includes flowing O 2 Flow into the process chamber. The ALE cycle then includes a second purge phase in which argon gas is flowed into the process chamber for a selected period of time, such as between 2s and 15s. Each cycle causes the removal of an atomic or molecular layer of the titanium nitride first gate metal 118. By controlling the number of cycles in the ALE process, the amount of the titanium nitride layer first gate metal 118 to be etched can be strictly controlled. Other ALE processes, cycles, durations, and materials may be utilized without departing from the scope of the present invention.

[0050] As will be described in more detail below, a machine learning process is utilized to dynamically select parameters for the ALE process. The machine learning process trains an analytical model to dynamically select parameters for each ALE process. In order to remove the desired amount of titanium nitride first gate metal, the analytical model can select the material, flow duration, flow pressure, temperature, and other parameters associated with the ALE process. Although an example in which the first gate metal 118 is titanium nitride is described herein, the first gate metal 118 may include other materials other than titanium nitride without departing from the scope of the present invention.

[0051] exist Figure 1F, the second gate metal 144 has been deposited on the integrated circuit 100. In particular, the second gate metal 144 is deposited on the high-K dielectric layer 120 in the trench 138 and in the gap 116 of the transistor 102, transistor 104, 106. The second gate metal 144 is deposited on the remaining portion 142 of the first gate metal at the bottom of the trench 138 and on the first gate metal 118 in the gap 116 of the transistor 106. The second gate metal 144 can be deposited by a PVD process, a CVD process, or an ALD process. In one example, the second gate metal includes titanium nitride. Alternatively, the second gate metal 144 can include one or more of TaN, WN, MoN or other suitable materials. The second gate metal 144 can have a thickness between 1nm and 5nm. The second gate metal 144 can be the same material as the first gate metal 118 or a different material. Without departing from the scope of the present invention, other materials, deposition processes and thicknesses can be used for the second gate metal 144.

[0052] exist Figure 1G , mask 146 has been formed on the second gate metal 144 of transistor 104 and transistor 106. Mask 146 fills the trench 138 of transistor 104 and transistor 106. Mask 146 is patterned so that the mask is not present on the second gate metal layer 144 of transistor 102. Accordingly, the second gate metal layer 144 for transistor 102 is exposed. Mask 140 may include a patterned photoresist. The patterned photoresist may be implemented using a standard photolithography process.

[0053] exist Figure 1H , the second gate metal 144 has been removed at the transistor 102. Notably, the second gate metal 144 is removed from both the trench 138 and from the gate structure 114 of the transistor 102. One result is that the void 116 of the gate structure 114 of the transistor 102 is larger than the void 116 of the gate structure 114 of the transistor 104 where the second gate metal 144 is still present. The void 116 of the gate structure 114 of the transistor 104 is larger than the void 116 of the gate structure 114 of the transistor 106 where the first gate metal 118 and the second gate metal 144 are still present. The second gate metal 144 may be removed by wet etching, dry etching, or any other suitable etching process.

[0054] exist Figure 1H , the photoresist mask 146 has been removed from the transistor 104 and the transistor 106. Accordingly, the second gate metal 144 is exposed at the transistor 104 and the transistor 106. The photoresist mask 146 may be removed by any standard photoresist removal process.

[0055] exist Fig. 1I 106. In the embodiment of the present invention, the second gate metal 144 has been etched back within the trench 138 of the transistor 104 and the transistor 106. The second gate metal 144 has not been completely removed from the trench 138 of the transistor 104 and the transistor 106. Instead, the second gate metal 144 has been etched back with a controlled etch that is selected to leave a remaining portion 150 of the second gate metal 144 at the bottom of the trenches of the transistor 104 and the transistor 106. In the transistor 104, the remaining portion 150 of the second gate metal 144 is disposed on the high-K dielectric layer 120 at the bottom of the trench 138. In the transistor 106, the remaining portion 150 of the second gate metal 144 is disposed on the remaining portion 142 of the first gate metal 118. The remaining portion 150 may extend vertically over the portion of the high-K dielectric layer 120 in the trench 138 in the transistor 104 and the transistor 106.

[0056] The controlled etching of etching back the second gate metal 144 is similar to that in Figure 1E The etch back process of the first gate metal 118 described in the embodiment is the same type of controlled etching. In particular, the second gate metal 144 can be etched back using an ALE process with dynamically controllable characteristics. The controlled etching can be controlled by an analytical model of the control system. The analytical model can be trained with a machine learning process to select the parameters of the ALE process based on the desired characteristics of the remaining portion 150 of the second gate metal 144.

[0057] exist Figure 1J , a third gate metal 152 has been deposited on the high-K dielectric layer 120 in the trenches of transistors 102, 104, and 106. The third gate metal 152 is disposed on the remaining portion 150 of the second gate metal 144 in the trenches 138 of transistors 104 and 106. The third gate metal 152 is disposed in the void 116 of the gate structure 114 of transistors 102, 104, and 106.

[0058] The third gate metal 152 may be deposited by a PVD process, a CVD process, or an ALD process. In one example, the third gate metal 152 includes titanium nitride. Alternatively, the third gate metal 152 may include one or more of TaN, WN, and MoN or other suitable materials. The third gate metal 152 may have a thickness between 1 nm and 5 nm. Other materials, deposition processes, and thicknesses may be used for the third gate metal 152 without departing from the scope of the present invention.

[0059] exist Figure 1JIn the embodiment, a silicon layer 156 has been formed on the third gate metal 152. In one example, the silicon layer 156 is deposited by a CVD process. In particular, the in-situ silane passivation layer can be deposited by a chemical vapor deposition process. After or during the deposition of the silane passivation layer, a thermal annealing process or other type of thermal treatment can be performed to raise the temperature of the silane to between 420° C. and 500° C. At this elevated temperature, the silane decomposes into silicon and hydrogen. The hydrogen is removed via ventilation, and the silicon layer 156 remains. Other processes can be used to perform the silicon layer 156 without departing from the scope of the present invention. The silicon layer 156 is formed on the third gate metal 152 in the trenches 138 of the transistor 102, the transistor 104, and the transistor 106. The silicon layer 156 is also present in the gate structure 114 of the transistor 102. In the exemplary Figure 1J 1 , because the voids 116 have been completely filled by the previously deposited layers, there is no silicon layer 156 in the gate structures 114 of transistors 104 and 106. However, depending on the size of the voids 116 and the thickness of the previously deposited layers, it is possible that the silicon layer 156 is present in the gate structures 114 of transistors 104 and 106. Furthermore, the silicon layer 156 may not completely fill the remaining voids 116 of the gate structure 114 of transistor 102.

[0060] exist Figure 1K , a titanium layer has been deposited on a silicon layer 156. The titanium layer may be deposited by CVD or another suitable process. The titanium layer 157 may have a thickness between 0.5 nm and 5 nm. In order to heat the titanium layer 157 and the silicon layer 156, a thermal annealing process or another thermal treatment may be performed after or during the deposition of the titanium layer 157. This results in a layer of titanium silicide 159 formed by the silicon layer 156 and the titanium layer 157. In one embodiment, the entirety of the silicon layer 156 and the titanium layer 157 may become a silicide. Alternatively, the silicide 159 may be formed at the interface between the silicon layer 156 and the titanium layer 157, leaving a portion of pure silicon below the silicide and / or a portion of pure titanium above the silicide. Other processes and thicknesses may be utilized for forming the titanium layer 157 and the silicide without departing from the scope of the present invention.

[0061] One advantage of depositing titanium without depositing aluminum is that some conventional processing steps can be avoided. For example, when aluminum is deposited, a protective layer is typically also deposited to prevent oxidation of the aluminum. However, because aluminum is not present, in one example, the formation of the protective layer can be omitted. Other types of silicides can be used for silicide 159. For example, silicide 159 can include TaSi, CoSi, NiSi, WSi, MoSi, and CuSi. In some embodiments, silicide 159 can also include Ge.

[0062] exist Figure 1LIn the embodiment of the present invention, if the entire titanium layer 157 becomes a silicide, an adhesion layer 158 is formed on the titanium layer 157 or on the silicide 159 produced by the titanium layer 157. The adhesion layer 158 is also deposited in the trench 138 of the transistor 102, the transistor 104, and the transistor 106. The adhesion layer 158 may include one or more of TiN, TaN, MoN, or WN. The adhesion layer 158 may be formed by an ALD process and may have a thickness between 0.5 nm and 5 nm. Other materials, processes, and thicknesses may be used for the adhesion layer 158 without departing from the scope of the present invention.

[0063] exist Figure 1L In the embodiment of the present invention, a fourth gate metal layer 160 has been deposited on the titanium nitride adhesion layer 158 in the trenches 138 of transistors 102, 104, and 106. The fourth gate metal layer 160 fills the remaining portion of the trenches 138. In practice, the fourth gate metal layer 160 may fill more than 100% of the trenches 138. Figure 1L A larger portion of the trench 138 is shown. The fourth gate metal 160 is a conductive gate fill material. Although Figure 1L The fourth gate metal layer 160 is shown filling a relatively small portion of the trench 138, in fact, the fourth gate metal layer 160 can fill most of the trench 138. Compared with the width of the trench 138, the thickness of the other layers in the trench 138 can be very small, even when a large number of different kinds of layers are shown, which is difficult to show. Accordingly, the fourth gate metal layer 160 can fill most of the volume of the trench 138. The fourth gate metal layer 160 can be referred to as a gate filling material or metal plug for the trench 138.

[0064] In one embodiment, the fourth gate metal layer 160 is tungsten deposited by a CVD process. Alternatively, the fourth gate metal layer may include one or more of Co, Ru, Ir, Mo, Cu or another low resistivity metal. The fourth gate metal layer 160 may be formed by a PVD process, an ALD process or by other deposition processes. Other materials and processes may be used for the fourth gate metal 160 without departing from the scope of the present invention.

[0065] exist Figure 1M , a chemical mechanical planarization (CMP) process has been performed. The CMP process removes the high-K dielectric material 120, the third gate metal 152, the silicon layer 156, the titanium nitride layer 158, and the fourth gate metal 160 located outside the trench 138. The CMP process also removes a portion of the first sidewall spacer 134 and the interlayer dielectric layer 128.

[0066] The remaining portions of the third gate metal 152, the silicon layer 156, the titanium nitride layer 158, and the fourth gate metal 160 correspond to the gate electrodes 162 of the transistors 102, 104, and 106. The gate electrode 162 of the transistor 104 also includes the remaining portion 150 of the second gate metal 144. The gate electrode 162 of the transistor 106 includes the remaining portion 142 of the first gate metal 118 and the remaining portion 150 of the second gate metal 144.

[0067] The conductive layer in the gate structure 114 is part of the gate electrode 162. The gate electrode 162 surrounds the semiconductor nanosheet 111, and can render a channel region corresponding to the semiconductor nanosheet 111 conductive or non-conductive by applying a voltage to the gate electrode.

[0068] The presence of the remaining portion 150 of the second gate metal 144 and the gate electrode 162 of the transistor 104 causes the transistor 104 to have a higher threshold voltage than the threshold voltage of the transistor 102. The presence of the remaining portion 142 of the first gate metal 118 and the remaining portion 150 of the second gate metal 144 in the transistor 106 causes the transistor 106 to have a higher threshold voltage than the transistor 104. This can be accomplished because the controlled etching process that etches back the first gate metal 118 does not completely remove the first gate metal 118 from the trench 138 of the transistor 106, and because the controlled etching process that etches back the second gate metal 144 does not completely remove the second gate metal 144 from the transistor 104 and the trench 138 of the transistor 106.

[0069] Due to the controlled etching process that defines the remaining portions 142 and 150 of the first gate material and the second gate metal 118, 144, the fourth gate metal 160 extends within the trench 138 to a higher vertical level than the first gate metal 118 and the remaining portions 142 and 150 of the second gate metal 144 in the trench 138 of the transistor 106. The fourth gate metal 160 extends to the top of the trench 138. Similarly, the fourth gate metal 160 extends within the trench 138 of the transistor 104 to a higher vertical level than the remaining portion 150 of the second gate metal 144. This may be one feature of the controlled etching process that ensures the formation of transistors with different threshold voltages.

[0070] The presence of the remaining portions 142 and 150 of the first and second gate metals in the transistor 106 causes the bottom of the fourth gate metal 160 to be further away from the bottom of the trench 138 of the transistor 106 than the fourth gate metal 160 of the transistor 104 is further away from the bottom of the trench 138 of the transistor 104. This contributes to a higher threshold voltage of the transistor 106. This is due in part to the fact that the first and second gate metals 118, 144 have a higher work function than the fourth gate metal 160.

[0071] The presence of the remaining portion 150 of the second gate metal in transistor 104 causes the bottom of the fourth gate metal 160 to be further away from the bottom of the trench 138 of transistor 104 than the fourth gate metal 160 of transistor 102 is further away from the bottom of the trench 138 of transistor 102. This contributes to a higher threshold voltage for transistor 104, in part because the second gate metal 144 has a higher work function than the fourth gate metal 160.

[0072] exist Figure 1N In FIG. 1 , a silicide layer 166 has been formed in the source and drain regions 112 of each transistor 102, 104, and 106. The silicide layer 166 may include titanium silicide, cobalt silicide, or other types of silicide. Figure 1N , a cobalt contact plug 168 has been formed in the interlayer dielectric layer 128 in each transistor 102, 104, and 106. The cobalt contact plug 168 can be used to apply voltage to the source and drain regions 112 of the transistors 102, 104, and 106. The plug 168 is surrounded by a titanium nitride adhesion layer 167. The plug 168, the adhesion layer 167, and the silicide layer 166 may include other materials without departing from the scope of the present invention.

[0073] Figures 1A to 1N The formation of an N-channel transistor is described. A P-channel ultra-low threshold voltage transistor, a P-channel low threshold voltage transistor, and a P-channel standard threshold voltage transistor can be formed during the same process. One difference is that the semiconductor material is doped differently in the areas of the integrated circuit 100 where the P-channel transistors will be formed. For example, the source and drain regions 112 of the P-channel transistor will be doped with P-type dopants. The semiconductor substrate 110 and the semiconductor nanosheets 111 can also be doped according to the process used to dope the P-channel transistors. For the P-channel transistors, Figure 1B The mask 140 shown will fill the trenches associated with the ultra-low threshold voltage P-channel transistor, ultimately resulting in the creation of a remaining portion 142 of the first gate metal 118 in the trench 138 of the ultra-low threshold voltage P-channel transistor, while completely removing the first gate metal 118 from the low threshold voltage and standard threshold voltage P-channel transistors. For the P-channel transistor, Figure 1G The mask 146 shown will fill the trenches 138 associated with the ultra-low threshold voltage P-channel transistor and the low voltage P-channel transistor, ultimately resulting in the creation of the remaining portion 150 of the second gate metal 144 in the trenches 138 of the ultra-low threshold voltage P-channel transistor and the low voltage P-channel transistor. Accordingly, according to one embodiment, Figures 1A to 1N The process shown will form both ultra low voltage, low voltage and standard threshold voltage N-channel transistors and P-channel transistors.

[0074] Figure 1O to Figure 1Q An alternative embodiment for forming integrated circuit 100 is shown. Fig.1O The structure shown is from Fig. 1I 1. The structure shown in FIG. 1 is started. A third gate metal 152 is deposited on the high-K dielectric layer 120 on top of the interlayer dielectric layer 128 and in the trenches 138 of the transistors 102, 104, and 106. After the third gate metal 152 is deposited, a controlled ALE process is performed to etch the third gate metal 152. The ALE process etches the third gate metal 152 from the high-K dielectric layer 120 on top of the interlayer dielectric layer 128 and the sidewalls of the trenches 138 in each transistor 102, 104, and 106. The parameters of the ALE process are selected to ensure that a portion of the third gate metal 152 remains on the bottom of the trenches 138. In fact, a portion of the third gate metal 152 remains on the high-K dielectric layer 120 at the bottom of the trenches 138 of the transistor 102. A portion of the third gate metal 152 remains on the remaining portion 150 of the second gate metal 144 at the bottom of the trenches of the transistors 104 and 106.

[0075] One reason to perform a controlled ALE etch is to reduce the amount of material on the sidewalls of the trench 138 prior to depositing the fourth gate metal 160. A larger volume of the trench 138 can be filled with the highly conductive fourth gate metal 160 as a result.

[0076] exist Figure 1N In the embodiment, a silicide layer 159 has been formed on the third gate metal 152 in the trenches 138 of the transistors 102, 104 and 106. The silicide layer 159 may include the Figure 1K The titanium silicide formed by the silicon layer 156 and the titanium layer 157. When initially formed, the silicide 159 can cover the gate dielectric 120 on the sidewalls of the trench 138 and on the top of the interlayer dielectric layer 128. The silicide 159 is patterned using a controlled ALE process as previously described. The parameters of the ALE process are selected by an analytical model trained with a machine learning process. The parameters are selected to ensure that the silicide 159 is removed from the sidewalls of the trench 138 and from the top of the interlayer dielectric layer 128, while leaving a remaining portion of the silicide 159 at the bottom of the trench 138 on the third gate metal 152. As previously described, this can ensure that a larger volume of the trench 138 is filled with the fourth gate metal 160.

[0077] exist Figure 1Q As previously mentioned Figure 1L As described above, titanium nitride adhesion layer 158 and fourth gate metal 160 have been deposited in trenches 138 of transistors 102, 104, and 106. Figure 1M As described above, a CMP process has been performed. Figure 1NAs described above, source and drain silicide 166, adhesion layer 167, and source and drain contact plugs 168 have been formed. Figure 1Q It can be seen that Figure 1N Compared to the embodiment of FIG. 1 , the fourth gate metal 160 fills a larger volume of the trench 138 due to Figure 1N In comparison, fewer layers are disposed on the sidewalls of the trench 138 .

[0078] Despite Figures 1A to 1Q Not shown in Figure 1A Prior to the structure shown, dielectric layer 120 is removed from sidewalls 170 of trenches 138 of transistors 102, 104, and 106. In this case, sidewalls 170 of trench 138 correspond to the sidewalls of sidewall spacers 124. In practice, dielectric layer 120 will only remain at the bottom of trench 138 on top of dielectric layer 122. This can be accomplished by utilizing a method as previously described and referring to Figure 2A-5 Patterning the dielectric layer 120 in this manner results in a greater volume of the trench 138 being filled by the fourth gate metal 160 .

[0079] Figure 2A 2 is an illustration of a semiconductor processing system 200 according to one embodiment. The semiconductor processing system 200 may be used to perform a controlled ALE process for forming the integrated circuit 100, as described with respect to FIG. Figures 1A to 1Q The semiconductor process system 200 includes a process chamber 202 including an interior volume 203. A support 206 is disposed within the interior volume 203, and the support 206 is configured to support a substrate 204 during a thin film etching process. The semiconductor process system 200 is configured to etch a thin film located on the substrate 204. The semiconductor process system 200 includes a control system 224 that dynamically adjusts thin film etching parameters. After describing the operation of the semiconductor process system 200, details of the control system 224 are provided.

[0080] In one embodiment, semiconductor processing system 200 includes a first fluid source 208 and a second fluid source 210. First fluid source 208 applies a first fluid to interior volume 203. Second fluid source 210 applies a second fluid to interior volume 203. Both the first and second fluids contribute to etching a thin film on substrate 204. Figure 2A Fluid sources 208 and 210 are shown, but in practice, fluid sources 208 and 210 may include or supply materials other than fluids. For example, fluid sources 208 and 210 may include material sources that provide all of the materials for the etching process.

[0081] In one embodiment, semiconductor process system 200 is an atomic layer etching (ALE) system that performs an ALE process. The ALE system performs an etching process cyclically. Each cycle includes flowing a first etching fluid from a fluid source 208, then purging the first etching fluid from the etching chamber by flowing a purge gas from one or both of purge sources 212 and 224, then flowing a second etching fluid from a fluid source 210, then purging the second etching fluid from the etching chamber by flowing a purge gas from one or both of purge sources 212 and 224. This corresponds to a single ALE cycle. Each cycle etches an atomic or molecular layer from the etched film.

[0082] The parameters of the thin film generated by the semiconductor processing system 200 may be affected by a number of process conditions. The process conditions may include, but are not limited to, the amount of fluid or material remaining in the fluid sources 208, 210, the flow rate of the fluid or material from the fluid sources 208, 210, the pressure of the fluid provided by the fluid sources 208 and 210, the length of the tube or conduit that delivers the fluid or material to the process chamber 202, the age of the ampoule defined or contained in the process chamber 202, the temperature within the process chamber 202, the humidity within the process chamber 202, the pressure within the process chamber 202, the absorption and reflection of light within the process chamber 202, the surface features of the semiconductor wafer 204, the composition of the material provided by the fluid sources 208 and 210, the phase of the material provided by the fluid sources 208 and 210, the duration of the etching process, the duration of the various stages of the etching process, and various other factors, including factors not specifically listed above.

[0083] The combination of various process conditions during the etching process determines the remaining thickness of the film etched by the ALE process. It is possible that the process conditions may cause the film to not have a remaining thickness that falls within the target parameters. If this occurs, the integrated circuit formed by the semiconductor wafer 204 may not operate accurately. The quality of a batch of semiconductor wafers may be affected. In some cases, it may be necessary to scrap certain semiconductor wafers.

[0084] The semiconductor processing system 200 utilizes a control system 224 to dynamically adjust process conditions to ensure that the etching process results in a thin film having parameters or characteristics that fall within target parameters or characteristics. The control system 224 is connected to processing equipment associated with the semiconductor processing system 200. The processing equipment may include Figure 2AThe control system 224 can control the flow rate of materials from the fluid sources 208 and 210, the temperature of the materials applied by the fluid sources 208 and 210, the pressure of the fluids applied by the fluid sources 208 and 210, the flow rate of materials from the purge sources 212 and 214, the duration of the flow of materials from the fluid sources 208 and 210 and the purge sources 212 and 214, the temperature within the process chamber 202, the pressure within the process chamber 202, the humidity within the process chamber 202, and other aspects of the thin film etching process. The control system 224 controls these process parameters so that the thin film etching process results in a thin film having target parameters such as a target remaining thickness, a target composition, a target crystal orientation, etc. With respect to Figures 3A to 5 Provides more details about the control system.

[0085] In one embodiment, the control system 224 is communicatively coupled to the first and second fluid sources 208, 210 via one or more communication channels 225. The control system 224 can send signals to the first and second fluid sources 208, 210 via the communication channels 225. The control system 224 can control the functions of the first and second fluid sources 208, 210 in part in response to the sensor signal from the byproduct sensor 222.

[0086] In one embodiment, the semiconductor processing system 200 may include one or more valves, pumps, or other flow control mechanisms for controlling the flow rate of the first fluid from the first fluid source 208. These flow control mechanisms may be part of the fluid source 208 or may be separate from the fluid source 208. The control system 224 may be communicatively coupled to these flow control mechanisms or to a system that controls these flow control mechanisms. The control system 224 may control the flow rate of the first fluid by controlling these mechanisms. The control system 200 may include valves, pumps, or other flow control mechanisms that control the flow of the second fluid from the second fluid source 210 in the same manner as above with reference to the first fluid and the first fluid source 208.

[0087] In one embodiment, the semiconductor processing system 200 includes a manifold mixer 216 and a fluid distributor 218. The manifold mixer 216 receives the first and second fluids from the first fluid source 208 and the second fluid source 210 together or separately. The manifold mixer 216 provides the first fluid, the second fluid, or a mixture of the first and second fluids to the fluid distributor 218. The fluid distributor 218 receives one or more fluids from the manifold mixer 216 and distributes the one or more fluids to the interior volume 203 of the process chamber 202.

[0088] In one embodiment, the first fluid source 208 is coupled to the manifold mixer 216 through a first fluid channel 230. The first fluid channel 230 delivers a first fluid from the fluid source 208 to the manifold mixer 216. The first fluid channel 230 may be a tube, a pipe, or other suitable channel for delivering the first fluid from the first fluid source 208 to the manifold mixer 216. The second fluid source 210 is coupled to the manifold mixer 216 through a second fluid channel 232. The second fluid channel 232 delivers a second fluid from the second fluid source 210 to the manifold mixer 216.

[0089] In one embodiment, the manifold mixer 216 is coupled to the fluid distributor 218 via a third fluid line 234. The third fluid line 234 delivers fluid from the manifold mixer 216 to the fluid distributor 218. The third fluid line 234 may deliver the first fluid, the second fluid, a mixture of the first and second fluids, or other fluids, as will be described in more detail below.

[0090] The first and second fluid sources 208, 210 may include a fluid tank. The fluid tank may store the first and second fluids. The fluid tank may selectively output the first and second fluids.

[0091] In one embodiment, semiconductor processing system 200 includes a first purge source 212 and a second purge source 214. The first purge source is coupled to first fluid line 230 via a first purge line 236. The second purge source is coupled to fluid line 232 via a second purge line 238. In practice, the first and second purge sources may be a single purge source.

[0092] In one embodiment, the first and second purge sources 212, 214 apply purge gas to the interior volume 203 of the process chamber 202. The purge fluid is a fluid that selectively purifies or transports the first fluid, the second fluid, the byproducts of the first or second fluid, or other fluids from the interior volume 203 of the process chamber 202. The purge fluid is selected so that it does not react with the substrate 204, the gate metal layer on the substrate 204, the first and second fluids, and the byproducts of the first or second fluid. Accordingly, the purge fluid may include, but is not limited to, Ar or N 2 of inert gas,.

[0093] although Figure 2A A first fluid source 208 and a second fluid source 210 are shown, but in practice, the semiconductor process system 200 may include other numbers of fluid sources. For example, the semiconductor process system 200 may include only a single fluid source or more than two fluid sources. Accordingly, the semiconductor process system 200 may include a number different from two fluid sources without departing from the scope of the present invention.

[0094] Figure 2B is a graph showing a cycle of an ALE process performed by a semiconductor processing system 200 according to one embodiment. At time T1, the first etching fluid begins to flow. Figure 2B In an example, the first etching fluid is WCl5. The first etching fluid flows from the fluid source 208 into the interior volume 203. In the interior volume 203, the first etching fluid reacts with the top exposed layer of the titanium nitride layer 124. At time T2, the first etching fluid WCl5 stops flowing. In an example, the time between T1 and T2 is between 1s and 10s.

[0095] At time T3, the purge gas begins to flow. The purge gas flows from one or both of the purge sources 212 and 224. In one example, the purge gas is argon, N 2 Or one of another inert gas. At time T4, the purge gas stops flowing. In an example, the time between T3 and T4 is between 2s and 15s.

[0096] At time T5, the second etching fluid flows into the interior volume 203. The second etching fluid flows into the interior volume 203 from the fluid source 210. In one example, the second etching fluid is O 2 .O 2 The second etching fluid stops flowing at time T6. In one example, the elapsed time between T5 and T6 is between 1s and 10s.

[0097] At time T7, the purge gas flows again and purges the inner volume 203 of the second etching fluid. At time T8, the purge gas stops flowing. The time between T1 and T8 corresponds to a single ALE cycle.

[0098] In practice, the ALE process may include between 5 and 50 cycles, depending on the initial thickness of the titanium nitride layer and the desired final thickness of the titanium nitride layer. Each cycle removes an atomic or molecular layer of the titanium nitride layer 124. Other materials, processes, and elapsed times may be utilized without departing from the scope of the present invention.

[0099] Figure 3A According to an embodiment Figure 2A According to one embodiment, Figure 3A The control system 224 is configured to perform the ALE process to form Figures 1A to 1QThe control system 224 controls the operation of the semiconductor process system 200 in the integrated circuit 100 of FIG. The control system 224 uses machine learning to adjust the parameters of the semiconductor process system 200. To ensure that the thin film layers formed by the ALE process fall within the selected specifications, the control system 224 can adjust the parameters of the semiconductor process system 200 between ALE runs or even between ALE cycles.

[0100] In one embodiment, the control system 224 includes an analytical model 302 and a training module 304. The training module trains the analytical model 302 using a machine learning process. The machine learning process trains the analytical model 302 to select parameters for the ALE process that will cause the film to have selected properties. Although the training module 304 is shown as being separate from the analytical model 302, in reality, the training module 304 can be part of the analytical model 302.

[0101] The control system 224 includes or stores training set data 306. The training set data 306 includes historical thin film data 308 and historical process condition data 310. The historical thin film data 308 includes data related to thin films generated by the ALE process. The historical process condition data 310 includes data related to process conditions during the ALE process that generated the thin film. As will be described in more detail below, the training module 304 utilizes the historical thin film data 308 and the historical process condition data 310 to train the analysis model 302 using a machine learning process.

[0102] In one embodiment, historical film data 308 includes data related to the remaining thickness of previously etched films. For example, during the operation of a semiconductor manufacturing facility, thousands of semiconductor wafers may be processed over the course of several months or years. Each semiconductor wafer may include a film etched by an ALE process. After each ALE process, as part of a quality control process, the thickness of the film will be measured. Historical film data 308 includes the remaining thickness of each film etched by an ALE process. Accordingly, historical film data 308 may include thickness data for a large number of films etched by an ALE process.

[0103] In one embodiment, historical thin film data 308 may also include data related to the thickness of the thin film at intermediate stages of the thin film etching process. For example, an ALE process may include a large number of etching cycles during which individual layers of the thin film are etched. Historical thin film data 308 may include data on the thickness of the thin film after individual etching cycles or groups of etching cycles. Therefore, historical thin film data 308 includes not only data related to the total thickness of the thin film after the ALE process is completed, but may also include data related to the thickness of the thin film at various stages of the ALE process.

[0104] In one embodiment, historical film data 308 includes data related to the composition of the remaining film etched by the ALE process. After etching the film, measurements can be taken to determine the elemental or molecular composition of the film. Successful etching of the film causes the film to include a specific remaining thickness. An unsuccessful etching process may cause the film to not contain a specific ratio of elements or compounds. Historical film data 308 may include data from measurements representing the elements or compounds that make up each film.

[0105] In one embodiment, historical process conditions 310 include various process conditions or parameters during an ALE process that etches a film associated with historical film data 308. Accordingly, for each film having data in historical film data 308, historical process condition data 310 may include process conditions or parameters that existed during etching of the film. For example, historical process condition data 310 may include data related to pressure, temperature, and fluid flow rate within a process chamber during an ALE process.

[0106] The historical process condition data 310 may include data related to the amount of precursor material remaining in the fluid source during the ALE process. The historical process condition data 310 may include data related to the age of the process chamber 202, the number of etching processes that have been performed in the process chamber 202, the number of etching processes that have been performed in the process chamber 202 since the most recent cleaning cycle of the process chamber 202, or other data related to the process chamber 202. The historical process condition data 310 may include data related to compounds or fluids introduced into the process chamber 202 during the etching process. The data related to the compound may include the type of compound, the phase of the compound (solid, gas, or fluid), a mixture of compounds, or other aspects related to the compound or fluid introduced into the process chamber 202. The historical process condition data 310 may include data related to humidity within the process chamber 202 during the ALE process. The historical process condition data 310 may include data related to light absorption and light reflection related to the process chamber 202. The historical process condition data 310 may include data related to the length of a pipe, tube, or conduit that delivers a compound or fluid to the process chamber 202 during an ALE process. The historical process condition data 310 may include data related to the conditions of a carrier gas that delivers a compound or fluid to the process chamber 202 during an ALE process.

[0107] In one embodiment, the historical process condition data 310 may include process conditions for each of a plurality of individual cycles of a single ALE process. Accordingly, the historical process condition data 310 may include process condition data for a very large number of ALE cycles.

[0108] In one embodiment, the training set data 306 associates the historical thin film data 308 with the historical process condition data 310. In other words, the film thickness, material composition, or crystal structure associated with the thin film in the historical thin film data 308 is associated with the process condition data associated with the etching process. As will be explained in more detail below, the labeled training set data can be used in a machine learning process to train the analysis model 302 to predict the semiconductor process conditions that will result in the correct formation of the thin film.

[0109] In one embodiment, the control system 324 includes processing resources 312, memory resources 314, and communication resources 316. The processing resources 312 may include one or more controllers or processors. The processing resources 312 are configured to execute software instructions, process data, make thin film etching control decisions, perform signal processing, read data from memory, write data to memory, and perform other processing operations. The processing resources 312 may include physical processing resources 312 located at a site or facility of the semiconductor process system 200. The processing resources may include virtual processing resources 312 at a site away from the semiconductor process system 200 or a facility located at the semiconductor process system 200. The processing resources 312 may include cloud-based processing resources, which include processors and servers accessed via one or more cloud computing platforms.

[0110] In one embodiment, the memory resource 314 may include one or more computer-readable memories. The memory resource 314 is configured to store software instructions related to the functions of the control system and its components, including but not limited to the analysis model 302. The memory resource 314 may store data related to the functions of the control system 224 and its components. The data may include training set data 306, current process condition data, and any other data related to the operation of the control system 224 or any of its components. The memory resource 314 may include physical memory resources located at a site or facility of the semiconductor process system 200. The memory resource may include a virtual memory resource located at a site or facility away from the semiconductor process system 200. The memory resource 314 may include cloud-based memory resources accessed via one or more cloud computing platforms.

[0111] In one embodiment, the communication resources may include resources that ensure that the control system 224 communicates with the devices associated with the semiconductor process system 200. For example, the communication resources 316 may include wired and wireless communication resources that ensure that the control system 224 receives sensor data associated with the semiconductor process system 200 and controls the devices of the semiconductor process system 200. The communication resources 316 may ensure that the control system 224 controls the flow of fluids or other materials from the fluid sources 208 and 210 and from the purification sources 212 and 214. The communication resources 316 may ensure that the control system 224 controls heaters, voltage sources, valves, exhaust channels, wafer transfer equipment, and any other equipment associated with the semiconductor process system 200. The communication resources 316 may ensure that the control system 224 communicates with remote systems. The communication resources 316 may include or facilitate communication via one or more networks such as a wired network, a wireless network, the Internet, or an intranet. The communication resources 316 may ensure that the components of the control system 224 communicate with each other.

[0112] In one embodiment, analytical model 302 is implemented via processing resources 312, memory resources 314, and communication resources 316. Control system 224 may be a distributed control system having components, resources, and locations that are remote from each other and from semiconductor processing system 200.

[0113] Figure 3B is a block diagram illustrating operational and training aspects of the analysis model 302 according to one embodiment. The analysis model 302 may be used to select Figure 2A The semiconductor process system 200 performs the steps of forming Figures 1A to 1Q The training set data 306 includes data related to a plurality of previously performed thin film etching processes. Each previously performed thin film etching process is performed under specific process conditions and results in a thin film having specific characteristics. The process conditions for each previously performed thin film etching process are formatted into a corresponding process condition vector 352. The process condition vector includes a plurality of data fields 354. Each data field 354 corresponds to a specific process condition.

[0114] Figure 3B The example of FIG. 3 shows a single process condition vector 352 that will be passed to the analytical model 302 during the training process. Figure 3BIn the example of , the process condition vector 352 includes nine data fields 354. The first data field 354 corresponds to the temperature during a previously performed thin film etching process. The second data field 356 corresponds to the pressure during a previously performed thin film etching process. The third data field 354 corresponds to the humidity during a previously performed thin film etching process. The fourth data field 354 corresponds to the flow rate of the etching material during the previously performed thin film etching process. The fifth data field 354 corresponds to the phase (fluid, solid, or gas) of the etching material during the previously performed thin film etching process. The sixth data field 354 corresponds to the age of the ampoule used in the previously performed thin film etching process. The seventh data field 354 corresponds to the size of the etched area on the wafer during the previously performed thin film etching process. The eighth data field 354 corresponds to the density of the surface features of the wafer utilized during the previously performed thin film etching process. The ninth data field corresponds to the angle of the sidewall of the surface feature during the previously performed thin film etching process. In fact, without departing from the scope of the present invention, each process condition vector 352 may include more than one data field. Figure 3B Each process condition vector 352 may include different types of process conditions without departing from the scope of the present invention. Figure 3B The specific process conditions shown are provided as examples only. Each process condition is represented by a numerical value in a corresponding data field 354. For condition types that are not naturally represented by numbers, such as the phase of a material, a number may be assigned to each possible phase.

[0115] The analysis model 302 includes a plurality of neural layers 356a-e. Each neural layer includes a plurality of nodes 358. Each node 358 may also be referred to as a neuron. Each node 358 from the first neural layer 356a receives a data value for each data field from the process condition vector 352. Accordingly, in Figure 3B In the example of FIG. 3 , each node 358 from the first neural layer 356a receives nine data values ​​because the process condition vector 352 has nine data fields. Each neuron 358 includes Figure 3B Each node 358 of the first neural layer 356a generates a scalar value by applying the internal mathematical function F(x) to the data value of the data field 354 from the process condition vector 352. More details about the internal mathematical function F(x) are provided below.

[0116] Each node 358 of the second neural layer 356b receives a scalar value generated by each node 358 of the first neural layer 356a. Figure 3BIn the example of , each node of the second neural layer 356b receives four scalar values ​​because there are four nodes 358 in the first neural layer 356a. Each node 358 of the second neural layer 356b generates a scalar value by applying a corresponding internal mathematical function F(x) to the scalar value from the first neural layer 356a.

[0117] Each node 358 of the third neural layer 356c receives a scalar value generated by each node 358 of the second neural layer 356b. Figure 3B In the example of FIG. 3 , each node of the third neural layer 356 c receives five scalar values ​​because there are five nodes 358 in the second neural layer 356 b. Each node 358 of the third neural layer 356 c generates a scalar value by applying a corresponding internal mathematical function F(x) to the scalar value of the node 358 from the second neural layer 356 b.

[0118] Each node 358 of the neural layer 356d receives a scalar value generated by each node 358 of the previous neural layer (not shown). Each node 358 of the neural layer 356d generates a scalar value by applying a corresponding internal mathematical function F(x) to the scalar value of the node 358 from the second neural layer 356b.

[0119] The final neural layer includes only a single node 358. The final neural layer receives the scalar values ​​generated by each node 358 of the previous neural layer 356d. The nodes 358 of the final neural layer 356e generate data values ​​368 by applying a mathematical function F(x) to the scalar values ​​received from the nodes 358 of the neural layer 356d.

[0120] exist Figure 3B In the example of , data value 368 corresponds to the predicted remaining thickness of the film generated by the process condition data corresponding to the value included in the process condition vector 352. In other embodiments, the final neural layer 356e can generate multiple data values, each corresponding to a specific film characteristic, such as film crystal orientation, film uniformity, or other characteristics of the film. The final neural layer 356e will include a corresponding node 358 for each output data value to be generated. In the case of predicted film thickness, the engineer can provide a constraint to specify that the predicted film thickness 368 must fall within a selected range, such as between 0nm and 50nm in one example. The analytical model 302 will adjust the internal function F(x) to ensure that the data value 368 corresponding to the predicted film thickness will fall within the specified range.

[0121] During the machine learning process, the analytical model compares the predicted remaining thickness in the data value 368 to the actual remaining thickness of the film, as represented by the data value 370. As previously described, for each set of historical process condition data, the training set data 306 includes film characteristic data representing film characteristics resulting from the historical film etching process. Accordingly, the data field 370 includes the actual remaining thickness of the film caused by the etching process as reflected in the process condition vector 352. The analytical model 302 compares the predicted remaining thickness from the data value 368 to the actual remaining thickness from the data value 370. The analytical model 302 generates an error value 372, which represents the error or difference between the predicted remaining thickness from the data value 368 and the actual remaining thickness from the data value 370. The error value 372 is used to train the analytical model 302.

[0122] The training of the analytical model 302 may be more fully understood by discussing the internal mathematical function F(x). Although all nodes 358 are labeled with an internal mathematical function F(x), the mathematical function F(x) of each node is unique. In one example, each internal mathematical function has the following formula:

[0123] F(x)=x 1 *w 1 +x 2 *w 2 +…x n *w 1 +b.

[0124] In the above equation, each value x 1 -x n Each value x corresponds to a data value received from a node 358 in a previous neural layer, or in the case of the first neural layer 356a. 1 -x n corresponds to the corresponding data value of the data field 354 from the process condition vector 352. Accordingly, n for a given node is equal to the number of nodes in the previous neural layer. 1 -w n is a scalar weight value associated with the corresponding node from the previous layer. The analytical model 302 selects the weight value w 1 -w n The constant b is a scalar bias value and can be multiplied by the weight value. The value generated by node 358 is based on the weight value w 1 -w n Accordingly, each node 358 has n weight values ​​w 1 -w nAlthough not shown above, each function F(x) may also include an activation function. The sum listed in the above equation is multiplied by the activation function. Examples of activation functions may include a rectified linear unit (ReLU) function, a sigmoid function, a hyperbolic tension function, or other types of activation functions.

[0125] After the error value 372 has been calculated, the analytical model 302 adjusts the weight value w for each node 358 of each neural layer 356a-356e. 1 -w n In the analysis model 302, the weight value w is adjusted 1 -w n Afterwards, the analytical model 302 again provides the process condition vector 352 to the input neural layer 356a. Because the weight values ​​for each node 358 of the analytical model 302 are different, the predicted remaining thickness 368 will be different from the previous iteration. The analytical model 302 again generates an error value 372 by comparing the actual remaining thickness 370 with the predicted remaining thickness 368.

[0126] The analytical model 302 again adjusts the weight value w associated with each node 358 1 -w n The analytical model 302 again processes the process condition vector 352 and generates a predicted remaining thickness 368 and an associated error value 372. The training process includes adjusting the weight value w in the iteration 1 -w n , until the error value 372 is minimized.

[0127] Figure 3B A single process condition vector 352 is shown being passed to the analytical model 302. In practice, the training process includes passing a large number of process condition vectors 352 through the analytical model 302, generating a predicted remaining thickness 368 for each process condition vector 352, and generating an error value 372 associated with each predicted remaining thickness. The training process may also include generating a total error value representing the average error of all predicted remaining thicknesses for a batch of process condition vectors 352. The analytical model 302 adjusts the weight value w after processing each batch of process condition vectors 352. 1 -w n. The training process continues until the average error of all process condition vectors 352 is less than a selected threshold tolerance. When the average error is less than the selected threshold tolerance, the training of the analysis model 302 is complete, and the analysis model is trained to accurately predict the thickness of the film based on the process conditions. The analysis model 302 can then be used to predict the film thickness and to select process conditions that will result in the desired film thickness. During use of the training model 302, a process condition vector representing the current process conditions of the current thin film etching process to be performed and having the same format as the process condition vector 352 is provided to the training analysis model 302. The training analysis model 302 can then predict the film thickness caused by those process conditions.

[0128] Already in about Figure 3B A specific example of a neural network-based analysis model 302 is described in . However, other types of neural network-based analysis models or types of analysis models other than neural networks may be utilized without departing from the scope of the present invention. Furthermore, a neural network may have a different number of neural layers with a different number of nodes without departing from the scope of the present invention.

[0129] Figure 4 is a flow chart of a process 400 for training an analytical model to identify process conditions that will result in appropriate etching of a thin film, according to one embodiment. An example of an analytical model is Figure 3A The various steps of process 400 can be utilized in relation to Figures 1A to 3B Accordingly, reference is made to the components, processes and techniques described in Figures 1A to 3B describe Figure 4 .

[0130] At 402, process 400 collects training set data including historical thin film data and historical process condition data. This may be accomplished using a data mining system or process. The data mining system or process may collect the training set data by accessing one or more databases associated with semiconductor process system 200 and collecting and organizing the various types of data contained in the one or more databases. To generate the training set data, the data mining system or process, or another system or process, may process and format the collected data. Training set data 306 may include historical thin film data 308 and historical process condition data 310, such as information about the thin film data 308 and the historical process condition data 310. Figure 3A Described in .

[0131] At 404, process 400 inputs historical process condition data into an analysis model. In one example, this may include, for example, Figure 3AAs described in the foregoing, historical process condition data 310 is input into the analysis model 302 using the training module 304. The historical process condition data may be provided to the analysis model 302 in a continuous discrete set. Each discrete set may correspond to a single thin film etching process or a portion of a single thin film etching process. The historical process condition data may be provided to the analysis model 302 as a vector. Each set may include one or more vectors formatted for processing by the analysis model 302. The historical process condition data may be provided to the analysis model 302 in other formats without departing from the scope of the present invention.

[0132] At 406, process 400 generates predicted thin film data based on the historical process condition data. Specifically, analytical model 302 generates predicted thin film data for each set of historical thin film condition data 310. The predicted thin film data corresponds to a prediction of a property (such as remaining thickness) of a thin film produced by a particular set of process conditions. The predicted thin film data may include thickness, uniformity, composition, crystal structure, or other aspects of the remaining thin film.

[0133] At 408, the predicted film data is compared to the historical film data 308. Specifically, the predicted film data for each set of historical process condition data is compared to the historical film data 308 associated with the set of historical process condition data. The comparison may result in an error function representing the error function of how closely the predicted film data matches the historical film data 308. The comparison is performed for each set of predicted film data. In one embodiment, this process may include generating a total error function or indicator representing how the total number of predicted film data compares to the historical film data 308. These comparisons may be performed by the training module 304 or by the analytical model 302. The comparisons may include other types of functions or data in addition to the types of functions or data described above without departing from the scope of the present invention.

[0134] At 410, the process 400 determines whether the predicted film data matches the historical film data based on the comparison generated at step 408. For example, the process determines whether the predicted remaining thickness after the historical etching process matches the actual remaining thickness. In one example, if the total error function is less than the error tolerance, the process 400 determines that the film data does not match the historical film data. In one example, if the total error function is greater than the error tolerance, the process 400 determines that the film data does match the historical film data. In one example, the error tolerance can include a tolerance between 0.1 and 0. In other words, if the total percentage error is less than 0.1 or 10%, the process 400 considers that the predicted film data matches the historical film data. If the total percentage error is greater than 0.1 or 10%, the process 400 considers that the predicted film data does not match the historical film data. Other tolerance ranges can be used without departing from the scope of the present invention. The error score can be calculated in a variety of ways without departing from the scope of the present invention. The training module 304 or the analytical model 302 can make a determination related to the process step 410.

[0135] In one embodiment, if the predicted film data does not match the historical film data 308 at step 410, the process proceeds to step 412. At step 412, the process 400 adjusts the internal function associated with the analytical model 302. In one example, the training module 304 adjusts the internal function associated with the analytical model 302. From step 412, the process returns to step 404. At step 404, the historical process condition data is again provided to the analytical model 302. Because the internal function of the analytical model 302 has been adjusted, the analytical model 302 will generate different predicted film data than in the previous cycle. The process proceeds to steps 406, 408, and 410, and the total error is calculated. If the predicted film data does not match the historical film data, the process returns to step 412 and the internal function of the analytical model 302 is adjusted again. This process proceeds in an iterative manner until the analytical model 302 generates predicted film data that matches the historical film data 308.

[0136] In one embodiment, if the predicted thin film data matches the historical thin film data, process step 410 in process 400 proceeds to 414. At step 414, training is complete. Analysis model 302 is now ready for identifying process conditions and can be utilized in a thin film etching process performed by semiconductor processing system 200. Process 400 may include other steps or arrangements of steps than those shown and described herein without departing from the scope of the present invention.

[0137] Figure 5FIG. 5 is a flow chart of a process 500 for dynamically selecting process conditions for a thin film etching process and for performing the thin film etching process according to one embodiment. The various steps of the process 500 may be utilized in connection with Figures 1A to 4 Accordingly, reference is made to the components, processes and techniques described in Figures 1A to 4 To describe Figure 5 .

[0138] At 502, process 500 provides target film condition data to analysis model 302. The target film condition data identifies selected characteristics of the film to be formed by the film etching process. The target film condition data may include a target remaining thickness, a target composition, a target crystal structure, or other characteristics of the film. The target film condition data may include a thickness range. The target conditions or characteristics that may be selected are based on the film characteristics utilized in the training process. Figure 5 In the example of , the training process focuses on film thickness.

[0139] At 504, the process 500 provides static process conditions to the analysis model 302. The static process conditions include process conditions that will not be adjusted for the next thin film etching process. The static process conditions may include a target device pattern density, which represents the pattern density on the wafer on which the thin film etching process will be performed. The static process conditions may include an effective plane area crystal orientation, an effective plane area roughness index, an effective sidewall area of ​​a component on the surface of a semiconductor wafer, an exposed effective sidewall tilt angle, an exposed surface film functional group, an exposed sidewall film functional group, a rotation or tilt of the semiconductor wafer, process gas parameters (material, phase of the material, and temperature of the material), a remaining amount of material fluid in the fluid sources 208 and 210, a remaining amount of fluid in the purge sources 212 and 214, humidity in the process chamber, age of the ampoule used in the etching process, light absorption or reflection in the process chamber, a length of a pipe or conduit that will provide fluid to the process chamber, or other conditions. Without departing from the scope of the present invention, the static process conditions may include conditions other than the above conditions. Furthermore, in some cases, some of the static process conditions listed above may be dynamic process conditions that require adjustment, which will be described in more detail below. Figure 5 In the example of , the dynamic process conditions include temperature, pressure, humidity and flow rate. The static process conditions include phase, age of ampoule, etch area, etch density and sidewall angle.

[0140] At 506, according to one embodiment, the process 500 selects dynamic process conditions for the analysis model. Dynamic process conditions may include any process conditions that are not specified as static process conditions. For example, the training set data may include a large amount of various types of process condition data in the historical process condition data 310. Some of these types of process conditions are defined as static process conditions, and some of these types of process conditions are defined as dynamic process conditions. Accordingly, when static process conditions are applied at step 504, the remaining types of process conditions may be defined as dynamic process conditions. The analysis model 302 may initially select initial values ​​for dynamic process conditions. After the initial values ​​for the dynamic process conditions have been selected, the analysis model has a full set of process conditions to be analyzed. In one embodiment, the initial values ​​for the dynamic process conditions may be selected based on previously determined start values ​​or according to other schemes.

[0141] The dynamic process conditions may include the flow rate of fluid or material from fluid sources 208 and 210 during the etching process. The dynamic process conditions may include the flow rate of fluid or material from purge sources 212 and 214. The dynamic process conditions may include the pressure within the process chamber, the temperature within the process chamber, the humidity within the process chamber, the duration of various steps of the etching process, or the voltage or electric field generated within the process chamber. The dynamic process conditions may include other types of conditions without departing from the scope of the present invention.

[0142] At 508, the analytical model 302 generates predicted film data based on the static and dynamic process conditions. The predicted film data includes the same types of film properties established in the target film condition data. In particular, the predicted film data includes information from the Figures 2A to 4 The predicted film data may include film thickness, film composition, or other parameters of the film.

[0143] At 510, the process compares the predicted thin film data to the target thin film data. In particular, the analytical model 302 compares the predicted thin film data to the target thin film data. The comparison indicates how closely the predicted thin film data matches the target thin film data. The comparison may indicate whether the predicted thin film data falls within a tolerance or range established by the target thin film data. For example, if the target film thickness is between 1 nm and 9 nm, the comparison will indicate whether the predicted thin film data falls within this range.

[0144] At 512, if the predicted thin film data does not match the target thin film data, the process proceeds to 514. At 514, the analysis model 302 adjusts the dynamic process condition data. The process returns from 514 to 508. At 508, the analysis model 302 again generates predicted thin film data based on the static process conditions and the adjusted dynamic process conditions. Then, at 510, the analysis model compares the predicted thin film data with the target thin film data. At 512, if the predicted thin film data does not match the target thin film data, the process proceeds to 514, and the analysis model 302 adjusts the dynamic process conditions again. The process proceeds until predicted thin film data that matches the target thin film data is generated. If the predicted thin film data matches the target thin film data 512, the process proceeds to 516.

[0145] At 516, the process 500 adjusts the thin film process conditions of the semiconductor process system 200 based on the dynamic process conditions that result in the predicted thin film data being within the target thin film data. For example, the control system 224 can adjust the fluid flow rate, etching step duration, pressure, temperature, humidity, or other factors based on the dynamic process condition data.

[0146] At 518, the semiconductor process system 200 performs a thin film etching process according to the adjusted dynamic process conditions identified by the analytical model. In one embodiment, the thin film etching process is an ALE process. However, other thin film etching processes may be utilized without departing from the scope of the present invention. In one embodiment, the semiconductor process system 200 adjusts process parameters based on the analytical model between separate etching stages in the thin film etching process. For example, in the ALE process, the thin film is etched one layer at a time. The analytical model 302 may identify the parameters to be used to etch the next layer. Accordingly, the semiconductor process system may adjust the etching conditions between the various etching stages.

[0147] In one embodiment, an integrated circuit includes an interlayer dielectric layer and a transistor. The transistor includes a trench formed in the interlayer dielectric layer, a gate dielectric disposed on the bottom of the trench, and a gate electrode. The gate electrode includes a gate metal disposed on the gate dielectric at the bottom of the trench, a silicide disposed in the trench above the gate metal, and a conductive gate fill material disposed above the gate metal and the silicide in the trench. The conductive gate fill material extends to a higher vertical level within the trench than the gate metal.

[0148] In one embodiment, a method includes forming a trench in an interlayer dielectric layer above a plurality of first semiconductor nanosheets corresponding to a channel region of a first transistor. The method includes: depositing a gate dielectric on a bottom of the trench; depositing a gate metal of the transistor in the trench on the gate dielectric; forming a silicide above the first gate metal in the trench. The method includes and filling the trench above the first gate metal and the silicide with a conductive gate fill material. The conductive gate fill material extends to a higher vertical level within the trench than the gate metal.

[0149] In one embodiment, a method includes training an analytical model with a machine learning process to select parameters for an atomic layer etching process. The method includes: depositing a gate metal of a transistor in a trench in an interlayer dielectric layer of an integrated circuit; selecting etching parameters for etching the gate metal with the analytical model; and etching the gate metal with an atomic layer etching process based on the selected etching parameters. The method includes forming a silicide over the gate metal in the trench.

[0150] An embodiment of the present application provides an integrated circuit, comprising: an interlayer dielectric layer; a first transistor, the first transistor comprising: a first trench formed in the interlayer dielectric layer; a gate dielectric disposed on the bottom of the first trench, a gate electrode, the gate electrode comprising: a first gate metal disposed on the gate dielectric at the bottom of the first trench, a silicide disposed in the first trench above the first gate metal; a conductive gate filling material disposed above the first gate metal and the silicide in the first trench; wherein the conductive gate filling material extends to a higher vertical level than the first gate metal in the first trench. In some embodiments, the silicide is titanium silicide. In some embodiments, the first transistor comprises a plurality of semiconductor nanosheets below the first trench, wherein the semiconductor nanosheet is a channel region of the first transistor. In some embodiments, the gate dielectric and the gate electrode surround the semiconductor nanosheet. In some embodiments, the conductive gate filling material extends in the first trench to be higher than the gate dielectric. In some embodiments, the gate dielectric comprises hafnium. In some embodiments, the present invention further comprises: a second transistor, the second transistor comprising: a second trench formed in the interlayer dielectric layer; the gate dielectric disposed on the bottom of the second trench; a gate electrode comprising the silicide and the conductive gate filling material disposed in the second trench above the gate dielectric, the conductive gate filling material of the second transistor being disposed closer to the bottom of the second trench than the conductive gate filling material of the first transistor disposed at the bottom of the first trench. In some embodiments, the first transistor has a higher threshold voltage than the second transistor. In some embodiments, the first gate metal is titanium nitride. In some embodiments, the conductive gate filling material comprises tungsten.

[0151] An embodiment of the present application provides a method, comprising: forming a first trench in an interlayer dielectric layer above a plurality of first semiconductor nanosheets corresponding to a channel region of a first transistor; depositing a gate dielectric on the bottom of the first trench; depositing a first gate metal of the first transistor in the first trench on the gate dielectric; forming a silicide on the first gate metal in the first trench; filling the first trench above the first gate metal and the silicide with a conductive gate fill material, wherein the conductive gate fill material extends to a higher vertical level in the first trench than the first gate metal. In some embodiments, forming the silicide comprises: depositing silane in the first trench; and depositing titanium on the silane. In some embodiments, it also comprises: selecting parameters of an atomic layer etching process for the first gate metal; and patterning the first gate metal located in the first trench with the atomic layer etching process before filling the first trench with the conductive gate fill material. In some embodiments, the parameters for the atomic layer etching process are selected using an analytical model trained by a machine learning process. In some embodiments, the method further includes: forming a second trench in the interlayer dielectric layer above a plurality of second semiconductor nanosheets corresponding to a channel region of a second transistor; depositing the gate dielectric on the bottom of the second trench; forming the silicide above the gate dielectric in the second trench; filling the second trench with the conductive gate filling material, wherein the conductive gate filling material of the second transistor is disposed closer to the bottom of the second trench than the conductive gate filling material of the first transistor disposed at the bottom of the first trench. In some embodiments, the method further includes, before depositing the gate filling material, etching the gate dielectric from the sidewall of the first trench using an ALE process, the ALE process having parameters selected by an analytical model trained using a machine learning process.

[0152] Embodiments of the present application also provide a method, comprising: training an analytical model with a machine learning process to select parameters for an atomic layer etching process; depositing a gate metal of a transistor in a trench in an interlayer dielectric layer of an integrated circuit; selecting etching parameters for etching the gate metal with the analytical model; and etching the gate metal with the atomic layer etching process based on the selected etching parameters; and forming a silicide over the gate metal in the trench. In some embodiments, the selected parameters include the number of atomic layer etching cycles. In some embodiments, the selected parameters include the flow rate of the etching fluid. In some embodiments, the analytical model selects the parameters based in part on the selected residual thickness of the gate metal.

[0153] The various embodiments described above can be combined to provide additional embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide additional embodiments.

[0154] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. An integrated circuit, comprising: interlayer dielectric layer; A first transistor, wherein the first transistor comprises: a first trench formed in the interlayer dielectric layer; a gate dielectric disposed on the bottom of the first trench, A gate electrode, the gate electrode comprising: a first gate metal disposed on the gate dielectric at the bottom of the first trench, silicide, disposed in the first trench above the first gate metal; a conductive gate fill material disposed over the first gate metal and the silicide in the first trench, wherein the conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, wherein the conductive gate fill material and the gate dielectric extend to the same vertical level within the first trench, The silicide surrounds the conductive gate filling material and extends to the same vertical level as the conductive gate filling material, and the bottoms of the conductive gate filling material and the silicide are both higher than the top of the first gate metal.

2. The integrated circuit according to claim 1, wherein: The silicide is titanium silicide.

3. The integrated circuit according to claim 1, wherein: The first transistor includes a plurality of semiconductor nanosheets below the first trench, wherein the semiconductor nanosheets are channel regions of the first transistor.

4. The integrated circuit according to claim 3, wherein: The gate dielectric and the gate electrode surround the semiconductor nanosheet.

5. The integrated circuit according to claim 4, wherein: The silicide extends within the first trench to be higher than the first gate metal.

6. The integrated circuit according to claim 5, wherein: The gate dielectric includes hafnium.

7. The integrated circuit of claim 4, further comprising: A second transistor, the second transistor comprising: a second trench formed in the interlayer dielectric layer; The gate dielectric is disposed on the bottom of the second trench; A gate electrode includes the silicide and the conductive gate filling material arranged in the second trench above the gate dielectric, and the conductive gate filling material of the second transistor is arranged closer to the bottom of the second trench than the conductive gate filling material of the first transistor is arranged at the bottom of the first trench.

8. The integrated circuit according to claim 7, wherein: The first transistor has a higher threshold voltage than the second transistor.

9. The integrated circuit of claim 1, wherein: The first gate metal is titanium nitride.

10. The integrated circuit of claim 9, wherein: The conductive gate fill material includes tungsten.

11. A method of forming an integrated circuit, comprising: forming a first trench in the interlayer dielectric layer over the plurality of first semiconductor nanosheets corresponding to a channel region of the first transistor; depositing a gate dielectric on a bottom of the first trench; depositing a first gate metal of the first transistor in the first trench on the gate dielectric; forming a silicide on the first gate metal in the first trench; filling the first trench above the first gate metal and the silicide with a conductive gate fill material, wherein the conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, wherein the conductive gate fill material and the gate dielectric extend to the same vertical level within the first trench, The silicide surrounds the conductive gate filling material and extends to the same vertical level as the conductive gate filling material, and the bottoms of the conductive gate filling material and the silicide are both higher than the top of the first gate metal.

12. The method of forming an integrated circuit according to claim 11, wherein: Forming the silicide comprises: depositing silane in the first trench; and Titanium is deposited on the silane.

13. The method of forming an integrated circuit according to claim 11, further comprising: selecting parameters for an atomic layer etch process for the first gate metal; as well as The first gate metal within the first trench is patterned using the atomic layer etching process before filling the first trench with the conductive gate fill material.

14. The method of forming an integrated circuit of claim 13, further comprising selecting the parameters for the atomic layer etch process using an analytical model trained by a machine learning process.

15. The method of forming an integrated circuit according to claim 11, further comprising: forming a second trench in the interlayer dielectric layer over a plurality of second semiconductor nanosheets corresponding to a channel region of a second transistor; depositing the gate dielectric on a bottom of the second trench; forming the silicide over the gate dielectric in the second trench; The second trench is filled with the conductive gate fill material, wherein the conductive gate fill material of the second transistor is disposed closer to a bottom of the second trench than the conductive gate fill material of the first transistor is disposed at a bottom of the first trench.

16. The method of forming an integrated circuit of claim 15, further comprising, before depositing the gate fill material, etching the gate dielectric from sidewalls of the first trench using an ALE process having parameters selected by an analytical model trained using a machine learning process.

17. A method of forming an integrated circuit, comprising: using a machine learning process to train an analytical model to select parameters for an atomic layer etch process; Depositing gate metal for transistors in trenches in interlayer dielectric layers of integrated circuits; selecting etching parameters for etching the gate metal using the analytical model; as well as etching the gate metal using the atomic layer etching process based on the selected etching parameters; as well as forming a silicide over the gate metal in the trench; as well as forming a conductive gate fill material over the silicide, The silicide surrounds the conductive gate filling material and extends to the same vertical level as the conductive gate filling material, and the bottoms of the conductive gate filling material and the silicide are both higher than the top of the gate metal.

18. The method of forming an integrated circuit according to claim 17, wherein: The selected parameters include the number of atomic layer etching cycles.

19. The method of forming an integrated circuit according to claim 18, wherein: The selected parameters include the flow rate of the etching fluid.

20. The method of forming an integrated circuit according to claim 17, wherein: The analytical model selects the parameters based in part on a selected remaining thickness of the gate metal.

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