Memory device and method of forming the same

Abstract

A memory device includes: a first transistor located above a semiconductor substrate, wherein the first transistor includes a first word line extending above the semiconductor substrate; a second transistor located above the semiconductor substrate, wherein the second transistor includes a second word line extending above the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along the first word line and the second word line and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is located between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is located between the bit line and the word line; and an isolation region located between the source line and the bit line. Embodiments of the present application provide a memory device and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones, and personal computer devices. Semiconductor memory includes two main categories. One is volatile memory and the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can also be divided into two subcategories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the stored information when power is lost.

[0003] On the other hand, nonvolatile memory can retain data stored therein. One type of nonvolatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include fast read / write speeds and small size. Summary of the invention

[0004] A memory device according to an embodiment of the present application includes: a semiconductor substrate; a first transistor located above the semiconductor substrate, wherein the first transistor includes a first word line extending above the semiconductor substrate; a second transistor located above the semiconductor substrate, wherein the second transistor includes a second word line extending above the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along the first word line and the second word line, wherein the memory film contacts the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is located between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is located between the bit line and the word line; and an isolation region located between the source line and the bit line.

[0005] An embodiment of the present application provides a device, comprising: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises: a first gate electrode comprising a portion of a first word line, wherein a bottom surface of the first gate electrode is exposed through a first air gap, wherein a top surface of the first gate electrode is exposed through a second air gap; a first portion of a ferroelectric material, wherein the first portion of the ferroelectric material is located on a sidewall of the first gate electrode; and a first channel region, located on a sidewall of the first portion of the ferroelectric material; a source line, wherein the first portion of the source line provides a first source / drain electrode for the first thin film transistor; a bit line, wherein the first portion of the bit line provides a second source / drain electrode for the first thin film transistor; and a first dielectric material separating the source line and the bit line.

[0006] An embodiment of the present application also provides a method, comprising: depositing alternating layers of conductive material and sacrificial material to form a multilayer stack comprising multiple conductive material layers and multiple sacrificial material layers; depositing a memory film along the sidewalls of the multilayer stack; depositing an oxide semiconductor (OS) layer above the memory film; forming an intermetallic dielectric (IMD) layer above the multilayer stack; patterning a plurality of grooves in the IMD, wherein each of the plurality of grooves exposes a corresponding sacrificial material layer among the plurality of sacrificial material layers; performing an etching process through the plurality of grooves to remove the plurality of sacrificial material layers, wherein removing the plurality of sacrificial layers forms air gaps between the conductive material layers of the plurality of conductive material layers; and depositing a dielectric material in the plurality of grooves, wherein the dielectric material seals the air gaps.

[0007] Embodiments of the present application provide air gaps in a memory array structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A , Figure 1B and Figure 1C A perspective view, a circuit diagram, and a top view of a memory array according to some embodiments are shown.

[0010] Figure 2 , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15 , Fig.16 , Fig.17A , Fig. 17B , Fig.18 , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21 , Fig. 22 , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31A , Fig.31B , Fig.31C and Fig.31D Various views showing intermediate steps in the fabrication of a memory array according to some embodiments.

[0011] Fig.32 , Fig.33 and Fig.34 Cross-sectional views showing intermediate steps in fabricating a memory array in accordance with some embodiments.

[0012] Fig.35A , Fig.35B and Fig.35C A plan view illustrating an intermediate step in the fabrication of a memory array in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides a variety of different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] Various embodiments provide a 3D memory array with a plurality of vertically stacked memory cells. Each memory cell includes a transistor having a word line region used as a gate electrode, a bit line region used as a first source / drain electrode, and a source line region used as a second source / drain electrode. Each transistor also includes an insulating memory film (e.g., as a gate dielectric) and an oxide semiconductor (OS) channel region. In some embodiments, the isolation region between adjacent word lines is formed as an air gap. By separating the word lines with an air gap, the capacitance between the word lines can be reduced. The air gap can be formed, for example, by first forming a sacrificial material between the word lines and then removing the sacrificial material using one or more etching processes. A material can be deposited to seal the end of the air gap to protect the air gap and provide additional structural support. Forming an air gap between word lines in this way can reduce parasitic effects such as parasitic capacitance between word lines, which can achieve higher frequency operation of transistors, improved device performance, and improved device efficiency.

[0016] Figure 1A , Figure 1B and Figure 1C An example of a memory array according to some embodiments is shown. According to some embodiments, Figure 1A An example of a portion of a memory array 200 is shown in a three-dimensional view; Figure 1B A circuit diagram showing a memory array 200; Figure 1CA top view (e.g., plan view) of a memory array 200 is shown. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors, etc.) formed on a semiconductor substrate.

[0017] In some embodiments, the memory array 200 is a non-volatile memory array such as a NOR memory array. Each memory cell 202 may include a transistor 204 having an insulating memory film 90 as a gate dielectric. In some embodiments, the transistor 204 may be a thin film transistor (TFT). In some embodiments, the gate of each transistor 204 is electrically coupled to a corresponding word line (e.g., conductor 72), the first source / drain region of each transistor 204 is electrically coupled to a corresponding bit line (e.g., conductor 106), and the second source / drain region of each transistor 204 is electrically coupled to a corresponding source line (e.g., conductor 108), which electrically grounds the second source / drain region. The memory cells 202 in the same horizontal row of the memory array 200 may share a common word line (e.g., 72), while the memory cells 202 in the same vertical column of the memory array 200 may share a common source line (e.g., 108) and a common bit line (e.g., 106).

[0018] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines), with air gaps 132 disposed between adjacent conductive lines 72. The conductive lines 72 are arranged parallel to the underlying substrate ( Figure 1A and Figure 1B The conductor 72 may have a stepped configuration such that the lower conductor 72 is longer than the upper conductor 72 and extends laterally beyond the end point of the upper conductor 72. For example, Figure 1A 2, a stack of multiple layers of conductive lines 72 is shown, wherein the topmost conductive line 72 is the shortest and the bottommost conductive line 72 is the longest. The respective lengths of conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductive line 72 may be accessed from above the memory array 200, and a conductive contact may be made to the exposed portion of each conductive line 72 (e.g., see FIG. 2). Fig.31A -D). Each air gap 132 may be sealed at one or both ends by a seal 140 formed of a dielectric material.

[0019] The memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). The conductive lines 106 and 108 may each extend in a direction perpendicular to the conductive line 72. The dielectric material 98 is disposed between the conductive lines 106 and 108 and isolates adjacent conductive lines 106 and 108. The paired conductive lines 106 and 108 together with the intersecting conductive lines 72 define the boundaries of each memory cell 202, and the dielectric material 102 is disposed between and isolates adjacent paired conductive lines 106 and 108. In some embodiments, the conductive line 108 is electrically grounded. Although Figure 1A A particular placement of conductors 106 relative to conductors 108 is shown, but it should be understood that in other embodiments, the placement of conductors 106 and 108 may be reversed.

[0020] As described above, the memory array 200 may further include an oxide semiconductor (OS) layer 92. The OS layer 92 may provide a channel region for the transistor 204 of the memory cell 202. For example, when an appropriate voltage (e.g., higher than a corresponding threshold voltage (V th )), the region of OS layer 92 that intersects conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (eg, in the direction indicated by arrow 207). Thus, in some cases, OS layer 92 may be considered a channel layer.

[0021] The memory film 90 is disposed between the conductive line 72 and the OS layer 92, and the memory film 90 can provide a gate dielectric for the transistor 204. In some embodiments, the memory film 90 includes a ferroelectric material such as hafnium oxide, zirconium oxide, hafnium oxide doped with silicon, etc. Therefore, the memory array 200 can also be referred to as a ferroelectric random access memory (FeRAM) array. Alternatively, the memory film 90 can be a multilayer structure including a plurality of SiO layers between two SiO layers. x SiN between layers x layers (e.g., ONO structures), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

[0022] In an embodiment where the memory film 90 includes a ferroelectric material, the memory film 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the memory film 90 and generating an appropriate electric field. The polarization can be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the memory film 90, the threshold voltage of the corresponding transistor 204 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 90 has a first electrical polarization direction, the corresponding transistor 204 can have a relatively low threshold voltage, and when a region of the memory film 90 has a second electrical polarization direction, the corresponding transistor 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 202.

[0023] In such an embodiment, in order to perform a write operation on the memory cell 202, a write voltage is applied to the portion of the memory film 90 corresponding to the memory cell 202. The write voltage can be applied by, for example, applying an appropriate voltage to the corresponding conductive line 72 (e.g., word line) and the corresponding conductive line 106 / 108 (e.g., bit line / source line). By applying a write voltage to a portion of the memory film 90, the polarization direction of the region of the memory film 90 can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 204 can also be switched from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in the memory cell 202. Because the conductive line 72 intersects with the conductive lines 106 and 108, a single memory cell 202 can be selected for a write operation.

[0024] In such an embodiment, to perform a read operation on memory cell 202, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to the corresponding conductive line 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of memory film 90, transistor 204 of memory cell 202 may be turned on or off. As a result, conductive line 106 may be discharged or not discharged through conductive line 108 (e.g., a grounded source line), and the digital value stored in memory cell 202 may be determined. Because conductive line 72 intersects conductive lines 106 and 108, a single memory cell 202 may be selected for a read operation.

[0025] Figure 1AReference cross sections of memory array 200 used in subsequent figures are further illustrated. Reference cross section BB' is along the longitudinal axis of conductive line 72 and in a direction, e.g., parallel to the direction of current flow of transistor 204. Reference cross section CC' is perpendicular to cross section BB' and parallel to the longitudinal axis of conductive line 72. Reference cross section CC' extends through conductive line 106 and / or conductive line 108. Reference cross section D-D' is parallel to cross reference cross section CC' and extends through dielectric material 102. For clarity, subsequent figures refer to these reference cross sections.

[0026] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a doped (e.g., doped with a p-type or n-type dopant) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, potassium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0027] Figure 2 Also shown is a circuit that may be formed above the substrate 50. The circuit includes an active device (e.g., a transistor) located at the top surface of the substrate 50. The transistor may include a gate dielectric layer 203 located above the top surface of the substrate 50 and a gate electrode 205 located above the gate dielectric layer 203. In the substrate 50, source / drain regions 206 are provided on opposite sides of the gate dielectric layer 203 and the gate electrode 205. Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 203 to separate the source / drain regions 206 from the gate electrode 205 by an appropriate lateral distance. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (FinFET), a nano field effect transistor (nanoFET), etc.

[0028] The first ILD 210 surrounds and isolates the source / drain regions 206, the gate dielectric layer 203, and the gate electrode 205, and the second ILD 212 is located above the first ILD 210. The source / drain contact 214 extends through the second ILD 212 and the first ILD 210 and is electrically coupled to the source / drain regions 206, and the gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 205. The interconnect structure 220, including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224, is located above the second ILD 212, the source / drain contacts 214, and the gate contacts 216. Although Figure 2 Two stacked dielectric layers 224 are shown, but it should be understood that the interconnect structure 220 may include any number of dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source / drain contacts 214 to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 220 may include a logic circuit, a memory circuit, a sense amplifier, a controller, an input / output circuit, an image sensor circuit, etc., or a combination thereof. Although Figure 2 Transistors formed over substrate 50 are discussed, but other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuits.

[0029] exist Figure 3A and Figure 3B in Figure 2 A multilayer stack 58 is formed above the structure. For simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structure 220 may be omitted from subsequent figures. Although the multilayer stack 58 is shown as being in contact with the dielectric layer 224 of the interconnect structure 220, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, one or more additional interconnect layers including conductive features disposed in an insulating layer (e.g., a low-k dielectric layer) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines for active devices on the substrate 50 and / or the memory array 200 (see Figure 1A and Figure 1B ).

[0030] The multilayer stack 58 includes alternating layers of conductive layers 54A-D (collectively, conductive layers 54) and sacrificial layers 52A-C (collectively, sacrificial layers 52). The multilayer stack 58 includes an insulating layer 74 located above the topmost conductive layer 54. The conductive layer 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). The conductive layer 54 may include a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof. The sacrificial layer 52 may be a material such as silicon, germanium, silicon germanium (SiGe), silicon nitride, silicon oxide, combinations thereof, and the like. The insulating layer 74 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. In some embodiments, the material of the insulating layer 74 and the material of the sacrificial layer 52 are selected so that the sacrificial layer 52 can be selectively etched without significantly etching the insulating layer 74. For example, the sacrificial layer 52 may be silicon and the insulating layer 74 may be silicon oxide, but other materials are also possible.

[0031] Conductive layer 54, sacrificial layer 52, and insulating layer 74 may each be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), etc. In some embodiments, sacrificial layer 52 is formed to have a thickness T0 in the range of about 20 nm to about 80 nm. Other thicknesses are possible. The sacrificial layers 52 of multilayer stack 58 may all have approximately the same thickness, or two or more sacrificial layers 52 may have different thicknesses. Although Figure 3A and Figure 3B A particular number of conductive layers 54 and sacrificial layers 52 are shown, but other embodiments may include different numbers of conductive layers 54 and sacrificial layers 52 .

[0032] Figures 4 to 12 FIG. 1 is a diagram showing an intermediate stage of manufacturing a staircase structure of a memory array 200 according to some embodiments. Figures 4 to 11 and Fig.12 .

[0033] exist Figure 4 , a photoresist 56 is formed over the multilayer stack 58. As described above, the multilayer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and sacrificial layers 52 (labeled 52A, 52B, and 52C), and may be covered with an insulating layer 74. The photoresist 56 may be formed using a suitable technique, such as a spin coating technique.

[0034] exist Figure 5In the embodiment of the present invention, the photoresist 56 is patterned to expose the multilayer stack 58 in the region 60 while masking the rest of the multilayer stack 58. For example, the topmost layer of the multilayer stack 58 (e.g., the insulating layer 74) may be exposed in the region 60. The photoresist 56 may be patterned using acceptable photolithography techniques.

[0035] exist Figure 6 In the embodiment of the present invention, the photoresist 56 is used as a mask to etch the exposed portion of the multilayer stack 58 in the region 60. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may remove portions of the conductive layer 54D and the sacrificial layer 52C in the region 60 and define the opening 61. Because the insulating layer 74, the conductive layer 54D, and the sacrificial layer 52C have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the sacrificial layer 52C is used as an etch stop layer when etching the conductive layer 54D, and the conductive layer 54C is used as an etch stop layer when etching the sacrificial layer 52C. As a result, portions of the insulating layer 74, the conductive layer 54D, and the sacrificial layer 52C may be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 may extend to a desired depth. Alternatively, after the opening 61 reaches the desired depth, a timed etching process may be used to stop the etching of the opening 61. In the resulting structure, conductive layer 54C is exposed in region 60 .

[0036] exist Figure 7 In the embodiment of the present invention, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. The photoresist can be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60 and 62 can be exposed. For example, the top surface of insulating layer 54C can be exposed in region 60, and the top surface of insulating layer 74 can be exposed in region 62.

[0037] exist Figure 8In the embodiment of the present invention, portions of the insulating layer 74, the conductive layer 54D, the sacrificial layer 52C, the conductive layer 54C, and the sacrificial layer 52B in the regions 60 and 62 are removed by an acceptable etching process using the photoresist 56 as a mask. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The etching may extend the opening 61 further into the multilayer stack 58. Since the insulating layer 74, the conductive layer 54D / 54C, and the sacrificial layer 52C / 52B have different material compositions, the etchants used to remove the exposed portions of these layers may be different. In some embodiments, the sacrificial layer 52C is used as an etch stop layer when etching the conductive layer 54D; the conductive layer 54C is used as an etch stop layer when etching the sacrificial layer 52C; the sacrificial layer 52B is used as an etch stop layer when etching the conductive layer 54C; and the conductive layer 54B is used as an etch stop layer when etching the sacrificial layer 52B. As a result, portions of the conductive layers 54D / 54C and the sacrificial layers 52C / 52B can be selectively removed without removing the remaining layers of the multilayer stack 58, and the opening 61 can be extended to a desired depth. In addition, during the etching process, the unetched portions of the conductive layers 54 and the sacrificial layers 52 are used as masks for the underlying layers, and as a result, the previous patterns of the conductive layers 54D and the sacrificial layers 52C (see FIG. Figure 7 ) is transferred to the underlying conductive layer 54C and sacrificial layer 52B. In the resulting structure, conductive layer 54B is exposed in region 60, and conductive layer 54C is exposed in region 62.

[0038] exist Fig. 9 In the embodiment of the present invention, photoresist 56 is trimmed to expose additional portions of multilayer stack 58. The photoresist may be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of photoresist 56 is reduced, and portions of multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, the top surface of conductive layer 54B may be exposed in region 60; the top surface of conductive layer 54C may be exposed in region 62; and the top surface of insulating layer 74 may be exposed in region 64.

[0039] exist Fig.10, portions of insulating layer 74 in region 64 and portions of conductive layers 54D, 54C, and 54B in regions 60, 62, and 64 are removed by an acceptable etching process using photoresist 56 as a mask. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The etching may extend opening 61 further into multilayer stack 58. In some embodiments, sacrificial layer 52C is used as an etch stop layer when etching conductive layer 54D; sacrificial layer 52B is used as an etch stop layer when etching conductive layer 54C; and sacrificial layer 52A is used as an etch stop layer when etching conductive layer 54B. As a result, portions of conductive layers 54D, 54C, and 54B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may be extended to a desired depth. In addition, during the etching process, each sacrificial layer 52 is used as a mask for the underlying layers, and as a result, the previous pattern of sacrificial layers 52C / 52B (see Fig. 9 ) can be transferred to the underlying conductive layer 54C / 54B. In the resulting structure, sacrificial layer 52A is exposed in region 60; sacrificial layer 52B is exposed in region 62; and sacrificial layer 52C is exposed in region 64.

[0040] exist Fig.11 , the photoresist 56 can be removed, for example, by an acceptable ashing or wet stripping process. Thus, a stair structure 68 is formed. The stair structure includes a stack of alternating conductive layers 54 and sacrificial layers 52, with the top conductive layer (e.g., conductive layer 54D) being covered by an insulating layer 74. The lower conductive layer 54 is wider and extends laterally beyond the upper conductive layer 54, and the width of each conductive layer 54 increases in a direction toward the substrate 50. For example, conductive layer 54A can be longer than conductive layer 54B; conductive layer 54B can be longer than conductive layer 54C; and conductive layer 54C can be longer than conductive layer 54D. As a result, in subsequent processing steps, conductive contacts can be made from above the stair structure 68 to each conductive layer 54.

[0041] exist Fig.12 In the embodiment of the present invention, an intermetallic dielectric layer (IMD) 70 is deposited above the multilayer stack 58. The ILD 70 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. The IMD 70 extends along the sidewalls of the insulating layer 74, the conductive layer 54 and the sacrificial layer 52. In addition, the IMD 70 can contact the top surface of each sacrificial layer 52.

[0042] like Fig.12 As further shown, IMD 70 may be subjected to a removal process to remove excess dielectric material above multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a grinding process, an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes multilayer stack 58 such that after the planarization process is completed, a top surface of multilayer stack 58 (e.g., a top surface of insulating layer 74) is flush with a top surface of IMD 70.

[0043] Figures 13 to 19B is a diagram of an intermediate stage in the fabrication of a memory array 200 according to some embodiments. Figures 13 to 19B In the embodiment, a multilayer stack 58 is formed, and a trench is formed in the multilayer stack 58, thereby defining a conductive line 72. The conductive line 72 may correspond to a word line in the memory array 200, and the conductive line 72 may further provide a gate electrode for a resulting transistor of the memory array 200. Fig.14A , Fig.17A and Fig.19A .along Figure 1A The reference cross section CC' shown in FIG. Fig.13 , Fig. 14B , Fig.15 , Fig.16 , Fig. 17B , Fig.18 and Fig.19B .

[0044] exist Fig.13 , a hard mask 80 and a photoresist 82 are deposited over the multilayer stack 58. The hard mask 80 may include, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist 82 may be formed by using a spin coating technique.

[0045] exist Fig.14A and Fig. 14B In the embodiment of the present invention, the photoresist 82 is patterned to form the groove 86. The photoresist 82 can be patterned using an acceptable photolithography technique. For example, the photoresist 82 is exposed to light for patterning. After the exposure process, depending on whether a negative resist or a positive resist is used, the photoresist 82 can be developed to remove the exposed or unexposed portion of the photoresist 82, thereby defining the pattern of the groove 86.

[0046] exist Fig.15In the embodiment of the present invention, the pattern of the photoresist 82 is transferred to the hard mask 80 using an acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. Thus, a trench 86 extending through the hard mask 80 is formed. For example, the photoresist 82 can be removed by an ashing process.

[0047] exist Fig.16 In the embodiment of the present invention, the pattern of the hard mask 80 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching process can be anisotropic. Therefore, the trench 86 extends through the multilayer stack 58, and the conductive line 72 (e.g., word line) is formed by the conductive layer 54. By etching the trench 86 through the conductive layer 54, adjacent conductive lines 72 can be separated from each other. Subsequently, in Fig.17A and Fig. 17B The hard mask 80 may then be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, or the like. Due to the stepped shape of the multilayer stack 58 (see, e.g., Fig.12 ), wires 72 may have varying lengths that increase in a direction toward substrate 50. For example, wire 72A may be longer than wire 72A; wire 72B may be longer than wire 72C; and wire 72C may be longer than wire 72D. In some embodiments, trench 86 may be formed to have a width W1 in a range of about 50 nm to about 100 nm, although other widths are possible.

[0048] exist Fig.18 In the embodiment, dielectric material 98 is deposited on the sidewalls and bottom surface of trench 86. Dielectric material 98 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Fig.18 As shown, dielectric material 98 may fill trench 86 and may cover multilayer stack 58 .

[0049] exist Fig.19A and Fig.19B In the embodiment of the present invention, the removal process then removes excess dielectric material 98 above the multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a grinding process, an etch-back process, a combination thereof, etc. may be utilized. The planarization process may expose the multilayer stack 58 so that after the planarization process is completed, the top surface of the multilayer stack 58 (e.g., the top surface of the insulating layer 74) is flush. Fig.19A Shows a three-dimensional view, Fig.19B Shown through Figure 1A A cross-sectional view of reference section CC' is shown.

[0050] exist Fig. 20A , Fig. 20B and Fig. 20C , trenches 88 are patterned through dielectric material 98. Fig. 20A . Shown in plan view Fig. 20B . Along Figure 1A The cross-sectional view of the reference section CC' shows Fig. 20C . The groove 88 can be disposed between opposing sidewalls of the multilayer stack 58 and define an area where a portion of the transistor is subsequently formed. In some embodiments, patterning the groove 88 can be performed by a combination of photolithography and etching. For example, a photoresist can be deposited over the multilayer stack 58. For example, the photoresist can be formed by using an appropriate technique such as a spin coating technique. The photoresist is then patterned to define an opening that exposes an area of ​​the dielectric material 98. The photoresist can be patterned using an acceptable photolithography technique. For example, the photoresist can be exposed to light for patterning, and after the exposure process, the photoresist can be developed to remove exposed or unexposed portions of the photoresist, depending on whether a negative resist or a positive resist is used, thereby defining a pattern of the opening.

[0051] Portions of dielectric material 98 exposed by the openings may be removed by etching, thereby forming trenches 88 in dielectric material 98. Etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching may be anisotropic. In some embodiments, trench 88 may have a length L1 in a range of about 80 nm to about 150 nm, but other dimensions are possible. In some embodiments, trenches 88 are spaced apart by a distance L2 in a range of about 30 nm to about 120 nm, but other distances are possible. In some embodiments, trench 88 may have a depth in a range of about 1000 nm to about 2000 nm, but other depths are possible. After patterning trench 88, the photoresist may be removed, for example, by ashing. In some cases, the shape of trench 88 in a plan view may be as follows: Fig. 20B The rectangle shown may alternatively be a rounded rectangular or circular shape, such as an oval or a circle.

[0052] exist Fig.21In the embodiment of the present invention, a memory film 90 is conformally deposited in the trench 88. The memory film 90 may include a material capable of storing bits, such as a material that can be switched between two different polarization directions by applying an appropriate differential voltage across the memory film 90. For example, the polarization of the memory film 90 may be changed due to an electric field generated by applying a differential voltage. In some embodiments, the memory film 90 includes a high-k dielectric material, such as a hafnium (Hf)-based dielectric material, etc. In some embodiments, the memory film 90 includes a ferroelectric material, such as hafnium oxide, zirconium oxide, silicon-doped hafnium oxide, etc. In other embodiments, the memory film 90 may include a dielectric layer located between two SiO x SiN between layers x In some embodiments, the memory film 90 may be a multilayer structure of a layer (e.g., an ONO structure). In other embodiments, the memory film 90 includes different ferroelectric materials or different types of memory materials. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, etc. to extend along the sidewalls and bottom surface of the trench 88. In some embodiments, after the memory film 90 is deposited, an annealing step may be performed. In some embodiments, the memory film 90 may be deposited to a thickness in the range of about 5 nm to about 15 nm, but other thicknesses are also possible.

[0053] exist Fig. 22 In the embodiment, OS layer 92 is conformally deposited in trench 88 above memory film 90. OS layer 92 includes a plurality of layers suitable for providing a plurality of transistors (e.g., transistor 204, see Figure 1A ) provides a material for the channel region. In some embodiments, the OS layer 92 includes an indium-containing material, such as In x Ga y Zn z MO, where M can be Ti, Al, Sn, W, etc. X, Y and Z can all be any value between 0 and 1. For example, the OS layer 92 may include indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, indium oxide, etc. or a combination thereof. In other embodiments, semiconductor materials different from these examples may be used for the OS layer 92. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, etc. The OS layer 92 may extend along the sidewalls and bottom surface of the memory film 90 within the trench 88. In some embodiments, after the OS layer 92 is deposited, an annealing step in an oxygen-related environment (e.g., at a temperature range of about 300° C. to about 450° C.) may be performed to activate the charge carriers of the OS layer 92. In some embodiments, the OS layer 92 may be deposited to a thickness in a range of about 1 nm to about 15 nm, but other thicknesses are also possible.

[0054] According to some embodiments, Fig.23A , Fig. 23B and Fig.23C, dielectric material 102 is deposited over OS layer 92 and fills trench 88 . Fig.23C Show Fig. 23B . The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof. The material of the dielectric material 102 may be the same as or different from the material of the dielectric material 98. The dielectric material 102 may be deposited using a suitable technique such as CVD, PVD, ALD, PECVD, etc. The dielectric material 102 may extend along the sidewalls and bottom surface of the OS layer 92 within the trench 88. After deposition, a planarization process (e.g., CMP, etch back, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, and the dielectric material 102 may be substantially flush.

[0055] FIG. 24A to FIG. 25C An intermediate step is shown in fabricating conductive lines 106 and 108 (eg, source lines and bit lines) in memory array 200. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive line 72 so that individual cells of memory array 200 may be selected for read and write operations. Fig.24A and Fig.25A A three-dimensional view is shown. Fig. 24B and Fig.25B A top view is shown. Fig.24C and Fig.25C Shown along Figure 1A and for example Fig.25B A cross-sectional view of reference section CC' is shown.

[0056] exist Fig.24A , Fig. 24B and Fig.24C In some embodiments, a trench 120 is patterned in the dielectric material 102. The trench 120 is patterned by patterning the dielectric material 102 using a combination of photolithography and etching. For example, a photoresist can be deposited over the multilayer stack 58, the dielectric material 98, the OS layer 92, the memory film 90, and the dielectric material 102. For example, the photoresist can be formed by using a spin coating technique. The photoresist is patterned to define an opening. Each opening can overlap with a corresponding area of ​​the dielectric material 102. The opening does not completely overlap with the dielectric material 102, and the portion of the dielectric material 102 that does not overlap with the opening defines an isolation region between adjacent wires 106 and 108. The photoresist can be patterned using an acceptable photolithography technique. For example, the photoresist is exposed to light for patterning. After the exposure process, depending on whether a negative resist or a positive resist is used, the photoresist can be developed to remove the exposed or unexposed portion of the photoresist, thereby defining the opening.

[0057] The portion of dielectric material 102 exposed by the opening can be removed by etching to form trench 120. Etching can be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching can be anisotropic. In this way, trench 120 can define a pattern of areas where conductive line 106 and conductive line 108 are formed. Fig.24C 1 shows an embodiment in which OS layer 92 remains above memory film 90 after forming trench 120. In other embodiments, etching may remove sidewall portions and / or a bottom portion of OS layer 92, which may expose memory film 90. After patterning trench 120, the photoresist may be removed, for example, by ashing. In some cases, the shape of trench 120 in a plan view may be as follows: Fig. 24B The rectangle shown may alternatively be a rounded rectangular or circular shape, such as an oval or a circle.

[0058] exist Fig.25A , Fig.25B and Fig.25C In some embodiments, the trench 120 is filled with a conductive material to form the conductive line 106 and the conductive line 108. The conductive material may include one or more materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, molybdenum, combinations thereof, etc., which may each be formed using, for example, CVD, ALD, PVD, PECVD, etc. After depositing the conductive material, a planarization process may be performed to remove excess portions of the conductive material. In the resulting structure, the top surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, the insulating layer 74, and the conductive lines 106 / 108 may be substantially flush (e.g., coplanar within process variations).

[0059] Conductive line 106 may correspond to a bit line in a memory array, and conductive line 108 may correspond to a source line in memory array 200. Although Fig.25C Only a cross-sectional view of conductive line 108 is shown, but a cross-sectional view of conductive line 106 may be similar. Adjacent conductive lines 106 and conductive lines 108 are separated by isolation regions formed by dielectric material 102.

[0060] In this way, stacked transistors 204 can be formed in the memory array 200. Each transistor 204 includes a gate electrode (e.g., corresponding to a portion of the conductive line 72), a gate dielectric (e.g., corresponding to a portion of the memory film 90), a channel region (e.g., corresponding to a portion of the OS layer 92), and source and drain electrodes (e.g., corresponding to a portion of the conductive lines 106 and 108). The dielectric material 102 isolates adjacent transistors 204 at the same column and the same vertical plane. The transistors 204 can be arranged in an array of vertically stacked rows and columns.

[0061] FIG. 26A to FIG. 30 26 to 27 show an intermediate step of making air gaps 132 between conductive lines 72 according to some embodiments. Air gaps 132 are formed between vertically adjacent conductive lines 72 by removing sacrificial layer 52, which will be described in more detail below. By replacing sacrificial layer 52 with air gaps 132, the capacitance between conductive lines 72 can be reduced, which can improve the speed and performance of the transistor, especially at higher operating frequencies. Fig.30 In the process described in , the same process steps are used to form a plurality of air gaps 132. In other embodiments, the air gaps 132 may be sequentially formed by repeating similar process steps for forming each air gap 132.

[0062] exist Fig.26A In -B, a groove 130 is formed to expose the sacrificial layer 52. The groove 130 allows the sacrificial layer 52 to be removed and the seal 140 to be formed (see Fig.28 ) and forming contact 110. In some embodiments, trench 130 may extend through sacrificial layer 52 to expose underlying conductive line 72, such as Fig.26A In other embodiments, the groove 130 may expose the sacrificial layer 52 without exposing the conductive line 72. For example, the groove 130 may expose the top surface of the sacrificial layer 52, such as Fig.26B As shown. Fig.26A As shown in FIG. 1-B, a groove 130 may be formed to expose one region of each sacrificial layer 52, or a plurality of grooves 130 may be formed to expose a plurality of regions of the sacrificial layer 52. Fig.33 An example in which the trenches 130 are formed at both ends of each sacrificial layer 52 is shown.

[0063] The trench 130 may be formed by patterning an opening in the IMD 70 using a combination of photolithography and etching. As an example, a photoresist may be deposited over the multilayer stack 58 and the IMD 70. For example, the photoresist may be formed using a spin coating technique. The photoresist is patterned using an acceptable photolithography technique to define the opening. For example, the photoresist is exposed to light for patterning. After the exposure process, depending on whether a negative resist or a positive resist is used, the photoresist may be developed to remove the exposed or unexposed portions of the photoresist, thereby defining the opening.

[0064] The portion of IMD 70 exposed by the opening may be removed by etching to form trench 130. The etching may be any acceptable etching process such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. In some embodiments, the opening in IMD 70 may extend through sacrificial layer 52 to form trench 130 exposing conductive line 72, such as Fig.26AAs shown. In these embodiments, the IMD 70 and the sacrificial layer 52 can be etched using the same etching step or different etching steps. For example, the IMD 70 can be etched using a first etching process, and the sacrificial layer 52 can be etched using a second etching process different from the first etching process. In some embodiments, the second etching process can also remove the sacrificial layer 52 to form the air gap 132, which will be described in more detail below. In some embodiments, the second etching process can selectively etch the sacrificial layer 52. After the trench 130 is patterned, the photoresist can be removed, for example, by ashing.

[0065] exist Fig. 27 In some embodiments, the sacrificial layer 52 is removed using an etching process, thereby forming an air gap 132 between the conductive lines 54. In some embodiments, as described above, the etching process for removing the sacrificial layer 52 can be performed as part of the formation of the groove 130. In other words, the etching process for removing the sacrificial layer 52 can be performed during the formation of the groove 130 or after the formation of the groove 130. The etching process for removing the sacrificial layer 52 can be performed before or after removing the photoresist used to pattern the groove 130. In some embodiments, the air gap 132 formed has a height H0 in the range of about 20nm to about 80nm. Other heights are also possible. The height H0 of the air gap 132 can be approximately the same as the thickness T0 of the corresponding sacrificial layer 52. In some embodiments, the height of the air gap 132 varies along its length, which is described in more detail below with respect to FIG. 35. All of the air gaps 132 can have approximately the same height, or two or more air gaps 132 can have different heights.

[0066] The etching process for removing the sacrificial layer 52 may include one or more dry etching processes and / or one or more wet etching processes. The groove 130 allows the etchant (e.g., process gas, plasma, wet etchant, etc.) of the etching process to reach and etch the exposed surface of the sacrificial layer 52. In some embodiments, the plasma etching process uses process gases such as O2, CF4, CHF3, C4F8, BCl3, CCl4, Cl2, SF6, HBr, H2, combinations thereof, etc. Other process gases are also possible. In some embodiments, the process gas flows at a rate ranging from about 5sccm to about 50sccm. In some embodiments, the plasma etching process is performed at a process temperature of about 200°C to about 450°C and a process pressure of about 0.1mTorr to about 100mTorr. In some embodiments, the plasma etching process is performed using a plasma power in the range of about 50W to about 500W, and the plasma etching process is performed using a bias power in the range of about 50W to about 500W. Other dry etching processes or process parameters are also possible.

[0067] In some embodiments, the wet etching process includes an etchant such as dilute hydrofluoric acid (dHF); a potassium hydroxide (KOH) solution; ammonia (NH4OH); a solution including HF, nitric acid (HNO3) and / or acetic acid (CH3COOH); a combination thereof; etc. Other etchants are also possible. The wet etching process can be performed in an appropriate manner, such as by immersing in the etchant for a period of time (e.g., less than one hour, etc.). Other wet etching processes are also possible. In some embodiments, the sacrificial layer 52 is removed by performing a dry etching process and then performing a wet etching process. In some embodiments, a wet cleaning process is performed after removing the sacrificial layer 52.

[0068] exist Fig.28 In some embodiments, the air gap 132 is at least partially filled with a sealing material 134. The sealing material 134 is deposited to partially extend into the air gap 132, thereby sealing the air gap 132. Sealing the air gap 132 in this manner can prevent the air gap 132 from being filled in subsequent processing steps and provide additional structural support. Additionally, sealing the air gap 132 isolates the air gap 132 from the subsequently formed contact 110, as described below. Fig.28 Sealing material 134 is shown partially filling trench 130, but in other embodiments, sealing material 134 completely fills trench 130. In some embodiments, sealing material 134 is deposited to a thickness sufficient to seal air gap 132, but does not fill trench 130. In some cases, such as Fig.28 As shown, sealing material 134 may be present on the sidewalls of trench 130 without filling trench 130. Sealing material 134 may extend along the sidewalls and bottom surface of trench 130. Sealing material 134 may extend on the surface of IMD 70 and / or on the surface of conductive line 72, which is exposed by removing sacrificial layer 52. The relative thickness or amount of sealing material 134 deposited within air gap 132 and within trench 130 may be different. Fig.28 The portion of the sealing material 134 extending into the air gap 132 may have a Fig.28 The substantially flat sidewalls shown may have concave sidewalls, or may have convex sidewalls, as described below with respect to Fig.33 As shown and described. Sealing material 134 may contain voids (not shown).

[0069] The sealing material 134 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof. The material of the sealing material 134 may be the same as or different from the material of the IMD 70. The sealing material 134 may be deposited using suitable techniques such as CVD, PVD, ALD, PECVD, etc. For example, in some embodiments, the sealing material 134 may be silicon oxide deposited using a PECVD process. For precursors, the PECVD process may use, for example, dichlorosilane, silane, oxygen, a combination thereof, etc. In some embodiments, the precursors of the PECVD process flow at a rate in the range of about 5 sccm to about 50 sccm. In some embodiments, the PECVD process is performed at a process temperature of about 150°C to about 350°C and a process pressure of about 0.1 mTorr to about 100 mTorr. In some embodiments, the PECVD process is performed using a plasma power in the range of about 5W to about 500W. This is an example, and other process parameters, materials, combinations of materials, or deposition processes are possible.

[0070] exist Fig.29 In some embodiments, an etching process is performed to remove excess portions of the sealing material 134 and form a seal 140. The seal 140 includes a portion of the sealing material 134 that remains after the etching process is performed. The etching process may, for example, remove a portion of the sealing material 134 from the sidewalls and / or bottom surface of the groove 130. In some embodiments, the etching process removes a portion of the sealing material 134 so that the underlying wire 72 is exposed. The etching process may include a dry etching process, a wet etching process, or a combination thereof. For example, the etching process may include an anisotropic dry etching process. In some embodiments, the etching process may include a process similar to the etching process previously described for etching the groove 130 or for removing the sacrificial layer 52, but another etching process may be used in other embodiments.

[0071] In some embodiments, seal 140 may have a total length L3 in the range of about 500 nm to about 1000 nm. In some embodiments, the length L3 of air gap 132 may be between about 5% to about 80% of the length of upper conductor 72, or may be between about 5% to about 80% of the length of lower conductor 72. In some embodiments, the length L3 of seal 140 may be between about 5% to about 80% of the length of correspondingly removed sacrificial layer 52. In some embodiments, seal 140 may protrude a distance L4 below upper conductor 72, which is in the range of about 250 nm to about 500 nm. Other lengths are possible.

[0072] In some embodiments, after the seal 140 is formed, the length L5 of the air gap 132 can be in the range of about 30 μm to about 100 μm. Other lengths are possible. In some embodiments, the length L5 of the air gap 132 can be between about 20% to about 90% of the length of the upper wire 72, or can be between about 20% to about 90% of the length of the lower wire 72. In some embodiments, the volume of the air gap 132 can be between about 20% to about 90% of the volume of the upper wire 72, or can be between about 20% to about 90% of the volume of the lower wire 72. In some embodiments, the length L5 of the air gap 132 can be between about 20% to about 90% of the length of the corresponding removed sacrificial layer 52.

[0073] In some embodiments, different seals 140 may have the same length L3 or L4, or may have different lengths L3 or L4. A seal 140 having a relatively shorter length L3 or L4 may allow the air gap 132 to have a relatively longer length L5. In some embodiments, the length L3 or L4 of the seal 140 may be controlled by controlling the parameters of the process for depositing the seal material 134. In some cases, forming a longer air gap 132 may allow the parasitic capacitance between the wires 72 to be further reduced, thereby improving device performance.

[0074] exist Fig.30 In some embodiments, contacts 110 are formed in trenches 130. In some embodiments, the stepped shape of conductive lines 72 can provide a surface on each conductive line 72 for contact 110 to make electrical contact. In some embodiments, a liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in trenches 130 to form contacts 110. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc. The conductive material may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, combinations thereof, etc. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 70 and multilayer stack 58. The remaining liner and conductive material in trenches 130 form contacts 110.

[0075] Go to Fig.31A , Fig.31B , Fig.31C and Fig.31D , contacts 110 may also be formed on the conductive lines 106 and 108 . Fig.31A A perspective view of a memory array 200 is shown; Fig.31B shows a top view of the memory array 200; Fig.31C Shown along Fig.31A A cross-sectional view of the device and the underlying substrate along line 31C'-31C'; and Fig.31D Shown along Figure 1ACross-sectional view of the device at reference section BB'.

[0076] like Fig.31A As shown in the perspective view of FIG. 70 , conductive contacts 112 and 114 may also be made for conductive lines 106 and conductive lines 108, respectively. Conductive contacts 110, 112, and 114 may be electrically connected to conductive lines 116A, 116B, and 116C, respectively, which connect the memory array to underlying / overlying circuits (e.g., control circuits) and / or signal, power, and ground lines in the semiconductor die. For example, conductive via 118 may extend through IMD 70 to electrically connect conductive line 116C to underlying circuits of interconnect structure 220 and active devices on substrate 50, such as Fig.31C Other conductive vias may be formed through IMD 70 to electrically connect conductors 116A and 116B to underlying circuitry of interconnect structure 220. In alternative embodiments, wiring and / or power lines to and from the memory array may be provided by an interconnect structure formed over memory array 200 in addition to or in lieu of interconnect structure 220. Thus, memory array 200 may be completed.

[0077] although Figures 2 to 31B The embodiments of the present invention show a specific pattern of conductors 106 and 108, but other configurations are also possible. For example, in these embodiments, the conductors 106 / 108 have a staggered pattern. In some embodiments, the conductors 106 / 108 in the same row of the array are all aligned with each other.

[0078] Fig.32 A cross-sectional view illustrating an intermediate step in the fabrication of a memory array 200 in accordance with some embodiments. Fig.32 The structure shown is similar to Fig.30The structure shown, except that the sidewalls of the seal 140 protruding into the air gap 132 have a generally convex shape rather than a generally flat shape. In some cases, one or more precursors that form the seal material 134 during deposition are less likely to adhere to a metal surface than a dielectric surface. For example, the precursor is less likely to adhere to the metal material of the conductive line 72 than the oxide material of the IMD 70. This can cause the deposition of the seal material 134 on the conductive line 72 to be slowed down or delayed, and can cause the seal material 134 to form a protruding sidewall when the seal material 134 is formed in the air gap 132. Once the air gap 132 is completely sealed by the seal material 134, no other precursors can enter the air gap 132 and maintain the protruding sidewalls of the seal material 134. In some cases, as described, the slow or delayed deposition of the seal material 134 on the conductive line 72 can limit the distance that the seal material 134 extends into the air gap 132. By limiting or reducing the protrusion of the seal 140 in the air gap 132 in this manner, the air gap 132 can be formed to have a relatively long length L5, which can reduce the parasitic capacitance between the conductive lines 72.

[0079] Fig.33 A cross-sectional view illustrating an intermediate step in the fabrication of a memory array 200 in accordance with some embodiments. Fig.33 The structure shown is similar to Fig.30 The structure shown, except that the seal 140 is formed at both ends of each air gap 132. In other embodiments, the seal 140 and / or the contact 110 can be formed in other configurations. For example, the seal 140 can be formed at one end of the wire 72, but the contact 110 is formed at both ends of the wire 72. As another example, the seal 140 can be formed at one end of the wire 72, but the contact 110 is formed at the opposite end of the wire 72. Other configurations are also possible and are considered to be within the scope of the present disclosure.

[0080] Fig.34 A cross-sectional view illustrating an intermediate step in the fabrication of a memory array 200 in accordance with some embodiments. Fig.34 The structure shown is similar to Fig.33 The structure shown, except that the conductive line 72 has a curved shape. In some cases, after removing the sacrificial layer 74 to form the air gap 132, the conductive line 72 may sag, bend, or sag. The conductive line 72 may have a curved shape. Fig.34The conductors 72 may have a greater or lesser curvature than the curvature shown, and / or different conductors 72 may have different curvatures. In some embodiments, the conductors 72 may sag a vertical distance within a range between about 30 μm and about 100 μm, but other distances are possible. In some embodiments, due to the sag, the height of the air gap 132 near the center of the air gap 132 may be greater than the height of the air gap 132 near the end of the air gap 132. For example, the height H1 near the center of the topmost air gap 132 of the multilayer stack 58 may be greater than the height H2 near the end of the topmost air gap 132. In other embodiments, the height H1 may be approximately the same as the height H2. In some embodiments, the height H3 of the air gap 132 near the center of the air gap 132 may be greater, smaller, or approximately the same as the height H4 of the air gap 132 near the end of the air gap 132. In an embodiment, one or more air gaps 132 below the topmost air gap 132 of the multilayer stack 58 may have a height that is less than the height H1 of the topmost air gap 132 (e.g., Fig.34 132 ). In other embodiments, the heights of different air gaps 132 may be similar, or the height of a first air gap 132 may be greater than the height of a second air gap 132 above it. In some embodiments, the topmost air gap 132 of a multilayer stack 58 may have the largest height of the air gaps 132 in the multilayer stack 58 (e.g., Fig.34 , and / or the bottom-most air gap 132 of the multilayer stack 58 may have the minimum height of the air gap 132 in the multilayer stack 58 (e.g., Fig.34 The height H5 in the multilayer stack 58). The height of the air gaps 132 in the multilayer stack 58 may be similar or different in other combinations than described herein, and all such combinations are considered to be within the scope of the present disclosure.

[0081] Fig.35A -C shows a plan view of transistor 204 having a different shape according to some embodiments. Fig.35A -C shows something like Fig.25B 1, except that the dielectric material 102, the memory film 90, the OS layer 92, the wires 106 / 108 and the dielectric material 98 have the same Fig.25B In different shapes. Fig.35A The embodiment shown in -C may be incorporated in part or in whole into other embodiments described herein. Fig.35A - The structure shown in C is an example, and other structures are possible.

[0082] exist Fig.35AIn some embodiments, the memory film 90, the OS layer 92, and the conductive lines 106 / 108 are formed to have rounded shapes, such as shapes having a circular, elliptical, or substantially circular cross-section. In some embodiments, the dielectric material 98 may be formed by etching a trench 88 (see FIG. Fig. 20A -C) to form Fig.35A The structure shown in FIG. 1 is such that the groove 88 has a rounded shape. The groove 88 having a rounded shape can be formed, for example, by patterning an opening having a rounded shape in a photoresist for patterning the groove 88. The OS layer 92 and the memory film 90 (see FIG. 1 ) deposited in the groove 88 are Figure 21-22 ) thus has a correspondingly rounded shape. Fig.23A -C) thereafter, a trench 120 may be formed in the dielectric material 102 having a rounded shape (see Fig.24A -C). Therefore, the conductive material 104 deposited in the trench 120 forms the conductive lines 106 / 108 having a rounded-like shape.

[0083] exist Fig.35B In the embodiment, the conductive lines 106 / 108 are formed to have a rounded shape, and the memory film 90 extending across the sidewalls of the dielectric material 98 is not formed. In some embodiments, the memory film 90 may be deposited in the trench 88 by using a selective deposition process (see Fig.21 ) to form Fig.35B For example, the precursors of the deposition process may be selected or controlled so that the memory film 90 is selectively deposited on surfaces other than the surface of the dielectric material 98. The material of the dielectric material 98 may be selected to enhance or provide this deposition selectivity. Figure 22-23C ) thereafter, a trench 120 may be formed in the dielectric material 102 having a rounded shape (see Fig.24A -C). Thus, the conductive material 104 deposited in the trench 120 forms the conductive line 106 / 108 having a similar rounded shape. In some cases, a conductive line 106 / 108 similar to a rounded shape is formed. Fig.35B The transistor 204 shown can increase the contact area between the conductive lines 106 / 108 and the OS layer 92, which can reduce the contact resistance between the conductive lines 106 / 108 and the OS layer 92. In some cases, forming the conductive lines 106 / 108 in this manner can increase the lateral extent of the contact area by a distance in the range of about 5 nm to about 15 nm.

[0084] exist Fig.35C In the embodiment, the memory film 90 and the OS layer 92 extending across the sidewall of the dielectric material 98 are not formed, and the formed conductive line 106 / 108 has a partially rounded shape and extends across the dielectric material 98. In some embodiments, the conductive line 106 / 108 may be formed by selectively depositing the OS layer 92. Fig.35C In some cases, a structure similar to Fig.35C The transistor 204 shown can increase the contact area between the conductive lines 106 / 108 and the OS layer 92, which can reduce the contact resistance between the conductive lines 106 / 108 and the OS layer 92. In some cases, forming the conductive lines 106 / 108 in this manner can increase the lateral extent of the contact area by a distance in the range of about 5 nm to about 30 nm.

[0085] Various embodiments provide a 3D memory array with vertically stacked memory cells. Each memory cell includes a transistor having a memory film, a gate dielectric material, and an oxide semiconductor channel region. The transistor includes a source / drain electrode, which is also a source line and a bit line in the memory array. The transistor also includes a gate electrode, which is also a word line in the memory array. The dielectric material is disposed between the source / drain electrodes and isolates adjacent source / drain electrodes. In some embodiments, a sacrificial layer is formed between each word line of the vertical stack of word lines. The sacrificial layer is removed, thereby forming an air gap between vertically adjacent word lines. Because air has a lower dielectric constant than many other dielectric materials (e.g., oxides, nitrides, etc.), separating word lines with air gaps instead of dielectric materials can reduce parasitic capacitance between different word lines. By reducing parasitic capacitance in this way, the speed of the device (e.g., response speed, switching speed, etc.) can be increased, and parasitic noise can be reduced. This can improve the operation of the device, especially when operating at a relatively high frequency.

[0086] According to some embodiments, a memory device includes: a semiconductor substrate; a first transistor located above the semiconductor substrate, wherein the first transistor includes a first word line extending above the semiconductor substrate; a second transistor located above the semiconductor substrate, wherein the second transistor includes a second word line extending above the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along the first word line and the second word line, wherein the memory film contacts the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is located between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is located between the bit line and the word line; and an isolation region located between the source line and the bit line. In an embodiment, at least one end of the air gap is sealed by a first dielectric material extending between the first word line and the second word line. In an embodiment, the memory device includes a conductive contact extending through the first dielectric material to physically contact the first word line. In an embodiment, the memory device includes an intermetallic dielectric layer (IMD) located above and in physical contact with the first word line and the first dielectric material. In an embodiment, the air gap has a first length and the second word line has a second length, wherein the first length is in a range of 5% to 80% of the second length. In an embodiment, the memory device includes a second dielectric material extending above and in physical contact with the second word line. In an embodiment, the memory device includes a third transistor located above the semiconductor substrate, wherein the third thin film transistor includes a third word line extending above the second word line; and a second air gap extending between the second word line and the third word line. In an embodiment, the volume of the second air gap is less than the volume of the first air gap.

[0087] According to some embodiments, a device includes: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell including a first thin film transistor, wherein the first transistor includes a first gate electrode, the first gate electrode including a portion of a first word line, wherein a bottom surface of the first gate electrode is exposed through a first air gap, wherein a top surface of the first gate electrode is exposed through a second air gap; a first portion of a ferroelectric material, wherein the first portion of the ferroelectric material is located on a sidewall of the first gate electrode; and a first channel region located on a sidewall of the first portion of the ferroelectric material; a source line, wherein the first portion of the source line provides a first source / drain electrode for the first transistor; a bit line, wherein the first portion of the bit line provides a second source / drain electrode for the first transistor; and a first dielectric material separating the source line and the bit line. In embodiments, the device includes a second memory cell located above the first memory cell, the second memory cell including a second transistor, wherein the second transistor includes a second gate electrode, the second gate electrode including a portion of a second word line, wherein a bottom surface of the second gate electrode is exposed through a second air gap. In an embodiment, the top surface of the second gate electrode is covered by a second dielectric material. In an embodiment, the bottom surface of the first gate electrode includes a first end and a second end, wherein a portion of the bottom surface between the first end and the second end is closer to the semiconductor substrate than the first end and the second end. In an embodiment, the height of the second air gap is greater than the height of the first air gap. In an embodiment, the device includes a first sealant located on the bottom surface of the first gate electrode and a second sealant located on the top surface of the first gate electrode, wherein the first sealant and the second sealant are sealing materials. In an embodiment, a cross section of the source line and a cross section of the bit line have a rounded shape.

[0088] According to some embodiments, a method includes: depositing alternating layers of conductive material and sacrificial material to form a multilayer stack including conductive material layers and sacrificial material layers; depositing a memory film along the sidewalls of the multilayer stack; depositing an oxide semiconductor (OS) layer over the memory film; forming an intermetallic dielectric (IMD) layer over the multilayer stack; patterning trenches in the IMD, wherein each trench in the trenches exposes a corresponding sacrificial material layer in the sacrificial material layer; performing an etching process through the trenches to remove the sacrificial material layer, wherein removing the sacrificial layer forms an air gap between the conductive material layers of the conductive material layer; and depositing a dielectric material in the trenches, wherein the dielectric material seals the air gap. In an embodiment, the sacrificial material is silicon. In an embodiment, the etching process includes performing a dry etching process and then performing a wet etching process. In an embodiment, depositing the dielectric material includes depositing an oxide using a PECVD process. In an embodiment, the method includes forming a contact of the conductive layer, including depositing the conductive material in the trench.

[0089] A memory device according to an embodiment of the present application includes: a semiconductor substrate; a first transistor located above the semiconductor substrate, wherein the first transistor includes a first word line extending above the semiconductor substrate; a second transistor located above the semiconductor substrate, wherein the second transistor includes a second word line extending above the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along the first word line and the second word line, wherein the memory film contacts the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is located between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is located between the bit line and the word line; and an isolation region located between the source line and the bit line. In some embodiments, at least one end of the air gap is sealed by a first dielectric material extending between the first word line and the second word line. In some embodiments, a conductive contact extending through the first dielectric material to physically contact the first word line is also included. In some embodiments, an intermetallic dielectric layer (IMD) is also included that is located above and in physical contact with the first word line and the first dielectric material. In some embodiments, the air gap has a first length and the second word line has a second length, wherein the first length is in a range of 5% to 80% of the second length. In some embodiments, a second dielectric material is also included that extends above and in physical contact with the second word line. In some embodiments, a third transistor is also included that is located above the semiconductor substrate, wherein the third transistor includes a third word line that extends above the second word line; and a second air gap that extends between the second word line and the third word line. In some embodiments, the volume of the second air gap is less than the volume of the first air gap.

[0090] An embodiment of the present application provides a device, comprising: a semiconductor substrate; a first memory cell located above the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises: a first gate electrode comprising a portion of a first word line, wherein the bottom surface of the first gate electrode is exposed through a first air gap, wherein the top surface of the first gate electrode is exposed through a second air gap; a first portion of a ferroelectric material, wherein the first portion of the ferroelectric material is located on a sidewall of the first gate electrode; and a first channel region located on a sidewall of the first portion of the ferroelectric material; a source line, wherein the first portion of the source line provides a first source / drain electrode for the first thin film transistor; a bit line, wherein the first portion of the bit line provides a second source / drain electrode for the first thin film transistor; and a first dielectric material separating the source line from the bit line. In some embodiments, a second memory cell located above the first memory cell is further included, the second memory cell comprising a second transistor, wherein the second transistor comprises a second gate electrode, the second gate electrode comprising a portion of a second word line, wherein the bottom surface of the second gate electrode is exposed through the second air gap. In some embodiments, the top surface of the second gate electrode is covered by a second dielectric material. In some embodiments, the bottom surface of the first gate electrode includes a first end and a second end, wherein a portion of the bottom surface between the first end and the second end is closer to the semiconductor substrate than the first end and the second end. In some embodiments, the height of the second air gap is greater than the height of the first air gap. In some embodiments, a first sealant located on the bottom surface of the first gate electrode and a second sealant located on the top surface of the first gate electrode are further included, wherein the first sealant and the second sealant include a sealing material. In some embodiments, a cross-section of the source line and a cross-section of the bit line have a rounded shape.

[0091] Embodiments of the present application also provide a method, comprising: depositing alternating layers of conductive material and sacrificial material to form a multilayer stack including multiple conductive material layers and multiple sacrificial material layers; depositing a memory film along the sidewalls of the multilayer stack; depositing an oxide semiconductor (OS) layer over the memory film; forming an intermetallic dielectric (IMD) layer over the multilayer stack; patterning multiple grooves in the IMD, wherein each of the multiple grooves exposes a corresponding sacrificial material layer in the multiple sacrificial material layers; performing an etching process through the multiple grooves to remove the multiple sacrificial material layers, wherein removing the multiple sacrificial layers forms air gaps between the conductive material layers of the multiple conductive material layers; and depositing a dielectric material in the multiple grooves, wherein the dielectric material seals the air gaps. In some embodiments, the sacrificial material is silicon. In some embodiments, the etching process comprises performing a dry etching process followed by a wet etching process. In some embodiments, depositing the dielectric material comprises depositing oxide using a PECVD process. In some embodiments, it also comprises forming contacts of the multiple conductive layers, comprising depositing a conductive material in the multiple grooves.

[0092] The components of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be appreciated by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: Semiconductor substrate; A first transistor located above the semiconductor substrate, wherein the first transistor includes a first word line extending above the semiconductor substrate; a second transistor disposed above the semiconductor substrate, wherein the second transistor comprises a second word line extending above the first word line; a first air gap extending between the first word line and the second word line; a memory film extending in a direction perpendicular to an extending direction of the first word line and the second word line and in a direction perpendicular to the semiconductor substrate, wherein the memory film contacts the first word line and the second word line; a channel layer extending along the sidewalls and bottom surface of the memory film; a source line extending along the channel layer and perpendicular to the first word line and the second word line, wherein the memory film is located between the source line and the second word line; a bit line extending along the channel layer and perpendicular to the first word line and the second word line, wherein the memory film is located between the bit line and the second word line; and An isolation region is located between the source line and the bit line.

2. The memory device according to claim 1, wherein: At least one end of the first air gap is sealed by a first dielectric material extending between the first word line and the second word line. 3 . The memory device of claim 2 , further comprising a conductive contact extending through the first dielectric material to physically contact the first word line. 4 . The memory device of claim 2 , further comprising an intermetallic dielectric layer over and in physical contact with the first word line and the first dielectric material.

5. The memory device according to claim 1, wherein: The first air gap has a first length and the second word line has a second length, wherein the first length is in a range of 5% to 80% of the second length. 6 . The memory device of claim 1 , further comprising a second dielectric material extending over and in physical contact with the second word line.

7. The memory device according to claim 1, further comprising: a third transistor located above the semiconductor substrate, wherein the third transistor includes a third word line extending above the second word line; and A second air gap extends between the second word line and the third word line.

8. The memory device according to claim 7, wherein: The volume of the second air gap is smaller than the volume of the first air gap.

9. A storage device comprising: Semiconductor substrate; A first memory cell is located above the semiconductor substrate, wherein the first memory cell comprises a first transistor, wherein the first transistor comprises: a first gate electrode including a portion of a first word line, wherein a bottom surface of the first gate electrode is exposed through a first air gap, and wherein a top surface of the first gate electrode is exposed through a second air gap; a second sealing member, located on a top surface of the first gate electrode; a conductive contact extending through the second seal to physically contact the first word line, wherein the conductive contact is laterally spaced apart from a second air gap by the second seal; a first portion of a ferroelectric material, wherein the first portion of the ferroelectric material is located on a sidewall of the first gate electrode; and a first channel region located on a sidewall of the first portion of the ferroelectric material; a source line, wherein a first portion of the source line provides a first source / drain electrode for the first transistor; a bit line, wherein a first portion of the bit line provides a second source / drain electrode for the first transistor; and A first dielectric material separates the source line from the bit line.

10. The memory device according to claim 9, further comprising a second memory cell located above the first memory cell, the second memory cell comprising a second transistor, wherein The second transistor includes a second gate electrode including a portion of a second word line, wherein a bottom surface of the second gate electrode is exposed through the second air gap.

11. The memory device according to claim 10, wherein: A top surface of the second gate electrode is covered by a second dielectric material.

12. The memory device according to claim 9, wherein: A bottom surface of the first gate electrode includes a first end and a second end, wherein a portion of the bottom surface between the first end and the second end is closer to the semiconductor substrate than the first end and the second end.

13. The memory device according to claim 9, wherein: The height of the second air gap is greater than the height of the first air gap.

14. The memory device according to claim 9, further comprising a first sealing member located on a bottom surface of the first gate electrode, wherein The first seal and the second seal include a sealing material.

15. The memory device according to claim 9, wherein: A cross section of the source line and a cross section of the bit line have a rounded shape.

16. A method of forming a memory device, comprising: depositing alternating layers of conductive material and sacrificial material to form a multilayer stack including a plurality of layers of conductive material and a plurality of layers of sacrificial material; depositing a memory film along sidewalls of the multilayer stack; depositing an oxide semiconductor layer over the memory film; forming an intermetal dielectric layer over the multilayer stack; patterning a plurality of trenches in the intermetal dielectric layer, wherein each trench of the plurality of trenches exposes a corresponding sacrificial material layer of the plurality of sacrificial material layers; performing an etching process through the plurality of trenches to remove the plurality of sacrificial material layers, wherein removing the plurality of sacrificial material layers forms air gaps between the conductive material layers of the plurality of conductive material layers; depositing a dielectric material in the plurality of trenches, wherein the dielectric material seals the air gap; performing an etching process within the plurality of trenches so that each trench extends through the dielectric material and exposes a corresponding layer of conductive material; and A conductive filling material is deposited in the plurality of trenches to form a plurality of contacts, wherein each contact physically and electrically contacts a corresponding conductive material layer.

17. The method for forming a memory device according to claim 16, wherein: The sacrificial material is silicon.

18. The method for forming a memory device according to claim 16, wherein: The etching process includes performing a dry etching process followed by a wet etching process.

19. The method for forming a memory device according to claim 16, wherein: Depositing the dielectric material includes depositing an oxide using a PECVD process.

20. The method for forming a memory device according to claim 16, wherein: Each contact is laterally separated from a corresponding air gap by the dielectric material.

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