Configuration Method, Device, and Storage Medium for the Logical Address Space of a Hardware Single Board

Abstract

Embodiments of the present invention relate to the field of communications, and disclose a method for configuring the logical address space of a hardware single board, including: dividing the logical address space of the hardware single board into N functional blocks according to the functions supported by the hardware single board, where each functional block corresponds to one function; in each functional block, respectively set a function information area, a function implementation area, and a function address area, where the function information area is used to record information about the functional block, the function implementation area is used to implement the function of the functional block, the function address area of the nth functional block is used to point to the starting address of the (n + 1)th functional block, n is a natural number less than N, and the function address area of the Nth functional block points to a preset value. The present invention also discloses a device and a storage medium. The method, device, and storage medium for configuring the logical address space of the hardware single board disclosed by the present invention reduce the impact of differences between different types of hardware single boards in the hardware system on the code design of the upper-layer software.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of communications, and particularly to a method, device, and storage medium for configuring the logical address space of a hardware single board. Background Art

[0002] Hardware Description Language (HDL) is a language for describing the behavior, structure, and data flow of the hardware of an electronic system. Using the hardware description language, the design idea of a digital circuit system can be described layer by layer from the top layer to the bottom layer (from abstract to concrete), and an extremely complex digital circuit system can be represented by a series of hierarchical modules.

[0003] Currently, in conventional hardware design, the hardware description language has been widely used. In a complete software and hardware system, the hardware description language configures the logical address space of the hardware single board, and is a layer that connects the upper layer software and the lower layer hardware.

[0004] However, the inventors found that: in a hardware system composed of multiple different types of hardware single boards, due to the differences between different types of hardware single boards, the upper layer software needs to perform code design for each type of hardware single board, resulting in poor compatibility of the hardware system. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a method, device, and storage medium for configuring the logical address space of a hardware single board, so as to reduce the impact of the differences between different types of hardware single boards in the hardware system on the code design of the upper layer software and improve the compatibility of the hardware system.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for configuring the logical address space of a hardware single board, including: dividing the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board, where N is a positive integer greater than 1, and each function block corresponds to a function supported by the hardware single board; in each function block, a function information area, a function implementation area, and a function address area are respectively set, where the function information area is used to record the information of the function block, the function implementation area is used to implement the function of the function block, the function address area of the nth function block is used to point to the starting address of the (n + 1)th function block, n is a natural number less than N, and the function address area of the Nth function block points to a preset value.

[0007] Embodiments of the present invention also provide a device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the configuration method of the logical address space of the above-mentioned hardware single board.

[0008] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the configuration method of the logical address space of the above-mentioned hardware single board is implemented.

[0009] Compared with the prior art, embodiments of the present invention divide the logical address space of a hardware single board into N functional blocks according to the functions supported by the hardware single board, and each functional block corresponds to one function supported by the hardware single board; in each functional block, a function information area, a function implementation area, and a function address area are respectively set, wherein the function information area is used to record information of the functional block, the function implementation area is used to implement the function of the functional block, the function address area of the nth functional block is used to point to the start address of the (n + 1)th functional block, and the function address area of the Nth functional block points to a preset value. Dividing the logical address space of the hardware single board into N functional blocks according to the functions supported by the hardware single board enables the upper-layer software not to consider the type of each specific single board, but to load code for each functional block. Moreover, after the upper-layer software loads one functional block, it can load the next functional block according to the address provided by the function address area of this functional block, and finally complete the loading of all functional blocks, thereby reducing the impact of differences between different types of hardware single boards in the hardware system on the code design of the upper-layer software and improving the compatibility of the hardware system.

[0010] In addition, after dividing the logical address space of the hardware single board into N functional blocks according to the functions supported by the hardware single board, it further includes: setting a reserved area in each functional block, and the reserved area of each functional block is a reserved space for function expansion or function upgrade of the functional block. By configuring a reserved area for function expansion or function upgrade of the functional block in each functional block, each functional block can utilize the reserved area for function expansion or function upgrade, thereby enabling the hardware single board to have scalability.

[0011] In addition, before setting the reserved area in each of the functional blocks, the following steps are further included: determining the size of the space occupied by the reserved area of each functional block according to the functions supported by the corresponding hardware single board of each functional block. Setting the reserved area in each functional block and respectively determining the size of the reserved area of each functional block according to the various functions supported by the hardware single board can ensure that the preset reserved area can meet the upgrade requirements of each functional block during subsequent function upgrades and will not cause problems with code compatibility before and after the upgrade.

[0012] In addition, the information of the functional block recorded in each functional information area includes the version number of the functional block. By recording the version number of each functional block in the functional information area of each functional block, it is convenient to obtain the version number of each functional block during subsequent management or maintenance of each functional block, improving the maintainability of the hardware single board.

[0013] In addition, after dividing the logical address space of the hardware single board into N functional blocks according to the functions supported by the hardware single board, the following steps are further included: marking a functional block identifier for each of the functional blocks; the information of the functional block recorded in each functional information area includes the functional block identifier of the functional block.

[0014] In addition, each of the functional information areas or each of the functional address areas occupies the same space.

[0015] In addition, the N functional blocks include a basic functional block; the basic functional block includes at least one of a logical device self-information functional block, a single board basic information functional block, a single board status information functional block, and a single board control class register functional block.

[0016] In addition, the N functional blocks further include a specific functional block; the specific functional block includes at least one of an I2C controller functional block, an SMI / MDIO controller functional block, a UART controller functional block, a SPI controller functional block, and a tooling test register functional block. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplary illustrations do not constitute limitations on the embodiments.

[0018] Figure 1 is a schematic flowchart of a method for configuring the logical address space of a hardware single board according to the first embodiment of the present invention;

[0019] Figure 2 is a schematic flowchart of a method for configuring the logical address space of a hardware single board according to the second embodiment of the present invention;

[0020] Figure 3It is a schematic diagram of dividing the logical address space of a hardware single board according to the second embodiment of the present invention;

[0021] Figure 4 It is a schematic flowchart of a configuration method for the logical address space of a hardware single board according to the third embodiment of the present invention;

[0022] Figure 5 It is a schematic diagram of dividing the logical address space of a hardware single board according to the third embodiment of the present invention;

[0023] Figure 6 It is a schematic structural diagram of a device according to the fourth embodiment of the present invention. Specific embodiments

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on each embodiment of the present invention with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0025] The first embodiment of the present invention relates to a configuration method for the logical address space of a hardware single board, including: dividing the logical address space of the hardware single board into N functional blocks according to the functions supported by the hardware single board, where N is a positive integer greater than 1, and each functional block corresponds to a function supported by the hardware single board; in each functional block, a function information area, a function implementation area, and a function address area are respectively set, where the function information area is used to record information of the functional block, the function implementation area is used to implement the function of the functional block, the function address area of the nth functional block is used to point to the starting address of the (n + 1)th functional block, n is a natural number less than N, and the function address area of the Nth functional block points to a preset value. This embodiment reduces the impact of differences between different hardware single boards in the hardware system on the code design of the upper-layer software and improves the compatibility of the hardware system. The following specifically describes the implementation details of the configuration method for the logical address space of the hardware single board in this embodiment. The following content is only implementation details provided for convenience of understanding and is not necessary for implementing this solution.

[0026] The configuration method for the logical address space of the hardware single board in this embodiment is as Figure 1 shown:

[0027] Step 101: Divide the logical address space of the hardware single board into N functional blocks according to the functions supported by the hardware single board, where N is a positive integer greater than 1, and each functional block corresponds to a function supported by the hardware single board.

[0028] Specifically, the logical address space of the hardware single board is divided according to the functions supported by the hardware single board, and N function blocks are obtained. When dividing the function blocks, there is no specific requirement for the sequence relationship between the function blocks, and the address space range and starting address of each function block can be determined in combination with the total address space in the specific system.

[0029] Step 102: In each of the function blocks, a function information area, a function implementation area, and a function address area are respectively set. The function information area is used to record information about the function block. The function implementation area is used to implement the function of the function block. The function address area of the nth function block is used to point to the starting address of the (n + 1)th function block, where n is a natural number less than N, and the function address area of the Nth function block points to a preset value.

[0030] Specifically, the function information area is used to record information about the function block. The information of the function block may include the function block identifier of the function block (the function block identifier can be marked for each function block after step 101 is executed), the version number of the function block, the generation date of the function block, etc.

[0031] It is worth mentioning that when the information of the function block recorded in each function information area includes the version number of the function block, it is convenient to obtain the version number of each function block during subsequent management or maintenance of each function block, improving the maintainability of the hardware single board.

[0032] The function implementation area is used to implement the function of the function block. The function implementation area of each function block is the Board Support Package (BSP) interface register that implements the function of the function block and is an interface for interacting with the upper-layer software.

[0033] The function address area is used to point to the starting address of another function block, and the function address area of the Nth function block points to a preset value (or an invalid address). The function blocks establish a mapping relationship by pointing to the starting address of the next function block through the function address area, so that the upper-layer software can, after loading a function block, load the next function block according to the starting address pointed to by the function address area of this function block, and complete the loading of all function blocks when loading to the preset value (or invalid address) pointed to by the function address area. For example, when N = 3, the function address area of the first function block points to the starting address of the second function block, the function address area of the second function block points to the starting address of the third function block, and the function address area of the third function block points to a preset value (or an invalid address).

[0034] In addition, in this embodiment, when setting the function information area, the information recorded in the function information area of each function block can be uniformly set. At this time, the space occupied by the function information area or the function address area of each function block is the same, which is beneficial to improving the loading efficiency of the upper-layer software for each function block.

[0035] Compared with the prior art, in this embodiment, according to the functions supported by the hardware single board, the logical address space of the hardware single board is divided into N function blocks, and each function block corresponds to one function supported by the hardware single board; in each function block, a function information area, a function implementation area, and a function address area are respectively set. Among them, the function information area of each function block is used to record the information of the function block, the function implementation area of each function block is used to implement the function of the function block, the function address area of the nth function block is used to point to the starting address of the (n + 1)th function block, and the function address area of the Nth function block points to a preset value. Dividing the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board enables the upper-layer software not to consider the type of each specific single board, but to load code for each function block; moreover, a mapping relationship is established between function blocks by the function address area pointing to the starting address of the next function block, so that after the upper-layer software loads a function block, it can load the next function block according to the address provided by the function address area of the function block, and finally complete the loading of all function blocks, thereby improving the compatibility of the hardware system.

[0036] The second embodiment of the present invention relates to a method for configuring the logical address space of a hardware single board. The second embodiment is a further improvement of the first embodiment. The main improvement lies in that in this embodiment, after the step of dividing the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board, it further includes setting a reserved area in each of the function blocks.

[0037] The method for configuring the logical address space of the hardware single board in this embodiment is as Figure 2 shown, and specifically includes:

[0038] Step 201: Divide the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board.

[0039] Step 201 is substantially the same as step 101 in the first embodiment. To avoid repetition, it will not be elaborated here.

[0040] Step 202: Set a reserved area in each of the function blocks. The reserved area is a reserved space for the function upgrade of the function block.

[0041] Specifically, the reserved area is the reserved space for the function block to upgrade the functions it supports. For example, the single-board status information function block supports the function of recording the reasons for single-board reset. It reserves 8 records of reset reasons. Subsequently, due to usage requirements, it may be necessary to increase the number of reserved reset reason records. At this time, by setting the reserved area as the reserved space for the function block to upgrade its functions, the space in the reserved area can be used for the upgrade of this function. In addition, when the interface control function block (such as the I2C control function block, which supports the function of controlling the I2C interface) expands the number of interfaces, it can also expand the number of interfaces by using the space in the reserved area.

[0042] Furthermore, in this embodiment, the size of the reserved area can be determined in the following manner: Before setting the reserved area in each function block, based on the functions supported by the corresponding hardware single board of each function block, determine the size of the space occupied by each reserved area. When determining the size of the reserved area of a function block, the size of the reserved area can be evaluated based on the maximum requirements for function upgrade supported by this function block (reference can be made to the function blocks of all single boards in the entire hardware system that support the same function as this function block, and the size of the reserved area can be determined according to the application that occupies the most space for the same function). By setting the reserved area in each function block and respectively determining the size of the reserved area of each function block according to the various functions supported by the hardware single board, it can be ensured that when performing function upgrades subsequently, the preset reserved area can meet the upgrade requirements of each function block and will not cause problems with code compatibility before and after the upgrade.

[0043] For example, when determining the size of the reserved area of the single-board status information function block, according to the function of "recording the reason for each single-board reset" supported by this function block, one record of reset reason requires 16 bits of occupancy. Currently, this function block supports reserving 8 records of reset reasons. Considering that in the single-board status information function blocks of all single boards in the entire hardware system, the application that occupies the most space for the function of "recording the reason for each single-board reset" is to reserve 12 records of reset reasons, the size of the reserved area is determined to be 64 bits ((12 - 8) * 16). In another example, when determining the size of the reserved area of the I2C control function block, this function block controls 16 physical channels through the chip select register. Currently, the chip select register of this function block occupies 16 bits, and each bit corresponds to a physical channel. Considering that the maximum usage requirement of this function requires 32 physical channels, the size of the reserved area is determined to be 16 bits.

[0044] Step 203: In each of the function blocks, respectively set a function information area, a function implementation area, and a function address area.

[0045] Step 203 is substantially the same as step 102 in the first embodiment. To avoid repetition, it will not be elaborated here.

[0046] It should be noted that in this embodiment, step 202, which is the step of setting the reserved area, and step 203, which is the step of setting the function information area, the function implementation area, and the function address area, do not limit the order. In actual applications, step 203 can also be executed first, followed by step 202, or steps 202 and 203 can be executed simultaneously.

[0047] For example, the logical address space division of a hardware single board in the system is as Figure 3 shown. The label X05 (X = 1, 2,..., N) is the logical address space based on a single independent function, and there are N in total. The logical address space of each independent function includes several parts: X01, X02, X03, and X04. X01 is the function information area, X02 is the function address area, X03 is the function implementation area, and X04 is the reserved area.

[0048] Compared with the previous embodiment, in this embodiment, after the step of dividing the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board, it further includes setting a reserved area in each of the function blocks. The reserved area of each function block is the reserved space for function upgrade of the function block. By configuring a reserved area for each function block as the reserved space for function upgrade of the function block, each function block can utilize the reserved area for function upgrade, thereby enabling the hardware single board to have scalability.

[0049] The third embodiment of the present invention relates to a method for configuring the logical address space of a hardware single board. The third embodiment is substantially the same as the second embodiment, except that in this embodiment, in the step of dividing the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board, the N function blocks include a basic function block and a specific function block.

[0050] The method for configuring the logical address space of the hardware single board in this embodiment is as Figure 4 shown, and specifically includes:

[0051] Step 301: Divide the logical address space of the hardware single board into N function blocks according to the functions supported by the hardware single board, where the N function blocks include a basic function block and a specific function block.

[0052] Specifically, the logical address space of the hardware single board is divided according to the functions supported by the hardware single board, and N functional blocks are obtained, including a basic functional block and specific functional blocks. Among them, the basic functional block is the basic functional block shared by all single boards within the same hardware system. Assume that the set of types of logical functions to be implemented by all different hardware single boards in the system is A, then N <= A, and the value of N can be different for different hardware single boards. Assume that the number of basic functional blocks shared by all hardware single boards is B, then 1 <= B <= A.

[0053] Furthermore, the basic functional block may include at least one of a logical device self-information functional block, a single board basic information functional block, a single board status information functional block, and a single board control class register functional block.

[0054] The specific functional block may include at least one of an I2C controller functional block, an SMI / MDIO controller functional block, a UART controller functional block, an SPI controller functional block, and a tooling test register functional block.

[0055] Step 302: Set a reserved area in each of the functional blocks. The reserved area of each functional block is the reserved space for function upgrade of the functional block.

[0056] Step 303: In each of the functional blocks, set a function information area, a function implementation area, and a function address area respectively.

[0057] Steps 302 to 303 are substantially the same as steps 202 to 203 in the second embodiment. To avoid repetition, they will not be elaborated here one by one.

[0058] For example, the division of the logical address space of a hardware single board in the system is as Figure 5 shown. In this example, according to different types of single boards, the logical functions of the board are classified into 9 types, as shown in Table 1 (FuncID represents the function block identifier of each functional block), which are: logical device self-information, single board basic information, single board status information, single board control class register, I2C controller, SMI / MDIO controller, UART controller, SPI controller, tooling test register. Among them, the first 4 are the basic functions shared by different single boards. Figure 5After the hardware single board in [[ ]] is divided by the logical address space, five functional blocks are obtained, namely the functional block of the programmable logic device's own information (corresponding function: reporting the information, version, generation date, etc. of the programmable logic device itself, functional block space length: 0x20), the functional block of the single board's basic information (corresponding function: reporting the basic information of the single board, such as BoardID, PCBID, etc., functional block space length: 0x40), the functional block of the single board's status information (corresponding function: reporting the status information of the single board, such as the presence information of daughter cards, etc., functional block space length: 0x40), the functional block of the single board's control (corresponding function: controlling the single board, functional block space length: 0x40), and the functional block of the I2C control (corresponding function: controlling the I2C interface, functional block space length: 0x40). For Figure 5 The English annotations in [[ ]] are described in Table 2.

[0059] Function Block Identifier Description FuncID:0 Self-Information of Logic Device FuncID:1 Basic Information of Single Board FuncID:2 Status Information of Single Board FuncID:3 Control Registers of Single Board FuncID:16 I2C Controller FuncID:17 SMI / MDIO Controller FuncID:18 UART Controller FuncID:19 SPI Controller FuncID:20 Tooling Test Register

[0060] Table 1

[0061] Item Description Register Bit Width 16 bits FuncID Function Block Identifier, 8 bits, range 0 - 255 Revision Version Number, 8 bits, range 0 - 255 NextPointer Function Address Area, 32 bits

[0062] Table 2

[0063] Furthermore, taking the functional block of the programmable logic device's own information as an example for the address space division of a single functional block, the corresponding function of this functional block is to report the information, version, generation date, etc. of the programmable logic device itself. Its functional block identifier is 0, the space length of the entire functional block is 0x20, and the register bit width is 16 bits. Among them, the functional information area and the functional address area are collectively called the logical function header. The functional information area includes: FuncID (functional block identifier), representing function classification, 8 bits, range 0 - 255; Revsion version number, representing the function version, 8 bits, range 0 - 255; Reserved, reserved for future function identifier expansion, 16 bits. The functional address area is represented as NextPointer, representing the start address of the next functional block, 32 bits. The above content, because it is defined uniformly in different functional modules and occupies the same bit width, is called the logical function header. The functional implementation area in the functional block of the programmable logic device's own information contains EpldVersion, representing the current Epld logic version number, 16 bits. EpldDate, representing the compilation date of the current logic version, 16 bits. The address space corresponding to the reserved area is the undefined area from 0xd to 0x20, a total of 160 bits, reserved for future function upgrades.

[0064] In this example, the functional address area of the logic device's own information function block points to the starting address of the single board basic information block, the single board basic information function block then points to the single board status information function block, the single board status information function block points to the single board control function block, and the single board control function block points to the I2C control function block. At this point, the current hardware single board logical functions have been listed, and the I2C controller interface area points to address 0xffff, indicating that the current functional module is the last functional module of the single board for software judgment.

[0065] Compared to the prior art, this embodiment divides the logical address space of a hardware board into N function blocks based on the functions supported by the hardware board, with each function block corresponding to a function supported by the hardware board. Within each function block, a function information area, a function implementation area, and a function address area are provided. The function information area of each function block is used to record information about the function block, the function implementation area of each function block is used to implement the function of the function block, the function address area of the nth function block is used to point to the starting address of the n+1th function block, and the function address area of the Nth function block points to a preset value. By dividing the logical address space of a hardware board into N function blocks based on the functions supported by the hardware board, upper-layer software can load code for each function block without considering the specific type of each board. Furthermore, a mapping relationship is established between function blocks, with the function address area pointing to the starting address of the next function block. This allows upper-layer software to load the next function block after loading one function block, based on the address provided by the function address area of the previous function block, ultimately completing the loading of all function blocks, thereby improving the compatibility of the hardware system.

[0066] The steps of the various methods above are divided only for the purpose of clear description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0067] A fourth embodiment of the present invention relates to a device, such as Figure 4 As shown, it includes at least one processor 401; and a memory 402 that is communicatively connected to the at least one processor 401; wherein the memory 402 stores instructions that can be executed by the at least one processor 401, and the instructions are executed by the at least one processor 401 to enable the at least one processor 401 to execute the logical address space configuration method in any of the above-mentioned method embodiments.

[0068] Among them, the memory 402 and the processor 401 are connected in a bus manner. The bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors 401 and the memory 402 together. The bus may also connect various other circuits together, such as peripheral devices, voltage regulators, and power management circuits, etc., which are well known in the art, so they will not be further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one component or multiple components, such as multiple receivers and transmitters, and provides a unit for communicating with various other devices on the transmission medium. The data processed by the processor 401 is transmitted on the wireless medium through the antenna. Further, the antenna also receives data and transmits the data to the processor 401.

[0069] The processor 401 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory 402 can be used to store the data used by the processor 401 when executing operations.

[0070] The embodiments of the present invention also provide a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, it implements the configuration method of the logical address space in any of the above method embodiments.

[0071] That is, those skilled in the art can understand that all or part of the steps in implementing the above method embodiments can be completed by instructing relevant hardware through a program. This program is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0072] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention.

Claims

1. A method for configuring the logical address space of a hardware board, characterized in that: include: Dividing the logical address space of the hardware board into N function blocks according to the functions supported by the hardware board, where N is a positive integer greater than 1, and each function block corresponds to a function supported by the hardware board; In each of the function blocks, a function information area, a function implementation area, and a function address area are respectively set, wherein the function information area is used to record information of the function block, the function implementation area is used to implement the function of the function block, and the function address area of the nth function block is used to point to the starting address of the (n+1)th function block, where n is a natural number less than N, and the function address area of the Nth function block points to a preset value; A reserved area is set in each of the functional blocks, and the reserved area is a reserved space for function upgrade of the functional block.

2. The method for configuring the logical address space of a hardware board according to claim 1, wherein: Before setting the reserved area in each of the functional blocks, the method further includes: The size of the space occupied by the reserved area of each functional block is determined according to the functions supported by the hardware board corresponding to each functional block.

3. The method for configuring the logical address space of a hardware board according to claim 1, wherein: The information of the function block recorded in each function information area includes a version number of the function block.

4. The method for configuring the logical address space of a hardware board according to claim 1, wherein: After dividing the logical address space of the hardware board into N functional blocks according to the functions supported by the hardware board, the method further includes: Marking each functional block with a functional block identifier; The information of the function block recorded in each function information area includes a function block identifier of the function block.

5. The method for configuring the logical address space of a hardware board according to claim 1, wherein: The space occupied by each of the function information areas or each of the function address areas is the same.

6. The method for configuring the logical address space of a hardware board according to claim 1, wherein: The N functional blocks include basic functional blocks; The basic function block includes at least one of a logic device self-information function block, a single board basic information function block, a single board status information function block and a single board control register function block.

7. The method for configuring the logical address space of a hardware board according to claim 6, wherein: The N functional blocks also include specific functional blocks; The specific function block includes at least one of an I2C controller function block, an SMI / MDIO controller function block, a UART controller function block, an SPI controller function block and a tooling test register function block.

8. A device, characterized in that include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for configuring the logical address space of the hardware board according to any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for configuring the logical address space of the hardware board according to any one of claims 1 to 7 is implemented.

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