Semiconductor memory device and method of operating a semiconductor memory device

Abstract

The present technology relates to a semiconductor memory device and a method for operating the semiconductor memory device. The semiconductor memory device includes: a memory block including memory cells; a peripheral circuit configured to program the memory cells in a set programming state during a test operation and perform a test erase voltage application operation on the memory cells programmed in the set programming state; and a control logic configured to control the peripheral circuit to count abnormal memory cells whose threshold voltages are less than the set threshold voltage among the memory cells.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2020-0047565 filed in the Korean Intellectual Property Office on April 20, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Art

[0004] Recently, the paradigm of computer environment has changed to ubiquitous computing, which enables computer systems to be used at any time and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras and notebook computers is rapidly increasing. Such portable electronic devices generally use a memory system that uses a semiconductor memory device, i.e., a data storage device. The data storage device is used as a primary storage device or an auxiliary storage device of the portable electronic device.

[0005] Semiconductor data storage devices using memory devices have the following advantages: because there is no mechanical drive, stability and durability are excellent, information access speed is very fast, and power consumption is low. As examples of memory systems having such advantages, data storage devices include universal serial bus (USB) memory devices, memory cards with various interfaces, solid state drives (SSDs), etc.

[0006] Memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

[0007] The writing speed and reading speed of non-volatile memory devices are relatively slow, however, non-volatile memory devices can maintain stored data even when the power is cut off. Therefore, non-volatile memory devices are used to store data that must be maintained regardless of the power supply. Non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR type and NAND type. Summary of the invention

[0008] A semiconductor memory device according to an embodiment of the present disclosure may include: a memory block including memory cells; a peripheral circuit configured to program the memory cells in a set programming state during a test operation and perform a test erase voltage application operation on the memory cells programmed in the set programming state; and a control logic configured to control the peripheral circuit to count abnormal memory cells among the memory cells whose threshold voltage is lower than the set threshold voltage.

[0009] A method for operating a semiconductor memory device according to an embodiment of the present disclosure may include: programming a memory block in a set programming state; applying a test erase voltage to the memory block being programmed in the set programming state for a set number of times; counting memory cells included in the memory block whose threshold voltage is lower than the lowest threshold voltage of the set programming state; and when the number of counted memory cells is greater than the set number, determining the memory block as a bad block.

[0010] According to an embodiment of the present disclosure, a semiconductor memory device may include: a memory block including memory cells in an erased state; a peripheral circuit configured to perform a test programming voltage application operation on the memory cells in the erased state during a test operation; and a control logic configured to control the peripheral circuit to count abnormal memory cells among the memory cells whose threshold voltage is higher than a set threshold voltage.

[0011] A method for operating a semiconductor memory device according to an embodiment of the present disclosure may include: applying a test programming voltage to a memory block in an erased state for a set number of times; counting memory cells included in the memory block whose threshold voltage is higher than the highest threshold voltage in the erased state; and when the number of counted memory cells is greater than the set number, determining the memory block as a bad block.

[0012] A semiconductor memory device according to an embodiment of the present disclosure may include: a memory block including memory cells; a peripheral circuit configured to program the memory cells in a set programming state during a test operation and to perform a test erase voltage application operation on the memory cells programmed in the set programming state; and a control logic configured to control the peripheral circuit to measure the slope of the left tail of the threshold voltage distribution of the memory cells, and when the measured slope of the left tail is lower than the set slope, the control logic determines the memory block as a bad block.

[0013] A method for operating a semiconductor memory device according to an embodiment of the present disclosure may include: programming a memory block including memory cells in a set programming state; applying a test erase voltage to the memory block being programmed in the set programming state for a set number of times; measuring the slope of the left tail of the threshold voltage distribution of the memory cells; and when the slope of the left tail is lower than the set slope, determining the memory block as a bad block.

[0014] A semiconductor memory device according to an embodiment of the present disclosure may include: a memory block including memory cells in an erased state; a peripheral circuit configured to perform a test programming voltage application operation programming on the memory cells in the erased state during a test operation; and a control logic configured to control the peripheral circuit to measure the slope of the right tail of the threshold voltage distribution of the memory cells, and when the measured slope of the right tail is lower than a set slope, the control logic determines the memory block as a bad block.

[0015] A method for operating a semiconductor memory device according to an embodiment of the present disclosure may include: applying a test programming voltage to a memory block in an erased state for a set number of times; measuring the slope of a right tail of a threshold voltage distribution of a memory cell; and determining the memory block as a bad block when the slope of the right tail is lower than a set slope. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram for describing a memory system according to an embodiment of the present disclosure.

[0017] Figure 2 Is used to describe Figure 1 A block diagram of a configuration of a semiconductor memory device.

[0018] Figure 3 Is used to describe Figure 2 A diagram of a memory block.

[0019] Figure 4 is a diagram for describing an embodiment of a memory block configured in three dimensions.

[0020] Figure 5 is a flowchart for describing a method of operating the semiconductor memory device according to the first embodiment of the present disclosure.

[0021] Figure 6 is used to describe Figure 5 FIG. 1 is a waveform diagram of a test erase voltage during a test erase voltage applying operation.

[0022] Figure 7 is a waveform diagram for describing another embodiment of a test erase voltage.

[0023] Figure 8 Is used to describe Figure 5A threshold voltage distribution diagram of a detection operation of an abnormal memory cell.

[0024] Fig. 9 is a flowchart for describing a method of operating a semiconductor memory device according to a second embodiment of the present disclosure.

[0025] Fig.10 is used to describe Fig. 9 1 is a waveform diagram of a test programming voltage during a test programming voltage applying operation.

[0026] Fig.11 is a waveform diagram for describing another embodiment of a test programming voltage.

[0027] Fig.12 Is used to describe Fig. 9 A threshold voltage distribution diagram of a detection operation of an abnormal memory cell.

[0028] Fig.13 is a flowchart for describing a method of operating a semiconductor memory device according to a third embodiment of the present disclosure.

[0029] Fig.14 Is used to describe Fig.13 A threshold voltage distribution graph of a slope detection operation.

[0030] Fig.15 is a flowchart for describing a method of operating a semiconductor memory device according to a fourth embodiment of the present disclosure.

[0031] Fig.16 Is used to describe Fig.15 A threshold voltage distribution graph of a slope detection operation.

[0032] Fig.17 is a diagram for describing another embodiment of a memory system.

[0033] Fig.18 is a diagram for describing another embodiment of a memory system.

[0034] Fig.19 is a diagram for describing another embodiment of a memory system.

[0035] Fig. 20 is a diagram for describing another embodiment of a memory system. DETAILED DESCRIPTION

[0036] Only specific structural or functional descriptions of embodiments according to the concepts disclosed in this specification or this application are illustrated to describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be carried out in various forms, and the description is not limited to the embodiments described in this specification or this application.

[0037] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains may easily carry out the technical spirit of the present disclosure.

[0038] Embodiments of the present disclosure may provide a semiconductor memory device for detecting an abnormally programmed or erased memory cell among memory cells included in the semiconductor memory device, and a method of operating the semiconductor memory device.

[0039] According to the present technology, the reliability of a semiconductor memory device can be improved by detecting memory cells included in the semiconductor memory device whose threshold voltage is changed by a test programming voltage lower than a normal programming voltage or a test erase voltage lower than a normal erase voltage.

[0040] Figure 1 is a block diagram for describing a memory system according to an embodiment of the present disclosure.

[0041] Reference Figure 1 , the memory system 1000 includes a memory device 1100 and a controller 1200. The memory device 1100 includes a plurality of semiconductor memory devices 100. The plurality of semiconductor memory devices 100 may be divided into a plurality of groups GR1 to GRn.

[0042] exist Figure 1 In the embodiment, a plurality of groups GR1 to GRn communicate with the controller 1200 through the first to nth channels CH1 to CHn, respectively. Figure 2 Each semiconductor memory device 100 is described.

[0043] Each of the plurality of groups GR1 to GRn is configured to communicate with the controller 1200 through a common channel. The controller 1200 is configured to control the plurality of semiconductor memory devices 100 of the memory device 1100 through the plurality of channels CH1 to CHn. Each semiconductor memory device 100 may include a plurality of memory blocks, and in an embodiment, each semiconductor memory device 100 may perform a test operation to detect an abnormal memory cell whose threshold voltage is abnormally moved. A memory block whose number of detected abnormal memory cells is equal to or greater than a set number may be registered as a bad block. In addition, during the test operation, the semiconductor memory device 100 may select a representative block to be subjected to a test operation among the plurality of memory blocks, and when the selected representative block is determined to be a bad block as a result of the test operation, the semiconductor memory device 100 may be determined as a defective memory chip.

[0044] In an embodiment, each semiconductor memory device 100 may perform a test operation to detect a slope of a threshold voltage distribution, and determine a memory block having a detected slope value lower than a set slope value as a bad block.

[0045] The controller 1200 is connected between the host 1400 and the memory device 1100. The controller 1200 is configured to access the memory device 1100 in response to a request from the host 1400. For example, the controller 1200 is configured to control the read, write, erase, and background operations of the memory device 1100 in response to a request received from the host 1400. The controller 1200 is configured to provide an interface between the memory device 1100 and the host 1400. The controller 1200 is configured to drive firmware for controlling the memory device 1100.

[0046] The controller 1200 may include a memory block management block 1210. The memory block management block 1210 stores information on each of a plurality of memory blocks included in the semiconductor memory 100. For example, the memory block management block 1210 may store information on a memory block determined to be a bad block among the memory blocks included in the semiconductor memory 100, and may store information on a memory block determined to be a normal block, and may receive bad block information to update the stored information according to a test operation result of the semiconductor memory 100.

[0047] The host 1400 controls the memory system 1000. The host 1400 includes portable electronic devices such as computers, PDAs, PMPs, MP3 players, cameras, video cameras, and mobile phones. The host 1400 can request a write operation, a read operation, an erase operation, etc. of the memory system 1000 through a command.

[0048] The controller 1200 and the memory device 1100 may be integrated into one semiconductor device. In an embodiment, the controller 1200 and the memory device 1100 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into one semiconductor device to form a memory card, such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or MMCmicro), an SD card (SD, mini SD, micro SD or SDHC), and a Universal Flash Memory (UFS).

[0049] The controller 1200 and the memory device 1100 may be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host 1400 connected to the memory system 1000 may be dynamically increased.

[0050] As another example, the memory system 1000 is provided as one of various components of the following electronic devices: such as, a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder and a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, or one of various components configuring a computing system.

[0051] In an embodiment, the memory device 1100 or the memory system 1000 may be installed as various types of packages. For example, the memory device 1100 or the memory system 1000 may be packaged and installed in a method such as package on package (PoP), ball grid array (BGA), chip size package (CSP), plastic lead chip carrier (PLCC), plastic dual in-line package (PDIP), waffle package die, wafer form die, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SQIC), shrink small outline package (SSOP), thin small outline (TSOP), system in package (SIP), multi-chip package (MCP), wafer level manufacturing package (WFP) or wafer level processing stacked package (WSP).

[0052] Figure 2 Is used to describe Figure 1 A block diagram of a configuration of a semiconductor memory device.

[0053] Reference Figure 2, the semiconductor memory device 100 may include a memory cell array 10 storing data. The semiconductor memory device 100 may include a peripheral circuit 200 configured to perform a programming operation for storing data in the memory cell array 10, a read operation for outputting the stored data, and an erase operation for erasing the stored data. In addition, the peripheral circuit 200 may perform a test operation. During the test operation, the peripheral circuit 200 may perform a test programming operation and a test erase voltage application operation on a selected memory block between a plurality of memory blocks MB1 to MBk included in the memory cell array 10 in sequence, and then a threshold voltage distribution may be read to detect an abnormal memory cell. In addition, during the test operation, the peripheral circuit 200 may perform a test programming voltage application operation on a selected memory block in an erased state among the plurality of memory blocks MB1 to MBk, and then a threshold voltage distribution may be read to detect an abnormal memory cell.

[0054] In an embodiment, the peripheral circuit 200 may perform a test operation. During the test operation, the peripheral circuit 200 may sequentially perform a test program operation and a test erase voltage application operation on a selected memory block among the plurality of memory blocks MB1 to MBk included in the memory cell array 10, and then may measure the slope of the threshold voltage distribution. In addition, during the test operation, the peripheral circuit 200 may perform a test program voltage application operation on a selected memory block in an erased state among the plurality of memory blocks MB1 to MBk, and then may measure the slope of the threshold voltage distribution.

[0055] The semiconductor memory device 100 may include a control logic 300. Figure 1 The peripheral circuit 200 is controlled under the control of the controller 1200. The control logic 300 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 300 can be a control logic circuit operating according to an algorithm and / or a processor executing a control logic code.

[0056] The memory cell array 10 may include a plurality of memory blocks MB1 to MBk; 11 (k is a positive integer). At least one of the plurality of memory blocks MB1 to MBk may be a content addressable memory (CAM) block, and the CAM block may store a bad block table. Local lines LL and bit lines BL1 to BLm (m is a positive integer) may be connected to each of the memory blocks MB1 to MBk; 11. For example, the local line LL may include a first selection line, a second selection line, and a plurality of word lines arranged between the first and second selection lines. In addition, the local line LL may include a dummy line arranged between the first selection line and the word line and between the second selection line and the word line. Here, the first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, the local line LL may include a word line, a drain and source selection line, and a source line SL. For example, the local line LL may further include a dummy line. For example, the local line LL may further include a pipeline line. The local lines LL may be connected to the memory blocks MB1 to MBk; 11, respectively, and the bit lines BL1 to BLm may be connected in common to the memory blocks MB1 to MBk; 11. The memory blocks MB1 to MBk; 11 may be implemented in a two-dimensional or three-dimensional structure. For example, the memory cells may be arranged in a direction parallel to the substrate in the memory block 11 of the two-dimensional structure. For example, the memory cells may be stacked in a direction perpendicular to the substrate in the memory block 11 of the three-dimensional structure.

[0057] The peripheral circuit 200 may be configured to perform programming, reading, and erasing operations of the selected memory block 11 under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a fail bit counter 260, and a source line driver 270.

[0058] The voltage generating circuit 210 may generate various operating voltages Vop used in programming, reading, and erasing operations in response to the operating signal OP_CMD. In addition, the voltage generating circuit 210 may selectively discharge the local line LL in response to the operating signal OP_CMD. For example, the voltage generating circuit 210 may generate a programming voltage, a verification voltage, a read voltage, a pass voltage, and a selection transistor operating voltage under the control of the control logic 300.

[0059] The row decoder 220 may deliver the operating voltage Vop to the local line LL connected to the selected memory block 11 in response to the row decoder control signal AD_signals. For example, the row decoder 220 may selectively apply the operating voltage (e.g., program voltage, verification voltage, read voltage, pass voltage, etc.) generated in the voltage generating circuit 210 to a word line among the local lines LL in response to the control signal AD_signals.

[0060] For example, during a program operation, the row decoder 220 applies a program voltage generated in the voltage generating circuit 210 to a selected word line among the local lines LL and applies a pass voltage generated in the voltage generating circuit 210 to the remaining unselected word lines in response to the row decoder control signal AD_signals. In addition, during a read operation, the row decoder 220 applies a read voltage generated in the voltage generating circuit 210 to a selected word line among the local lines LL and applies a pass voltage generated in the voltage generating circuit 210 to the remaining unselected word lines in response to the row decoder control signal AD_signals.

[0061] The page buffer group 230 may include a plurality of page buffers PB1 to PBm; 231 connected to the bit lines BL1 to BLm. The page buffers PB1 to PBm; 231 may operate in response to a page buffer control signal PBSIGNALS. For example, the page buffers PB1 to PBm; 231 may temporarily store data to be programmed during a programming operation, or sense a voltage or current of the bit lines BL1 to BLm during a read operation or a verification operation. In addition, the page buffers PB1 to PBm; 231 may apply an erase voltage to the corresponding bit lines BL1 to BLm during an erase operation, or float the bit lines BL1 to BLm.

[0062] During the test operation, the page buffer group 230 can detect memory cells whose threshold voltage is lower than the solid-state programming state in the detection operation of abnormal memory cells, and can generate a page buffer voltage VPB whose potential level is adjusted based on the number of detected memory cells. In addition, the page buffer group 230 can detect memory cells whose threshold voltage is higher than the solid-state programming state in the detection operation of abnormal memory cells, and can generate a page buffer voltage VPB whose potential level is adjusted based on the number of detected memory cells.

[0063] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 may exchange data with the page buffer 231 through the data line DL, or may exchange data with the input / output circuit 250 through the column line CL.

[0064] The input / output circuit 250 can convert Figure 1The controller 1200 may receive an internal command CMD, a test command Test_CMD, and an address ADD to the control logic 300, or may receive bad block information BB_info from the control logic 300 and transmit the bad block information BB_info to the controller 1200. In addition, the input / output circuit 250 may exchange data DATA with the column decoder 240.

[0065] When detecting abnormal memory cells during the test operation, the fail bit counter 260 may count abnormal memory cells whose threshold voltage is lower than the reference read voltage, and may output the counted number of abnormal memory cells as the fail bit Fail_bit. In addition, when detecting abnormal memory cells, the fail bit counter 260 may count abnormal memory cells whose threshold voltage is higher than the read voltage, and may output the counted number of abnormal memory cells as the fail bit Fail_bit.

[0066] The source line driver 270 may be connected to the memory cells included in the memory cell array 10 through the source lines SL, and may control a voltage to be applied to the source lines SL. The source line driver 270 may receive a source line control signal CTRL_SL from the control logic 300, and may control a source line voltage (e.g., an erase voltage) applied to the source lines SL based on the source line control signal CTRL_SL.

[0067] The control logic 300 may output an operation signal OP_CMD, a row decoder control signal AD_signals, and a page buffer control signal PBSIGNALS in response to an internal command CMD and an address ADD to control the peripheral circuit 200 to perform an overall operation, such as a programming operation, a reading operation, an erasing operation, etc. In addition, the control logic 300 may control the peripheral circuit 200 to perform a test operation on a selected memory block in response to a test command Test_CMD. For example, during the test operation, the control logic 300 may control the peripheral circuit 200 to sequentially perform a test programming operation and a test erasing voltage application operation on a selected memory block among a plurality of memory blocks MB1 to MBk included in the memory cell array 10, and then read a threshold voltage distribution to detect an abnormal memory cell. In addition, during the test operation, the control logic 300 may control the peripheral circuit 200 to perform a test programming voltage application operation on a selected memory block in an erased state among a plurality of memory blocks MB1 to MBk, and then read a threshold voltage distribution to detect an abnormal memory cell. When the number of detected abnormal memory cells exceeds a set number, the control logic 300 may determine the selected memory block as a bad block and generate bad block information BB_info.

[0068] In another embodiment, during the test operation, the control logic 300 may control the peripheral circuit 200 to sequentially perform a test programming operation and a test erase voltage application operation on a selected memory block among the plurality of memory blocks MB1 to MBk included in the memory cell array 10, and then the slope of the threshold voltage distribution may be measured. In addition, during the test operation, the control logic 300 may control the peripheral circuit 200 to perform a test programming voltage application operation on a selected memory block in an erased state among the plurality of memory blocks MB1 to MBk, and then the slope of the threshold voltage distribution may be measured. When the slope value of the detected threshold voltage distribution is lower than the set slope value, the control logic 300 may determine the selected memory block as a bad block and generate bad block information BB_info.

[0069] Figure 3 Is used to describe Figure 2 A diagram of a memory block.

[0070] Reference Figure 3 , the memory block 11 may be connected to a plurality of word lines WL1 to WL16 arranged in parallel with each other between a first selection line and a second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block 11 may include a plurality of strings ST connected between the bit lines BL1 to BLm and the source line SL. The bit lines BL1 to BLm may be connected to the strings ST, respectively, and the source line SL may be connected to the strings ST in common. Since the strings ST may be configured to be identical to each other, the string ST connected to the first bit line BL1 will be specifically described as an example.

[0071] The string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. One string ST may include at least one or more of the source selection transistor SST and the drain selection transistor DST, and may include more memory cells MC1 to MC16 than the number shown in the drawings.

[0072] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be connected to the source select line SSL, the gates of the drain select transistors DST may be connected to the drain select line DSL, and the gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PPG. Therefore, the memory block 11 may include a physical page PPG of a plurality of word lines WL1 to WL16.

[0073] One memory cell can store one bit of data. This is usually called a single-level cell (SLC). In this case, one physical page PPG can store one logical page (LPG) of data. One logical page (LPG) of data can include data bits of multiple cells included in one physical page PPG. In addition, one memory cell can store two or more bits of data. This is usually called a multi-level cell (MLC). In this case, one physical page PPG can store two or more logical pages (LPG) of data.

[0074] Figure 4 is a diagram for describing an embodiment of a memory block configured in three dimensions.

[0075] Reference Figure 4 , the memory cell array 10 may include a plurality of memory blocks MB1 to MBk; 11. The memory block 11 may include a plurality of strings ST11 to ST1m and ST21 to ST2m. Each of the plurality of strings ST11 to ST1m and ST21 to ST2m may extend in a vertical direction (Z direction). In the memory block 11, m strings may be arranged along a row direction (X direction). Figure 4 , two character strings are arranged along the column direction (Y direction), but this is for convenience of description, and three or more character strings may be arranged along the column direction (Y direction).

[0076] Each of the plurality of strings ST11 to ST1m and ST21 to ST2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0077] The source selection transistor SST of each string may be connected between the source line SL and the memory cells MC1 to MCn. The source selection transistors of the strings arranged in the same row may be connected to the same source selection line. The source selection transistors of the strings ST11 to ST1m arranged in the first row may be connected to the first source selection line SSL1. The source selection transistors of the strings ST21 to ST2m arranged in the second row may be connected to the second source selection line SSL2. In an embodiment, the source selection transistors of the strings ST11 to ST1m and ST21 to ST2m may be connected to one source selection line in common.

[0078] First to nth memory cells MC1 to MCn of each string may be connected in series to each other between source select transistors SST and drain select transistors DST. Gates of the first to nth memory cells MC1 to MCn may be connected to first to nth word lines WL1 to WLn, respectively.

[0079] As an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding string may be stably controlled. Therefore, the reliability of the data stored in the memory block 11 may be improved.

[0080] The drain selection transistor DST of each string may be connected between the bit line and the memory cells MC1 to MCn. The drain selection transistors DST of the strings arranged in the row direction may be connected to the drain selection line extending in the row direction. The drain selection transistors DST of the strings ST11 to ST1m of the first row may be connected to the first drain selection line DSL1. The drain selection transistors DST of the strings ST21 to ST2m of the second row may be connected to the second drain selection line DSL2.

[0081] Among the plurality of memory blocks MB1 to MBk, one memory block may share word lines WL1 to WLn with another memory block, and the memory blocks sharing the word lines WL1 to WLn may be defined as shared memory blocks.

[0082] Figure 5 is a flowchart for describing a method of operating the semiconductor memory device according to the first embodiment of the present disclosure.

[0083] The following will refer to Figures 1 to 5 A method of operating a semiconductor memory device according to a first embodiment of the present disclosure is described.

[0084] In step S510, during the test operation, the selected semiconductor memory device 100 included in the memory device 1100 receives a test command Test_CMD from the controller 1200. The control logic 300 of the selected semiconductor memory device 100 may control the peripheral circuit 200 to perform a test operation on a selected memory block (e.g., MB1) among the plurality of memory blocks MB1 to MBk included in the memory cell array 10 in response to the received test command Test_CMD.

[0085] In step S520, the peripheral circuit 200 performs a test programming operation on the selected memory block MB1 under the control of the control logic 300. For example, the memory cells included in the selected memory block MB1 are programmed in a solid-state programming state in the test programming operation. The solid-state programming state may be a programming state corresponding to a specific threshold voltage distribution having a higher potential than the threshold voltage distribution corresponding to the erased state. For example, the solid-state programming state may have a threshold voltage distribution higher than 0V.

[0086] In an embodiment of the present disclosure, during a test programming operation, memory cells included in a selected memory block MB1 are programmed in a solid-state programming state, but are not limited thereto, and random data may be programmed into the memory cells included in the selected memory block MB1.

[0087] In step S530, a test erase voltage is applied to the selected memory block MB1 to test program operation completion. The test erase voltage may be an erase voltage having a potential level lower than an erase voltage used during an erase operation of the semiconductor memory device 100 (ie, a normal erase voltage).

[0088] For example, the source line driver 270 may apply a test erase voltage to the source line SL of the selected memory block MB1 during the test erase voltage application operation. The page buffers PB1 to PBm; 231 may apply a test erase voltage to the corresponding bit lines BL1 to BLm during the test erase operation, or float the bit lines BL1 to BLm. The row decoder 220 may apply a ground voltage to the word line WL of the selected memory block MB1 during the test erase voltage application operation.

[0089] When a test erase voltage is applied to the source line SL or the source line SL and the bit lines BL1 to BLm of the selected memory block MB1, since the test erase voltage is lower than the normal erase voltage, the threshold voltages of normal memory cells among the memory cells included in the selected memory block MB1 do not change, and the threshold voltages of abnormal memory cells with a faster erase speed are reduced.

[0090] The test erase voltage application operation may be repeatedly performed by setting the number of times the test erase voltage application operation is performed. For example, the test erase voltage application operation may be repeatedly performed 100 to 1000 times.

[0091] In step S540, after the test erase voltage application operation is completed, an abnormal memory cell whose threshold voltage is reduced is detected. For example, the peripheral circuit 200 detects a memory cell whose threshold voltage is lower than the lowest threshold voltage of the solid-state programming state among the plurality of memory cells included in the selected memory block MB1. The detection operation of the abnormal memory cell can be performed as a read operation using a read voltage whose potential is equal to or lower than the lowest threshold voltage of the solid-state programming state.

[0092] In step S550, it is determined whether the number of abnormal memory cells detected is greater than the set number. For example, the page buffer group 230 generates and outputs the page buffer voltage VPB according to the number of abnormal memory cells (i.e., memory cells whose threshold voltage is lower than the lowest threshold voltage of the solid-state programming state) detected during the above-mentioned abnormal memory cell detection operation. The fault bit counter 260 counts the number of abnormal memory cells based on the potential of the page buffer voltage VPB, and generates and outputs the fault bit Fail_bit. The control logic 300 determines whether the number of abnormal memory cells is greater than the set number based on the fault bit Fail_bit.

[0093] When it is determined that the number of detected abnormal memory cells is greater than the set number as a result of the determination of the above step S550 (yes), the selected memory block MB1 is determined as a bad block and is registered in the memory block management block 1210. For example, when the number of abnormal memory cells among the memory cells included in the selected memory block MB1 is greater than the set number, the control logic 300 generates and outputs bad block information BB_info, and the memory block management block of the controller 1200 registers the selected memory block MB1 as a bad block based on the bad block information BB_info, and manages the selected memory block MB1.

[0094] When it is determined that the number of detected abnormal memory cells is equal to or less than the set number as a result of the determination of the above step S550 (No), the selected memory block MB1 is determined as a normal block and is registered in the memory block management block 1210 .

[0095] According to the above-described embodiments of the present disclosure, after programming the memory cells included in the selected memory block in a specific programming state, a test erase voltage lower than a normal erase voltage is applied to detect abnormal memory cells with reduced threshold voltages. When the number of abnormal memory cells detected is greater than a set number, the corresponding memory block can be determined as a bad block.

[0096] In the above-mentioned embodiment of the present disclosure, the test programming operation and the abnormal memory cell detection operation are performed on all the memory cells included in the selected memory block. However, the test programming operation and the abnormal memory cell detection operation may be performed on some of the memory cells included in the selected memory block. For example, the test programming operation and the abnormal memory cell detection operation may be selectively performed on the following memory cells: the memory cells included in at least one page among a plurality of pages (included in the selected memory block), or the memory cells included in at least one string among a plurality of strings (included in the selected memory block). Alternatively, the test programming operation and the abnormal memory cell detection operation may be selectively performed on the memory cells selected by, for example but not limited to, the checkerboard method among the plurality of memory cells included in the selected memory block.

[0097] Figure 6 Is used to describe Figure 5 FIG. 1 is a waveform diagram of a test erase voltage during a test erase voltage applying operation.

[0098] Reference Figure 6 ,exist Figure 5 The potential level of the test erase voltage Vera_test applied to the source line SL or the source line SL and the bit line BL in step S530 is lower than the potential level of the normal erase voltage Vera_normal used during an erase operation (ie, a normal erase operation) of the semiconductor memory device.

[0099] Figure 7 is a waveform diagram for describing another embodiment of a test erase voltage.

[0100] Reference Figure 7 ,exist Figure 5 In step S530, during the test erase voltage application operation, the normal erase voltage Vera_normal used during the normal erase operation is applied to the source line SL of the selected memory block or the source line SL and the bit line BL of the selected memory block, and before reaching the flat section of the normal erase voltage Vera_normal, the test erase voltage application operation is stopped. Therefore, during the test erase voltage application operation, the test erase voltage Vera_test of the flat band potential lower than the normal erase voltage Vera_normal can be applied to the source line SL of the selected memory block or the source line SL and the bit line BL of the selected memory block.

[0101] As another example, in Figure 5In step S530, during the test erase voltage application operation, the normal erase voltage Vera_normal used during the normal erase operation is applied to the source line SL of the selected memory block or the source line SL and the bit line BL of the selected memory block, and a voltage higher than the ground voltage may be applied to the word line of the selected memory block. Therefore, the potential level difference between the gate of the memory cell and the channel of the memory cell is reduced, and thus the threshold voltage of the abnormal memory cell among the memory cells included in the selected memory block can be reduced.

[0102] Figure 8 Is used to describe Figure 5 A threshold voltage distribution diagram of a detection operation of an abnormal memory cell.

[0103] Reference Figure 8 ,exist Figure 5 In step S540, an abnormal memory cell A having a lower threshold voltage than the threshold voltage distribution corresponding to the solid-state programming state SP is detected. The detection operation of the abnormal memory cell can be performed as a read operation using a read voltage Vread lower than the lowest threshold voltage of the solid-state programming state SP. That is, a memory cell having a threshold voltage lower than the read voltage Vread among the memory cells included in the selected memory block is detected, and the detected memory cell is determined to be an abnormal memory cell A.

[0104] Fig. 9 is a flowchart for describing a method of operating a semiconductor memory device according to a second embodiment of the present disclosure.

[0105] The following will refer to Figures 1 to 4 and Fig. 9 A method of operating a semiconductor memory device according to a second embodiment of the present disclosure is described.

[0106] In step S610, during the test operation, the selected semiconductor memory device 100 included in the memory device 1100 receives a test command Test_CMD from the controller 1200. The control logic 300 of the selected semiconductor memory device 100 may control the peripheral circuit 200 to perform a test operation on a selected memory block (e.g., MB1) among the plurality of memory blocks MB1 to MBk included in the memory cell array 10 in response to the received test command Test_CMD. The selected memory block (e.g., MB1) may be in an erased state. That is, all memory cells included in the selected memory block (e.g., MB1) may be in an erased state.

[0107] In step S620, the peripheral circuit 200 applies a test programming voltage to the word lines WL1 to WLn of the selected memory block MB1 under the control of the control logic 300. For example, the voltage generating circuit 210 generates and outputs the test programming voltage, and the row decoder 220 applies the test programming voltage to the word lines WL1 to WLn of the selected memory block MB1. The row decoder 220 may apply the test programming voltage to the word lines WL1 to WLn of the selected memory block MB1 in sequence, or simultaneously apply the test programming voltage to the word lines WL1 to WLn of the selected memory block MB1. The test programming voltage may be a programming voltage having a potential level lower than a programming voltage (i.e., a normal programming voltage) used during a programming operation of the semiconductor memory device 100.

[0108] When a test programming voltage is applied to word lines WL1 to WLn of a selected memory block MB1, since the test programming voltage is lower than a normal programming voltage, the threshold voltages of normal memory cells among the memory cells included in the selected memory block MB1 do not change, and the threshold voltages of abnormal memory cells with a fast programming speed increase.

[0109] The above-mentioned test program voltage applying operation may be repeatedly performed a set number of times. For example, the test program voltage applying operation may be repeatedly performed 100 to 1000 times.

[0110] In step S630, after the test programming voltage application operation is completed, an abnormal memory cell whose threshold voltage increases is detected. For example, the peripheral circuit 200 detects a memory cell whose threshold voltage is higher than the highest threshold voltage of the solid-state programming state among the plurality of memory cells included in the selected memory block MB1. The detection operation of the abnormal memory cell can be performed as a read operation using a read voltage having a potential equal to or higher than the highest threshold voltage of the solid-state programming state.

[0111] In step S640, it is determined whether the number of abnormal memory cells detected is greater than the set number. For example, the page buffer group 230 generates and outputs the page buffer voltage VPB according to the number of abnormal memory cells (i.e., memory cells whose threshold voltage is higher than the highest threshold voltage of the solid-state programming state) detected during the above-mentioned abnormal memory cell detection operation. The fault bit counter 260 counts the number of abnormal memory cells based on the potential of the page buffer voltage VPB, and generates and outputs the fault bit Fail_bit. The control logic 300 determines whether the number of abnormal memory cells is greater than the set number based on the fault bit Fail_bit.

[0112] When it is determined that the number of detected abnormal memory cells is greater than the set number as a result of the determination of the above-mentioned step S640 (yes), the selected memory block MB1 is determined as a bad block and is registered in the memory block management block 1210. For example, when the number of abnormal memory cells among the memory cells included in the selected memory block MB1 is greater than the set number, the control logic 300 generates and outputs bad block information BB_info, and the memory block management block of the controller 1200 registers the selected memory block MB1 as a bad block based on the bad block information BB_info and manages the selected memory block MB1.

[0113] When it is determined that the number of detected memory cells is equal to or less than the set number as a result of the determination of the above-described step S640 (No), the selected memory block MB1 is determined as a normal block and is registered in the memory block management block 1210 .

[0114] According to the above-described embodiment of the present disclosure, a test programming voltage lower than a normal programming voltage is applied to memory cells included in a selected memory block in an erased state to detect abnormal memory cells with increased threshold voltages. When the number of abnormal memory cells detected is greater than a set number, the corresponding memory block can be determined as a bad block.

[0115] In the above-mentioned embodiment of the present disclosure, the test programming operation and the abnormal memory cell detection operation are performed on all the memory cells included in the selected memory block. However, the test programming voltage application operation and the abnormal memory cell detection operation can be performed on some memory cells included in the selected memory block. For example, the test programming voltage application operation and the abnormal memory cell detection operation can be selectively performed on the following memory cells: memory cells included in at least one page among multiple pages (included in the selected memory block), or memory cells included in at least one string among multiple strings (included in the selected memory block). Alternatively, the test programming voltage application operation and the abnormal memory cell detection operation can be selectively performed on the memory cells selected by, for example but not limited to, the chessboard method among the multiple memory cells included in the selected memory block.

[0116] Fig.10 Is used to describe Fig. 9 1 is a waveform diagram of a test programming voltage during a test programming voltage applying operation.

[0117] Reference Fig.10 ,exist Fig. 9The potential level of the test programming voltage Vpgm_test applied to the word line WL in step S620 is lower than the potential level of the normal programming voltage Vpgm_normal used during a programming operation (ie, a normal programming operation) of the semiconductor memory device.

[0118] Fig.11 is a waveform diagram for describing another embodiment of a test programming voltage.

[0119] Reference Fig.11 ,exist Fig. 9 In step S620, during the test erase voltage application operation, the normal programming voltage Vpgm_normal used during the normal programming operation is applied to the word line WL of the selected memory block, and the test programming voltage application operation is stopped before the normal programming voltage Vpgm_normal reaches the flat section. Therefore, during the test programming voltage application operation, a test programming voltage Vpgm_test having a flat band potential lower than the normal programming voltage Vpgm_normal may be applied to the word line WL of the selected memory block.

[0120] As another example, in Fig. 9 In step S620, during the test programming voltage application operation, the channel of the selected memory block may be precharged to a state higher than the channel potential during the normal programming operation, and the normal programming voltage Vpgm_normal may be applied to the word line of the selected memory block. Therefore, the potential difference between the gate of the memory cell and the channel of the memory cell is reduced, so that the threshold voltage of the abnormal memory cell among the memory cells included in the selected memory block can be increased.

[0121] Fig.12 Is used to describe Fig. 9 A threshold voltage distribution diagram of a detection operation of an abnormal memory cell.

[0122] Reference Fig.12 ,exist Fig. 9 In step S630, an abnormal memory cell B having a higher threshold voltage than the threshold voltage distribution corresponding to the erase state Erase is detected. The detection operation of the abnormal memory cell can be performed as a read operation using a read voltage Vread higher than the highest threshold voltage of the erase state Erase. That is, a memory cell having a threshold voltage higher than the read voltage Vread among the memory cells included in the selected memory block is detected, and the detected memory cell is determined to be an abnormal memory cell B.

[0123] The test operation according to the above-mentioned first embodiment and the test operation according to the second embodiment can be performed in sequence. For example, during the test operation, the semiconductor memory device can perform the test operation according to the first embodiment and then perform the test operation according to the second embodiment, or can perform the test operation according to the second embodiment and then perform the test operation according to the first embodiment.

[0124] Fig.13 is a flowchart for describing a method of operating a semiconductor memory device according to a third embodiment of the present disclosure.

[0125] Fig.14 Is used to describe Fig.13 A threshold voltage distribution graph of a slope detection operation.

[0126] The following will refer to Figures 1 to 4 , Fig.13 and Fig.14 A method of operating a semiconductor memory device according to a third embodiment of the present disclosure is described.

[0127] In step S710, during the test operation, the selected semiconductor memory device 100 included in the memory device 1100 receives a test command Test_CMD from the controller 1200. The control logic 300 of the selected semiconductor memory device 100 may control the peripheral circuit 200 to perform a test operation on a selected memory block (e.g., MB1) among the plurality of memory blocks MB1 to MBk included in the memory cell array 10 in response to the received test command Test_CMD.

[0128] In step S720, the peripheral circuit 200 performs a test programming operation on the selected memory block MB1 under the control of the control logic 300. For example, in the test programming operation, the memory cells included in the selected memory block MB1 are programmed in a solid-state programming state. The solid-state programming state may be a programming state corresponding to a specific threshold voltage distribution having a higher potential than the threshold voltage distribution corresponding to the erased state. For example, the solid-state programming state may have a threshold voltage distribution higher than 0V.

[0129] In an embodiment of the present disclosure, during a test program operation, memory cells included in a selected memory block MB1 are programmed in a solid-state program state, but is not limited thereto, and random data may be programmed into the memory cells included in the selected memory block MB1.

[0130] In step S730, a test erase voltage is applied to the selected memory block MB1 where the test program operation is completed. The test erase voltage may be an erase voltage having a potential level lower than an erase voltage used during an erase operation of the semiconductor memory device 100 (ie, a normal erase voltage).

[0131] For example, during the test erase voltage application operation, the source line driver 270 may apply the test erase voltage to the source line SL of the selected memory block MB1. The page buffers PB1 to PBm; 231 may apply the test erase voltage to the corresponding bit lines BL1 to BLm during the test erase operation, or float the bit lines BL1 to BLm. The row decoder 220 may apply the ground voltage to the word line WL of the selected memory block MB1 during the test erase voltage application operation.

[0132] When a test erase voltage is applied to the source line SL of a selected memory block MB1 or the source line SL and the bit lines BL1 to BLm of a selected memory block MB1, since the test erase voltage is lower than the normal erase voltage, the threshold voltages of normal memory cells among the memory cells included in the selected memory block MB1 do not change, and the threshold voltages of abnormal memory cells with a faster erase speed are reduced.

[0133] The above-mentioned test erase voltage application operation may be repeatedly performed a set number of times. For example, the test erase voltage application operation may be repeatedly performed 100 to 1000 times.

[0134] The test erase voltage application operation can be performed by applying a test erase voltage lower than a normal erase voltage to the above Figure 6 and 7 The source line or source line and bit line shown, or is performed by applying a normal erase voltage to the source line or source line and bit line, and applying a voltage higher than a ground voltage to the word line.

[0135] In step S740, after the test erase voltage application operation is completed, the slope of the threshold voltage distribution of the memory cells of the selected memory block MB1 is detected. For example, the peripheral circuit 200 performs a read operation on the selected memory block MB1 using the first read voltage Vread1 to detect a first memory cell having a threshold voltage lower than the first read voltage, and the fail bit counter 260 counts the number of the detected first memory cells and transmits the number of the detected first memory cells to the control logic 300. In addition, the peripheral circuit 200 performs a read operation on the selected memory block MB1 using the second read voltage Vread2 to detect a second memory cell having a threshold voltage lower than the second read voltage, and the fail bit counter 260 counts the number of the detected second memory cells and transmits the number of the detected second memory cells to the control logic 300. The control logic 300 detects the slope of the threshold voltage distribution of the selected memory block MB1 based on the number of the first memory cells and the number of the second memory cells, that is, the slope (CD) of the left tail of the threshold voltage distribution of the selected memory block MB1.

[0136] The first read voltage Vread1 has a potential that is the same as or lower than the lowest threshold voltage of the solid-state program state, and the second read voltage Vread2 is lower than the first read voltage Vread1 .

[0137] In an embodiment of the present disclosure, the slope of the left tail of the threshold voltage distribution of the selected memory block MB1 is detected by performing a read operation using the first read voltage Vread1 and the second read voltage Vread2. However, the slope of the left tail of the threshold voltage distribution of the selected memory block MB1 can be more accurately detected by performing a read operation using three or more read voltages.

[0138] In step S750, by comparing the slope value of the detected threshold voltage distribution with the set slope value, it is determined whether the slope value of the detected threshold voltage distribution is less than the set slope value. For example, the set slope value can be the slope value of the middle threshold voltage and the slope value of the lowest threshold voltage of the threshold voltage distribution of the solid state programming state SP.

[0139] When it is determined as a result of the determination of the above-mentioned step S750 (yes), that the slope value of the detected threshold voltage distribution is less than the set slope value, the selected memory block MB1 is determined as a bad block and is registered in the memory block management block 1210. For example, when the number of abnormal memory cells among the memory cells included in the selected memory block MB1 is greater than the set number, the control logic 300 generates and outputs bad block information BB_info, and the memory block management block of the controller 1200 registers the selected memory block MB1 as a bad block based on the bad block information BB_info and manages the selected memory block MB1.

[0140] When it is determined as a result of the determination of the above step S750 (No) that the slope value of the detected threshold voltage distribution is equal to or greater than the set slope value, the selected memory block MB1 is determined as a normal block and registered in the memory block management block 1210 .

[0141] According to the above-mentioned embodiments of the present disclosure, after programming the memory cells included in the selected memory block in a specific programming state and applying a test erase voltage lower than the normal erase voltage, the slope of the left tail of the threshold voltage distribution of the memory cells is detected, and when the detected slope value is lower than the set slope value, the corresponding memory block can be determined as a bad block.

[0142] In the above-mentioned embodiment of the present disclosure, the test programming operation and the slope detection operation of the threshold voltage distribution are performed on all the memory cells included in the selected memory block. However, the test programming operation and the slope detection operation of the threshold voltage distribution may be performed on some of the memory cells included in the selected memory block. For example, the test programming operation and the slope detection operation of the threshold voltage distribution may be selectively performed on the following memory cells: memory cells included in at least one page among a plurality of pages (included in the selected memory block), or memory cells included in at least one string among a plurality of strings (included in the selected memory block). Alternatively, the test programming operation and the slope detection operation of the threshold voltage distribution may be selectively performed on the memory cells selected by, for example, but not limited to, the checkerboard method among the plurality of memory cells included in the selected memory block.

[0143] Fig.15 is a flowchart for describing a method of operating a semiconductor memory device according to a fourth embodiment of the present disclosure.

[0144] Fig.16 Is used to describe Fig.15 A threshold voltage distribution graph of a slope detection operation.

[0145] The following will refer to Figures 1 to 4 , Fig.15 and Fig.16 A method of operating the semiconductor memory device according to the fourth embodiment of the present disclosure is described.

[0146] In step S810, during the test operation, the selected semiconductor memory device 100 included in the memory device 1100 receives a test command Test_CMD from the controller 1200. The control logic 300 of the selected semiconductor memory device 100 may control the peripheral circuit 200 to perform a test operation on a selected memory block (e.g., MB1) among a plurality of memory blocks MB1 to MBk included in the memory cell array 10 in response to the received test command Test_CMD. The selected memory block (e.g., MB1) may be in an erased state. That is, all memory cells included in the selected memory block (e.g., MB1) may be in an erased state.

[0147] In step S820, the peripheral circuit 200 applies a test programming voltage to the word lines WL1 to WLn of the selected memory block MB1 under the control of the control logic 300. For example, the voltage generating circuit 210 generates and outputs the test programming voltage, and the row decoder 220 applies the test programming voltage to the word lines WL1 to WLn of the selected memory block MB1. The row decoder 220 may apply the test programming voltage to the word lines WL1 to WLn of the selected memory block MB1 in sequence, or simultaneously apply the test programming voltage to the word lines WL1 to WLn of the selected memory block MB1. The test programming voltage may be a programming voltage having a potential level lower than a programming voltage (i.e., a normal programming voltage) used during a programming operation of the semiconductor memory device 100.

[0148] When a test programming voltage is applied to word lines WL1 to WLn of a selected memory block MB1, since the test programming voltage is lower than a normal programming voltage, the threshold voltages of normal memory cells among the memory cells included in the selected memory block MB1 do not change, and the threshold voltages of abnormal memory cells with a faster programming speed increase.

[0149] The above-mentioned test program voltage applying operation may be repeatedly performed a set number of times. For example, the test program voltage applying operation may be repeatedly performed 100 to 1000 times.

[0150] This can be done by applying a test programming voltage lower than the normal programming voltage to the Fig.10 and Fig.11 The word lines shown are used to perform the above-mentioned test programming voltage application operation.

[0151] In step S830, after the test programming voltage application operation is completed, the slope of the threshold voltage distribution of the memory cells of the selected memory block MB1 is detected. For example, the peripheral circuit 200 performs a read operation on the selected memory block MB1 using the first read voltage Vread1 to detect a first memory cell having a threshold voltage higher than the first read voltage, and the fail bit counter 260 counts the number of the detected first memory cells and transmits the number of the detected first memory cells to the control logic 300. In addition, the peripheral circuit 200 performs a read operation on the selected memory block MB1 using the second read voltage Vread2 to detect a second memory cell having a threshold voltage higher than the second read voltage, and the fail bit counter 260 counts the number of the detected second memory cells and transmits the number of the detected second memory cells to the control logic 300. The control logic 300 detects the slope of the threshold voltage distribution of the selected memory block MB1 based on the number of the first memory cells and the number of the second memory cells, that is, the slope (EF) of the right tail of the threshold voltage distribution of the selected memory block MB1.

[0152] The first read voltage Vread1 has a potential that is the same as or lower than a highest threshold voltage of a solid-state program state, and the second read voltage Vread2 is higher than the first read voltage Vread1 .

[0153] In the embodiment of the present disclosure, the slope of the right tail of the threshold voltage distribution of the selected memory block MB1 is detected by performing a read operation using the first read voltage Vread1 and the second read voltage Vread2. However, the slope of the right tail of the threshold voltage distribution of the selected memory block MB1 can be more accurately detected by performing a read operation using three or more read voltages.

[0154] In step S840, by comparing the slope value of the detected threshold voltage distribution with the set slope value, it is determined whether the slope value of the detected threshold voltage distribution is less than the set slope value. For example, the set slope value can be the slope value of the middle threshold voltage and the slope value of the highest threshold voltage of the threshold voltage distribution of the erase state Erase.

[0155] When it is determined that the slope value of the detected threshold voltage distribution is less than the set slope value as a result of the determination of the above-mentioned step S840 (yes), the selected memory block MB1 is determined as a bad block and is registered in the memory block management block 1210. For example, when the number of abnormal memory cells among the memory cells included in the selected memory block MB1 is greater than the set number, the control logic 300 generates and outputs bad block information BB_info, and the memory block management block of the controller 1200 registers the selected memory block MB1 as a bad block based on the bad block information BB_info, and manages the selected memory block MB1.

[0156] When it is determined as a result of the determination of the above step S840 (No) that the slope value of the detected threshold voltage distribution is equal to or greater than the set slope value, the selected memory block MB1 is determined as a normal block and is registered in the memory block management block 1210 .

[0157] According to the above-mentioned embodiments of the present disclosure, after a test programming voltage lower than a normal programming voltage is applied to memory cells in an erased state included in a selected memory block, the slope of the right tail of the threshold voltage distribution is detected, and when the detected slope value is lower than the set slope value, the corresponding memory block can be determined as a bad block.

[0158] In the above-mentioned embodiment of the present disclosure, the test programming operation and the slope detection operation of the threshold voltage distribution are performed on all the memory cells included in the selected memory block. However, the test programming voltage application operation and the slope detection operation of the threshold voltage distribution can be performed on some memory cells included in the selected memory block. For example, the test programming voltage application operation and the slope detection operation of the threshold voltage distribution can be selectively performed on the following memory cells: memory cells included in at least one page among multiple pages (included in the selected memory block), or memory cells included in at least one string among multiple strings (included in the selected memory block). Alternatively, the test programming voltage application operation and the slope detection operation of the threshold voltage distribution can be selectively performed on the memory cells selected by the checkerboard method among the multiple memory cells included in the selected memory block.

[0159] Fig.17 is a diagram for describing another embodiment of a memory system.

[0160] Reference Fig.17, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a controller 1200 capable of controlling the operation of the memory device 1100. The controller 1200 may control the data access operation of the memory device 1100, such as a program operation, an erase operation, or a read operation, under the control of the processor 3100.

[0161] Data programmed in the memory device 1100 may be output through the display 3200 under the control of the controller 1200 .

[0162] The radio transceiver 3300 can transmit and receive radio signals through the antenna ANT. For example, the radio transceiver 3300 can convert the radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300, and transmit the processed signal to the controller 1200 or the display 3200. The controller 1200 can program the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 can convert the signal output from the processor 3100 into a radio signal, and output the converted radio signal to an external device through the antenna ANT. The input device 3400 can be a device capable of inputting a control signal to control the operation of the processor 3100 or the data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device, such as a touch pad or a computer mouse, a keyboard or a keypad. The processor 3100 may control the operation of the display 3200 so that data output from the controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output through the display 3200 .

[0163] According to an embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 , and may also be implemented as a chip separate from the processor 3100 .

[0164] Fig.18 is a diagram for describing another example of a memory system.

[0165] Reference Fig.18 , the memory system 40000 may be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0166] The memory system 40000 may include a memory device 1100 and a controller 1200 capable of controlling a data processing operation of the memory device 1100 .

[0167] The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0168] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the controller 1200. According to an embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or may be implemented as a chip separate from the processor 4100.

[0169] Fig.19 is a diagram for describing another embodiment of a memory system.

[0170] Reference Fig.19 , the memory system 50000 may be implemented as an image processing device, for example, a digital camera, a portable phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

[0171] The memory system 50000 includes a memory device 1100 and a controller 1200 capable of controlling a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 1100 .

[0172] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be transmitted to the processor 5100 or the controller 1200. The converted digital signal may be output through the display 5300 under the control of the processor 5100, or may be stored in the memory device 1100 through the controller 1200. In addition, the data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the controller 1200.

[0173] According to an embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100 , or may be implemented as a chip separate from the processor 5100 .

[0174] Fig. 20 is a diagram for describing another embodiment of a memory system.

[0175] Reference Fig. 20, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a controller 1200 , and a card interface 7100 .

[0176] The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto. Figure 2 An example implementation of controller 1200 is shown.

[0177] The card interface 7100 may connect the host 60000 and the controller 1200 to exchange data according to the protocol interface of the host 60000. According to an embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0178] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box), the interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor 6100.

[0179] Although the detailed description of the present disclosure describes some embodiments, various changes and modifications can be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above embodiments, but should be determined by the claims of the present disclosure and the equivalents of the following claims.

Claims

1. A semiconductor memory device, comprising: a memory block including a memory cell; a peripheral circuit configured to program the memory cell to a set programming state during a test operation and to perform a test erase voltage application operation on the memory cell programmed to the set programming state; as well as a control logic configured to control the peripheral circuit to count abnormal memory cells whose threshold voltages are lower than a set threshold voltage among the memory cells, The test erase voltage is a voltage lower than a normal erase voltage used during a normal erase operation.

2. The semiconductor memory device according to claim 1, wherein during the test erase voltage applying operation, the peripheral circuit applies a test erase voltage to a source line of the memory block, or applies the test erase voltage to the source line and a bit line of the memory block.

3. The semiconductor memory device according to claim 1, wherein during the test erase voltage application operation, the peripheral circuit applies a test erase voltage to a source line or the source line and a bit line, and stops increasing the test erase voltage before the test erase voltage is equal to a normal erase voltage.

4. The semiconductor memory device according to claim 1, wherein during the test erase voltage application operation, the peripheral circuit applies an erase voltage to a source line of the memory block and applies a voltage greater than a ground voltage to a word line of the memory block. 5 . The semiconductor memory device according to claim 1 , wherein the peripheral circuit repeatedly performs the test erase voltage applying operation a set number of times. 6 . The semiconductor memory device according to claim 1 , wherein the set threshold voltage is equal to or lower than a lowest threshold voltage of the set programming state. 7 . The semiconductor memory device according to claim 1 , wherein when the counted number of the abnormal memory cells is greater than a set number, the control logic determines the memory block as a bad block.

8. A method of operating a semiconductor memory device, the method comprising: programming the memory block in a set programming state; applying a test erase voltage to the memory block programmed in the set programming state a set number of times; counting memory cells whose threshold voltage is lower than the lowest threshold voltage of the set programming state among the memory cells included in the memory block; as well as When the number of memory cells counted is greater than a set number, the memory block is determined to be a bad block, The test erase voltage is a voltage that is smaller than a normal erase voltage used during a normal erase operation.

9. The method of claim 8, wherein applying the test erase voltage comprises: The test erase voltage is applied to a source line of the memory block, or the test erase voltage is applied to the source line and a bit line of the memory block.

10. The method of claim 8, wherein applying the test erase voltage comprises: The test erase voltage is applied to a source line of the memory block or the source line and a bit line of the memory block, and the increase of the test erase voltage is stopped before the test erase voltage is equal to a normal erase voltage.

11. The method of claim 8, wherein applying the test erase voltage comprises: A voltage greater than a ground voltage is applied to a word line of the memory block.

12. A semiconductor memory device comprising: a memory block including memory cells in an erased state; a peripheral circuit configured to perform a test programming voltage application operation on the memory cell in the erased state during a test operation; as well as a control logic configured to control the peripheral circuit to count abnormal memory cells among the memory cells whose threshold voltage is greater than a set threshold voltage, Wherein the test programming voltage is a voltage lower than a normal programming voltage used during a normal programming operation. 13 . The semiconductor memory device according to claim 12 , wherein the peripheral circuit applies a test program voltage to a plurality of word lines of the memory block sequentially or simultaneously during the test program voltage applying operation.

14. The semiconductor memory device according to claim 12, wherein during the test programming voltage applying operation, the peripheral circuit applies a test programming voltage to a word line of the memory block and stops increasing the test programming voltage before the test programming voltage is equal to a normal programming voltage. 15 . The semiconductor memory device according to claim 12 , wherein the peripheral circuit repeatedly performs the test program voltage applying operation a set number of times.

16. The semiconductor memory device according to claim 12, wherein the set threshold voltage is equal to or greater than a highest threshold voltage of the erase state. 17 . The semiconductor memory device according to claim 12 , wherein when the counted number of abnormal memory cells is greater than a set number, the control logic determines the memory block as a bad block.

18. A method of operating a semiconductor memory device, the method comprising: applying a test programming voltage to the memory block in an erased state for a set number of times; counting memory cells whose threshold voltage is greater than a highest threshold voltage of the erased state among the memory cells included in the memory block; as well as When the number of memory cells counted is greater than a set number, the memory block is determined to be a bad block, Wherein the test programming voltage is a voltage lower than a normal programming voltage used during a normal programming operation.

19. The method of claim 18, wherein applying the test programming voltage comprises: The test program voltage is applied to a plurality of word lines of the memory block.

20. The method of claim 19, wherein applying the test programming voltage comprises: The test program voltage is applied to the plurality of word lines of the memory block sequentially or simultaneously.

21. The method of claim 19, wherein applying the test programming voltage comprises: The test program voltage is applied to the plurality of word lines of the memory block, and the increase of the test program voltage is stopped before the test program voltage is equal to a normal program voltage.

22. A semiconductor memory device comprising: a memory block including a memory cell; a peripheral circuit configured to program the memory cells in a set programming state during a test operation and to perform a test erase voltage applying operation on the memory cells programmed in the set programming state; as well as control logic configured to control the peripheral circuit to measure the slope of the left tail of the threshold voltage distribution of the memory cell, When the measured slope of the left tail is less than a set slope, the control logic determines the memory block as a bad block, and The test erase voltage is a voltage lower than a normal erase voltage used during a normal erase operation.

23. The semiconductor memory device according to claim 22, wherein during the test erase voltage applying operation, the peripheral circuit applies a test erase voltage to a source line of the memory block, or applies the test erase voltage to the source line and a bit line of the memory block.

24. A semiconductor memory device according to claim 22, wherein during the test erase voltage application operation, the peripheral circuit applies a test erase voltage to a source line or the source line and a bit line, and stops increasing the test erase voltage before the test erase voltage is equal to a normal erase voltage.

25. The semiconductor memory device according to claim 22, wherein during the test erase voltage applying operation, the peripheral circuit applies an erase voltage to a source line of the memory block and applies a voltage greater than a ground voltage to a word line of the memory block.

26. The semiconductor memory device according to claim 22, wherein the peripheral circuit repeatedly performs the test erase voltage applying operation a set number of times.

27. A method of operating a semiconductor memory device, the method comprising: programming a memory block including memory cells in a set programming state; applying a test erase voltage to the memory block programmed in the set programming state a set number of times; measuring a slope of a left tail of a threshold voltage distribution of the memory cell; as well as When the slope of the left tail is less than a set slope, the memory block is determined to be a bad block, The test erase voltage is a voltage that is smaller than a normal erase voltage used during a normal erase operation.

28. The method of claim 27, wherein applying the test erase voltage comprises: The test erase voltage is applied to a source line of the memory block, or the test erase voltage is applied to the source line and a bit line of the memory block.

29. The method of claim 27, wherein applying the test erase voltage comprises: The test erase voltage is applied to a source line of the memory block, or the source line and a bit line of the memory block, and the increase of the test erase voltage is stopped before the test erase voltage is equal to a normal erase voltage.

30. The method of claim 27, wherein applying the test erase voltage comprises: A voltage greater than a ground voltage is applied to a word line of the memory block.

31. A semiconductor memory device comprising: a memory block including memory cells in an erased state; a peripheral circuit configured to perform a test programming voltage application operation on the memory cell in the erased state during a test operation; as well as a control logic configured to control the peripheral circuit to measure a slope of a right tail of a threshold voltage distribution of the memory cell, When the measured slope of the right tail is less than a set slope, the control logic determines the memory block as a bad block, and Wherein the test programming voltage is a voltage lower than a normal programming voltage used during a normal programming operation.

32. The semiconductor memory device according to claim 31, wherein the peripheral circuit applies a test program voltage to a plurality of word lines of the memory block sequentially or simultaneously during the test program voltage applying operation.

33. A semiconductor memory device according to claim 31, wherein during the test programming voltage application operation, the peripheral circuit applies a test programming voltage to a word line of the memory block and stops increasing the test programming voltage before the test programming voltage is equal to a normal programming voltage.

34. The semiconductor memory device according to claim 31, wherein the peripheral circuit repeatedly performs the test program voltage applying operation a set number of times.

35. A method of operating a semiconductor memory device, the method comprising: applying a test programming voltage to the memory block a set number of times; measuring the slope of the right tail of the threshold voltage distribution of the memory cell; as well as When the slope of the right tail is less than a set slope, the memory block is determined to be a bad block, Wherein the test programming voltage is a voltage lower than a normal programming voltage used during a normal programming operation.

36. The method of claim 35, wherein applying the test programming voltage comprises: The test program voltage is applied to a plurality of word lines of the memory block.

37. The method of claim 35, wherein applying the test programming voltage comprises: The test program voltage is applied to a plurality of word lines of the memory block sequentially or simultaneously.

38. The method of claim 37, wherein applying the test programming voltage comprises: The test program voltage is applied to the plurality of word lines of the memory block, and the increase of the test program voltage is stopped before the test program voltage is equal to a normal program voltage.

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