Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate having a gate structure thereon, and source and drain regions in the substrate on both sides of the gate structure; forming an interlayer dielectric layer covering the gate structure, the source region, and the drain region on the substrate; forming a first contact hole exposing the source region and the drain region in the interlayer dielectric layer; forming a metal silicide stack at the bottom of the first contact hole, the metal silicide stack including at least one stacking unit, and the stacking unit including a silicon layer and a metal layer sequentially formed at the bottom of the first contact hole; annealing the metal silicide stack to obtain a metal silicide layer. The method for forming a semiconductor structure provided by the embodiments of the present invention not only avoids the problems of stress reduction and channel resistance increase caused by ion implantation in the source region and the drain region, but also greatly reduces the thermal accumulation brought about during the formation of the metal silicide, and a metal silicide layer with uniform composition and good quality can be obtained, which is beneficial to reducing the contact resistance and RC delay and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly relates to a method for forming a semiconductor structure. Background Art

[0002] As the integration degree of semiconductor devices continues to increase, the critical dimensions related to semiconductor devices continue to decrease, and correspondingly, many problems have emerged. For example, the surface resistance and contact resistance of the source and drain regions of the device increase accordingly, resulting in a decrease in the response speed of the device and signal delay. Therefore, a low-resistivity interconnect structure has become a key element in the manufacture of high-integration semiconductor devices.

[0003] In order to reduce the contact resistance of the source and drain doping regions of the device, a metal contact layer is formed on the source and drain doping regions, and the material of the metal contact layer is metal silicide. The metal silicide has a low resistivity and can significantly reduce the contact resistance of the source and drain regions. Metal silicides and their formation processes have been widely used to reduce the surface resistance and contact resistance of the source and drain regions of devices, thereby reducing the resistance-capacitance delay.

[0004] However, the electrical performance of the semiconductor structure formed by the prior art still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can form a metal silicide layer with uniform composition, is beneficial to reducing the contact resistance, and reducing the RC delay.

[0006] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a gate structure is formed, and source and drain regions are formed in the substrate on both sides of the gate structure; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the gate structure, the source region, and the drain region; forming a first contact hole in the interlayer dielectric layer, the first contact hole exposing the source region and the drain region; forming a metal silicide stack at the bottom of the first contact hole, the metal silicide stack including at least one stacking unit, and the stacking unit including a silicon layer and a metal layer formed in sequence at the bottom of the first contact hole; annealing the metal silicide stack to obtain a metal silicide layer.

[0007] Optionally, the metal silicide stack further includes a silicon layer formed on the surface of the stacking unit.

[0008] Optionally, the ratio of the thickness of the silicon layer to the thickness of the metal layer is 0.1 to 10.

[0009] Optionally, the total thickness of the metal silicide stack is 0.5 nm to 30 nm.

[0010] Optionally, when the gate structure is a metal gate structure, after forming the metal silicide stack at the bottom of the first contact hole, the method further includes: forming a second contact hole in the interlayer dielectric layer, where the second contact hole exposes the surface of the gate structure.

[0011] Optionally, when the gate structure is a polysilicon gate structure, before forming the metal silicide stack at the bottom of the first contact hole, the method further includes: forming a second contact hole in the interlayer dielectric layer, where the second contact hole exposes the surface of the gate structure.

[0012] Optionally, after forming the second contact hole, the method further includes: forming a metal silicide stack at the bottom of the first contact hole and at the bottom of the second contact hole.

[0013] Optionally, after forming the second contact hole, the method further includes: forming a barrier layer on the sidewall and bottom of the first contact hole and on the sidewall and bottom of the second contact hole.

[0014] After forming a metal silicide stack at the bottom of the first contact hole and at the bottom of the second contact hole, the method further includes: forming a barrier layer on the sidewall and bottom of the first contact hole and on the sidewall and bottom of the second contact hole.

[0015] Optionally, the step of forming the metal silicide stack at the bottom of the first contact hole includes: forming a metal silicide stacked film on the bottom and sidewall of the first contact hole; filling the first contact hole with a sacrificial layer; back-etching the sacrificial layer to expose the metal silicide stacked film on the sidewall of the first contact hole; etching and removing the metal silicide stacked film on the sidewall of the first contact hole to form a metal silicide stack at the bottom of the first contact hole.

[0016] Optionally, the material of the sacrificial layer includes a bottom anti-reflection material or a spin-coated carbon-containing compound.

[0017] Optionally, when forming a metal silicide stack at the bottom of the first contact hole, the method further includes: forming a metal silicide stack on the sidewall of the first contact hole.

[0018] Optionally, when forming a metal silicide stack at the bottom of the first contact hole and at the bottom of the second contact hole, the method further includes: forming a metal silicide stack on the sidewall of the first contact hole and on the sidewall of the second contact hole.

[0019] Optionally, the annealing treatment method includes a uniform temperature annealing process, a spike annealing process, a flash annealing process, or a laser annealing.

[0020] Optionally, the process parameters of the annealing treatment include: the annealing temperature is 400°C to 1000°C, the annealing time is 0.4 microseconds to 60 seconds, the annealing atmosphere includes one or more of nitrogen, hydrogen, ammonia, oxygen or argon, and the annealing pressure is 0.001 Torr to 780 Torr.

[0021] Optionally, the material of the metal layer includes titanium or nickel or cobalt.

[0022] Optionally, the material of the barrier layer includes titanium nitride or tantalum nitride.

[0023] Optionally, after forming the barrier layer, it further includes: filling a conductive layer in the first contact hole and the second contact hole.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] A metal silicide stack is formed at the bottom of the first contact hole. The metal silicide stack includes at least one stacking unit, and the stacking unit includes a silicon layer and a metal layer formed in sequence at the bottom of the first contact hole. When annealing to form a metal silicide layer, on the one hand, since there is a layer of silicon on the surface of the bottom of the first contact hole, it can avoid the problems of stress reduction and channel resistance increase caused by silicon consumption in the source region and the drain region, and greatly reduce the heat accumulation during the formation of the metal silicide; on the other hand, by depositing multiple layers of silicon and metal layers, the stacked silicon and metal layers can react completely during annealing, and the formed metal silicide layer has uniform composition and good quality, without forming holes, which is beneficial to reducing the contact resistance and RC delay. Description of the Drawings

[0026] Figures 1 to 9 is a schematic structural diagram corresponding to each step of the method for forming a semiconductor structure in the first embodiment of the present invention;

[0027] Figures 10 to 16 is a schematic structural diagram corresponding to each step of the method for forming a semiconductor structure in the second embodiment of the present invention. Detailed Embodiments

[0028] As can be seen from the background technology, metal silicides and their formation processes have been widely used to reduce the surface resistance and contact resistance of the source and drain regions of devices, thereby reducing the resistance-capacitance delay time.

[0029] The existing method for forming metal silicides is to form a metal layer in a contact hole by deposition. Since it is difficult for the metal to be deposited at the bottom of the contact hole with a high aspect ratio, it is not easy to increase the thickness of the metal silicide. In order to increase the thickness of the metal silicide, before depositing the metal layer, a pre-amorphization treatment is usually used to form an amorphous layer at the bottom of the contact hole, and on the basis of the amorphous layer, a metal silicide layer is formed again.

[0030] The inventors found that in the process of forming metal silicide by the above method, firstly, the pre-amorphization treatment would cause stress release in the source and drain regions, which would reduce the breakdown voltage; secondly, the silicon in the source and drain regions would be consumed when forming the metal silicide layer, and if the amorphous layer could not react completely with the metal layer, the contact capacitance would increase; finally, when the thicker amorphous layer reacted with the thicker metal layer, voids were also likely to be generated, resulting in poor quality of the formed metal silicide. Moreover, when the thermal budget was limited, the components of the formed metal silicide were inconsistent, which was not conducive to the electrical performance of the semiconductor structure.

[0031] To solve the above problems, through research, the inventors provided a method for forming a semiconductor structure, in which a metal silicide stack was formed at the bottom of the first contact hole. The metal silicide stack included at least one stacking unit, and the stacking unit included a silicon layer and a metal layer formed in sequence at the bottom of the first contact hole. During the annealing treatment, the metal layer would not react with the silicon in the source and drain regions, avoiding the consumption of the silicon in the source and drain regions. At the same time, the silicon layer and the metal layer stacking structure was adopted. On the one hand, the pre-amorphization treatment was not required, avoiding the stress release of the source and drain; on the other hand, the silicon layer and the metal layer were stacked alternately, and the reaction could be more complete during the reaction. The components of the formed metal silicide layer were uniform, and voids were not easily generated, which was beneficial to reducing the contact resistance and contact capacitance and further improving the performance of the semiconductor structure.

[0032] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0033] First Embodiment

[0034] Figures 1 to 9 FIG. is a schematic structural diagram corresponding to each step of the method for forming a semiconductor structure in the first embodiment of the present invention.

[0035] Reference Figure 1 , a substrate was provided, and a gate structure 200 was formed on the substrate. Source regions 101 and drain regions 102 were formed in the substrate 100 on both sides of the gate structure 200.

[0036] In this embodiment, taking the formed semiconductor structure as a Fin FET (fin field effect transistor) structure as an example, the substrate included: a substrate 100; discrete fin portions 110 located on the substrate 100; an isolation structure (not shown in the figure) located on the substrate 100 exposed by the fin portions 110, the isolation structure covering part of the side walls of the fin portions 110, and the top of the isolation structure being lower than the top of the fin portions 110.

[0037] In other embodiments, the semiconductor device may also be a planar device, and the substrate is a planar substrate.

[0038] The material of the substrate 100 is silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin portion 110 includes silicon, germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the substrate 100 is a silicon substrate, and the material of the fin portion 110 is silicon.

[0039] The isolation structure serves to electrically isolate adjacent fin portions 110, and the material of the isolation structure is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride or carbon oxynitride. In this embodiment, the material of the isolation structure is silicon oxide.

[0040] In this embodiment, the substrate 100 only includes an NMOS region, and the corresponding formed FinFET device is an NMOS transistor; in other embodiments, the substrate may also include an NMOS region and a PMOS region, and the corresponding semiconductor device is a CMOS transistor, or may only include a PMOS region, and the corresponding formed FinFET device is a PMOS transistor.

[0041] The gate structure 200 is located on the isolation structure and straddles the fin portion 110, and the gate structure 200 covers a part of the top and the sidewalls of the fin portion 110.

[0042] In this embodiment, the gate structure 200 is a metal gate structure, and the gate electrode material of the gate structure 200 includes copper, aluminum or tungsten.

[0043] A sidewall 210 is further formed on the sidewall of the gate structure 200. The material of the sidewall 210 includes one or more of silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, the material of the sidewall 210 is silicon nitride.

[0044] In this embodiment, the doping ions of the source region 101 and the drain region 102 are N-type ions, such as P, As or Sb.

[0045] Reference Figure 2 , an interlayer dielectric layer 120 is formed on the substrate exposed by the gate structure 200, and the interlayer dielectric layer 120 covers the gate structure 200, the source region 101 and the drain region 102. In this embodiment, the material of the interlayer dielectric layer 120 is silicon oxide; in other embodiments, the material of the interlayer dielectric layer may also be silicon nitride or silicon oxynitride.

[0046] In this embodiment, the interlayer dielectric layer 120 is formed by a chemical vapor deposition process; in other embodiments, a physical vapor deposition process or an atomic layer deposition process may also be used to form the interlayer dielectric layer 120.

[0047] In this embodiment, the process steps for forming the gate structure 200 and the source region 101 and drain region 102 include: forming a dummy gate across the fin 110; forming sidewalls 210 on the sidewalls of the dummy gate; forming the source region 101 and drain region 102 in the substrate on both sides of the dummy gate; forming a first dielectric layer on the substrate exposed by the dummy gate, with the top of the dummy gate exposed by the first dielectric layer; removing the dummy gate; forming a gate structure at the position where the dummy gate was located; forming an upper dielectric layer on the first dielectric layer and on the top of the gate structure 200, and the first dielectric layer and the upper dielectric layer constitute the interlayer dielectric layer 120.

[0048] Reference Figure 3 , forming a first contact hole 310 in the interlayer dielectric layer 120, and the first contact hole 310 exposes the surfaces of the source region 101 and the drain region 102.

[0049] The first contact hole 310 provides a process basis for subsequently forming a conductive plug electrically connected to the source-drain doping region; in addition, the first contact hole 310 also provides a process basis for subsequently forming a metal silicide layer electrically connected to the source-drain doping region.

[0050] The process steps for forming the first contact hole 310 include: forming a first photoresist layer (not shown) on the interlayer dielectric layer 120, and the first photoresist layer defines the position and size of the to-be-formed first contact hole 310; using the first photoresist layer as a mask, etching the interlayer dielectric layer 120 to form the first contact hole 310 penetrating the interlayer dielectric layer 120, and the bottom of the first contact hole 310 exposes the surface of the source region 101 and the surface of the drain region 102; removing the first photoresist layer.

[0051] After forming the first contact hole 310, forming a metal silicide stack at the bottom of the first contact hole 310, and the metal silicide stack includes at least one stacking unit, and the stacking unit includes a silicon layer and a metal layer formed in sequence at the bottom of the first contact hole 310.

[0052] In this embodiment, the metal silicide stack includes one stacking unit, that is, it only includes a layer of silicon layer formed at the bottom of the first contact hole 310 and a layer of metal layer formed on the silicon layer. In other embodiments, the metal silicide stack may include multiple stacking units, that is, multiple layers of silicon layers and multiple layers of metal layers are cross-stacked, such as a silicon layer-metal layer-silicon layer-metal layer structure.

[0053] In this embodiment, the metal silicide stack further includes a layer of silicon layer formed on the stacking unit, and the structure of the metal silicide stack is a silicon layer-metal layer-silicon layer structure.

[0054] It should be noted that the silicon layer formed on the stacking unit refers to the silicon layer formed on the topmost stacking unit, rather than forming a silicon layer on each stacking unit.

[0055] In other embodiments, the metal silicide stack may include only one or more stacking units, and a silicon layer may not be formed on the topmost stacking unit.

[0056] It should be noted that forming the metal silicide stack means that when the metal silicide stack includes one stacking unit, a silicon layer is first deposited, then a metal layer is deposited, and subsequently, a silicon layer may or may not be deposited on the metal layer; when the metal silicide stack includes multiple stacking units, and so on, the silicon layer and the metal layer are arranged alternately until the last stacking unit is formed, and subsequently, a silicon layer may or may not be deposited on the topmost stacking unit. And the thickness of each deposited silicon layer may be equal or not equal; the thickness of each deposited metal layer may be equal or not equal. In this embodiment, the thickness of each deposited silicon layer is equal.

[0057] Specifically, the step of forming the metal silicide stack at the bottom of the first contact hole 310 includes:

[0058] Refer to Figure 3 , and form a metal silicide stacked film on the bottom and sidewalls of the first contact hole 310.

[0059] In this embodiment, the metal silicide stacked film includes a silicon layer 311 formed on the bottom and sidewalls of the first contact hole 310, a metal layer 312 formed on the silicon layer 311, and a silicon layer formed on the metal layer 312.

[0060] In this embodiment, the metal layer 312 is titanium metal; in other embodiments, the metal layer may also be nickel metal or cobalt metal.

[0061] In this embodiment, the method of depositing the silicon layer 311 is chemical vapor deposition process; in other embodiments, physical vapor deposition process or atomic layer deposition process may also be used to deposit the silicon layer.

[0062] In this embodiment, the method of depositing the metal layer 312 is atomic layer deposition method; in other embodiments, physical vapor deposition, chemical vapor deposition or electrochemistry plating method may also be used to deposit the metal layer.

[0063] In this embodiment, the metal silicide stacked film also covers the surface of the interlayer dielectric layer 120.

[0064] The ratio of the thickness of the silicon layer to the thickness of the metal layer is 0.1 to 10. If the ratio is less than 0.1 or greater than 10, there will be too much silicon material or too much metal material, resulting in the precipitation of silicon material or metal material during the reaction, leading to an increase in resistance.

[0065] The total thickness of the metal silicide stacked film formed on the bottom and side walls of the first contact hole 310 is greater than or equal to 0.5 nm and less than 30 nm. If the total thickness is less than 0.5 nm, it is difficult to complete in the manufacturing process. If the total thickness is greater than or equal to 30 nm, the subsequent formed metal silicide layer will be too thick, affecting the thickness of the conductive layer formed on the metal silicide layer and having an adverse effect on the resistance.

[0066] In this embodiment, by forming a metal silicide stacked film on the bottom and side wall surfaces of the first contact hole 310, and sequentially forming a silicon layer 311, a metal layer 312, and a silicon layer 311. On the one hand, there is no need to form an amorphous layer to increase the thickness of the metal silicide, avoiding the situation of stress loss in the source / drain epitaxial layer during the pre-amorphization process; on the other hand, when the silicon layer and the metal layer react to form a metal silicide layer, it avoids consuming the silicon in the source / drain region, and the alternately arranged silicon layer and metal layer can react more fully, avoiding the appearance of voids, and the formed metal silicide has a more uniform composition and better quality, which is beneficial to reducing the RC delay and contact resistance and improving the performance of the semiconductor structure.

[0067] Reference Figure 4 , the first contact hole 310 is filled with a sacrificial layer 400, and the sacrificial layer 400 also covers the surface of the metal silicide stacked film on the interlayer dielectric layer 120.

[0068] In this embodiment, the sacrificial layer 400 is a bottom anti-reflection layer; in other embodiments, the sacrificial layer 400 can also be a spin-coated carbon-containing material layer.

[0069] In this embodiment, the method for forming the sacrificial layer 400 is the spin coating method; in other embodiments, the sacrificial layer can also be formed by chemical vapor deposition.

[0070] After forming the sacrificial layer 400, the sacrificial layer 400 is etched back to expose the metal silicide stacked film on the side wall of the first contact hole 310, and at the same time, the metal silicide stacked film on the surface of the interlayer dielectric layer 120 is exposed.

[0071] The method for etching back the sacrificial layer 400 includes one or a combination of dry etching and wet etching. In this embodiment, the dry etching process is used to etch back the sacrificial layer 400.

[0072] Reference Figure 5, etch and remove the metal silicide stacked film on the sidewall of the first contact hole 310, and at the same time remove the metal silicide stacked film on the surface of the interlayer dielectric layer 120 to form a metal silicide stack at the bottom of the first contact hole.

[0073] The method for etching and removing the metal silicide stacked film includes one or a combination of dry etching and wet etching. In this embodiment, a dry etching process is used to etch and remove the metal silicide stacked film.

[0074] After removing the metal silicide stacked film on the sidewall, remove the sacrificial layer 400.

[0075] In other embodiments, when forming the metal silicide stack at the bottom of the first contact hole 310, it further includes forming the metal silicide stack on the sidewall of the first contact hole 310, that is, after forming the metal silicide stacked film on the bottom and sidewalls of the first contact hole 310, do not remove the metal silicide stacked film on the sidewall of the first contact hole 310. The metal silicide stacked film on the bottom and sidewalls of the first contact hole 310 serves as the metal silicide stack, which can reduce steps such as forming the sacrificial layer and simplify the process flow.

[0076] Reference Figure 6 , after forming the metal silicide stack at the bottom of the first contact hole 310, form a second contact hole 320 in the interlayer dielectric layer 120, and the second contact hole 320 exposes the surface of the gate structure 200.

[0077] In this embodiment, since the gate structure 200 is a metal gate structure, it is not necessary to form a metal silicide layer to reduce the contact resistance, so it is not necessary to deposit a metal silicide stack in the second contact hole 320.

[0078] Reference Figure 7 , after forming the second contact hole 320, form a barrier layer 500 on the sidewall surface of the first contact hole 310, the surface of the metal silicide stack in the first contact hole 310, the sidewalls and bottom surface of the second contact hole 320.

[0079] In this embodiment, the barrier layer 500 also covers the top surface of the interlayer dielectric layer 120.

[0080] In this embodiment, the material of the barrier layer 500 is titanium nitride; in other embodiments, the material of the barrier layer 500 can also be tantalum nitride.

[0081] In this embodiment, the method for forming the barrier layer 500 includes chemical vapor deposition; in other embodiments, physical vapor deposition or atomic layer deposition can also be used to form the barrier layer.

[0082] In this embodiment, the function of the barrier layer 500 is to prevent the conductive metal in the first contact hole 310 and the second contact hole 320 from diffusing into the interlayer dielectric layer 120 later. The barrier layer 500 located on the interlayer dielectric layer 120 can serve as a polishing stop layer for subsequent polishing of the conductive metal material.

[0083] Reference Figure 8 , after forming the barrier layer 500, an annealing treatment is performed on the metal silicide stack to cause the silicon layer and the titanium layer in the metal silicide stack to react to generate a metal silicide layer 600.

[0084] The annealing treatment includes a soak annealing process, a spike annealing process, a flash annealing process, or a laser annealing. In this embodiment, the spike annealing process is used for the annealing treatment.

[0085] In this embodiment, the process parameters of the annealing treatment include: the annealing temperature is 400°C to 1000°C, the annealing time is 0.4 microseconds to 60 seconds, the annealing atmosphere includes one or more of nitrogen, hydrogen, ammonia, oxygen, or argon, and the annealing pressure is 0.001 torr to 780 torr.

[0086] Reference Figure 9 , after generating the metal silicide layer 600, the first contact hole 310 and the second contact hole 320 are filled with a conductive layer 330 to form a conductive plug.

[0087] In this embodiment, the specific steps for forming the conductive plug include: filling a conductive material layer (not shown in the figure) in the first contact hole 310 and the second contact hole 320, and the conductive material layer also covers the barrier layer 500 on the top surface of the interlayer dielectric layer 120; performing chemical mechanical polishing on the conductive material layer until the surface of the interlayer dielectric layer 120 is exposed to form the conductive plug.

[0088] In this embodiment, the material of the conductive material layer is tungsten; in other embodiments, the material of the conductive material layer can also be aluminum, copper, platinum, cobalt, etc.

[0089] In this embodiment, the method for filling the conductive material layer is atomic layer deposition; in other embodiments, chemical vapor deposition, physical vapor deposition, or electrochemistry plating methods can also be used to fill the conductive material layer.

[0090] In this embodiment, a metal silicide layer is formed at the bottom of the first contact hole 310 to reduce the contact resistance and the RC delay. The metal silicide layer is formed by laminating and depositing a silicon layer and a metal layer, without the need for pre-amorphization treatment, avoiding the loss of source-drain stress during the pre-amorphization treatment. At the same time, the alternately arranged silicon layer and metal layer can react completely during the annealing treatment, and voids are not likely to appear. The obtained metal silicide layer has uniform composition and good quality, which is beneficial to improving the performance of the semiconductor structure.

[0091] Second Embodiment

[0092] Figures 10 to 16 FIG. is a schematic structural diagram corresponding to each step of the method for forming a semiconductor structure in the second embodiment of the present invention.

[0093] In this embodiment, the gate structure 200 is a polysilicon gate structure. In order to reduce the contact resistance and contact capacitance of the conductive plug on the polysilicon gate structure, a metal silicide layer also needs to be formed in the contact hole on the polysilicon gate structure.

[0094] In this embodiment, the step of providing the substrate is the same as that in the first embodiment and will not be described in detail here.

[0095] Reference Figure 10 , in this embodiment, the process steps of forming the gate structure 200 and the source region 101 and drain region 102 include: forming a gate structure 200 and sidewalls 210 on both sides of the gate structure 200 on the substrate; forming a source region 101 and a drain region 102 in the substrate on both sides of the gate structure 200.

[0096] The subsequent process steps further include: forming an interlayer dielectric layer 120 on the substrate exposed by the gate structure 200 and on the top of the gate structure 200.

[0097] Reference Figure 11 , after forming the interlayer dielectric layer 120, a first contact hole 310 and a second contact hole 320 are formed in the interlayer dielectric layer 120. The first contact hole 310 exposes the surfaces of the source region 101 and the drain region 102, and the second contact hole 320 exposes the surface of the gate structure 200.

[0098] After forming the first contact hole 310 and the second contact hole 320, a metal silicide stack is formed at the bottoms of the first contact hole 310 and the second contact hole 320.

[0099] Specifically, the step of forming a metal silicide stack at the bottoms of the first contact hole 310 and the second contact hole 320 includes:

[0100] Reference Figure 12, a metal silicide stacked film is formed on the bottom and side walls of the first contact hole 310 and on the bottom and side walls of the second contact hole 320, and the metal silicide stacked film also covers the surface of the interlayer dielectric layer 120;

[0101] The first contact hole 310 and the second contact hole 320 are filled with a sacrificial layer (not shown in the figure), and the sacrificial layer also covers the surface of the metal silicide stacked film on the interlayer dielectric layer 120;

[0102] Etch back the sacrificial layer to expose the metal silicide stacked film on the side walls of the first contact hole 310 and the side walls of the second contact hole 320, and at the same time expose the metal silicide stacked film on the surface of the interlayer dielectric layer 120.

[0103] Reference Figure 13 , remove the metal silicide stacked film on the side walls of the first contact hole 310 and the second contact hole 320.

[0104] In this embodiment, the method for removing the metal silicide stacked film on the side walls of the first contact hole 310 and the second contact hole 320 is the same as that described in the first embodiment, and will not be elaborated here.

[0105] Similarly, in other embodiments, when forming a metal silicide stack at the bottom of the first contact hole 310 and the second contact hole 320, a metal silicide stack is also formed on the side walls of the first contact hole 310 and the second contact hole 320, that is, the metal silicide stacked film on the side walls of the first contact hole 310 and the second contact hole 320 is not removed, and a metal silicide stack is formed on the side walls of the first contact hole 310 and the side walls of the second contact hole 320.

[0106] Reference Figure 14 , a barrier layer 500 is formed on the side wall surface of the first contact hole 310, the side wall surface of the second contact hole 320, and the surface of the metal silicide stack.

[0107] In this embodiment, the material and formation method of the barrier layer 500 are the same as those described in the first embodiment, and will not be elaborated here.

[0108] Reference Figure 15 , perform an annealing treatment on the metal silicide stack to obtain a metal silicide layer.

[0109] In this embodiment, the process and process parameters of the annealing treatment are the same as those described in the first embodiment, and will not be elaborated here.

[0110] Reference Figure 16, the first contact hole 310 and the second contact hole 320 are filled with a conductive layer 330 to form a conductive plug.

[0111] In this embodiment, the material and formation method of the conductive layer 330 are the same as those described in the first embodiment, and will not be elaborated here.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, on which a gate structure is formed, and source regions and drain regions are formed in the substrate on both sides of the gate structure; Forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the gate structure, the source regions and the drain regions; Forming a first contact hole in the interlayer dielectric layer, the first contact hole exposing the source regions and the drain regions; Forming a metal silicide stack at the bottom of the first contact hole, the metal silicide stack including two or more stacked units and a silicon layer on the topmost stacked unit among the two or more stacked units, and the stacked unit including a silicon layer and a metal layer formed in sequence at the bottom of the first contact hole; Performing an annealing treatment on the metal silicide stack to obtain a metal silicide layer; Forming a barrier layer on the sidewalls and the bottom of the first contact hole, the metal silicide stack being located between the barrier layer and the bottom of the first contact hole; Filling a conductive layer in the first contact hole.

2. The method for forming a semiconductor structure according to claim 1, wherein, In the metal silicide stack, the ratio of the thickness of the silicon layer to the thickness of the metal layer is 0.1 to 10.

3. The method for forming a semiconductor structure according to claim 2, wherein The total thickness of the metal silicide stack is 0.5 nm to 30 nm.

4. The method for forming a semiconductor structure according to claim 1, wherein When the gate structure is a metal gate structure, after forming the metal silicide stack at the bottom of the first contact hole, it further includes: forming a second contact hole in the interlayer dielectric layer, the second contact hole exposing the surface of the gate structure.

5. The method for forming a semiconductor structure according to claim 1, wherein When the gate structure is a polysilicon gate structure, before forming the metal silicide stack at the bottom of the first contact hole, it further includes: forming a second contact hole in the interlayer dielectric layer, the second contact hole exposing the surface of the gate structure.

6. The method for forming a semiconductor structure according to claim 5, wherein, After forming the second contact hole, forming a metal silicide stack at the bottom of the first contact hole and at the bottom of the second contact hole.

7. The method for forming a semiconductor structure according to claim 4, wherein After forming the second contact hole, it further includes: forming a barrier layer on the sidewalls and the bottom of the second contact hole.

8. The method for forming a semiconductor structure according to claim 7, wherein After forming the metal silicide stack at the bottom of the second contact hole, it further includes: forming a barrier layer on the sidewalls and the bottom of the second contact hole.

9. The method for forming a semiconductor structure according to claim 1, wherein The step of forming the metal silicide stack at the bottom of the first contact hole includes: Forming a metal silicide stacked film on the bottom and the sidewalls of the first contact hole; Filling the first contact hole with a sacrificial layer; Etching back the sacrificial layer to expose the metal silicide stacked film on the sidewalls of the first contact hole; Etching and removing the metal silicide stacked film on the sidewalls of the first contact hole to form a metal silicide stack at the bottom of the first contact hole.

10. The method for forming a semiconductor structure according to claim 9, wherein, The material of the sacrificial layer includes a bottom anti-reflection material or a spin-coated carbon-containing compound.

11. The method for forming a semiconductor structure according to claim 1, wherein, When forming the metal silicide stack at the bottom of the first contact hole, it further includes: forming a metal silicide stack on the sidewalls of the first contact hole.

12. The method for forming a semiconductor structure according to claim 6, wherein When forming the metal silicide stack at the bottom of the first contact hole and at the bottom of the second contact hole, it further includes: forming a metal silicide stack on the sidewalls of the first contact hole and on the sidewalls of the second contact hole.

13. The method for forming a semiconductor structure according to claim 1, wherein The method of the annealing treatment includes a soak annealing process, a spike annealing process, a flash annealing process or a laser annealing.

14. The method for forming a semiconductor structure according to claim 13, wherein, The process parameters of the annealing treatment include: the annealing temperature is 400°C to 1000°C, the annealing time is 0.4 microseconds to 60 seconds, the annealing atmosphere includes one or more of nitrogen, hydrogen, ammonia, oxygen or argon, and the annealing pressure is 0.001 Torr to 780 Torr.

15. The method for forming a semiconductor structure according to claim 1, wherein, The material of the metal layer includes titanium or nickel or cobalt.

16. The method for forming a semiconductor structure according to claim 7 or 8, characterized in that, The material of the barrier layer includes titanium nitride or tantalum nitride.

17. The method for forming a semiconductor structure according to claim 7 or 8, characterized in that, After forming the barrier layer, it further includes: filling a conductive layer in the second contact hole.

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