Substrates and semiconductor package devices and methods for manufacturing the same

Abstract

A substrate, a semiconductor package device, and a method of manufacturing a semiconductor package device are provided. The substrate includes a low-density wiring structure, a first medium-density wiring structure, and a high-density wiring structure. The first medium-density wiring structure is electrically connected to the low-density wiring structure. The high-density wiring structure is electrically connected to the low-density wiring structure. The high-density wiring structure and the first medium-density wiring structure are disposed side-by-side. A line pitch of a circuit layer of the low-density wiring structure is greater than a line pitch of a circuit layer of the first medium-density wiring structure. The line pitch of the circuit layer of the first medium-density wiring structure is greater than a line pitch of a circuit layer of the high-density wiring structure.

Description

Technical Field

[0001] This disclosure relates to a substrate, a semiconductor packaging apparatus, and a method for manufacturing the substrate and the semiconductor packaging apparatus, and further relates to a substrate including a wiring structure and a method for manufacturing the substrate. Background Technology

[0002] As semiconductor manufacturing processes continue to advance, semiconductor devices produced by these technologies can carry more signals and operate at higher bandwidths. Simultaneously, several new packaging technologies are being implemented in these advanced semiconductor devices. For example, one advanced semiconductor device can be electrically connected to a packaging substrate via a silicon interposer structure. Furthermore, an advanced semiconductor device can be electrically connected to another advanced semiconductor device via an embedded bridge die. However, the high cost of these packaging technologies is a major obstacle to their development. Summary of the Invention

[0003] In some embodiments, a substrate includes a low-density wiring structure, a first medium-density wiring structure, and a high-density wiring structure. The first medium-density wiring structure is electrically connected to the low-density wiring structure. The high-density wiring structure and the first medium-density wiring structure are arranged side-by-side. The line spacing of the circuit layers of the low-density wiring structure is greater than the line spacing of the circuit layers of the first medium-density wiring structure. The line spacing of the circuit layers of the first medium-density wiring structure is greater than the line spacing of the circuit layers of the high-density wiring structure.

[0004] In some embodiments, a semiconductor packaging device includes a substrate and a first die. The substrate includes a low-density wiring structure, a first medium-density wiring structure, and a high-density wiring structure. The first medium-density wiring structure is electrically connected to the low-density wiring structure. The high-density wiring structure is electrically connected to the low-density wiring structure. The high-density wiring structure and the first medium-density wiring structure are disposed side-by-side. The line spacing of the circuit layers of the low-density wiring structure is greater than the line spacing of the circuit layers of the first medium-density wiring structure. The line spacing of the circuit layers of the first medium-density wiring structure is greater than the line spacing of the circuit layers of the high-density wiring structure. The first die is disposed on the substrate. The first die is electrically connected to the high-density wiring structure.

[0005] In some embodiments, a method of manufacturing a semiconductor packaging device includes: providing a carrier; attaching a first medium-density wiring structure to the carrier; attaching a high-density wiring structure to the carrier, wherein the high-density wiring structure and the first medium-density wiring structure are arranged side-by-side; forming a low-density wiring structure onto the first medium-density wiring structure and the high-density wiring structure; removing the carrier to form a substrate comprising the low-density wiring structure, the first medium-density wiring structure, and the high-density wiring structure; and bonding a first die to the substrate. The line spacing of the circuit layers of the low-density wiring structure is greater than the line spacing of the circuit layers of the first medium-density wiring structure. The line spacing of the circuit layers of the first medium-density wiring structure is greater than the line spacing of the circuit layers of the high-density wiring structure. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of some embodiments of this disclosure will be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A top view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0008] Figure 2 Description of some embodiments according to this disclosure Figure 1 The cross-sectional view taken from line 2-2 of the semiconductor packaging device.

[0009] Figure 3 A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0010] Figure 4 A top view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0011] Figure 5 Description of some embodiments according to this disclosure Figure 4 The cross-sectional view taken from line 5-5 of the semiconductor packaging device.

[0012] Figure 6 A top view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0013] Figure 7 Description of some embodiments according to this disclosure Figure 6 The cross-sectional view taken from line 7-7 of the semiconductor packaging device.

[0014] Figure 8 Description of some embodiments according to this disclosure Figure 2An enlarged cross-sectional view of an example of a portion of the first medium-density wiring structure of a semiconductor packaging device.

[0015] Figure 9A Description of some embodiments according to this disclosure Figure 2 A top view of an example of the transport layer of the first medium-density wiring structure of a semiconductor packaging device.

[0016] Figure 9B Description of some embodiments according to this disclosure Figure 2 A top view of an example of the transport layer of the first medium-density wiring structure of a semiconductor packaging device.

[0017] Figure 10A Description of some embodiments according to this disclosure Figure 2 A top view of an example of the ground layer of the first medium-density wiring structure of a semiconductor packaging device.

[0018] Figure 10B Description of some embodiments according to this disclosure Figure 2 A top view of an example of the ground layer of the first medium-density wiring structure of a semiconductor packaging device.

[0019] Figure 10C The illustrations illustrate some embodiments according to this disclosure. Figure 2 A top view of an example of the ground layer of the first medium-density wiring structure of a semiconductor packaging device.

[0020] Figure 11 Description of some embodiments according to this disclosure Figure 2 An enlarged cross-sectional view of an example of a part of a high-density wiring structure of a semiconductor packaging device.

[0021] Figure 12A Description of some embodiments according to this disclosure Figure 2 A top view of an example of a transmission layer in a high-density wiring structure of a semiconductor packaging device.

[0022] Figure 12B Description of some embodiments according to this disclosure Figure 2 A top view of an example of a transmission layer in a high-density wiring structure of a semiconductor packaging device.

[0023] Figure 13A Description of some embodiments according to this disclosure Figure 2 A top view of an example of a ground plane in a high-density wiring structure of a semiconductor packaging device.

[0024] Figure 13B Description of some embodiments according to this disclosure Figure 2 A top view of an example of a ground plane in a high-density wiring structure of a semiconductor packaging device.

[0025] Figure 13C Description of some embodiments according to this disclosure Figure 2 A top view of an example of a ground plane in a high-density wiring structure of a semiconductor packaging device.

[0026] Figure 14A Description of some embodiments according to this disclosure Figure 7 A top view of an example of the ground layer of the second medium-density wiring structure of a semiconductor packaging device.

[0027] Figure 14B Description of some embodiments according to this disclosure Figure 7 A top view of an example of the ground layer of the second medium-density wiring structure of a semiconductor packaging device.

[0028] Figure 14C Description of some embodiments according to this disclosure Figure 7 A top view of an example of the transport layer of the second medium-density wiring structure of a semiconductor packaging device.

[0029] Figure 15 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0030] Figure 16 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0031] Figure 17 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0032] Figure 18 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0033] Figure 19 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0034] Figure 20 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0035] Figure 21 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0036] Figure 22 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0037] Figure 23 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0038] Figure 24 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0039] Figure 25 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0040] Figure 26 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0041] Figure 27 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0042] Figure 28 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0043] Figure 29 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0044] Figure 30 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0045] Figure 31 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0046] Figure 32 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0047] Figure 33 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. Detailed Implementation

[0048] Common reference numerals are used throughout the drawings and detailed embodiments to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0049] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features are formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0050] Figure 1 A top view illustrating a semiconductor packaging apparatus 1 according to some embodiments of the present disclosure. Figure 2 Explanation along Figure 1 A cross-sectional view taken along line 2-2 of the semiconductor packaging device 1. (See attached image.) Figure 1 and Figure 2 As shown, the semiconductor package device 1 includes a substrate 1S, a first die 16, a second die 17, a third die 18, and a plurality of first connecting elements 19, a plurality of second connecting elements 19', a plurality of third connecting elements 20, and a plurality of fourth connecting elements 20'. The substrate 1S includes a low-density wiring structure 10, a first middle-density wiring structure 11, a high-density wiring structure 12, a dielectric layer 13, a first protective layer 14, and conductive studs 15.

[0051] refer to Figure 2The low-density wiring structure 10 includes an insulating layer 101, a first circuit layer 102, a second circuit layer 103, and a protective layer 104. The low-density wiring structure 10 has a first surface 1001 and a second surface 1002 opposite to the first surface 1001. The insulating layer 101 is in contact with the first circuit layer 102. The first circuit layer 102 includes a via portion 1021 exposed from the insulating layer 101 and a main portion 1022 embedded within the insulating layer 101. The via portion 1021 and the main portion 1022 may be integrally formed and simultaneously. The via portion 1021 has a portion exposed from the first surface 1001 and embedded in the dielectric layer 13. In some embodiments, the height of the via portion 1021 may be in the range of about 5 μm to about 50 μm or about 40 μm. The second circuit layer 103 is disposed on the insulating layer 101. A portion of the second circuit layer 103 (e.g., via portions) may extend through the insulating layer 101 to contact and electrically connect to the first circuit layer 102. A protective layer 104 is disposed on the insulating layer 101 to cover the second circuit layer 103. Additionally, the protective layer 104 may define a plurality of openings 105 to expose portions of the second circuit layer 103. In some embodiments, the exposed portions of the second circuit layer 103 may contact connecting elements (e.g., solder) to electrically connect to an external printed circuit board (PCB). The first circuit layer 102 or the second circuit layer 103 may also be referred to as a “low-density circuit layer.” In some embodiments, the density of circuit lines (including, for example, traces or pads) in a medium-density circuit layer (e.g., the first circuit layer 112 or the third circuit layer 114 of the first medium-density wiring structure 11) is greater than the density of circuit lines in a low-density circuit layer (e.g., the first circuit layer 102 or the second circuit layer 103 of the low-density wiring structure 10). In other words, the number of circuit lines (including, for example, traces or pads) per unit area of ​​a medium-density circuit layer is greater than the number of circuit lines per unit area of ​​a low-density circuit layer, i.e., about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively, or in combination, the line width / line space (L / S) of a low-density circuit layer is greater than the L / S of a medium-density circuit layer, for example, about 90% or more, about 50% or more, or about 20% or more. Furthermore, a wiring structure including a low-density circuit layer may be designated as a "low-density wiring structure," such as low-density wiring structure 10. In some embodiments, the L / S of low-density wiring structure 10 may be greater than or equal to about 10 μm / about 10 μm.

[0052] In some embodiments, the insulating layer 101 may be made of pre-impregnated composite fibers (e.g., a prepreg material). Examples of prepreg materials may include, but are not limited to, multilayer structures formed by stacking or laminating several prepreg materials (e.g., epoxy resin and fiberglass cloth) or sheets. The insulating layer 101 with pre-impregnated composite fibers provides mechanical support for the low-density wiring structure 10. In some embodiments, the materials of the first circuit layer 102 and the second circuit layer 103 may each comprise one or more metals, such as copper (Cu), gold (Au), aluminum (Al), titanium (Ti), etc. In some embodiments, the material of the protective layer 104 may comprise an insulating material, such as a solder mask.

[0053] Still referencing Figure 2 A first medium-density wiring structure 11 includes a dielectric structure 111, a first circuit layer 112, a second circuit layer 113, and a third circuit layer 114. The first medium-density wiring structure 11 has a first surface 1101 facing away from a low-density wiring structure 10, a second surface 1102 facing the low-density wiring structure 10, and a side surface 1103 extending between the first surface 1101 and the second surface 1102. The first circuit layer 112 includes a plurality of conductive pads adjacent to the first surface 1101. The second circuit layer 113 includes a plurality of conductive pads adjacent to the second surface 1102. The first circuit layer 112, the second circuit layer 113, and the third circuit layer 114 are embedded in the dielectric structure 111. The first circuit layer 112 is electrically connected to the second circuit layer 113 through the third circuit layer 114. Figure 2As shown, the high-density wiring structure 12 includes a dielectric structure 121, a first circuit layer 122, a second circuit layer 123, and a third layer 124. The high-density wiring structure 12 has a first surface 1201 facing away from the low-density wiring structure 10, a second surface 1202 facing the low-density wiring structure 10, and a side surface 1203 extending between the first surface 1201 and the second surface 1202. The first circuit layer 122 includes a plurality of conductive pads adjacent to the first surface 1201. The second circuit layer 123 includes a plurality of conductive pads adjacent to the second surface 1202. The first circuit layer 122, the second circuit layer 123, and the third circuit layer 124 are embedded in the dielectric structure 121. The first circuit layer 122 is electrically connected to the second circuit layer 123 through the third circuit layer 124. The first circuit layer 122 or the third circuit layer 124 may also be referred to as a "medium-density circuit layer." The first circuit layer 122 or the third circuit layer 124 may also be referred to as a "high-density circuit layer." In some embodiments, the density of circuit lines (including traces or pads) in a high-density circuit layer (e.g., first circuit layer 122 or third circuit layer 124) is greater than the density of circuit lines in a medium-density circuit layer (e.g., first circuit layer 112 or third circuit layer 114). That is, the count of circuit lines (including traces or pads) per unit area in a high-density circuit layer is greater than the count of circuit lines per unit area in a medium-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, or about 2 times or more. Alternatively, or in combination, the linewidth / spacing (L / S) of a medium-density circuit layer is greater than the L / S of a high-density circuit layer, for example, about 20% or more, about 50% or more, or about 90% or more. Furthermore, a wiring structure containing a medium-density circuit layer may be designated as a "medium-density wiring structure," such as a first medium-density wiring structure 11, and a wiring structure containing a high-density circuit layer may be designated as a "high-density wiring structure," such as a high-density wiring structure 12. In some embodiments, the L / S ratio of the first medium-density wiring structure 11 may be in the range of about 2 μm / about 2 μm to about 10 μm / about 10 μm or equal to about 5 μm / about 5 μm. In some embodiments, the L / S ratio of the high-density wiring structure 12 may be less than or equal to about 2 μm / about 2 μm.

[0054] In some embodiments, the materials of dielectric structure 111 and dielectric structure 121 may each comprise, but are not limited to, organic materials, such as molding compounds, epoxy-based materials, Ajinomoto build-up films (ABF), or other suitable organic materials. In some embodiments, the materials of the first circuit layer 112, the second circuit layer 113, and the third circuit layer 114 of the first medium-density wiring structure 11 may each comprise one or more metals, such as copper (Cu), gold (Au), aluminum (Al), titanium (Ti), etc. In some embodiments, the materials of the first circuit layer 122, the second circuit layer 123, and the third circuit layer 124 of the high-density wiring structure 12 may each comprise one or more metals, such as copper (Cu), gold (Au), aluminum (Al), titanium (Ti), etc.

[0055] Still referencing Figure 2 A first medium-density wiring structure 11 is disposed adjacent to the first surface 1001 of the low-density wiring structure 10. A high-density wiring structure 12 is disposed adjacent to the first surface 1001 of the low-density wiring structure 10. The high-density wiring structure 12 and the first medium-density wiring structure 11 are disposed side by side. The first medium-density wiring structure 11 is electrically connected to the low-density wiring structure 10. For example, the second circuit layer 113 of the first medium-density wiring structure 11 is electrically connected to the first circuit layer 102 of the low-density wiring structure 10. Furthermore, the high-density wiring structure 12 is electrically connected to the low-density wiring structure 10. For example, the second circuit layer 123 of the high-density wiring structure 12 is electrically connected to the first circuit layer 102 of the low-density wiring structure 10.

[0056] A dielectric layer 13 is disposed on a first surface 1001 of a low-density wiring structure 10. The dielectric layer 13 may contact the first surface 1001 of the low-density wiring structure 10. The dielectric layer 13 surrounds and encapsulates a first medium-density wiring structure 11 and / or a high-density wiring structure 12. Therefore, the first medium-density wiring structure 11 and / or the high-density wiring structure 12 are embedded in the dielectric layer 13. A portion of the dielectric layer 13 is located between the first medium-density wiring structure 11 and the high-density wiring structure 12. The dielectric layer 13 is substantially free of reinforcing elements, such as glass fibers. That is, the dielectric layer 13 is fiber-free. The dielectric layer 13 may not contain reinforcing elements, such as glass fibers, and may contain only homogeneous resin. Additionally, the material of the dielectric layer 13 may contain one or more organic materials, such as molding materials, polyimide (PI), Ajinomoto deposited film (ABF), epoxy materials (e.g., epoxy resin), or combinations of two or more thereof. The fiber-free dielectric layer 13 facilitates the reconfiguration process of the first medium-density wiring structure 11 and the high-density wiring structure 12.

[0057] The dielectric layer 13 has a first surface 1301 facing away from the low-density wiring structure 10 and a second surface 1302 facing the low-density wiring structure 10. The first surface 1301 of the dielectric layer 13 and the first surface 1101 of the first medium-density wiring structure 11 are substantially coplanar. The first surface 1301 of the dielectric layer 13 and the first surface 1201 of the high-density wiring structure 12 are substantially coplanar. In some embodiments, the first surface 1101 of the first medium-density wiring structure 11 and the first surface 1201 of the high-density wiring structure 12 are substantially coplanar. The first surface 1101 of the first medium-density wiring structure 11, the first surface 1201 of the high-density wiring structure 12, and the first surface 1301 of the dielectric layer 13 can form a substantially smooth surface, which effectively improves the yield of the bonding process for the first die 16, the second die 17, or the third die 18.

[0058] A protective layer 14 is disposed on a generally smooth surface comprising a first surface 1101 of a first medium-density wiring structure 11, a first surface 1201 of a high-density wiring structure 12, and a first surface 1301 of a dielectric layer 13. The protective layer 14 covers the surface 1301 of the dielectric layer 13. The protective layer 14 defines a plurality of openings 141 to expose a portion of the first surface 1101 of the first medium-density wiring structure 11 and / or a portion of the first surface 1201 of the high-density wiring structure 12. In some embodiments, the material of the protective layer 14 may comprise an insulating material, such as a solder mask.

[0059] like Figure 2 As shown, dielectric layer 13 has a first height H1, while the first medium-density wiring structure 11 has a second height H2, which is smaller than the first height H1. The via portion 1021 of the first circuit layer 102 of the low-density wiring structure 10 compensates for the height difference between the first height H1 and the second height H2, allowing the first medium-density wiring structure 11 to be electrically connected to the low-density wiring structure 10. Furthermore, the high-density wiring structure 12 has a third height H3, different from the second height H2. In some embodiments, the second height H2 is greater than the third height H3. The via portion 1021 of the first circuit layer 102 of the low-density wiring structure 10 may not be sufficient to compensate for the height difference between the first height H1 and the third height H3. To solve this technical problem, a conductive post 15 with a fourth height H4, inserted between the high-density wiring structure 12 and the low-density wiring structure 10, further compensates for the spatial distance between the high-density wiring structure 12 and the via portion 1021, allowing the high-density wiring structure 12 to be electrically connected to the low-density wiring structure 10 via the conductive post 15. The conductive post 15 is surrounded by dielectric layer 13. The conductive post 15 has a first surface 1501 facing the high-density wiring structure 12 and a second surface 1502 facing the low-density wiring structure 10. For example... Figure 2As shown, the second surface 1502 of the conductive post 15 may be substantially coplanar with the second surface 1102 of the first medium-density wiring structure 11. In some embodiments, the conductive post 15 is in contact with the low-density wiring structure 10 and / or the high-density wiring structure 12. In some embodiments, the material of the conductive post 15 may include one or more metals, such as copper (Cu), gold (Au), aluminum (Al), titanium (Ti), etc. In some alternative embodiments, the high-density wiring structure 12 and the first medium-density wiring structure 11 may have substantially the same height.

[0060] refer to Figure 2 A first die 16 is disposed on a substrate 1S, and a second die 17 is disposed on the substrate 1S. In some embodiments, the first die 16 can operate at a first bandwidth (e.g., high bandwidth). In some embodiments, the second die 17 can operate at a second bandwidth (e.g., medium-high bandwidth or medium bandwidth). The first bandwidth is higher than the second bandwidth. For example, the first die 16 can operate at a bandwidth of about 1 terabyte per second (TB / s) or greater. The first die 16 may include, for example (but not limited to), a processor, a controller, high bandwidth memory (HBM), or other semiconductor dies. For example, the second die 17 can operate at a bandwidth of about 100 gigabytes per second (GB / s) or in the range of about 5 GB / s to about 27 GB / s. The second die 17 may include, for example (but not limited to), a processor, a logic die, a serializer / deserializer (SerDes), or other semiconductor dies. The third die 18 is disposed on the substrate 1S. The third die 18 may include, for example (but not limited to), a logic die, an application-specific integrated circuit (ASIC) die, or other semiconductor dies.

[0061] The first die 16 is electrically connected to the high-density wiring structure 12. For example, the first die 16 has a plurality of conductive pads 161 electrically connected to the first circuit layer 122 of the high-density wiring structure 12 via a first connecting element 19. The second die 17 is electrically connected to the first medium-density wiring structure 11. For example, the second die 17 has a plurality of conductive pads 171 electrically connected to the first circuit layer 112 of the first medium-density wiring structure 11 via a second connecting element 19'. The third die 18 is electrically connected to both the high-density wiring structure 12 and the first medium-density wiring structure 11. For example, the third die 18 has a plurality of first conductive pads 181 electrically connected to the first circuit layer 122 of the high-density wiring structure 12 via a third connecting element 20. Furthermore, the third die 18 has a plurality of second conductive pads 182 electrically connected to the first circuit layer 112 of the first medium-density wiring structure 11 via a fourth connecting element 20'. In addition, the first die 16 is electrically connected to the low-density wiring structure 10 via the high-density wiring structure 12. The third die 18 is electrically connected to the first die 16 via a high-density wiring structure 12. The second die 17 is electrically connected to the low-density wiring structure 10 via a first medium-density wiring structure 11. The second die 17 is also electrically connected to the third die 18 via the first medium-density wiring structure 11. The high-density wiring structure 12, having a relatively small L / S (e.g., about 2 μm / about 2 μm or less L / S), enables high-bandwidth electrical transmission between the first die 16 and the third die 18, or between the first die 16 and the low-density wiring structure 10. Meanwhile, the first medium-density wiring structure 11, having a medium L / S (e.g., about 5 μm / about 5 μm L / S), enables medium-high or medium-bandwidth electrical transmission between the second die 17 and the third die 18, or between the second die 17 and the low-density wiring structure 10. The substrate 1S of the semiconductor package device 1, which includes a multi-density wiring structure (e.g., a first medium-density wiring structure 11 and a high-density wiring structure 12), is compatible with dies (e.g., a first die 16, a second die 17, and a third die 18) operating at different bandwidths. In a comparative embodiment, the semiconductor dies are electrically connected to the package substrate via a silicon interposer structure. In another comparative embodiment, the semiconductor dies are electrically connected to another semiconductor die via an embedded bridging interconnect. In this disclosure, the material of the multi-density wiring structure comprises an organic material that significantly reduces the manufacturing cost of the semiconductor package device 1.

[0062] refer to Figure 2The first die 16 has a first projection area A1 in the Z direction on the first surface 1001 of the lower wiring structure 10, and the high-density wiring structure 12 has a second projection area A2 in the Z direction on the first surface 1001 of the lower wiring structure 10. The first projection area A1 and the second projection area A2 overlap. Furthermore, the second die 17 has a third projection area A3 in the Z direction on the first surface 1001 of the lower wiring structure 10, and the first medium-density wiring structure 11 has a fourth projection area A4 in the Z direction on the first surface 1001 of the lower wiring structure 10. The third projection area A3 and the fourth projection area A4 overlap. Additionally, the third die 18 has a fifth projection area A5 in the Z direction on the first surface 1001 of the lower wiring structure 10.

[0063] The fifth projection region A5 overlaps with the second projection region A2 and / or the fourth projection region A4.

[0064] Figure 3 This illustration shows a cross-sectional view of a semiconductor packaging apparatus 2 according to some embodiments of the present disclosure. The semiconductor packaging apparatus 2 is similar to... Figure 2 The semiconductor packaging device 1 differs from the semiconductor packaging device 2 in that the substrate 2S of the semiconductor packaging device 2 additionally includes a device 21 disposed on a low-density wiring structure 10. The device 21 and the high-density wiring structure 12 are arranged side-by-side. In some alternative embodiments, the device 21 and the first medium-density wiring structure 11 may be arranged side-by-side. Figure 3As shown, spacer 22 is mounted on device 21 via adhesive layer 23. Device 21 has a fifth height H5, and spacer 22 and adhesive layer 23 together have a sixth height H6. The sum of the fifth height H5 and the sixth height H6 is approximately equal to the second height H2. That is, spacer 22 and adhesive layer 23 together compensate for the height difference between device 21 and the first medium-density wiring structure 11, allowing device 21 to be electrically connected to low-density wiring structure 10. For example, device 21 includes a plurality of conductive pads 211 electrically connected to via portions 1021 of the first circuit layer 102 of low-density wiring structure 10. Device 21 may include passive electronic components, such as capacitors, inductors, or resistors. Device 21 may include active electronic components, such as transistors or diodes. Device 21 can operate at medium to low bandwidth or low bandwidth. For example, device 21 can operate at a bandwidth on the megabytes per second (MB / s) scale. A low-density wiring structure 10 with a relatively large L / S (e.g., about 10 μm / about 10 μm or greater L / S) enables medium-to-low bandwidth electrical transmission between the device 21 and an external PCB. The substrate 2S of the semiconductor package device 1, which includes multi-density wiring structures (e.g., a first medium-density wiring structure 11, a high-density wiring structure 12, and a low-density wiring structure 10), is compatible with dies (e.g., a first die 16, a second die 17, and a third die 18) and the device 21, respectively, operating at different bandwidths.

[0065] Figure 4 A top view illustrating a semiconductor packaging apparatus 3 according to some embodiments of the present disclosure. Figure 5 Explanation along Figure 4 The semiconductor packaging device 3 is a cross-sectional view taken along line 5-5. The semiconductor packaging device 3 is similar to... Figure 1 and Figure 2 The semiconductor packaging device 1 differs from the semiconductor packaging device 3 in that the substrate 3S of the semiconductor packaging device 3 additionally includes a plurality of through-holes 31 disposed on the low-density wiring structure 10 and extending through the dielectric layer 13. For example... Figure 5 As shown, each of the through-vias 31 has a first surface 311 facing away from the low-density wiring structure 10 and a second surface 312 facing the low-density wiring structure 10. Each of the through-vias 31 has a tapered profile. For example, the portion of each of the through-vias 31 adjacent to the second surface 312 is wider than the other portion adjacent to the first surface 311. The third die 18 includes a plurality of conductive pads 183 electrically connected to the through-vias 31 via a plurality of fifth connection elements 30. Each of the through-vias 31 is disposed directly beneath the third die 18 and electrically connected to the low-density wiring structure 10. Therefore, the substrate 3S with the through-vias 31 provides a direct transport path between the third die 18 and the low-density wiring structure 10.

[0066] Figure 6A top view illustrating a semiconductor packaging device 4 according to some embodiments of the present disclosure. Figure 7 Explanation along Figure 6 The semiconductor packaging device 4 is a cross-sectional view taken along line 7-7. The semiconductor packaging device 4 is similar to... Figure 1 and Figure 2 The semiconductor packaging device 1 differs from the semiconductor packaging device 4 in that the substrate 4S of the semiconductor packaging device 4 additionally includes a second medium-density wiring structure 41 disposed on a low-density wiring structure 10. The second medium-density wiring structure 41 is disposed between a first medium-density wiring structure 11 and a high-density wiring structure 12. The second medium-density wiring structure 41 is electrically connected to the low-density wiring structure 10. The second medium-density wiring structure 41 includes a dielectric structure 411, a first circuit layer 412, a second circuit layer 413, and a third circuit layer 414. The second medium-density wiring structure 41 has a first surface 4101 facing away from the low-density wiring structure 10, a second surface 4102 facing the low-density wiring structure 10, and a side surface 4103 extending between the first surface 4101 and the second surface 4102. The first circuit layer 412, which includes a plurality of conductive pads, is adjacent to the first surface 4101. The second circuit layer 413, which includes a plurality of conductive pads, is adjacent to the second surface 4102. The first circuit layer 412, the second circuit layer 413, and the third circuit layer 414 are embedded in the dielectric structure 411. The first circuit layer 412 is electrically connected to the second circuit layer 413 via the third circuit layer 414. The first circuit layer 412 or the third circuit layer 414 may also be referred to as a "medium-density circuit layer". In some embodiments, the line width / line spacing (line spacing, L / S) of the first circuit layer 412 and the third circuit layer 414 may be equal to or greater than the line width / line spacing of the circuit layers (e.g., the first circuit layer 112 and the third circuit layer 114) of the first medium-density wiring structure 11.

[0067] like Figure 7 As shown, the third die 18 includes a plurality of conductive pads 184 electrically connected to the second medium-density wiring structure 41 via a sixth plurality of connection elements 40. The substrate 4S having the second medium-density wiring structure 41 provides a direct transmission path between the third die 18 and the low-density wiring structure 10. For example, the second medium-density wiring structure 41 transmits input / output signals, power signals, or ground signals between the third die 18 and the low-density wiring structure 10.

[0068] In some embodiments, the material of the dielectric structure 411 may include, but is not limited to, molding materials, epoxy materials, Ajinomoto deposited film (ABF), or other suitable organic materials. In some embodiments, the materials of the first circuit layer 412, the second circuit layer 413, and the third circuit layer 414 of the second medium-density wiring structure 41 may each include one or more metals, such as copper (Cu), gold (Au), aluminum (Al), titanium (Ti), etc.

[0069] Figure 8 Description of some embodiments according to this disclosure Figure 2 An enlarged cross-sectional view of an example of a portion of the first medium-density wiring structure 11 of a semiconductor packaging device 1. The third circuit layer 114 may include a first metal layer 51, a second metal layer 52, a third metal layer 53, and a fourth metal layer 54. Furthermore, the third circuit layer 114 may additionally include at least one first conductive via 61, at least one second conductive via 62, at least one third conductive via 63, and at least one fourth conductive via 64. The first circuit layer 112 is electrically connected to the first metal layer 51 through the first conductive via 61. In some embodiments, the first circuit layer 112 and the first conductive via 61 may be integrally formed and simultaneously. Furthermore, the first metal layer 51 is electrically connected to the third metal layer 53 through the second conductive via 62. In some embodiments, the first metal layer 51 and the second conductive via 62 may be integrally formed and simultaneously. Furthermore, the third metal layer 53 is electrically connected to the second circuit layer 113 through the third conductive via 63. In some embodiments, the third metal layer 53 and the third conductive via 63 may be integrally formed and simultaneously. Furthermore, the fourth metal layer 54 is electrically connected to the second circuit layer 113 through the fourth conductive via 64. In some embodiments, the fourth metal layer 54 and the fourth conductive via 64 may be formed integrally and simultaneously.

[0070] The first metal layer 51 and the third metal layer 53 can be used to transmit data signals, so they are also referred to as transmission layers. For example, the first metal layer 51 may be a patterned layer containing a plurality of traces 511 or pads. The traces 511 may be isolated from each other by a first space S1 that may be filled with a dielectric material. The L / S ratio of the traces 511 of the first metal layer 51 may be in the range of about 2 μm / about 2 μm to about 10 μm / about 10 μm or equal to about 5 μm / about 5 μm. Furthermore, the third metal layer 53 may be a patterned layer containing a plurality of traces 531 or pads. The L / S ratio of the traces 531 of the third metal layer 53 may be in the range of about 2 μm / about 2 μm to about 10 μm / about 10 μm or equal to about 5 μm / about 5 μm.

[0071] A second metal layer 52 is disposed below a first metal layer 51. A fourth metal layer 54 is disposed below a third metal layer 53. The second metal layer 52 and the fourth metal layer 54 may be power / ground planes providing power / ground, and are therefore also referred to as power / ground layers. Furthermore, the second metal layer 52 may be a patterned layer comprising a plurality of metal blocks 521. A first gap G1 is located between the metal blocks 521. A first space S1 may be directly above the first gap G1. The first space S1 may be substantially aligned with the first gap G1 in the Z direction. Alternatively, the area of ​​the second metal layer 52 may completely cover one or more traces 511 of the first metal layer 51 in the Z direction. In some embodiments, the area of ​​the fourth metal layer 54 may completely cover one or more traces 531 of the third metal layer 53 in the Z direction. In some embodiments, the power / ground layer may be a solid metal layer or a blanket-covered metal layer, and therefore the first gap G1 may not be present.

[0072] Figure 9A Description of some embodiments according to this disclosure Figure 2 A top view of an example of the transport layer of the first medium-density wiring structure 11 of a semiconductor package device 1. Figure 9A As shown, the transport layer (e.g., the first metal layer 51) may be a patterned layer containing multiple traces (e.g., multiple traces 511). In some embodiments, the third metal layer 53 may be similar to... Figure 9A The patterned layer of the transport layer shown.

[0073] Figure 9B Description of some embodiments according to this disclosure Figure 2 A top view of an example of the transport layer of the first medium-density wiring structure 11 of a semiconductor package device 1. Figure 9B As shown, the transmission layer (e.g., a first metal layer 51) may be a patterned layer comprising multiple traces (e.g., multiple traces 511) and a grid-patterned portion 512 surrounding the traces 511. The grid-patterned portion 512 may transmit ground signals or power signals to a ground layer beneath the transmission layer via multiple vias. For example, the density of the total area of ​​the metal portions in a unit region of the grid-patterned portion 512 may be in the range of about 20% to about 60%. In some embodiments, the third metal layer 53 may be similar to... Figure 9B The patterned layer of the transport layer shown.

[0074] Figure 10A Description of some embodiments according to this disclosure Figure 2 A top view of an example of the power / ground layer of the first medium-density wiring structure 11 of a semiconductor package device 1. Figure 10AAs shown, the power / ground layer (e.g., the second metal layer 52 and the fourth metal layer 54) has a reverse dot patterned portion 52'. The reverse dot patterned portion 52' can transmit a ground signal or a power signal. The reverse dot patterned portion 52' may include a solid metal portion 521 and define a plurality of through-holes 522 extending through the solid metal portion 521. In some embodiments, a dielectric material may be disposed within the plurality of through-holes 522. For example, the ratio of the area of ​​the solid metal portion 521 to the total area of ​​the reverse dot patterned portion 52' may be in the range of about 40% to about 80%.

[0075] Figure 10B Description of some embodiments according to this disclosure Figure 2 A top view of an example of the power / ground layer of the first medium-density wiring structure 11 of a semiconductor package device 1. Figure 10B As shown, the power / ground layers (e.g., the second metal layer 52 and the fourth metal layer 54) have a grid-patterned portion 52". The grid-patterned portion 52" can transmit ground signals or power signals. The grid-patterned portion 52" may contain a plurality of metal blocks spaced apart from each other and arranged in an array. For example, the density of the total area of ​​the metal portions (i.e., metal blocks) in a unit area of ​​the grid-patterned portion 52" may be in the range of about 20% to about 60%.

[0076] Figure 10C Description of some embodiments according to this disclosure Figure 2 A top view of an example of the power / ground layer of the first medium-density wiring structure 11 of a semiconductor package device 1. Figure 10C As shown, the grounding layer (e.g., the second metal layer 52 and the fourth metal layer 54) has a grid-patterned portion 52” and a reverse dot-patterned portion 52' surrounded by the grid-patterned portion 52”. The grid-patterned portion 52” and the reverse dot-patterned portion 52' can each transmit a ground signal or a power signal. For example, the density of the total area of ​​the metal portion (i.e., metal block) of the grid-patterned portion 52” in a unit area can be between about 20% and about 60%. For example, the ratio of the area of ​​the solid metal portion 521 to the total area of ​​the reverse dot-patterned portion 52' can be between about 40% and about 80%. In some embodiments, from a top view, the total area of ​​the metal portions of the reverse dot patterned portion 52' in a unit area is greater than the total area of ​​the metal portions of the grid patterned portion 52" in an equal unit area. The relatively low density of the grid patterned portion 52" (or the relatively large total area of ​​the metal portions in a unit area) can improve the warping of the first medium-density wiring structure 11.

[0077] Figure 11 Description of some embodiments according to this disclosureFigure 2 An enlarged cross-sectional view of an example of a portion of the high-density wiring structure 12 of a semiconductor packaging device 1. The third circuit layer 124 may include a first metal layer 71, a second metal layer 72, a third metal layer 73, and a fourth metal layer 74. Furthermore, the third circuit layer 124 may additionally include at least one first conductive via 81, at least one second conductive via 82, at least one third conductive via 83, and at least one fourth conductive via 84. The first circuit layer 122 is electrically connected to the first metal layer 71 through the first conductive via 81. In some embodiments, the first circuit layer 122 and the first conductive via 81 may be integrally formed and simultaneously. Furthermore, the first metal layer 71 is electrically connected to the third metal layer 73 through the second conductive via 82. In some embodiments, the first metal layer 71 and the second conductive via 82 may be integrally formed and simultaneously. Furthermore, the third metal layer 73 is electrically connected to the second circuit layer 123 through the third conductive via 83. In some embodiments, the third metal layer 73 and the third conductive via 83 may be integrally formed and simultaneously. Furthermore, the fourth metal layer 74 is electrically connected to the second circuit layer 123 through the fourth conductive via 84. In some embodiments, the fourth metal layer 74 and the fourth conductive via 84 may be formed integrally and simultaneously.

[0078] The first metal layer 71 and the third metal layer 73 can be used to transmit data signals, thus they are also referred to as transmission layers. For example, the first metal layer 71 may be a patterned layer containing a plurality of traces 711 or pads. The traces 711 may be isolated from each other by a second space S2 that may be filled with a dielectric material. The L / S ratio of the traces 711 of the first metal layer 71 may be equal to or less than about 2 μm / about 2 μm. Furthermore, the third metal layer 73 may be a patterned layer containing a plurality of traces 731 or pads. The L / S ratio of the traces 731 of the third metal layer 73 may be equal to or less than about 2 μm / about 2 μm.

[0079] A second metal layer 72 is disposed below a first metal layer 71. A fourth metal layer 74 is disposed below a third metal layer 73. The second metal layer 72 and the fourth metal layer 74 may be power / ground planes providing power / ground, and are therefore also referred to as power / ground layers. Furthermore, the second metal layer 72 may be a patterned layer comprising a plurality of metal blocks 721. A second gap G2 is located between the metal blocks 721. A second space S2 may be directly above the second gap G2. The second space S2 may be substantially aligned with the second gap G2 in the Z direction. Alternatively, the area of ​​the second metal layer 72 may completely cover one or more traces 711 of the first metal layer 71 in the Z direction. In some embodiments, the area of ​​the fourth metal layer 74 may completely cover one or more traces 731 of the third metal layer 73 in the Z direction. In some embodiments, the power / ground layer may be a solid metal layer or a blanket-covered metal layer, and therefore the second gap G2 may not be present.

[0080] Figure 12A Description of some embodiments according to this disclosure Figure 2 A top view of an example of the transport layer of the high-density wiring structure 12 of a semiconductor packaging device 1. (See attached image.) Figure 12A As shown, the transport layer (e.g., the first metal layer 71) may be a patterned layer containing multiple traces (e.g., multiple traces 711). In some embodiments, the third metal layer 73 may be similar to... Figure 12A The patterned layer of the transport layer shown.

[0081] Figure 12B Description of some embodiments according to this disclosure Figure 2 A top view of an example of the transport layer of the high-density wiring structure 12 of a semiconductor packaging device 1. (See attached image.) Figure 12B As shown, the transmission layer (e.g., a first metal layer 71) may be a patterned layer comprising multiple traces (e.g., multiple traces 711) and a grid-patterned portion 712 surrounding the traces 711. The grid-patterned portion may transmit ground signals or power signals to a ground layer beneath the transmission layer via multiple vias. The density of the total area of ​​the metal portions in a unit area of ​​the grid-patterned portion may be in the range of about 20% to about 60%. In some embodiments, the third metal layer 73 may be similar to... Figure 12B The patterned layer of the transport layer shown.

[0082] Figure 13A Description of some embodiments according to this disclosure Figure 2 A top view of an example of the ground layer of the high-density wiring structure 12 of a semiconductor packaging device 1. (See attached image.) Figure 13A As shown, the power / ground layer (e.g., the second metal layer 72 and the fourth metal layer 74) has a reverse dot patterned portion 72'. The reverse dot patterned portion 72' can transmit a ground signal or a power signal. The reverse dot patterned portion 72' may include a solid metal portion 721 and define a plurality of through-holes 722 extending through the solid metal portion 721. In some embodiments, a dielectric material may be disposed within the plurality of through-holes 722. For example, the ratio of the area of ​​the solid metal portion 721 to the total area of ​​the reverse dot patterned portion 72' may be in the range of about 60% to about 100%.

[0083] Figure 13B Description of some embodiments according to this disclosure Figure 2 A top view of an example of the ground layer of the high-density wiring structure 12 of a semiconductor packaging device 1. (See attached image.) Figure 13BAs shown, the grounding layer (e.g., the second metal layer 72 and the fourth metal layer 74) has a grid-patterned portion 72". The grid-patterned portion 72" can transmit ground signals or power signals. The grid-patterned portion 72" may contain a plurality of metal blocks spaced apart from each other and arranged in an array. For example, the density of the total area of ​​the metal portions (i.e., metal blocks) in a unit region of the grid-patterned portion 72" may be in the range of about 20% to about 60%.

[0084] Figure 13C Description of some embodiments according to this disclosure Figure 2 A top view of an example of the ground layer of the high-density wiring structure 12 of a semiconductor packaging device 1. (See example...) Figure 13C As shown, the grounding layer (e.g., the second metal layer 72 and the fourth metal layer 74) has a grid-patterned portion 72" and a reverse dot-patterned portion 72' surrounded by the grid-patterned portion 72". The grid-patterned portion 72" and the reverse dot-patterned portion 72' can each transmit a ground signal or a power signal. For example, the density of the total area of ​​the metal portions (i.e., metal blocks) in a unit area of ​​the grid-patterned portion can be between about 20% and about 60%. For example, the ratio of the area of ​​the solid metal portion 721 to the total area of ​​the reverse dot-patterned portion 72' can be between about 60% and about 100%. The relatively low density of the grid-patterned portion 72" can improve the warpage of the high-density wiring structure 12.

[0085] Figure 14A Description of some embodiments according to this disclosure Figure 7 A top view of an example of the ground layer of the second medium-density wiring structure 41 of the semiconductor package device 4. (See attached image.) Figure 14A As shown, the grounding layer has brick-shaped patterned portions. For example, the density of the total area of ​​the metal portions in a unit area of ​​the brick-shaped patterned portion can be in the range of about 20% to about 60%.

[0086] Figure 14B Description of some embodiments according to this disclosure Figure 7 A top view of an example of the ground layer of the second medium-density wiring structure 41 of the semiconductor package device 4. (See attached image.) Figure 14B As shown, the grounding layer has a grid-patterned portion. For example, the density of the total area of ​​the metal portions in a unit area of ​​the grid-patterned portion can be in the range of about 20% to about 60%.

[0087] Figure 14C Description of some embodiments according to this disclosure Figure 7 A top view of an example of the transport layer of the second medium-density wiring structure 41 of the semiconductor package device 4. (See attached image.) Figure 14CAs shown, the transmission layer of the second medium-density wiring structure 41 includes a blanket-covered portion 415 and a plurality of vias 416. The material of the blanket-covered portion 415 may include a dielectric material. The material of the vias 416 may include one or more metals, such as copper (Cu), gold (Au), aluminum (Al), titanium (Ti), etc.

[0088] Figures 15 to 29 This invention describes a method for manufacturing a semiconductor packaging apparatus according to some embodiments of the present disclosure. In some embodiments, the method is used for manufacturing... Figure 2 The substrate 1S and / or shown in the figure Figure 2 The semiconductor packaging device 1 shown in the figure.

[0089] refer to Figure 15 A carrier 90 is provided. The carrier 90 has a release layer 91 formed thereon. (Reference) Figure 16 A first medium-density wiring structure 11 is attached to a carrier 90 via a release layer 91. The first medium-density wiring structure 11 has a first surface 1101 facing the carrier 90 and a second surface 1102 facing away from the carrier 90. Furthermore, a high-density wiring structure 12 is attached to the carrier 90 via the release layer 91. The high-density wiring structure 12 has a first surface 1201 facing the carrier 90 and a second surface 1202 facing away from the carrier 90. The high-density wiring structure 12 and the first medium-density wiring structure 11 are arranged side-by-side. Before the high-density wiring structure 12 is attached to the carrier 90, a conductive post 15 is formed on the second surface 1202 of the high-density wiring structure 12. The conductive post 15 has a first surface 1501 facing the high-density wiring structure 12 and a second surface 1502 facing away from the high-density wiring structure 12. Figure 16 As shown by the reference dashed line, the second surface 1502 of the conductive pillar 15 and the second surface 1102 of the first medium-density wiring structure 11 are substantially coplanar.

[0090] refer to Figure 17 The dielectric layer 13 is formed onto the carrier 90 by, for example, a molding process followed by a polishing process. A first medium-density wiring structure 11 and / or a high-density wiring structure 12 are embedded within the dielectric layer 13. The dielectric layer 13 has a first surface 1301 facing the carrier 90 and a second surface 1302 facing away from the carrier 90. The dielectric layer 13 has a first height H1, and the first medium-density wiring structure 11 has a second height H2 different from the first height H1. In some embodiments, the first height H1 is greater than the second height H2.

[0091] refer to Figure 18The dielectric layer 13 is patterned to form a first opening 131. The first opening 131 is substantially aligned with and exposes the conductive pillar 15. Furthermore, the dielectric layer 13 is patterned to form a second opening 132. The second opening 132 is substantially aligned with and exposes the second circuit layer 113 of the first medium-density wiring structure 11.

[0092] refer to Figure 19 The conductive layer 92 is formed on the second surface 1302 of the dielectric layer 13 and is located within the first opening 131 and the second opening 132.

[0093] refer to Figure 20 The conductive layer 92 is patterned to form an opening 921. The patterned conductive layer 92 is indicated as follows: Figure 21 The first circuit layer 102 shown.

[0094] refer to Figure 21 An insulating material 93 is formed to cover the first circuit layer 102.

[0095] refer to Figure 22 The patterned insulating material 93 forms an opening 931 in a planar region of the insulating material 93. The patterned insulating material 93 is indicated as follows: Figure 23 The insulating layer 101 shown.

[0096] refer to Figure 23 A conductive layer 94 is formed on the insulating layer 101. In some embodiments, a portion of the conductive layer 94 may contact the first circuit layer 102.

[0097] refer to Figure 24 The conductive layer 94 is patterned to form openings 941 in planar regions of the conductive layer 94. The patterned conductive layer 94 is indicated as follows: Figure 25 The second circuit layer 103 is shown in the figure.

[0098] refer to Figure 25 A protective material 95 is formed to cover the second circuit layer 103.

[0099] refer to Figure 26 The patterned protective material 95 forms a plurality of openings 105. The openings 105 expose portions of the second circuit layer 103. The patterned protective material 95 is indicated as follows: Figure 26 The protective layer 104 is shown. (Reference) Figure 26 The insulating layer 101, the first circuit layer 102, the second circuit layer 103, and the protective layer 104 together indicate as follows: Figure 2The low-density wiring structure 10 is described herein. The low-density wiring structure 10 is formed on a first medium-density wiring structure 11 and a high-density wiring structure 12. In some embodiments, the line spacing of the circuit layer of the low-density wiring structure 10 is greater than the line spacing of the circuit layer of the first medium-density wiring structure 11, and the line spacing of the circuit layer of the first medium-density wiring structure 11 is greater than the line spacing of the circuit layer of the high-density wiring structure 12.

[0100] like Figure 27 As shown, the carrier 90 and the release layer 91 are removed. The first surface 1101 of the first medium-density wiring structure 11, the first surface 1201 of the high-density wiring structure 12, and the first surface 1301 of the dielectric layer 13 are exposed and are substantially coplanar.

[0101] refer to Figure 28 A protective layer 14 is formed on the first medium-density wiring structure 11, the high-density wiring structure 12, and the dielectric layer 13 and is patterned to form a plurality of openings 141, thereby exposing the first surface 1101 of the first medium-density wiring structure 11 and / or the first surface 1201 of the high-density wiring structure 12. Figure 28 As shown, the low-density wiring structure 10, the first medium-density wiring structure 11, the high-density wiring structure 12, the dielectric layer 13, the protective layer 14, and the conductive pillars 15 together indicate as follows: Figure 2 The substrate 1S described herein.

[0102] refer to Figure 29 A first die 16 is attached to a substrate 1S via a plurality of first connecting elements 19. A second die 17 is attached to the substrate 1S via a plurality of second connecting elements 19'. A third die 18 is attached to the substrate 1S near the first die 16 via a plurality of third connecting elements 20 and / or a plurality of fourth connecting elements 20'. In some embodiments, the first die 16, the second die 17, and the third die 18 may be attached sequentially or in a single step. Since the first surface 1101 of the first medium-density wiring structure 11, the first surface 1201 of the high-density wiring structure 12, and the first surface 1301 of the dielectric layer 13 are substantially coplanar, the yield of the die attachment process can be improved. In some embodiments, fewer than three or more dies may be attached to the substrate 1S. Figure 29 After the steps, a singulation process is performed to form Figure 2 The semiconductor packaging device 1 shown in the figure.

[0103] Figure 30 This describes one or more stages of an example of a method for manufacturing a semiconductor packaging apparatus according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 3 The substrate 2S and / or shown in the figure Figure 3The semiconductor packaging device 2 is shown in the diagram. The initial stage of the process described is related to... Figures 15 to 16 The stages described herein are the same or similar. Figure 30 Depicted in Figure 16 The stage following the stage described in the text.

[0104] refer to Figure 30 The device 21 is attached to the carrier 90 via a spacer 22 and an adhesive layer 23. In some embodiments, it may be... Figure 16 The attachment device 21 is attached prior to the stage. Device 21 has a surface 2101 facing away from the carrier 90. The surface 2101 of device 21, the second surface 1102 of the first medium-density wiring structure 11, and the second surface 1202 of the high-density wiring structure 12 are substantially coplanar. Then, execution is possible. Figures 17 to 29 One or more stages and individual processes to form Figure 3 The semiconductor packaging device 2 with substrate 2S is shown in the figure.

[0105] Figure 31 and Figure 5 This describes one or more stages of an example of a method for manufacturing a semiconductor packaging apparatus according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing... Figure 5 The substrate 3S and / or shown in the figure Figures 15 to 17 The semiconductor packaging device 3 is shown in the diagram. The initial stage of the process described is related to... Figure 31 The stages described herein are the same or similar. Figure 17 Depicted in Figure 31 The stage following the stage described in the text.

[0106] refer to Figure 17 In similar Figure 17 Following the initial stage, the dielectric layer 13 is patterned to form a plurality of openings 133, wherein the difference lies in the distance between the first medium-density wiring structure 11 and the high-density wiring structure 12 being greater than [missing information]. Figure 32 The distance in the middle. The plurality of openings 33 extend through the dielectric layer 13 and are disposed between the first medium-density wiring structure 11 and the high-density wiring structure 12.

[0107] refer to Figures 18 to 29 Multiple through-holes 31 are formed in multiple openings 33 by, for example, electroplating followed by polishing. Then, it is possible to perform... Figure 5 One or more stages and individual processes to form Figure 33 The semiconductor packaging device 3 shown in the figure has a substrate 3S.

[0108] Figure 7This describes one or more stages of an example of a method for manufacturing a semiconductor packaging apparatus according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing... Figure 7 The substrate 4S and / or shown in the image Figure 15 The semiconductor packaging device 4 shown in the image illustrates the initial stage of the process and... Figure 33 The stages described herein are the same or similar. Figure 15 Depicted in Figure 33 The stage following the stage described in the text.

[0109] refer to Figures 17 to 29 The first medium-density wiring structure 11, the high-density wiring structure 12, and the second medium-density wiring structure 41 are attached to the carrier 90 sequentially or in a single step via a release layer 91. The second medium-density wiring structure 41 has a first surface 4101 facing the carrier 90 and a second surface 1402 facing away from the carrier 90. In some embodiments, the second surface 1402 of the second medium-density wiring structure 41 and the second surface 1102 of the first medium-density wiring structure 11 are substantially at the same height. Then, it is possible to perform... Figure 7 One or more stages and individual processes to form ​ The semiconductor packaging device 4 with substrate 4S is shown in the image.

[0110] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “on top,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangements.

[0111] As used herein, the terms “approximately,” “basically,” “about,” and “approximately” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same or equal.

[0112] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0113] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators.

[0114] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit very little or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes change with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0115] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0116] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this invention and the actual apparatus. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A substrate comprising: A high-density wiring structure comprising a dielectric structure and multiple circuit layers embedded in the dielectric structure, wherein the high-density wiring structure is composed of multiple layers of organic material stacked from the bottom to the top. Dielectric layer, encapsulating the high-density wiring structure; A low-density wiring structure is disposed under the dielectric layer and electrically connected to the high-density wiring structure, wherein the line spacing of the circuit layer of the low-density wiring structure is greater than the line spacing of multiple circuit layers of the high-density wiring structure. and A first medium-density wiring structure includes a dielectric structure and a plurality of circuit layers embedded in the dielectric structure. The first medium-density wiring structure is formed by stacking multiple layers of organic material from bottom to top. The line spacing of the circuit layers in the low-density wiring structure is greater than the line spacing of the plurality of circuit layers in the first medium-density wiring structure, and the line spacing of the plurality of circuit layers in the first medium-density wiring structure is greater than the line spacing of the plurality of circuit layers in the high-density wiring structure. The dielectric layer further encapsulates the first medium-density wiring structure, and the low-density wiring structure is further electrically connected to the first medium-density wiring structure.

2. The substrate according to claim 1, wherein the top surface of the dielectric layer and the top surface of the high-density wiring structure are substantially coplanar, the height of the dielectric layer is greater than the height of the high-density wiring structure, wherein the circuit layer of the low-density wiring structure is located in an opening of the dielectric layer to electrically connect to the high-density wiring structure.

3. A semiconductor packaging apparatus, comprising: Substrate, comprising: Low-density wiring structure, which includes an insulating layer and a circuit layer; A first medium-density wiring structure includes a first dielectric structure and a first circuit layer, wherein the first medium-density wiring structure is electrically connected to the low-density wiring structure. A high-density wiring structure includes a second dielectric structure and a second circuit layer, wherein the high-density wiring structure is electrically connected to the low-density wiring structure, and wherein the high-density wiring structure and the first medium-density wiring structure are arranged side by side. The line spacing of the circuit layers in the low-density wiring structure is greater than that of the circuit layers in the first medium-density wiring structure, and the line spacing of the circuit layers in the first medium-density wiring structure is greater than that of the circuit layers in the high-density wiring structure; and A first die is disposed on the substrate, wherein the first die is directly electrically connected to the high-density wiring structure and the first medium-density wiring structure; A second die, disposed on the substrate, wherein the second die is directly electrically connected to the high-density wiring structure; and A dielectric layer disposed on the low-density wiring structure, wherein the dielectric layer does not include fibers, wherein the dielectric layer encapsulates and contacts the side surfaces of the first medium-density wiring structure and the side surfaces of the high-density wiring structure, and the dielectric layer encapsulates and contacts the bottom surface of the first medium-density wiring structure and the bottom surface of the high-density wiring structure. The top surfaces of the first die and the second die are substantially coplanar.

4. The semiconductor packaging apparatus of claim 3, further comprising a third die disposed on the substrate, wherein the third die is directly electrically connected to the first medium-density wiring structure, wherein the top surface of the first die and the top surface of the third die are substantially coplanar.

5. The semiconductor packaging apparatus of claim 3, further comprising a protective layer disposed on and in contact with the top surface of the first medium-density wiring structure, the top surface of the high-density wiring structure and the top surface of the dielectric layer, the protective layer completely covering the top surface of the dielectric layer.

6. The semiconductor packaging apparatus of claim 5, wherein the protective layer defines a plurality of openings to expose a portion of the top surface of the first medium-density wiring structure and a portion of the top surface of the high-density wiring structure.

7. A method for manufacturing a semiconductor packaging device, comprising: Provide a carrier; The high-density wiring structure and the first medium-density wiring structure are attached side by side to the carrier; A dielectric layer is formed on the carrier to encapsulate the high-density wiring structure and the first medium-density wiring structure; Pattern the dielectric layer; A low-density wiring structure is formed on the dielectric layer, the first medium-density wiring structure, and the high-density wiring structure. The line spacing of the circuit layer in the low-density wiring structure is greater than that of the circuit layer in the first medium-density wiring structure, and the line spacing of the circuit layer in the first medium-density wiring structure is greater than that of the circuit layer in the high-density wiring structure. Remove the carrier to form a substrate comprising the dielectric layer, the low-density wiring structure, the first medium-density wiring structure, and the high-density wiring structure; and The first die is bonded to the substrate.

8. The method of claim 7, wherein patterning the dielectric layer comprises: The dielectric layer is patterned to form a second opening and expose the second circuit layer of the first medium-density wiring structure.

9. The method according to claim 7, further comprising: Conductive pillars are formed on the surface of the high-density wiring structure. The dielectric layer is patterned to form a first opening and expose the conductive pillar.

10. The method of claim 9, wherein the circuit layer of the low-density wiring structure is located in an opening in the dielectric layer to contact the conductive post.

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