Semiconductor package including a package substrate having staggered bonding fingers

Abstract

A semiconductor package including a package substrate having staggered bonding fingers. A semiconductor package includes: a package substrate including a first bonding finger array and a second bonding finger array, each of the first bonding finger array and the second bonding finger array being arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bonding finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bonding finger array; first bonding wires connecting bonding fingers of the first bonding finger array to chip pads of the first chip pad array; and second bonding wires connecting bonding fingers of the second bonding finger array to chip pads of the second chip pad array.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor packages, and more particularly, to a semiconductor package including a package substrate having bonding fingers staggered along a direction. Background Art

[0002] Generally, a semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The semiconductor chip may be electrically connected to the package substrate through connection means such as bumps or bonding wires.

[0003] Recently, in response to the push toward lighter and shorter package products, research has been conducted on the structures of package substrates and semiconductor chips to efficiently arrange a plurality of circuit patterns within a limited area. Summary of the invention

[0004] A semiconductor package according to an embodiment of the present disclosure may include: a package substrate including a first bonding finger array and a second bonding finger array, each of the first bonding finger array and the second bonding finger array being arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bonding finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bonding finger array; a first bonding wire connecting the bonding fingers of the first bonding finger array to the chip pads of the first chip pad array; and a second bonding wire connecting the bonding fingers of the second bonding finger array to the chip pads of the second chip pad array. The bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array at least partially overlap each other along the first direction.

[0005] According to another embodiment of the present disclosure, a semiconductor package may include: a packaging substrate, which includes a first bonding finger array and a second bonding finger array arranged along a first line and a second line in a first direction on a surface of the packaging substrate, respectively; a first semiconductor chip, which includes a first chip pad array on the surface of the packaging substrate corresponding to the first bonding finger array and arranged to be closer to the second bonding finger array than the first bonding finger array; a second semiconductor chip, which includes a second chip pad array on the surface of the packaging substrate corresponding to the second bonding finger array and arranged to be closer to the first bonding finger array than the second bonding finger array; a first bonding lead connecting the bonding fingers of the first bonding finger array to the chip pads of the first chip pad array; a second bonding lead connecting the bonding fingers of the second bonding finger array to the chip pads of the second chip pad array; a first trace pattern electrically connecting the bonding fingers of the first bonding finger array to the first wiring of the packaging substrate on the surface of the packaging substrate; and a second trace pattern electrically connecting the bonding fingers of the second bonding finger array to the second wiring of the packaging substrate on the surface of the packaging substrate. The bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array are staggered along a first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view schematically showing a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 2 and Figure 3 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 4 yes Figure 3 An enlarged view of area A1.

[0009] Figure 5 is a plan view of a semiconductor package according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] The terms used herein may correspond to words selected considering their functions in the embodiments presented, and the meaning of the terms may be interpreted as being different according to the ordinary technicians in the field to which the embodiments belong. If defined in detail, the terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings commonly understood by ordinary technicians in the field to which the embodiments belong. In the description of the embodiments of the present disclosure, descriptions such as "first" and "second", "upper" and "lower", and "left" and "right" are to distinguish components, rather than to limit the components themselves or to mean a specific order.

[0011] The semiconductor chip described herein may include a semiconductor substrate integrated with an electronic circuit cut into a form of a die. The semiconductor chip may correspond to a memory chip, a logic chip (including an application-specific integrated circuit (ASIC) chip) or a system chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND flash memory circuit, a NOR flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include a logic circuit integrated on a semiconductor substrate. The semiconductor chip may be referred to as a semiconductor die according to its shape after the dicing process.

[0012] In this specification, a semiconductor package may include a package substrate on which a semiconductor chip is mounted. The package substrate may include at least one layer of integrated circuit patterns and may be referred to as a printed circuit board (PCB) in this specification. The semiconductor package may include a plurality of semiconductor chips stacked on the package substrate.

[0013] Semiconductor packages may be used in various communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems.

[0014] Throughout the specification, the same reference numerals may denote the same elements. Even if a reference numeral is not mentioned or described with reference to one figure, the reference numeral may be mentioned or described with reference to another figure. In addition, even if a reference numeral is not shown in one figure, it may be mentioned or described with reference to another figure.

[0015] In this specification, a Cartesian coordinate system having xyz axes perpendicular to each other is used to illustrate a semiconductor package. In this case, the X direction may refer to a direction parallel to the X axis. Similarly, the Y direction and the Z direction may refer to a direction parallel to the Y axis and a direction parallel to the Z axis, respectively.

[0016] Figure 1 is a cross-sectional view schematically showing a semiconductor package 1a according to an embodiment of the present disclosure. Figure 1 , the semiconductor package 1a may include a package substrate 100, a first semiconductor chip 200 disposed on the package substrate 100, and a second semiconductor chip 300 disposed to be spaced apart from the first semiconductor chip 200 in a lateral direction. The first semiconductor chip 200 and the second semiconductor chip 300 may be isomorphic chips or heterogeneous chips. The first semiconductor chip 200 and the second semiconductor chip 300 may be electrically connected to the package substrate 100 by wire bonding, respectively.

[0017] The package substrate 100 may include a substrate main body portion 110. The substrate main body portion 110 may include an upper surface 110S1 and a lower surface 110S2 opposite to the upper surface 110S1. The first bonding finger array 120 and the second bonding finger array 130 may be respectively arranged in a line along a first direction (i.e., Y direction) between the first semiconductor chip 200 and the second semiconductor chip 300 on the upper surface 110S1 of the substrate main body portion 110. That is, on the upper surface 110S1 of the substrate main body portion 110, the first bonding finger array 120 may be arranged along a first line in the Y direction and the second bonding finger array 130 may be arranged along a second line in the Y direction. Although not shown, each of the first bonding finger array 120 and the second bonding finger array 130 may include a plurality of bonding fingers. As will be described later in conjunction with Figures 2 to 4 As described above, the bonding fingers of the first bonding finger array 120 and the bonding fingers of the second bonding finger array 130 may be arranged to be spaced apart from each other. In addition, the bonding fingers of the first bonding finger array 120 and the bonding fingers of the second bonding finger array 130 may be staggered along the first direction (i.e., the Y direction). Here, at least a portion of each bonding finger of the first bonding finger array 120 and a portion of the bonding fingers of the second bonding finger array 130 may overlap along the first direction (i.e., the Y direction).

[0018] Reference Figure 1 , the first trace pattern 122 and the second trace pattern 132 may be disposed on the upper surface 110S1. The first trace pattern 122 may electrically connect the bonding fingers of the first bonding finger array 120 to the first wiring (not shown) of the package substrate 100. Similarly, the second trace pattern 132 may electrically connect the bonding fingers of the second bonding finger array 130 to the second wiring (not shown) of the package substrate 100. The first trace pattern 122 and the second trace pattern 132 may extend to the lower portions of the first semiconductor chip 200 and the second semiconductor chip 300 on the upper surface 110S1, respectively, without being in electrical contact with the first semiconductor chip 200 and the second semiconductor chip 300. That is, although not shown, the first trace pattern 122 and the second trace pattern 132 may extend in a lateral direction (e.g., an X direction) below the first semiconductor chip 200 and the second semiconductor chip 300.

[0019] The first semiconductor chip 200 may be arranged adjacent to the second bonding finger array 130 on the upper surface 110S1. The first semiconductor chip 200 may include a first chip main body 210. The first chip main body 210 may include a plurality of active components and passive components for the operation of the first semiconductor chip 200. As an example, the active component may include at least a field effect transistor. As an example, the passive component may include at least a capacitor or a resistor. The active component and the passive component may be arranged in an inner region of the first chip main body 210 adjacent to the upper surface 210S1. The active component and the passive component may be connected to each other by wiring to form a semiconductor integrated circuit. In addition, the first chip main body 210 may be bonded to the upper surface 110S1 of the substrate main body 110 by the first adhesive layer 410.

[0020] The first chip pad array 220 including a plurality of chip pads may be disposed on the upper surface 210S1 of the first chip body portion 210. The first chip pad array 220 may be disposed on the side of the upper surface 210S1 and may be arranged in a line along the first direction (ie, the Y direction) corresponding to the first bonding finger array 120. Figures 2 to 4 A specific configuration of the first chip pad array 220 is described.

[0021] In addition, the second semiconductor chip 300 may be disposed adjacent to the first bonding finger array 120 on the upper surface 110S1. The second semiconductor chip 300 may include a second chip body portion 310. The second chip body portion 310 may include a plurality of active elements and passive elements for operation of the second semiconductor chip 300. The active elements and passive elements may be disposed in an inner region of the second chip body portion 310 adjacent to the upper surface 310S1. The second chip body portion 310 may be bonded to the upper surface 110S1 of the substrate body portion 110 by a second adhesive layer 420.

[0022] The second chip pad array 320 including a plurality of chip pads may be disposed on the upper surface 310S1 of the second chip body portion 310. The second chip pad array 320 may be disposed on one side of the upper surface 310S1 and may be arranged in a line along the first direction (ie, the Y direction) corresponding to the second bonding finger array 130. Figures 2 to 4 A specific configuration of the second chip pad array 320 is described.

[0023] Reference Figure 1, a first bonding wire 701 is shown, which connects the bonding fingers of the first bonding finger array 120 disposed on the upper surface 110S1 of the substrate main body portion 110 to the chip pads of the first chip pad array 220 disposed on the upper surface 210S1 of the first chip main body portion 210. In addition, a second bonding wire 702 is shown, which connects the bonding fingers of the second bonding finger array 130 disposed on the upper surface 110S1 of the substrate main body portion 110 to the chip pads of the second chip pad array 320 disposed on the upper surface 310S1 of the second chip main body portion 310. As shown below with reference to Figure 2 As described, the first bonding wires 701 and the second bonding wires 702 may be staggered with each other along the first direction (ie, the Y direction).

[0024] In addition, the connection pad 160 may be disposed near the lower surface 110S2 of the substrate body portion 110. Figure 1 As shown, each connection pad 160 may be partially embedded in the substrate main body portion 110, and one surface of the connection pad 160 may be exposed at the lower surface 110S2. However, the present disclosure is not limited thereto, and in other embodiments not shown, the connection pad 160 may be disposed on the lower surface 110S2 of the substrate main body portion 110. A connection structure 180 connected to an external system may be disposed on the connection pad 160. For example, each connection structure 180 may include a solder bump or a solder ball. An external power source or an electrical signal may be input to the connection pad 160 from the external system through the connection structure 180. In addition, a ground potential of an external ground terminal may be provided through the connection structure 180. The external power source or electrical signal input to the connection pad 160 may be transmitted to the bonding fingers of the first bonding finger array 120 and the second bonding finger array 130 through the first wiring and the second wiring (not shown) in the substrate main body portion 110 and the first trace pattern 122 and the second trace pattern 132 on the substrate main body portion 110, respectively. In addition, a ground potential may be provided to the bonding fingers of the first bonding finger array 120 and the second bonding finger array 130. Next, an external power source, an electrical signal, and a ground potential may be transmitted to the chip pads of the corresponding first semiconductor chip 200 and the second semiconductor chip 300 through the first bonding wire 701 and the second bonding wire 702, respectively, and then the first semiconductor chip 200 and the second semiconductor chip 300 may use the external power source and the ground potential or may process an electrical signal.

[0025] Figure 2 and Figure 3 is a plan view of a semiconductor package 1a according to an embodiment of the present disclosure. Specifically, Figure 2 and Figure 3 Can be Figure 1 A plan view of region "A" of the semiconductor package 1a. That is, Figure 2It is shown Figure 1 FIG. 1 is a plan view of a pad arrangement of area “A” of a semiconductor package. Figure 3 yes Figure 2 Illustration of the first bonding wire 701 and the second bonding wire 702 is omitted in the plan view of FIG. Figure 4 yes Figure 3 Hereinafter, for convenience, reference will be made to Figure 3 and Figure 4 The configuration related to the arrangement of the bonding finger array of the package substrate and the chip pad array of the semiconductor chip will be described in detail, and then reference will be made to Figure 2 Configurations related to the arrangement of bonding wires connecting a bonding finger array and a chip pad array are described.

[0026] Reference Figure 3 and Figure 4 , the first bonding finger array 120 and the second bonding finger array 130 may be disposed on the upper surface 110S1 of the substrate main body portion 110. The first bonding finger array 120 and the second bonding finger array 130 may each be arranged in a line along the first direction (ie, the Y direction). Figure 3 As an embodiment, the first bonding finger array 120 may include first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f spaced apart from each other. In addition, the second bonding finger array 130 may include first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f spaced apart from each other at intervals. Although Figure 3 Each of the first bonding finger array 120 and the second bonding finger array 130 is shown to have six bonding fingers, but the disclosure is not necessarily limited thereto. In some embodiments, each of the first bonding finger array 120 and the second bonding finger array 130 may have different and varying numbers of bonding fingers.

[0027] In an embodiment, each of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 may be one of a signal finger, a power finger, and a ground finger. The bonding fingers corresponding to the signal fingers among the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f may be electrically separated from each other. On the other hand, the bonding fingers corresponding to the power fingers among the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f may be electrically connected to each other. Although Figure 3 and Figure 4Although not shown in the figure, the electrical connection of the bonding fingers corresponding to the power fingers can be realized by the first trace pattern 122 and other wirings of the package substrate 100. Similarly, the bonding fingers corresponding to the ground fingers among the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f can be electrically connected to each other. Figure 3 and Figure 4 Not shown in the figure, the electrical connection of the bonding fingers corresponding to the ground fingers may be achieved by the first trace pattern 122 and other wirings of the package substrate 100 .

[0028] In addition, each of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 may be one of a signal finger, a power finger and a ground finger, respectively. The bonding fingers corresponding to the signal fingers among the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f may be electrically separated from each other. On the other hand, the bonding fingers corresponding to the power fingers among the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f may be electrically connected to each other. Similarly, the bonding fingers corresponding to the ground fingers among the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f may be electrically connected to each other.

[0029] Reference Figure 3 and Figure 4 , the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 may be arranged spaced apart from each other on the upper surface 110S1 of the substrate main body portion 110. In addition, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 may be staggered along the first direction (i.e., the Y direction). Referring to Figure 4As an example, the first bonding finger 120a of the first bonding finger array 120 may be disposed between the first bonding finger 130a and the second bonding finger 130b of the second bonding finger array 130 along the first direction (i.e., the Y direction). As another example, the second bonding finger 130b of the second bonding finger array 130 may be disposed between the first bonding finger 120a and the second bonding finger 120b of the first bonding finger array 120 along the first direction (i.e., the Y direction). Figure 3 As described in , the remaining bonding fingers of the first bonding finger array 120 and the second bonding finger array 130 may also be arranged on the upper surface 110S1 of the package substrate 100 in the same manner.

[0030] In an embodiment, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 may be arranged to at least partially overlap each other along the first direction (ie, the Y direction). Figure 4 As an example, the first bonding finger 120a and the second bonding finger 120b of the first bonding finger array 120 and the first bonding finger 130a and the second bonding finger 130b of the second bonding finger array 130 may have an overlapping area within a first distance S1 along a first direction (ie, Y direction) on the upper surface 110S1 of the substrate main body portion 110. Similarly, Figure 3 The third to sixth bonding fingers 120c, 120d, 120e and 120f of the first bonding finger array 120 and the third to sixth bonding fingers 130c, 130d, 130e and 130f of the second bonding finger array 130 shown may also have an overlapping area within the same first distance S1 along the first direction (i.e., the Y direction). In the overlapping area, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 may face each other along the first direction.

[0031] As described above, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 are arranged to have an overlapping area along the first direction (i.e., the Y direction) so that the integration density of the first bonding finger array 120 and the second bonding finger array 130 with respect to the second direction (i.e., the X direction) can be improved. That is, the first bonding finger array 120 and the second bonding finger array 130 are arranged in a denser shape with respect to the second direction (i.e., the X direction) so that the space for arranging the bonding fingers of the first bonding finger array 120 and the second bonding finger array 130 on the upper surface 110S1 of the substrate main body portion 110 can be saved.

[0032] In addition, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 may be arranged to partially overlap each other along a second direction (i.e., X direction) perpendicular to the first direction. Figure 4 , the first bonding fingers 120a of the first bonding finger array 120 and the first bonding fingers 130a of the second bonding finger array 130 may have an overlapping area within a second distance S2 along the second direction (ie, the X direction) on the upper surface 110S1 of the substrate main body portion 110. Similarly, referring to Figure 3 and Figure 4 , the second to sixth bonding fingers 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the second to sixth bonding fingers 130b, 130c, 130d, 120e and 130f of the second bonding finger array 130 may also have an overlapping area within the same second distance S2 along the second direction (i.e., the X direction). In the overlapping area, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 may face each other along the second direction.

[0033] As described above, the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 and the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 are arranged to at least partially overlap each other along the second direction (i.e., the X direction) so that the integration density of the first bonding finger array 120 and the second bonding finger array 130 with respect to the first direction (i.e., the Y direction) can be improved. That is, the first bonding finger array 120 and the second bonding finger array 130 are arranged in a denser form with respect to the first direction (i.e., the Y direction) so that the space for arranging the bonding fingers on the upper surface 110S1 of the substrate main body portion 110 can be saved.

[0034] For some embodiments, as described above with reference to Figure 4 As described herein, the partially overlapping engagement fingers means that regions associated with the engagement fingers (rather than the engagement fingers themselves) overlap each other. Similarly, for some embodiments, the overlapping portions of the engagement fingers means regions associated with portions of the engagement fingers that overlap each other, rather than those portions of the engagement fingers themselves.

[0035] Refer to Figure 3 and Figure 4 , each of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 may include a finger body portion B and a finger edge portion E. Each of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f may have a substantially uniform width W1 in the finger body portion B. Each of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f may have a width that decreases along the second direction (i.e., the X direction) in the finger edge portion E. Each of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f may have a minimum width W2 at an end Ea of the finger edge portion E that is farthest from the finger body portion B. As an example, Figure 3 and Figure 4 As shown, each of the first to sixth bonding fingers 120 a , 120 b , 120 c , 120 d , 120 e , and 120 f may have a hexagonal planar shape on the upper surface 110S 1 of the substrate body portion 110 .

[0036] Similarly, each of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 may include a finger body portion B and a finger edge portion E. Each of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f may have a substantially uniform width W1 in the finger body portion B. Each of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f may have a width that decreases along the second direction (i.e., the X direction) in the finger edge portion E. Each of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f may have a minimum width W2 at an end Ea of the finger edge portion E that is farthest from the finger body portion B. As an example, Figure 3 and Figure 4 As shown, each of the first to sixth bonding fingers 130 a , 130 b , 130 c , 130 d , 130 e , and 130 f may have a hexagonal planar shape on the upper surface 110S 1 of the substrate body portion 110 .

[0037] Reference Figure 3 and Figure 4 The overlap between the bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and the bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130 along the first direction (i.e., the Y direction) can be the overlap between the bonding fingers 120a, 120b, 120c, 120d, 120e and 120f and the edge portions E of the bonding fingers 130a, 130b, 130c, 130d, 130e and 130f.

[0038] Refer to Figure 3 and Figure 4 , the finger edge portions E of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 may be disposed to face the corresponding chip pads 220a, 220b, 220c, 220d, 220e, and 220f of the first chip pad array 220. The finger edge portions E of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 may be disposed to face the corresponding chip pads 320a, 320b, 320c, 320d, 320e, and 320f of the second chip pad array 320.

[0039] As an example, the first extension line C1 passes through the central axis of the first bonding finger 120a of the first bonding finger array 120 and extends in the second direction (ie, the X direction). The first extension line C1 may meet the first chip pad 220a of the first chip pad array 220. Figure 3 and Figure 4 Not shown in the figure, a plurality of extension lines each passing through the central axis of the second to sixth bonding fingers 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 and extending in the second direction (i.e., the X direction) may be provided. Each of the plurality of extension lines meets the corresponding second to sixth chip pads 220b, 220c, 220d, 220e and 220f of the first chip pad array 220. The plurality of extension lines extending through the central axis of the second to sixth bonding fingers 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120 may be parallel to the first extension line C1 extending through the central axis of the first bonding finger 120a in the second direction (i.e., the X direction).

[0040] As another example, the second extension line C2 passes through the central axis of the first bonding finger 130a of the second bonding finger array 130 and extends in the second direction (ie, the X direction). The second extension line C2 may meet the first chip pad 320a of the second chip pad array 320. Figure 3 and Figure 4 Not shown in the figure, a plurality of extension lines extending in the second direction (i.e., the X direction) through the central axis of the second to sixth bonding fingers 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 may be provided. Each of the plurality of extension lines meets the corresponding second to sixth chip pads 320b, 320c, 320d, 320e, and 320f of the second chip pad array 320. The plurality of extension lines passing through the central axis of the second to sixth bonding fingers 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 may be parallel to the second extension line C2 extending in the second direction (i.e., the X direction) through the central axis of the first bonding finger 130a.

[0041] In addition, the first extension line C1 and the second extension line C2 may be parallel to each other. Therefore, the plurality of extension lines parallel to the first extension line C1 and the plurality of extension lines parallel to the second extension line C2 may be parallel to each other. Figure 2As shown, the first bonding wire 701 and the second bonding wire 702 can be effectively arranged to prevent electrical short circuit between each other when forming the first bonding wire 701 and the second bonding wire 702. That is, the first bonding wire 701 and the second bonding wire 702 can be alternately arranged along the first direction (ie, the Y direction) to be spaced apart from each other by a distance.

[0042] In addition, when the first extension line C1, the second extension line C2 and other extension lines are formed parallel to each other, defects occurring in the process of connecting the chip pad and the bonding finger to the bonding wire can be alleviated or suppressed. Specifically, the wire bonding can be formed using a wire bonding capillary. The shape of the wire bonding or connection path can be adjusted by the movement of the wire bonding capillary. When the bonding wires connecting the chip pad and the bonding finger are parallel to each other, the movement paths of the wire bonding capillaries used to connect the bonding wires can be maintained parallel to each other. Therefore, the connection process can be performed without the wire bonding capillary contacting other adjacent bonding wires. In other words, deformation or damage of adjacent bonding wires caused by the movement of the wire bonding capillary in the wire bonding process can be alleviated or prevented.

[0043] Refer to Figure 3 and Figure 4 The first trace pattern 122 and the second trace pattern 132 may be disposed on the upper surface 110S1 of the substrate body portion 110. The first trace pattern 122 may extend from the finger body portions B of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f in the direction of the second semiconductor chip 300. Figure 4 The width W3 of the first trace pattern 122 in the finger body portion B may be smaller than the width W1 of the finger body portion B. Although not specifically shown, the first trace pattern 122 may extend to the lower portion of the second semiconductor chip 300 and may be electrically connected to the first wiring of the package substrate 100. As an example, the first wiring may include an outer layer circuit pattern, an inner layer circuit pattern, and a through hole of the package substrate 100. The first trace pattern 122 may be electrically connected to the first wiring such as a through hole. Figure 1 The corresponding connection pads 160 in the package substrate 100 are shown. Therefore, external signals and external power input to the connection pads 160 through the connection structure 180 can be transmitted to the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e and 120f of the first bonding finger array 120.

[0044] Similarly, the second trace pattern 132 may extend from the finger body portions B of the first to sixth bonding fingers 130 a , 130 b , 130 c , 130 d , 130 e , and 130 f in the direction of the first semiconductor chip 200 . Figure 4The width W3 of the second trace pattern 132 in the finger body portion B may be smaller than the width W1 of the finger body portion B. Although not specifically shown, the second trace pattern 132 may extend to the lower portion of the first semiconductor chip 200 and may be electrically connected to the second wiring of the package substrate 100. The second trace pattern 132 may be electrically connected to the second wiring such as a through hole. Figure 1 The corresponding connection pads 160 in the package substrate 100 are shown. Therefore, external signals and external power input to the connection pads 160 through the connection structure 180 can be transmitted to the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e and 130f of the second bonding finger array 130.

[0045] Reference Figure 3 , the first semiconductor chip 200 may be disposed closer to the second bonding finger array 130 than the first bonding finger array 120 on the upper surface 110S1. The first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 may be spaced apart from the first semiconductor chip 200 by a distance d. In addition, the second semiconductor chip 300 may be disposed closer to the first bonding finger array 120 than the second bonding finger array 130. The first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 may be spaced apart from the second semiconductor chip 300 by a distance d.

[0046] Refer to Figures 2 to 4 , the first bonding wire 701 may connect the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 to the corresponding first to sixth chip pads 220a, 220b, 220c, 220d, 220e, and 220f of the first chip pad array 220. In addition, the second bonding wire 702 may connect the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 to the corresponding first to sixth chip pads 320a, 320b, 320c, 320d, 320e, and 320f of the second chip pad array 320.

[0047] The first to sixth chip pads 220a, 220b, 220c, 220d, 220e, and 220f of the first semiconductor chip 200 may be connected to the corresponding first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f of the first bonding finger array 120 through the first bonding wires 701. The first bonding finger array 120 is disposed farther away from the first semiconductor chip 200 than the second bonding finger array 130. In addition, the first to sixth chip pads 320a, 320b, 320c, 320d, 320e, and 320f of the second semiconductor chip 300 may be connected to the corresponding first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f of the second bonding finger array 130 through the second bonding wires 702. The second bonding finger array 130 is disposed farther from the second semiconductor chip 300 than the first bonding finger array 120 .

[0048] In an embodiment, reference is made to Figure 2 and Figure 3 , the first bonding wire 701 and the second bonding wire 702 can be formed as follows. First, one end of the bonding wire is bonded to the first chip pad 320a of the second semiconductor chip 300 using a wire bonding capillary. Subsequently, the second bonding wire 702 is formed by moving the wire bonding capillary to bond the other end of the bonding wire to the first bonding finger 130a of the second bonding finger array 130. Finally, the bonding wire is disconnected from the second bonding wire 702. At this time, the first bonding finger 130a is set to be sufficiently spaced apart from the first semiconductor chip 200 by a distance d so that the wire bonding capillary does not contact the semiconductor chip and a loop shape of the bonding wire can be formed. In order to form the first bonding wire 701, the wire bonding capillary is moved to the first chip pad 220a of the first semiconductor chip 200. One end of the bonding wire is bonded to the first chip pad 220a of the first semiconductor chip 200. Subsequently, the first bonding wire 701 is formed by moving the wire bonding capillary to bond the other end of the bonding wire to the first bonding finger 120a of the first bonding finger array 120. Finally, the bonding wire is disconnected from the first bonding wire 701. At this time, the first bonding finger 120a is set to be sufficiently spaced apart from the second semiconductor chip 300 by a distance d so that the wire bonding capillary does not contact the semiconductor chip and a loop shape of the bonding wire can be formed. In the same manner, the second bonding wire 702 and the first bonding wire 701 can be alternately formed along the first direction (i.e., the Y direction).

[0049] In addition, as mentioned above Figure 3As described above, the plurality of extension lines extending through the central axes of the first to sixth bonding fingers 120a, 120b, 120c, 120d, 120e, and 120f and the plurality of extension lines extending through the central axes of the first to sixth bonding fingers 130a, 130b, 130c, 130d, 130e, and 130f may be parallel to each other. Therefore, the first bonding wire 701 and the second bonding wire 702 may be staggered with each other along the first direction (i.e., the Y direction) in a state of reducing or preventing electrical short circuits. In addition, as described above, deformation or damage of adjacent bonding wires caused by movement of the wire bonding capillary in the wire bonding process may be reduced or prevented.

[0050] Figure 5 is a plan view of a semiconductor package 1 b according to another embodiment of the present disclosure. Figure 5 The above reference can be shown Figures 1 to 4 The first trace pattern 122 and the second trace pattern 132 provided on the package substrate 100 of the semiconductor package 1a are modified as described above. In addition to the first trace pattern 124 and the second trace pattern 134, Figure 5 The semiconductor package 1b shown may have the same Figures 1 to 4 The semiconductor package 1a described above has basically the same configuration.

[0051] Reference Figure 5 , the first trace pattern 124 of this embodiment may extend from the finger edge portion E of the bonding finger of the first bonding finger array 120 toward the first semiconductor chip 200. Although not shown, the first trace pattern 124 may extend to the lower portion of the first semiconductor chip 200 and may be electrically connected to the first wiring of the package substrate 100. The first trace pattern 124 may be electrically connected to the first wiring such as a through hole. Figure 1 The corresponding connection pads 160 of the package substrate 100 are shown. In this way, the bonding fingers of the first bonding finger array 120 corresponding to the signal fingers, power fingers and ground fingers respectively can receive external signals, external power and external ground potential input through the connection pads 160.

[0052] Similarly, the second trace pattern 134 may extend from the finger edge portion E of the bonding finger of the second bonding finger array 130 toward the second semiconductor chip 300. The second trace pattern 134 may extend to the lower portion of the second semiconductor chip 300 and may be electrically connected to the second wiring of the package substrate 100. The second trace pattern 134 may be electrically connected to the second wiring such as a through hole. Figure 1The corresponding connection pads 160 of the package substrate 100 are shown. In this way, the bonding fingers of the second bonding finger array 130 can receive external signals and external power input through the connection pads 160, and can be connected to external ground terminals through the connection pads 160.

[0053] As described above, the semiconductor package according to some embodiments of the present disclosure includes a first bonding finger array and a second bonding finger array that are respectively wire-bonded to different semiconductor chips on a packaging substrate. The first bonding finger array and the second bonding finger array can be arranged in a line along a first direction, respectively. The bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array are arranged to at least partially overlap each other along the first direction and a second direction perpendicular to the first direction. Therefore, the integration of the bonding fingers on the packaging substrate in the first direction and the second direction can be improved. As a result, the first bonding finger array and the second bonding finger array can be effectively arranged on the packaging substrate. In addition, by saving the arrangement space of the first bonding finger array and the second bonding finger array, the design freedom of various other patterns implemented on the packaging substrate can be improved.

[0054] The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure and the appended claims.

[0055] CROSS-REFERENCE TO RELATED APPLICATIONS

[0056] This application claims priority to Korean Application No. 10-2020-0047748, filed on Apr. 20, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: a package substrate comprising a first bonding finger array and a second bonding finger array, each of the first bonding finger array and the second bonding finger array being arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and comprising a first chip pad array corresponding to the first bonding finger array; a second semiconductor chip disposed on the surface of the package substrate and comprising a second chip pad array corresponding to the second bonding finger array; first bond wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bond wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array, wherein the bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array at least partially overlap each other along the first direction, wherein the bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array are arranged alternately in the first direction, wherein each of the bonding fingers of the first bonding finger array and the second bonding finger array comprises: a finger body portion having a uniform width along a second direction perpendicular to the first direction; and a finger edge portion having a width that decreases along the second direction, and Wherein, the finger edge portion of the first bonding finger array and the finger edge portion of the second bonding finger array are arranged to face in opposite directions.

2. The semiconductor package according to claim 1, wherein The bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array at least partially overlap each other along a second direction perpendicular to the first direction.

3. The semiconductor package according to claim 1, wherein: Each of the bonding fingers of the first bonding finger array and the second bonding finger array has a minimum width at an end of the finger edge portion farthest from the finger body portion.

4. The semiconductor package according to claim 1, wherein: Each of the bonding fingers of the first bonding finger array and the second bonding finger array has a hexagonal planar shape on the surface of the package substrate.

5. The semiconductor package according to claim 1, wherein The finger edge portions of the first bonding finger array and the finger edge portions of the second bonding finger array overlap each other along the first direction.

6. The semiconductor package according to claim 1, wherein The finger edge portions of the first bonding finger array are arranged to face the chip pads of the first chip pad array, and Wherein, the finger edge portions of the second bonding finger array are arranged to face the chip pads of the second chip pad array.

7. The semiconductor package according to claim 1, further comprising: a first trace pattern extending from the bonding fingers of the first bonding finger array on the surface of the package substrate, the first trace pattern being electrically connected to a first wiring of the package substrate; as well as A second trace pattern extends from the bonding fingers of the second bonding finger array on the surface of the package substrate, the second trace pattern being electrically connected to a second wiring of the package substrate on the surface.

8. The semiconductor package according to claim 7, wherein: The first trace pattern extends from the finger body portion of the first bonding finger array toward the second semiconductor chip, and Wherein, the second trace pattern extends from the finger body portion of the second bonding finger array toward the first semiconductor chip.

9. The semiconductor package according to claim 7, wherein: The first trace pattern extends from the finger edge portion of the first bonding finger array toward the first semiconductor chip, and The second trace pattern extends from the finger edge portion of the second bonding finger array toward the second semiconductor chip.

10. The semiconductor package according to claim 1, wherein The first semiconductor chip is disposed closer to the second bonding finger array than to the first bonding finger array, and Wherein, the second semiconductor chip is arranged closer to the first bonding finger array than to the second bonding finger array.

11. The semiconductor package according to claim 1, wherein The bond fingers of the first bond finger array are spaced apart from the second semiconductor chip, and The bonding fingers of the second bonding finger array are spaced apart from the first semiconductor chip.

12. The semiconductor package according to claim 1, wherein A first extension line passing through a central axis of the bonding finger of the first bonding finger array and extending in a second direction perpendicular to the first direction is arranged to meet a chip pad in the first chip pad array of the first semiconductor chip, wherein a second extension line passing through a central axis of the bonding finger of the second bonding finger array and extending in the second direction is arranged to meet a chip pad in the second chip pad array of the second semiconductor chip, and Wherein, the first extension line and the second extension line are parallel to each other.

13. A semiconductor package, comprising: A package substrate, the package substrate comprising a first bonding finger array and a second bonding finger array, the first bonding finger array and the second bonding finger array being arranged along a first line and a second line, respectively, in a first direction on a surface of the package substrate; a first semiconductor chip including a first chip pad array corresponding to the first bonding finger array and disposed closer to the second bonding finger array than to the first bonding finger array on the surface of the package substrate; a second semiconductor chip including a second chip pad array corresponding to the second bonding finger array and disposed on the surface of the package substrate closer to the first bonding finger array than to the second bonding finger array; first bond wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; second bond wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array; a first trace pattern extending from the bonding fingers of the first bonding finger array on the package substrate, the first trace pattern electrically connecting the bonding fingers of the first bonding finger array to a first wiring of the package substrate; as well as a second trace pattern extending from the bonding fingers of the second bonding finger array on the package substrate, the second trace pattern electrically connecting the bonding fingers of the second bonding finger array to a second wiring of the package substrate, wherein the bonding fingers of the first bonding finger array and the bonding fingers of the second bonding finger array are staggered along the first direction, wherein each of the bonding fingers of the first bonding finger array and the second bonding finger array comprises: a finger body portion having a uniform width along a second direction perpendicular to the first direction; and a finger edge portion having a width that decreases along the second direction, and Wherein, the finger edge portion of the first bonding finger array and the finger edge portion of the second bonding finger array are arranged to face in opposite directions.

14. The semiconductor package according to claim 13, wherein: The finger edge portions of the first bonding finger array are arranged to face the chip pads of the first chip pad array, and Wherein, the finger edge portions of the second bonding finger array are arranged to face the chip pads of the second chip pad array.

15. The semiconductor package according to claim 14, wherein: The finger edge portions of the first bonding finger array and the second bonding finger array overlap each other along the first direction.

16. The semiconductor package according to claim 13, wherein: The first trace pattern extends from the finger body portion of the first bonding finger array toward the second semiconductor chip, and Wherein, the second trace pattern extends from the finger body portion of the second bonding finger array toward the first semiconductor chip.

17. The semiconductor package according to claim 13, wherein: The bond fingers of the first bond finger array are spaced apart from the second semiconductor chip, and The bonding fingers of the second bonding finger array are spaced apart from the first semiconductor chip.

18. The semiconductor package according to claim 13, wherein: A first extension line passing through a central axis of the bonding finger of the first bonding finger array and extending in a second direction perpendicular to the first direction is arranged to meet a chip pad in the first chip pad array of the first semiconductor chip, wherein a second extension line passing through a central axis of the bonding finger of the second bonding finger array and extending in the second direction is arranged to meet a chip pad in the second chip pad array of the second semiconductor chip, and Wherein, the first extension line and the second extension line are parallel to each other.

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