Display device

Abstract

The present invention provides a display device. The display device includes: a first active layer, which is arranged on a substrate and is composed of a first substance; a second active layer, which is arranged on the first active layer and is composed of a second substance different from the first active layer; a first gate layer, which is arranged on the second active layer; and an inorganic film pattern, which is arranged at the lower part of the second active layer and overlaps with a part of the first gate layer, wherein the second active layer includes a conductor part, which is arranged between a part of the first gate layer and the inorganic film pattern.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] With the development of the information society, the requirements for display devices for displaying images have increased to various forms. For example, display devices are used in a variety of electronic devices such as smart phones, digital cameras, laptops, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device (Liquid Crystal Display Device), a field emission display device (Field Emission Display Device), an organic light emitting display device (Organic Light Emitting Display Device), etc. In such a flat panel display device, the organic light emitting display device includes a light emitting element that can make the pixels of the display panel emit light by themselves, so that the image can be displayed even if there is no backlight unit that provides light in the display panel.

[0003] Each of the multiple pixels of the display panel may include multiple thin film transistors. Thin film transistors can be classified according to the material constituting the active layer. For example, the thin film transistor can be implemented as a low temperature polycrystalline silicon thin film transistor including an active layer composed of low temperature polycrystalline silicon (LTPS), or a metal oxide thin film transistor including an active layer of an oxide substrate. The active region and the conductive region of the metal oxide thin film transistor can be formed by heat treating the metal oxide. In this case, in the process of designing the metal oxide thin film transistor of the display device, the design freedom of the pixel circuit may be reduced, conductivity deviation may occur, and the resolution of the display device may be adversely affected. Summary of the invention

[0004] The problem to be solved by the present invention is to provide a display device, which configures an inorganic film pattern with a high hydrogen content under the active layer of the oxide substrate, so that during the heat treatment process, even if a gate electrode is configured on the active layer of the oxide substrate, the active layer overlapping with the inorganic film pattern can be made conductive.

[0005] The problem to be solved by the present invention is to provide a display device which can improve the conductivity of the active layer overlapping with the inorganic film pattern during heat treatment by disposing an inorganic film pattern with a high hydrogen content under an active layer of an oxide base.

[0006] The objects of the present invention are not limited to the objects mentioned above, and other objects that have not been mentioned can be clearly understood by those skilled in the art through the following description.

[0007] In order to solve the problem, a display device according to one embodiment includes: a first active layer, arranged on a substrate and composed of a first substance; a second active layer, arranged on the first active layer and composed of a second substance different from the first substance; a first gate layer, arranged on the second active layer; and an inorganic film pattern, arranged at the lower part of the second active layer and overlapping with a part of the first gate layer, the second active layer including a conductor portion arranged between a part of the first gate layer and the inorganic film pattern.

[0008] The display device may further include a first gate insulating film to insulate the second active layer from the first gate layer, and the hydrogen content of the inorganic film pattern is higher than that of the first gate insulating film.

[0009] The display device may further include: a second gate layer, arranged on the first active layer; a first interlayer insulating film, arranged on the second gate layer; a third gate layer, arranged on the first interlayer insulating film; and a second interlayer insulating film, arranged on the third gate layer, and the inorganic film pattern is arranged between the second interlayer insulating film and the conductor portion of the second active layer.

[0010] The inorganic film pattern may have a higher hydrogen content than that of the second interlayer insulating film.

[0011] The conductivity of the conductor portion may be higher than that of a region other than the conductor portion of the second active layer.

[0012] In order to solve the problem, a display device according to one embodiment includes a display panel for driving a plurality of pixels having light-emitting elements, wherein the plurality of pixels respectively include: a driving transistor, included in an active region configured in a first active layer composed of a first substance, controlling a driving current flowing in the light-emitting element; a first transistor, included in an active region configured in a second active layer composed of a second substance different from the first substance, selectively connecting a first node serving as a drain electrode of the driving transistor and a second node serving as a gate electrode of the driving transistor; a first scanning line, configured in a first gate layer on the second active layer, connected to the gate electrode of the first transistor; and an inorganic film pattern, overlapping with an intersection region of the second active layer and the first scanning line.

[0013] The inorganic film pattern may be in direct contact with a lower portion of the second active layer, and the second active layer may include a conductor portion disposed between the first scan line and the inorganic film pattern.

[0014] The gate electrode of the driving transistor and the source electrode of the first transistor may be electrically connected via a conductor portion of the second active layer.

[0015] It can be that the multiple pixels also include: a second transistor, which supplies a data voltage to a third node serving as a source electrode of the driving transistor based on a voltage of a second scanning line configured on a second gate layer on the first active layer; and a first capacitor, which is connected between the second scanning line and the second node, with a first electrode of the first capacitor configured on the second gate layer and a second electrode of the first capacitor configured on the second active layer.

[0016] The gate electrode of the driving transistor and the second electrode of the first capacitor may be electrically connected via a conductor portion of the second active layer.

[0017] The plurality of pixels may each further include a second capacitor connected between the second node and the driving voltage line, and a first electrode of the second capacitor and a second electrode of the first capacitor may be electrically connected via a portion of the conductive second active layer.

[0018] It can be that the multiple pixels also include a first connecting electrode of the source-drain layer configured on the first gate layer, and the first connecting electrode is connected to the gate electrode of the driving transistor configured on the second gate layer through a first contact hole, and is connected to the second active layer through a second contact hole.

[0019] The multiple pixels may also include: a third transistor that selectively supplies an initialization voltage to the second node; a fourth transistor that selectively supplies a driving voltage to the third node; a fifth transistor that selectively connects the first node to a fourth node that serves as an anode electrode of the light-emitting element; and a sixth transistor that selectively supplies the initialization voltage to the fourth node.

[0020] It can be that the gate electrode of the third transistor is connected to the third scan line configured in the first gate layer, the gate electrodes of the fourth transistor and the fifth transistor are respectively connected to the light emitting control line configured in the second gate layer, and the gate electrode of the sixth transistor is connected to the second scan line.

[0021] In order to solve the above-mentioned problem, a display device according to one embodiment includes a display panel for driving a plurality of pixels having light-emitting elements, wherein the plurality of pixels respectively include: a driving transistor, including an active region configured in a first active layer composed of a first substance, and controlling a driving current flowing in the light-emitting element; a first transistor, including an active region configured in a second active layer composed of a second substance different from the first substance, and connecting a first node serving as a drain electrode of the driving transistor and a second node serving as a gate electrode of the driving transistor based on a voltage of a first scanning line configured in a first gate layer on the second active layer; a first capacitor, including a first electrode and a second electrode, the first electrode being equivalent to a part of a second scanning line configured in a second gate layer on the first active layer, the second electrode being connected to the second node and configured in the second active layer; and an inorganic film pattern, configured in a lower portion of the second electrode of the first capacitor, the conductivity of the second electrode of the first capacitor being higher than the conductivity of the second active layer that does not overlap with the inorganic film pattern.

[0022] It may be that the conductivity of the second electrode of the first capacitor is higher than the conductivity of the source electrode of the first transistor.

[0023] It can be that the multiple pixels also include a second connecting electrode of the source-drain layer configured on the first gate layer, and the first connecting electrode is connected to the gate electrode of the driving transistor configured on the second gate layer through a third contact hole, and is connected to the second electrode of the first capacitor configured on the second active layer through a fourth contact hole.

[0024] The plurality of pixels may further include a second transistor respectively, and supply a data voltage to a third node serving as a source electrode of the driving transistor based on a voltage of the second scanning line.

[0025] The plurality of pixels may further include a third transistor respectively for selectively supplying an initialization voltage to the second node, and the conductivity of the second electrode of the first capacitor is higher than the conductivity of the source electrode of the third transistor.

[0026] The multiple pixels may further include: a fourth transistor that selectively supplies a driving voltage to the third node; a fifth transistor that selectively connects the first node to a fourth node that is an anode electrode of the light-emitting element; and a sixth transistor that selectively supplies the initialization voltage to the fourth node.

[0027] Specific matters of other embodiments are included in the detailed description and drawings.

[0028] According to the display device of the embodiment, each of the multiple pixels of the display device may include a low-temperature polysilicon thin film transistor and a metal oxide thin film transistor. The active layer of the oxide substrate of the metal oxide thin film transistor can be made conductive by transferring hydrogen from the inorganic film configured on the active layer through a heat treatment process. When each of the multiple pixels is provided with a gate electrode between the active layer and the inorganic film of the oxide substrate, an inorganic film pattern with a high hydrogen content can be provided at the lower part of the active layer of the oxide substrate overlapping with the gate electrode. During the heat treatment process of the display device, even if a gate electrode is provided on the active layer of the oxide substrate, the inorganic film pattern with a high hydrogen content can be used to make the active layer conductive. Therefore, the display device can use the active layer configured at the lower part of the gate electrode as wiring, so that the design freedom can be improved through a variety of connection structures and bridge structures. The display device can improve the spatial utilization and the resolution of the display device by increasing the design freedom.

[0029] According to the display device of the embodiment, the display device can improve the conductivity of the active layer overlapped with the inorganic film pattern during the heat treatment process by configuring the inorganic film pattern with a high hydrogen content under the active layer of the oxide substrate. Therefore, the display device can eliminate the spots caused by the conductivity deviation of multiple pixels, and the reliability of the display device can be improved.

[0030] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a perspective view showing a display device according to an embodiment.

[0032] Figure 2 is an exploded perspective view showing a display device according to an embodiment.

[0033] Figure 3 is a top view showing a display panel according to an embodiment.

[0034] Figure 4 is a block diagram showing a display panel and a display driving part according to an embodiment.

[0035] Figure 5 is a circuit diagram showing a sub-pixel according to an embodiment.

[0036] Figure 6 Yes Figure 5 Graph showing waveforms of signals supplied to sub-pixels shown in FIG.

[0037] Figure 7 It is shown Figure 5 0 is a top view of an example of a sub-pixel shown in FIG.

[0038] Figure 8 It is shown Figure 7 A top view of a portion of the layers of a sub-pixel shown in FIG.

[0039] Fig. 9 It is shown Figure 7 A top view of another partial layer of the sub-pixel shown in FIG.

[0040] Fig.10 It is along Figure 7 A cross-sectional view taken along the cutting line II`.

[0041] Fig.11 It is along Figure 7 Cross-sectional view taken along the cutting line II-II`.

[0042] Fig.12 It is shown Figure 5 FIG. 4 is a top view of another example of a sub-pixel shown in FIG.

[0043] Fig.13 It is shown Fig.12 A top view of a portion of the layers of a sub-pixel shown in FIG.

[0044] Fig.14 It is shown Fig.12 A top view of another partial layer of the sub-pixel shown in FIG.

[0045] Fig.15 It is along Fig.12 A cross-sectional view taken along the line III-III`.

[0046] Fig.16 It is along Fig.12 Cross-sectional view taken along the cutting line IV-IV`.

[0047] Reference numerals:

[0048] 10: display device, 100: cover window, 300: display panel, 310: display driving unit, 320: power supply unit, 330: power supply unit, 340: touch driving unit, 600: bracket, 700: main circuit board, 900: lower cover, DT: driving transistor, EL: light emitting element, ST1~ST6: first transistor to sixth transistor, ACTL1: first active layer, GTL1: first gate layer, GTL2: second gate layer, ACTL2: second active layer, GTL3: third gate layer, SDL: source-drain layer DETAILED DESCRIPTION

[0049] The advantages, features and methods of achieving the same will be described in detail in the accompanying drawings. Figure 1The present invention will become clear through the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms different from each other. This embodiment is only used to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with common knowledge in the technical field to which the present invention belongs. The present invention is only defined by the scope of the claims.

[0050] When an element or layer is said to be "on" another element or layer, it includes all situations where it is directly above the other element or sandwiched between other layers or other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the figures for the purpose of illustrating the embodiments are only examples, and therefore the present invention is not limited to the matters shown in the figures.

[0051] The terms "first", "second", etc. are used to describe a variety of constituent elements, but it should be clear that the constituent elements are not limited by such terms. Such terms are used only to distinguish one constituent element from other constituent elements. Therefore, it should be clear that the first constituent element mentioned below can also be the second constituent element within the technical concept of the present invention.

[0052] The various features of the multiple embodiments of the present invention may be combined or combined with each other in part or in whole, may be technically linked and driven in a variety of ways, and the various embodiments may be implemented independently of each other or implemented together as a related relationship.

[0053] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view showing a display device according to an embodiment, Figure 2 is an exploded perspective view showing a display device according to an embodiment.

[0055] refer to Figure 1 as well as Figure 2 , a display device 10 according to an embodiment includes a cover window 100 , a display panel 300 , a bracket 600 , a main circuit board 700 , and a lower cover 900 .

[0056] In this specification, "upper", "top", and "above" refer to the upper direction, that is, the Z-axis direction, based on the display device 10, and "lower", "bottom", and "below" refer to the lower direction, that is, the opposite direction of the Z-axis direction, based on the display device 10. In addition, "left", "right", "upper", and "lower" refer to directions when the display device 10 is viewed from a plane. For example, "left" refers to the opposite direction of the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Y-axis direction, and "lower" refers to the opposite direction of the Y-axis direction.

[0057] The display device 10 is a device for displaying dynamic images or static images. It is not only a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic manual, an electronic book, a PMP (Portable Multimedia Player), a navigator, and an UMPC (Ultra Mobile PC), but can also be used as a display screen for a variety of products such as televisions, notebooks, monitors, billboards, and the Internet of Things (IOT).

[0058] The display device 10 may be rectangular in plan view. Figure 1 as well as Figure 2 As shown, the display device 10 may have a rectangular planar shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may be rounded or right angled to have a predetermined curvature. The planar shape of the display device 10 is not limited to a rectangle, and may be formed into other polygonal shapes, a circle, or an ellipse.

[0059] The display device 10 may include a first region DR1 formed flat and a second region DR2 extending from the left and right sides of the first region DR1. The second region DR2 may be formed flat or formed as a curved surface. When the second region DR2 is formed flat, the angle between the first region DR1 and the second region DR2 may be an obtuse angle. When the second region DR2 is formed as a curved surface, it may have a certain curvature or a varying curvature.

[0060] Figure 1 , the second region DR2 is shown to extend from the left and right sides of the first region DR1, but the present invention is not limited thereto. That is, the second region DR2 may extend from only one of the left and right sides of the first region DR1. Alternatively, the second region DR2 may extend from not only the left and right sides of the first region DR1, but also at least one of the upper and lower sides. The following description will focus on the case where the second region DR2 is arranged at the left and right side edges of the display device 10.

[0061] The cover window 100 may be disposed on the upper portion of the display panel 300 to cover the upper surface of the display panel 300. The cover window 100 may protect the upper surface of the display panel 300.

[0062] The cover window 100 may be disposed on the first region DR1 and the second region DR2. The cover window 100 may include a first transparent portion DA1 and a second transparent portion DA2 corresponding to the display panel 300, and a light shielding portion NDA1 corresponding to an area outside the display panel 300. The second transparent portion DA2 may be disposed on one side of the first transparent portion DA1, for example, Figure 1 as well as Figure 2 As shown, it can be arranged on the upper side. The first transparent portion DA1 and the second transparent portion DA2 can be arranged in the first area DR1 and the second area DR2. The light shielding portion NDA1 can be formed to be opaque. Alternatively, the light shielding portion NDA1 can be formed as a decorative layer having a pattern that can be viewed by the user when no image is displayed.

[0063] The display panel 300 may be disposed at the lower portion of the cover window 100. The display panel 300 may be disposed in the first region DR1 and the second region DR2. The image displayed by the display panel 300 may be recognized in the first region DR1 and the second region DR2 through the cover window 100. Therefore, the image displayed by the display panel 300 may be recognized on the upper side and the left and right side edges of the display device 10 through the cover window 100.

[0064] The display panel 300 may be a light-emitting display panel including a light emitting element. For example, the display panel 300 may be an organic light-emitting display panel using an organic light-emitting diode (OLED) including an organic light-emitting layer, an ultra-small light-emitting diode display panel using an ultra-small light-emitting diode (Micro LED), a quantum dot light-emitting display panel using a quantum dot light-emitting diode (Quantum dot Light Emitting Diode) including a quantum dot light-emitting layer, or an inorganic light-emitting display panel using an inorganic light-emitting element including an inorganic semiconductor. The following description will focus on the case where the display panel 300 is an organic light-emitting display panel.

[0065] The display panel 300 may include a main area MA and a protrusion area PA protruding from one side of the main area MA.

[0066] The main area MA may include a general area MDA, a sensing area SDA, and a non-display area NDA.

[0067] The general area MDA may be arranged to overlap with the first transparent portion DA1 of the cover window 100. The sensing area SDA may be arranged to overlap with the second transparent portion DA2 of the cover window 100. The sensing area SDA may be arranged on one side of the general area MDA, for example Figure 2As shown, the sensing area SDA may be arranged on the upper side, but is not limited thereto. As another example, the sensing area SDA may be arranged to be surrounded by the general area MDA, and may be arranged to be adjacent to the corner of the display panel 300. In addition, Figure 2 In the example, the display panel 300 includes one sensing area SDA, but is not limited thereto. For example, the display panel 300 may include a plurality of sensing areas SDA.

[0068] Each of the general area MDA and the sensing area SDA may include a plurality of pixels, scan lines and data lines connected to the plurality of pixels, and a power supply line.

[0069] The non-display area NDA may be defined as an edge area of ​​the display panel 300. The non-display area NDA may include a scan driving part for applying a scan signal to the scan line and a connection line connecting the data line and the display driving part 310.

[0070] The protrusion area PA may protrude from one side of the main area MA. Figure 2 In the embodiment, the protrusion area PA may protrude from the lower side of the general area MDA. For example, the length of the protrusion area PA in the first direction (X-axis direction) may be smaller than the length of the main area MA in the first direction (X-axis direction).

[0071] The protruding area PA may include a bending area and a pad area. In this case, the pad area may be arranged on one side of the bending area, and the main area MA may be arranged on the other side of the bending area. For example, the pad area may be arranged on the lower side of the bending area, and the main area MA may be arranged on the upper side of the bending area.

[0072] The display panel 300 may be flexibly formed to be able to be bent, curved, folded, or rolled. Therefore, the display panel 300 may be bent in the thickness direction (Z-axis direction) at the bending region.

[0073] The display panel 300 may include a display driving part 310 , a circuit board 320 , a power supply part 330 , and a touch driving part 340 .

[0074] The display driving unit 310 may output signals and voltages for driving the display panel 300. For example, the display driving unit 310 may supply data voltages to the data lines. In addition, the display driving unit 310 may supply power voltages to the power lines and may supply scan control signals to the scan driving unit.

[0075] The circuit board 320 can be attached to the pad using anisotropic conductive film (ACF). Then, the wires of the circuit board 320 can be electrically connected to the pads of the display panel 300. For example, the circuit board 320 can be a flexible film (Flexible Film) such as a Flexible Printed Circuit Board (FPCB), a Printed Circuit Board (PCB), or a chip on film (COF).

[0076] The power supply unit 330 may be disposed on the circuit board 320 to supply a driving voltage to the display driving unit 310 and the display panel 300. Specifically, the power supply unit 330 may generate a driving voltage and supply it to a driving voltage line, and the power supply unit 330 may generate a low potential voltage and supply it to a cathode electrode of a light emitting element of each sub-pixel. For example, the driving voltage may be a high potential voltage for driving a light emitting element, such as an organic light emitting diode, and the low potential voltage may be a low potential voltage for driving an organic light emitting diode.

[0077] The touch drive unit 340 can be configured on the circuit board 320 to measure the electrostatic capacitance of the touch electrode. For example, the touch drive unit 340 can determine whether the user touches and the user's touch position based on the change in the electrostatic capacitance of the touch electrode. The user's touch refers to the situation where the user's finger or an object such as a pen directly contacts one side of the display device 10 configured on the touch sensing layer. Then, the touch drive unit 340 can distinguish between the part of the multiple touch electrodes that the user touches and the part that the user does not touch, and determine the user's touch position.

[0078] The bracket 600 may be disposed at the lower portion of the display panel 300. The bracket 600 may be made of plastic, metal, or a combination thereof. For example, the bracket 600 may include a first camera hole CMH1 into which the first camera sensor 720 is inserted, a battery hole BH into which a battery is disposed, a cable hole CAH through which a cable connected to the display driving unit 310 or the circuit board 320 passes, and a sensor hole SH into which the sensor devices 740, 750, 760, and 770 are disposed. As another example, the bracket 600 may not include the sensor hole SH, but may instead be formed so as not to overlap with the sensor area SDA of the display panel 300.

[0079] The main circuit board 700 and the battery 790 may be disposed at the lower portion of the bracket 600. The main circuit board 700 may be a printed circuit board (PCB) or a flexible printed circuit board.

[0080] The main circuit board 700 may include a main processor 710, a first camera sensor 720, a main connector 730, and sensing devices 740, 750, 760, 770. The first camera sensor 720 may be configured on both the upper and lower sides of the main circuit board 700, the main processor 710 may be configured on the upper side of the main circuit board 700, and the main connector 730 may be configured on the lower side of the main circuit board 700. The sensing devices 740, 750, 760, 770 may be configured on the upper side of the main circuit board 700.

[0081] The main processor 710 can control all functions of the display device 10. For example, the main processor 710 can supply digital video data to the display driver 310 for the display panel 300 to display images. The main processor 710 can obtain touch data from the touch driver 340, and after determining the user's touch coordinates, execute the application indicated by the icon displayed in the user's touch coordinates.

[0082] The main processor 710 may control the display device 10 according to the sensing signals input from the sensing devices 740, 750, 760, and 770. For example, the main processor 710 may determine whether an object is located above the display device 10 according to the proximity sensing signal input from the proximity sensor 740. When the object is located above the display device 10 in the call mode, the main processor 710 may not execute the application indicated by the icon displayed in the touch coordinates even if the user performs a touch.

[0083] The main processor 710 may determine the brightness of the top surface of the display device 10 according to the brightness sensing signal input from the brightness sensor 750. The main processor 710 may adjust the brightness of the image displayed by the display panel 300 according to the brightness of the top surface of the display device 10.

[0084] The main processor 710 can determine whether the user's iris image is the same as the iris image pre-stored in the memory according to the iris sensing signal input from the iris sensor 760. When the user's iris image is the same as the iris image pre-stored in the memory, the main processor 710 can unlock the display device 10 and display the main screen on the display panel 300.

[0085] The first camera sensor 720 can process image frames such as static images or dynamic images obtained by the image sensor and output them to the main processor 710. For example, the first camera sensor 720 can be a CMOS image sensor or a CCD sensor, but is not necessarily limited thereto. The first camera sensor 720 can be exposed to the bottom of the lower cover plate 900 through the second camera hole CMH2, and can shoot objects or backgrounds configured at the bottom of the display device 10.

[0086] A cable passing through the cable hole CAH of the bracket 600 may be connected to the main connector 730 . Thus, the main circuit board 700 may be electrically connected to the display driving unit 310 or the circuit board 320 .

[0087] The sensing device may include a proximity sensor 740 , an illumination sensor 750 , an iris sensor 760 , and a second camera sensor 770 .

[0088] The proximity sensor 740 can sense whether an object is close to the top of the display device 10. For example, the proximity sensor 740 may include a light source that outputs light and a light receiving unit that receives light reflected by the object. The proximity sensor 740 can determine whether there is an object located near the top of the display device 10 based on the amount of light reflected by the object. The proximity sensor 740 is overlapped with the sensing hole SH, the sensing area SDA of the display panel 300, and the second transparent portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, so that a proximity sensing signal can be generated based on whether there is an object located near the top of the display device 10 and output to the main processor 710.

[0089] The illumination sensor 750 can sense the brightness of the top of the display device 10. The illumination sensor 750 may include a resistor whose resistance value changes with the brightness of the incident light. The illumination sensor 750 can determine the brightness of the top of the display device 10 based on the resistance value of the resistor. The illumination sensor 750 is overlapped with the sensing hole SH, the sensing area SDA of the display panel 300, and the second transparent portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, so that an illumination sensing signal can be generated according to the brightness of the top of the display device 10 and output to the main processor 710.

[0090] The iris sensor 760 can sense whether the image of the user's iris is the same as the iris image stored in the memory in advance. The iris sensor 760 can generate an iris sensing signal according to whether the user's iris image is the same as the iris image stored in the memory in advance, and output it to the main processor 710.

[0091] The second camera sensor 770 can process image frames such as static images or dynamic images obtained by the image sensor and output them to the main processor 710. For example, the second camera sensor 770 can be a CMOS image sensor or a CCD sensor, but it is not necessarily limited to this. The number of pixels of the second camera sensor 770 can be smaller than the number of pixels of the first camera sensor 720, and the size of the second camera sensor 770 can be smaller than the size of the first camera sensor 720. The second camera sensor 770 is overlapped with the sensing hole SH, the sensing area SDA of the display panel 300, and the second transparent portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, so that objects or backgrounds configured on the upper part of the display device 10 can be photographed.

[0092] The battery 790 may be arranged so as not to overlap with the main circuit board 700 in the third direction (Z-axis direction). The battery 790 may overlap with the battery hole BH of the bracket 600.

[0093] The main circuit board 700 may also include a mobile communication module, which can send and receive wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network. The wireless signal may include a voice signal, a video call signal, or data in various forms based on text / multimedia message transmission and reception.

[0094] The lower cover plate 900 may be disposed below the main circuit board 700 and the battery 790. The lower cover plate 900 may be coupled and fixed to the bracket 600. The lower cover plate 900 may form the lower appearance of the display device 10. The lower cover plate 900 may be made of plastic, metal, or a combination thereof.

[0095] The lower cover plate 900 may include a second camera hole CMH2 exposing the lower surface of the first camera sensor 720. The position of the first camera sensor 720 and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the first camera sensor 720 are not limited to Figure 2 The embodiment shown in FIG.

[0096] Figure 3 is a top view showing a display panel according to an embodiment, Figure 4 is a block diagram showing a display panel and a display driving part according to an embodiment.

[0097] refer to Figure 3 as well as Figure 4 , the display panel 300 may include a general area MDA, a sensing area SDA, and a non-display area NDA.

[0098] The general area MDA may include the first sub-pixel SP1 , a driving voltage line VDDL connected to the first sub-pixel SP1 , a scan line SL, a light emitting control line EML, and a data line DL.

[0099] The first subpixel SP1 may be connected to at least one scan line SL, at least one data line DL, at least one emission control line EML, and at least one driving voltage line VDDL. Figure 3 as well as Figure 4 In the embodiment, the first sub-pixel SP1 is connected to two scan lines SL, one data line DL, one emission control line EML and one driving voltage line VDDL, but the present invention is not limited thereto. For example, the first sub-pixel SP1 can also be connected to more than three scan lines SL.

[0100] The first sub-pixels SP1 may each include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor.

[0101] The first sub-pixel SP1 may be supplied with a driving voltage through the driving voltage line VDDL. Here, the driving voltage may be a high potential voltage for driving the light emitting element of the first sub-pixel SP1.

[0102] The scan lines SL and the emission control lines EML may be extended in a first direction (X-axis direction), and may be spaced apart from each other in a second direction (Y-axis direction) crossing the first direction (X-axis direction).

[0103] The data line DL and the driving voltage line VDDL may be extended in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction).

[0104] The sensing area SDA may include the second sub-pixel SP2 , a driving voltage line VDDL connected to the second sub-pixel SP2 , a scan line SL, a light emitting control line EML, and a data line DL.

[0105] The second sub-pixel SP2 may be connected to at least one scan line SL, at least one data line DL, at least one emission control line EML, and at least one driving voltage line VDDL. Figure 3 as well as Figure 4 In the embodiment, the second sub-pixel SP2 is connected to two scan lines SL, one data line DL, one emission control line EML and one driving voltage line VDDL, but the present invention is not limited thereto. For example, the second sub-pixel SP2 can also be connected to more than three scan lines SL.

[0106] The second sub-pixels SP2 may each include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor.

[0107] The second sub-pixel SP2 may be supplied with a driving voltage through the driving voltage line VDDL. Here, the driving voltage may be a high potential voltage for driving the light emitting element of the second sub-pixel SP2.

[0108] For example, the number of first sub-pixels SP1 per unit area of ​​the general area MDA may be greater than the number of second sub-pixels SP2 per unit area of ​​the sensing area SDA. The general area MDA is an area for displaying images as the main function of the display device 10, and the first sub-pixels SP1 may be densely configured. The sensing area SDA may include a pixel area configured with the second sub-pixels SP2 and a transmission area for transmitting light. Therefore, the larger the area of ​​the transmission area of ​​the sensing area SDA, the smaller the number of second sub-pixels SP2 per unit area may be than the number of first sub-pixels SP1 per unit area.

[0109] The non-display area NDA may be defined as a remaining area on the display panel 300 except for the general area MDA and the sensing area SDA. The non-display area NDA may include a scan driver 410 for applying a scan signal to the scan line SL, a fan-out line FL connecting the data line DL and the display driver 310, and a pad DP connected to the circuit board 320. The display driver 310 and the pad DP may be configured in the pad area of ​​the display panel 300. The pad DP may be configured to be closer to one side edge of the pad area than the display driver 310.

[0110] Figure 4 In the embodiment, the display driving section 310 may include a timing control section 311 and a data driving section 312 .

[0111] The timing control section 311 may receive the digital video data DATA and the timing signal from the circuit board 320. Based on the timing signal, the timing control section 311 may generate a scan control signal SCS to control the operation timing of the scan driving section 410, may generate a light emission control signal ECS to control the operation timing of the light emission control driving section 420, and may generate a data control signal DCS to control the operation timing of the data driving section 312. The timing control section 311 may output the scan control signal SCS to the scan driving section 410 through the first scan control line SCL1. The timing control section 311 may output the light emission control signal ECS to the light emission control driving section 420 through the second scan control line SCL2. The timing control section 311 may output the digital video data DATA and the data control signal DCS to the data driving section 312.

[0112] The data driving unit 312 can convert the digital video data DATA into analog data voltages and output them to the data lines DL through the fan-out lines FL. The scan signals of the scan driving unit 410 can select sub-pixels to which data voltages are supplied, and the selected sub-pixels can receive the data voltages through the data lines DL.

[0113] Figure 3 In the embodiment, the scanning driving unit 410 can be arranged outside one side of the general area MDA and the sensing area SDA or one side of the non-display area NDA. The light emitting control driving unit 420 can be arranged outside the other side of the general area MDA and the sensing area SDA or the other side of the non-display area NDA. As another example, the scanning driving unit 410 and the light emitting control driving unit 420 can also be arranged outside one side of the general area MDA and the sensing area SDA.

[0114] The scan driver 410 may include a plurality of thin film transistors for generating scan signals based on the scan control signal SCS, and the light emission control driver 420 may include a plurality of thin film transistors for generating emission signals based on the light emission control signal ECS. For example, the thin film transistors of the scan driver 410 and the thin film transistors of the light emission control driver 420 may be formed on the same layer as the thin film transistors of the first sub-pixel SP1 and the second sub-pixel SP2.

[0115] Figure 5 is a circuit diagram showing a sub-pixel according to an embodiment, Figure 6 Yes Figure 5 The waveform diagram of the signal supplied to the sub-pixel shown in FIG. Figure 5 The sub-pixel shown in the figure can be equivalent to Figure 3 as well as Figure 4 The first sub-pixel SP1 or the second sub-pixel SP2 shown in the figure.

[0116] refer to Figure 5 as well as Figure 6 The display panel 300 may include a plurality of sub-pixels arranged along p rows (p is a natural number) and q columns (q is a natural number). The plurality of sub-pixels may be connected to the first scan line SLa, the second scan line SLb, the third scan line SLc, the emission control line EML, the data line DL, the driving voltage line VDDL, and the initialization voltage line VIL, respectively.

[0117] The sub-pixel may include a driving transistor DT, a light emitting element EL, a plurality of switching elements, a first capacitor C1 and a second capacitor C2. The switching element may include first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6.

[0118] The driving transistor DT may include a gate electrode, a source electrode, and a drain electrode. The driving transistor DT may control a source-drain current Isd (hereinafter referred to as a “driving current”) according to a data voltage applied to the gate electrode. The driving current Isd flowing through the channel of the driving transistor DT may be proportional to the square of the difference between the voltage Vsg between the source electrode and the gate electrode of the driving transistor DT and the threshold voltage Vth ((Isd=k×(Vsg–Vth) 2 ). Here, k refers to a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vsg refers to a source-gate voltage of the driving transistor DT, and Vth refers to a threshold voltage of the driving transistor DT.

[0119] The light emitting element EL can receive the driving current to emit light, and the amount of light emitted or the brightness of the light emitting element EL can be proportional to the magnitude of the driving current.

[0120] The light emitting element EL may be an organic light emitting diode including an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be a quantum dot light emitting element including an anode electrode, a cathode electrode, and a quantum dot light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be a micro light emitting diode.

[0121] The anode electrode of the light emitting element EL may be connected to the fourth node N4. The anode electrode of the light emitting element EL may be connected to the drain electrode of the fifth transistor ST5 and the drain electrode of the sixth transistor ST6 through the fourth node N4. The cathode electrode of the light emitting element EL may be connected to the low potential line VSSL. Parasitic capacitance may be formed between the anode electrode and the cathode electrode of the light emitting element EL.

[0122] The first transistor ST1 can be turned on by the first scan signal SCa of the first scan line SLa, thereby connecting the first node N1 as the drain electrode of the driving transistor DT and the second node N2 as the gate electrode of the driving transistor DT. The gate electrode of the first transistor ST1 can be connected to the first scan line SLa, the drain electrode can be connected to the first node N1, and the source electrode can be connected to the second node N2. The drain electrode of the first transistor ST1 can be connected to the drain electrode of the driving transistor DT and the source electrode of the fifth transistor ST5 through the first node N1. The source electrode of the first transistor ST1 can be connected to the gate electrode of the driving transistor DT, the source electrode of the third transistor ST3, the second electrode of the first capacitor C1, and the first electrode of the second capacitor C2 through the second node N2.

[0123] The second transistor ST2 may be turned on by the second scan signal SCb of the second scan line SLb, thereby connecting the data line DL and the third node N3 as the source electrode of the driving transistor DT. The second transistor ST2 may be turned on based on the second scan signal SCb, thereby supplying a data voltage to the third node N3. The gate electrode of the second transistor ST2 may be connected to the second scan line SLb, the source electrode may be connected to the data line DL, and the drain electrode may be connected to the third node N3. The drain electrode of the second transistor ST2 may be connected to the source electrode of the driving transistor DT and the drain electrode of the fourth transistor ST4 through the third node N3.

[0124] The third transistor ST3 can be turned on by the third scan signal SCc of the third scan line SLc, thereby connecting the initialization voltage line VIL and the second node N2 as the gate electrode of the driving transistor DT. The third transistor ST3 can be turned on based on the third scan signal SCc, so that the gate electrode of the driving transistor DT can be discharged to the initialization voltage. The gate electrode of the third transistor ST3 can be connected to the third scan line SLc, the drain electrode can be connected to the initialization voltage line VIL, and the source electrode can be connected to the second node N2. The source electrode of the third transistor ST3 can be connected to the gate electrode of the driving transistor DT, the source electrode of the first transistor T1, the second electrode of the first capacitor C1, and the first electrode of the second capacitor C2 through the second node N2.

[0125] The fourth transistor ST4 may be turned on by the light emission signal EM of the light emission control line EML, thereby connecting the driving voltage line VDDL and the third node N3 as the source electrode of the driving transistor DT. The gate electrode of the fourth transistor ST4 may be connected to the light emission control line EML, the source electrode may be connected to the driving voltage line VDDL, and the drain electrode may be connected to the third node N3. The drain electrode of the fourth transistor ST4 may be electrically connected to the source electrode of the driving transistor DT and the drain electrode of the second transistor ST2 through the third node N3.

[0126] The fifth transistor ST5 may be turned on by the light emission signal EM of the light emission control line EML, thereby connecting the first node N1 as the drain electrode of the driving transistor DT and the fourth node N4 as the anode electrode of the light emitting element EL. The gate electrode of the fifth transistor ST5 may be connected to the light emission control line EML, the source electrode may be connected to the first node N1, and the drain electrode may be connected to the fourth node N4. The source electrode of the fifth transistor ST5 may be connected to the drain electrode of the driving transistor DT and the drain electrode of the first transistor ST1 through the first node N1. The drain electrode of the fifth transistor ST5 may be connected to the anode electrode of the light emitting element EL and the drain electrode of the sixth transistor ST6 through the fourth node N4.

[0127] When the fourth transistor ST4 , the driving transistor DT, and the fifth transistor ST5 are all turned on, a driving current may be supplied to the light emitting element EL.

[0128] The sixth transistor ST6 can be turned on by the second scan signal SCb of the second scan line SLb, thereby connecting the initialization voltage line VIL and the fourth node N4 as the anode electrode of the light emitting element EL. The sixth transistor ST6 can be turned on based on the second scan signal SCb, thereby discharging the anode electrode of the light emitting element EL to the initialization voltage. The gate electrode of the sixth transistor ST6 can be connected to the second scan line SLb, the source electrode can be connected to the initialization voltage line VIL, and the drain electrode can be connected to the fourth node N4. The drain electrode of the sixth transistor ST6 can be connected to the anode electrode of the light emitting element EL and the drain electrode of the fifth transistor ST5 through the fourth node N4.

[0129] The driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may include an active layer of a silicon substrate, respectively. For example, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may include an active layer composed of low temperature polycrystalline silicon (LTPS), respectively. The active layer composed of low temperature polycrystalline silicon may have high electron mobility and excellent turn-on characteristics. Therefore, the display device 10 can stably and effectively drive multiple sub-pixels by including the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 with excellent turn-on characteristics.

[0130] The driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 may be p-type transistors, respectively. For example, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 may output the current flowing into the source electrode to the drain electrode based on the gate low voltage applied to the gate electrode.

[0131] The first transistor ST1 and the third transistor ST3 may include an active layer of an oxide substrate, respectively. For example, the first transistor ST1 and the third transistor ST3 may have a coplanar structure in which a gate electrode is disposed on the upper portion of the active layer of the oxide substrate, respectively. The transistor having the coplanar structure has an excellent off current characteristic and can be driven at a low frequency, thereby reducing power consumption. Therefore, the display device 10 includes the first transistor ST1 and the third transistor ST3 having excellent off current characteristics, thereby preventing the off current from flowing inside the sub-pixel and stably maintaining the voltage inside the sub-pixel.

[0132] The first transistor ST1 and the third transistor ST3 may be equivalent to n-type transistors. For example, the first transistor ST1 and the third transistor ST3 may output the current flowing into the drain electrode to the source electrode based on the gate high voltage applied to the gate electrode.

[0133] The first capacitor C1 may be connected between the second scan line SLb and the second node N2. For example, the first electrode of the first capacitor C1 may be connected to the second scan line SLb, and the second electrode of the first capacitor C1 may be connected to the second node N2 as the gate electrode of the driving transistor DT. The first capacitor C1 may control the voltage of the gate electrode of the driving transistor DT by storing the differential voltage between the second scan line SLb and the gate electrode of the driving transistor DT.

[0134] The first capacitor C1 can use the gate low voltage of the second scan signal SCb to couple the gate electrode of the driving transistor DT. For example, when the second scan signal SCb provided by the second scan line SLb rises, the first capacitor C1 can increase the voltage of the second node N2, and when the second scan signal SCb falls, the first capacitor C1 can reduce the voltage of the second node N2. Therefore, the first capacitor C1 can be synchronized with the rising time or falling time of the second scan signal SCb, thereby controlling the voltage of the gate electrode of the driving transistor DT.

[0135] The second capacitor C2 may be connected between the second node N2 as the gate electrode of the driving transistor DT and the driving voltage line VDDL. For example, the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode of the second capacitor C2 is connected to the driving voltage line VDDL, so that the potential difference between the driving voltage line VDDL and the gate electrode of the driving transistor DT can be maintained.

[0136] Will Figure 6 and Figure 5By combining the above, the display device 10 can be driven from the first period t1 to the fourth period t4 of one frame.

[0137] The third transistor ST3 may receive a high-level third scan signal SCc during the first period t1. The third transistor ST3 may be turned on based on the high-level third scan signal SCc, and may supply an initialization voltage (hereinafter represented by "VI") to the second node N2 as the gate electrode of the driving transistor DT. Therefore, the third transistor ST3 may initialize the gate electrode of the driving transistor DT during the first period t1.

[0138] The sixth transistor ST6 may receive the second scan signal SCb of the low level during the second period t2. The sixth transistor ST6 may be turned on based on the second scan signal SCb of the low level, and may supply the initialization voltage V1 to the fourth node N4 as the anode electrode of the light emitting element EL. Therefore, the sixth transistor ST6 may initialize the anode electrode of the light emitting element EL during the second period t2.

[0139] The second transistor ST2 may receive a low-level second scan signal SCb during the second period t2. The second transistor ST2 may be turned on based on the low-level second scan signal SCb and may supply a data voltage (hereinafter referred to as "Vdata") to the third node N3 as the source electrode of the driving transistor DT.

[0140] The first transistor ST1 may receive a high-level first scan signal SCa during the third period t3. The first transistor ST1 may be turned on based on the high-level first scan signal SCa and may connect the first node N1 and the second node N2.

[0141] When the source electrode of the driving transistor DT receives the data voltage Vdata, the source-gate voltage Vsg of the driving transistor DT may be equivalent to the difference voltage Vdata-VI between the data voltage Vdata and the initialization voltage VI, and the driving transistor DT may be turned on (Vdata-VI>=Vth) because the source-gate voltage Vsg is greater than the threshold voltage (hereinafter represented by "Vth"). Therefore, at the moment when the driving transistor DT is turned on during the second period T2, the source-gate current Isd of the driving transistor DT may be determined by the data voltage Vdata, the initialization voltage VI and the threshold voltage Vth of the driving transistor DT (Isd=k*(Vdata-VI-Vth)^2). The driving transistor DT may supply the source-drain current Isd to the first node N1 until the source-gate voltage Vsg reaches the threshold voltage Vth of the driving transistor DT. Then, the first transistor ST1 may be turned on during the third period t3 to supply the voltage of the first node N1 to the second node N2. In this way, while the driving transistor DT is turned on, the voltage of the second node N2 and the source-drain current Isd of the driving transistor DT can change, and finally the voltage of the second node N2 can converge to the difference voltage Vdata-Vth between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0142] The emission signal EM may have a gate low voltage during the fourth period t4. When the emission signal EM has a low level, the fourth transistor ST4 and the fifth transistor ST5 are turned on to supply a driving current to the light emitting element EL.

[0143] Figure 7 It is shown Figure 5 A top view of an example of a sub-pixel is shown in FIG. Figure 8 It is shown Figure 7 A top view of a portion of the layers of a sub-pixel shown in FIG. Fig. 9 It is shown Figure 7 A top view of another portion of the sub-pixel layer shown in FIG. Figure 7 It may be equivalent to a diagram in which a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a source-drain layer are sequentially stacked. Figure 8 It can be equivalent to a diagram in which a first active layer, a first gate layer, and a second gate layer are stacked in sequence. Fig. 9 It can be equivalent to a diagram in which the second active layer, the third gate layer, and the source-drain layer are stacked in sequence. Figures 7 to 9 The stacking relationship of the layers is as follows Fig.10 as well as Fig.11 Detailed description is given in .

[0144] refer to Figures 7 to 9The driving transistor DT may include an active region DT_ACT, a gate electrode DT_G, a source electrode DT_S, and a drain electrode DT_D. The active region DT_ACT of the driving transistor DT may be configured in the first active layer and may overlap with the gate electrode DT_G of the driving transistor DT. For example, the first active layer may be composed of low temperature polysilicon (LTPS).

[0145] The gate electrode DT_G of the driving transistor DT may be connected to the first connection electrode BE1 through the first contact hole CNT1, and the first connection electrode BE1 may be connected to the conductor portion CON of the second active layer through the second contact hole CNT2. For example, the second active layer may be composed of an oxide-based material. In addition, the region of the gate electrode DT_G of the driving transistor DT that overlaps with the second electrode CE22 of the second capacitor C2 may be equivalent to the first electrode CE21 of the second capacitor C2.

[0146] The source electrode DT_S of the driving transistor DT may be connected with the drain electrode D2 of the second transistor ST2 and the drain electrode D4 of the fourth transistor ST4 .

[0147] The drain electrode DT_D of the driving transistor DT may be connected to the third connection electrode BE3 through the seventh contact hole CNT7, and the third connection electrode BE3 may be connected to the drain electrode D1 of the first transistor ST1 through the sixth contact hole CNT6. In addition, the drain electrode DT_D of the driving transistor DT may be connected to the source electrode S5 of the fifth transistor ST5.

[0148] The conductor portion CON of the second active layer may be disposed on the inorganic film pattern PTN, and may be disposed at the lower portion of the first scan line SLa. For example, the conductor portion CON of the second active layer, the second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 may be conductorized by heat-treating the second active layer of the oxide substrate.

[0149] The second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 can be conductive by transferring hydrogen from the inorganic film configured on the second active layer. The inorganic film configured on the second active layer can cover the gate insulating film and the gate layer on the second active layer. For example, the inorganic film configured on the second active layer may include a silicon oxide film SiOx or a silicon nitride film SiNx with a relatively high hydrogen content. The hydrogen contained in the silicon oxide film SiOx or the silicon nitride film SiNx can be diffused to the second active layer through a heat treatment process, and the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 can be conductive.

[0150] For example, the conductor portion CON of the second active layer may overlap the first scan line SLa disposed on the second active layer. That is, the inorganic film disposed on the second active layer may cover the first scan line SLa, so the first scan line SLa may prevent hydrogen of the inorganic film from diffusing to the conductor portion CON of the second active layer during the heat treatment process.

[0151] The conductor portion CON of the second active layer can transfer hydrogen from the inorganic film pattern PTN arranged at the bottom of the conductor portion CON during the heat treatment process. For example, the inorganic film pattern PTN may include a silicon oxide film SiOx or a silicon nitride film SiNx having a relatively high hydrogen content. The hydrogen content of the inorganic film pattern PTN may be higher than the hydrogen content of the gate insulating film covering the second active layer or the interlayer insulating film arranged at the bottom of the second active layer. Therefore, even if the conductor portion CON of the second active layer is arranged at the bottom of the first scan line SLa, it can be used as a wiring connecting the second electrode CE12 of the first capacitor C1 or the source electrode S1 of the first transistor ST1 and the gate electrode DT_G of the driving transistor DT. The display device 10 uses the active layer (e.g., the conductor portion CON) arranged at the bottom of the gate electrode (e.g., the first scan line SLa) as a wiring, so that a variety of connection structures and bridge structures can be embodied, and the design freedom of the pixel circuit can be increased. The display device 10 can improve the space utilization and the resolution of the display device 10 by increasing the design freedom.

[0152] The first transistor ST1 may include an active region ACT1, a gate electrode G1, a source electrode S1, and a drain electrode D1. The active region ACT1 of the first transistor ST1 may overlap with the gate electrode G1 of the first transistor ST1. For example, the active region ACT1 of the first transistor ST1 may be composed of an oxide-based material. The gate electrode G1 of the first transistor ST1, as a part of the first scan line SLa, may correspond to a region of the first scan line SLa that overlaps with the active region ACT1.

[0153] The drain electrode D1 of the first transistor ST1 may be connected to the third connection electrode BE3 through the sixth contact hole CNT6 , and the third connection electrode BE3 may be connected to the drain electrode DT_D of the driving transistor DT and the source electrode S5 of the fifth transistor ST5 through the seventh contact hole CNT7 .

[0154] The source electrode S1 of the first transistor ST1 can be connected to the source electrode S3 of the third transistor ST3 and the second electrode CE12 of the first capacitor C1. In addition, the source electrode S1 of the first transistor ST1 can be connected to the first connection electrode BE1 through the conductor portion CON and the second contact hole CNT2, and the first connection electrode BE1 can be connected to the gate electrode DT_G of the driving transistor DT or the first electrode CE21 of the second capacitor C2 through the first contact hole CNT1.

[0155] The second transistor ST2 may include an active region ACT2, a gate electrode G2, a source electrode S2, and a drain electrode D2. The active region ACT2 of the second transistor ST2 may overlap with the gate electrode G2 of the second transistor ST2. For example, the active region ACT2 of the second transistor ST2 may be composed of low temperature polysilicon LTPS. The gate electrode G2 of the second transistor ST2, as a part of the second scan line SLb, may be equivalent to the region of the second scan line SLb that overlaps with the active region ACT2.

[0156] The source electrode S2 of the second transistor ST2 may be connected to the fourth link electrode BE4 through the eighth contact hole CNT8, and the fourth link electrode BE4 may be connected to the data line DL. Therefore, the source electrode S2 of the second transistor ST2 may receive the data voltage from the data line DL.

[0157] The drain electrode D2 of the second transistor ST2 may be connected with the source electrode DT_S of the driving transistor DT and the drain electrode D2 of the fourth transistor ST4 .

[0158] The third transistor ST3 may include an active region ACT3, a gate electrode G3, a drain electrode D3, and a source electrode S3. The active region ACT3 of the third transistor ST3 may overlap with the gate electrode G3 of the third transistor ST3. For example, the active region ACT3 of the third transistor ST3 may include an active layer of an oxide substrate. The gate electrode G3 of the third transistor ST3, as a part of the third scan line SLc, may be equivalent to the region of the third scan line SLc that overlaps with the active region ACT3.

[0159] The drain electrode D3 of the third transistor ST3 may be connected to the initialization voltage line VIL through the tenth contact hole CNT10 to receive the initialization voltage VI.

[0160] The source electrode S3 of the third transistor ST3 can be connected to the source electrode S1 of the first transistor ST1 and the second electrode CE12 of the first capacitor C1. In addition, the source electrode S3 of the third transistor ST3 can be connected to the first connection electrode BE1 through the conductor portion CON and the second contact hole CNT2, and the first connection electrode BE1 can be connected to the gate electrode DT_G of the driving transistor DT or the first electrode CE21 of the second capacitor C2 through the first contact hole CNT1.

[0161] The fourth transistor ST4 may include an active region ACT4, a gate electrode G4, a source electrode S4, and a drain electrode D4. The active region ACT4 of the fourth transistor ST4 may overlap with the gate electrode G4 of the fourth transistor ST4. For example, the active region ACT4 of the fourth transistor ST4 may be composed of low temperature polysilicon LTPS. The gate electrode G4 of the fourth transistor ST4, as a part of the light emitting control line EML, may be equivalent to the region of the light emitting control line EML that overlaps with the active region ACT4.

[0162] The source electrode S4 of the fourth transistor ST4 may be connected to the driving voltage line VDDL through the twelfth contact hole CNT12. Therefore, the source electrode S4 of the fourth transistor ST4 may receive the driving voltage from the driving voltage line VDDL.

[0163] The drain electrode D4 of the fourth transistor ST4 may be connected to the source electrode DT_S of the driving transistor DT and the drain electrode D2 of the second transistor ST2 .

[0164] The fifth transistor ST5 may include an active region ACT5, a gate electrode G5, a source electrode S5, and a drain electrode D5. The active region ACT5 of the fifth transistor ST5 may overlap with the gate electrode G5 of the fifth transistor ST5. For example, the active region ACT5 of the fifth transistor ST5 may be composed of low temperature polycrystalline silicon LTPS. The gate electrode G5 of the fifth transistor ST5, as a part of the light emitting control line EML, may be equivalent to the region of the light emitting control line EML that overlaps with the active region ACT5.

[0165] The source electrode S5 of the fifth transistor ST5 can be connected to the drain electrode DT_D of the driving transistor DT. In addition, the source electrode S5 of the fifth transistor ST5 can be connected to the third connection electrode BE3 through the seventh contact hole CNT7, and the third connection electrode BE3 can be connected to the drain electrode D1 of the first transistor ST1 through the sixth contact hole CNT6.

[0166] The drain electrode D5 of the fifth transistor ST5 may be connected to the first anode connection electrode ANDE1 through the ninth contact hole CNT9. The first anode connection electrode ANDE1 may be connected to the anode electrode of the light emitting element EL.

[0167] The sixth transistor ST6 may include an active region ACT6, a gate electrode G6, a drain electrode D6, and a source electrode S6. The active region ACT6 of the sixth transistor ST6 may overlap with the gate electrode G6 of the sixth transistor ST6. For example, the active region ACT6 of the sixth transistor ST6 may be composed of low temperature polysilicon LTPS. The gate electrode G6 of the sixth transistor ST6, as a part of the second scan line SLb, may be equivalent to the region of the second scan line SLb that overlaps with the active region ACT6.

[0168] The source electrode S6 of the sixth transistor ST6 may be connected to the initialization voltage line VIL through the eleventh contact hole CNT11 , thereby receiving the initialization voltage VI.

[0169] The drain electrode D6 of the sixth transistor ST6 may be connected to the first anode connection electrode ANDE1 through the ninth contact hole CNT9. The first anode connection electrode ANDE1 may be connected to the anode electrode of the light emitting element EL.

[0170] The first capacitor C1 may include a first electrode CE11 and a second electrode CE12. The first electrode CE11 of the first capacitor C1, as a part of the second scan line SLb, may correspond to a region of the second scan line SLb that overlaps with the second active layer. The second electrode CE12 of the first capacitor C1, as a part of the second active layer, may correspond to a region of the second active layer that overlaps with the second scan line SLb.

[0171] The second electrode CE12 of the first capacitor C1 can be connected to the first connection electrode BE1 through the conductor portion CON and the second contact hole CNT2, and the first connection electrode BE1 can be connected to the gate electrode DT_G of the driving transistor DT or the first electrode CE21 of the second capacitor C2 through the first contact hole CNT1. The first capacitor C1 can couple (Coupling) the gate electrode DT_G of the driving transistor DT using the gate low voltage of the second scan signal SCb. Therefore, the first capacitor C1 can be synchronized with the falling moment of the second scan signal SCb to reduce the voltage of the gate electrode DT_G of the driving transistor DT, thereby improving the turn-on characteristics of the driving transistor DT and improving the brightness of the light-emitting element EL.

[0172] The second capacitor C2 may include a first electrode CE21 and a second electrode CE22. The first electrode CE21 of the second capacitor C2, as a part of the gate electrode DT_G of the driving transistor DT, may correspond to a region of the gate electrode DT_G of the driving transistor DT that overlaps with the second gate layer. The first electrode CE21 of the second capacitor C2 may be connected to the first connection electrode BE1 through the first contact hole CNT1, and the first connection electrode BE1 may be connected to the conductor portion CON of the second active layer through the second contact hole CNT2.

[0173] The second electrode CE22 of the second capacitor C2 may be connected to the driving voltage line VDDL through the fifth contact hole CNT5. Therefore, the second electrode CE22 of the second capacitor C2 may receive the driving voltage from the driving voltage line VDDL.

[0174] Fig.10 It is along Figure 7 The cross-sectional view taken along the interception line II', Fig.11 It is along Figure 7 Cross-sectional view taken along the cutting line II-II`.

[0175] Will Fig.10 as well as Fig.11 and Figures 7 to 9 When combined, the display panel 300 may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a first interlayer insulating film ILD1, a second gate layer GTL2, a second interlayer insulating film ILD2, an inorganic film pattern PTN, a second active layer ACTL2, a second gate insulating layer GI2, a third gate layer GTL3, a third interlayer insulating film ILD3, and a source-drain layer SDL.

[0176] The substrate SUB may be a base substrate, and may be made of insulating materials such as polymer resins. For example, the substrate SUB may be a flexible substrate that can be bent, folded, or rolled.

[0177] For example, the display panel 300 may further include a light shielding layer BML overlapping at least one of the driving transistor DT and the first to sixth transistors ST1 to ST6. The light shielding layer BML blocks light incident to the driving transistor DT or the first to sixth transistors ST1 to ST6, thereby improving the turn-on characteristics of the transistors.

[0178] The buffer layer BF may be disposed on the substrate SUB. For example, the buffer layer BF may include a plurality of inorganic films and may be formed on the entire surface of the substrate SUB in order to block moisture from penetrating into the light emitting element EL through the substrate SUB.

[0179] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may be formed of a silicon-based material. For example, the first active layer ACTL1 may be formed of low-temperature polycrystalline silicon LTPS. The active regions DT_ACT, ACT2, ACT4, ACT5, ACT6, source electrodes DT_S, S2, S4, S5, S6, and drain electrodes DT_D, D2, D4, D5, D6 of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be disposed on the first active layer ACTL1.

[0180] The first gate insulating film GI1 may cover the buffer layer BF and the first active layer ACTL1 , and may insulate the first active layer ACTL1 from the first gate layer GTL1 .

[0181] The first gate layer GTL1 may be disposed on the first gate insulating film GI1. The gate electrode DT_G of the driving transistor DT, the second scan line SLb, and the light emission control line EML may be disposed on the first gate layer GTL1.

[0182] A portion of the first gate electrode DT_G may overlap with the second electrode CE22 of the second capacitor C2 disposed at the second gate layer GTL2 to form a first electrode CE21 of the second capacitor C2 .

[0183] A portion of the second scan line SLb may overlap with the active area ACT2 of the second transistor ST2 to form a gate electrode G2 of the second transistor ST2. Another portion of the second scan line SLb may overlap with the active area ACT6 of the sixth transistor ST6 to form a gate electrode G6 of the sixth transistor ST6. Another portion of the second scan line SLb may overlap with the second electrode CE12 of the first capacitor C1 configured in the second active layer ACTL2 to form a first electrode CE11 of the first capacitor C1.

[0184] A portion of the emission control line EML may overlap the active region ACT4 of the fourth transistor ST4 to form a gate electrode G4 of the fourth transistor ST4 , and another portion of the emission control line EML may overlap the active region ACT5 of the fifth transistor ST5 to form a gate electrode G5 of the fifth transistor ST5 .

[0185] The first interlayer insulating film ILD1 may cover the first gate layer GTL1 and the first gate insulating film GI1. The first interlayer insulating film ILD1 may insulate the first gate layer GTL1 and the second gate layer GTL2.

[0186] The second gate layer GTL2 may be disposed on the first interlayer insulating film ILD1. The light shielding layer BML and the second electrode CE22 of the second capacitor C2 may be disposed on the second gate layer GTL2. The light shielding layer BML may overlap with the first transistor ST1, thereby blocking light incident to the first transistor ST1. The second electrode CE22 of the second capacitor C2 may overlap with the first electrode CE21 disposed on the first gate layer GTL1.

[0187] The second interlayer insulating film ILD2 may cover the second gate layer GTL2 and the first interlayer insulating film ILD1. The second interlayer insulating film ILD2 may insulate the second gate layer GTL2 and the second active layer ACTL2.

[0188] The inorganic film pattern PTN may be interposed between the second interlayer insulating film ILD2 and the second active layer ACTL2. For example, the inorganic film pattern PTN may overlap with the second active layer ACTL2 and the intersection area of ​​the first scan line SLa. The conductor portion CON of the second active layer ACTL2 may be disposed on the inorganic film pattern PTN and may be disposed at the lower portion of the first scan line SLa. For example, the conductor portion CON, the second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 may be conductorized by heat treating the second active layer ACTL2 of the oxide substrate.

[0189] The second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 can be conductively connected by hydrogen transferred from the third interlayer insulating film ILD3. Here, the third interlayer insulating film ILD3 can cover the second gate insulating film GI2 and the third gate layer GTL3 on the second active layer ACTL2. For example, the third interlayer insulating film ILD3 may include a silicon oxide film SiOx or a silicon nitride film SiNx having a relatively high hydrogen content. The hydrogen contained in the silicon oxide film SiOx or the silicon nitride film SiNx can be diffused to the second active layer ACTL2 through a heat treatment process, and the second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 can be conductively connected.

[0190] For example, the conductor portion CON of the second active layer ACTL2 may overlap with the first scan line SLa configured on the second active layer ACTL2. That is, the third interlayer insulating film ILD3 may cover the first scan line SLa configured on the third gate layer GTL3, and therefore, the first scan line SLa may prevent hydrogen of the third interlayer insulating film ILD3 from diffusing to the conductor portion CON of the second active layer ACTL2 during the heat treatment process.

[0191] The conductor portion CON of the second active layer ACTL2 can obtain hydrogen by transfer from the inorganic film pattern PTN configured at the lower part of the conductor portion CON during the heat treatment process. For example, the inorganic film pattern PTN may include a silicon oxide film SiOx or a silicon nitride film SiNx having a relatively high hydrogen content. The hydrogen content of the inorganic film pattern PTN may be higher than the hydrogen content of the second gate insulating film GI2 covering the second active layer ACTL2 or the second interlayer insulating film ILD2 configured at the lower part of the second active layer ACTL2. Therefore, even if the conductor portion CON of the second active layer ACTL2 is configured at the lower part of the first scan line SLa, hydrogen can be transferred from the inorganic film pattern PTN for conductorization. The conductor portion CON of the second active layer ACTL2 can be used as a wiring for connecting the second electrode CE12 of the first capacitor C1 connected to one end of the conductor portion CON, the source electrode S1 of the first transistor ST1, or the source electrode S3 of the third transistor ST3, and the gate electrode DT_G of the driving transistor DT connected to the other end of the conductor portion CON, or the first electrode CE21 of the second capacitor C2. The display device 10 uses the conductor portion CON disposed at the bottom of the first scanning line S1a disposed in the third gate layer GTL3 as wiring, thereby being able to embody a variety of connection structures and bridge structures, and increasing the degree of freedom in designing the pixel circuit. The display device 10 can improve space utilization and increase the resolution of the display device 10 by increasing the degree of freedom in design.

[0192] The second active layer ACTL2 may be disposed on the second interlayer insulating film ILD2. For example, the second active layer ACTL2 may be formed of an oxide-based material. The active regions ACT1, ACT3, drain electrodes D1, D3, and source electrodes S1, S3 of the first transistor ST1 and the third transistor ST3, respectively, may be disposed on the second active layer ACTL2. In addition, a portion of the second active layer ACTL2 may overlap with the second scan line SLb disposed on the first gate layer GTL1 to form a second electrode CE12 of the first capacitor C1.

[0193] The second gate insulating film GI2 may cover the second interlayer insulating film ILD2 and the second active layer ACTL2 , and may insulate the second active layer ACTL2 from the third gate layer GTL3 .

[0194] The third gate layer GTL3 may be disposed on the second gate insulating film GI2. The first scan line SLa and the third scan line SLc may be disposed on the third gate layer GTL3. A portion of the first scan line SLa may overlap with the active area ACT1 of the first transistor ST1 to form the gate electrode G1 of the first transistor ST1. A portion of the third scan line SLc may overlap with the active area ACT3 of the third transistor ST3 to form the gate electrode G3 of the third transistor ST3.

[0195] The third interlayer insulating film ILD3 may cover the third gate layer GTL3 and the second gate insulating film GI2. The third interlayer insulating film ILD3 may insulate the third gate layer GTL3 and the source-drain layer SDL.

[0196] The source-drain layer SDL may be disposed on the third interlayer insulating film ILD3. The first connection electrode BE1, the third connection electrode BE3, the fourth connection electrode BE4, the driving voltage line VDDL, the initialization voltage line VIL and the first anode connection electrode ANDE1 may be disposed on the source-drain layer SDL.

[0197] The first connection electrode BE1 may be connected to the gate electrode DT_G of the driving transistor DT through the first contact hole CNT1 , and may be connected to the conductor portion CON of the second active layer through the second contact hole CNT2 .

[0198] The third connection electrode BE3 may be connected to the source electrode S1 of the first transistor ST1 through the sixth contact hole CNT6 , and may be connected to the drain electrode DT_D of the driving transistor DT through the seventh contact hole CNT7 .

[0199] The fourth link electrode BE4 may be connected to the source electrode S2 of the second transistor ST2 through the eighth contact hole CNT8. In addition, the fourth link electrode BE4 may be connected to the data line DL.

[0200] The driving voltage line VDDL may be connected to the second electrode CE22 of the second capacitor C2 through the fifth contact hole CNT5 , and may be connected to the source electrode S4 of the fourth transistor ST4 through the twelfth contact hole CNT12 .

[0201] The initialization voltage line VIL may be connected to the drain electrode D3 of the third transistor ST3 through the tenth contact hole CNT10 , and may be connected to the source electrode S6 of the sixth transistor ST6 through the eleventh contact hole CNT11 .

[0202] The first anode connection electrode ANDE1 may be connected to the drain electrode D5 of the fifth transistor ST5 through the ninth contact hole CNT9. In addition, the first anode connection electrode ANDE1 may be connected to the anode electrode of the light emitting element EL.

[0203] Fig.12 It is shown Figure 5 A top view of another example of a sub-pixel is shown in FIG. Fig.13 It is shown Fig.12 A top view of a portion of the layers of a sub-pixel shown in FIG. Fig.14 It is shown Fig.12 A top view of another portion of the sub-pixel layer shown in FIG. Fig.12 It may be equivalent to a diagram in which a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a source-drain layer are sequentially stacked. Fig.13 It can be equivalent to a diagram in which a first active layer, a first gate layer, and a second gate layer are stacked in sequence. Fig.14 It can be equivalent to a diagram in which the second active layer, the third gate layer and the source-drain layer are stacked in sequence. In addition, Fig.15 It is along Fig.12 The cross-sectional view taken along the interception line III-III`, Fig.16 It is along Fig.12 Cross-sectional view taken along the cutting line IV-IV`.

[0204] Figures 12 to 16 The sub-pixel shown in the figure is different from the above-mentioned sub-pixel in that the configuration of the inorganic film pattern PTN and the connection structure of the pixel circuit based thereon are set differently, and the same structure as the above-mentioned structure is briefly described or omitted.

[0205] refer to Figures 12 to 16 The display panel 300 may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a first interlayer insulating film ILD1, a second gate layer GTL2, a second interlayer insulating film ILD2, an inorganic film pattern PTN, a second active layer ACTL2, a second gate insulating layer GI2, a third gate layer GTL3, a third interlayer insulating film ILD3, and a source-drain layer SDL. The plurality of sub-pixels of the display panel 300 may include a driving transistor DT, first to sixth transistors ST1, ST2, ST3, ST4, ST5, ST6, a first capacitor C1, and a second capacitor C2.

[0206] The display panel 300 may further include a second connection electrode BE2 configured on the source-drain layer SDL. The gate electrode DT_G of the driving transistor DT may be connected to the second connection electrode BE2 through the third contact hole CNT3, and the second connection electrode BE2 may be connected to the second electrode CE12 of the first capacitor C1 through the fourth contact hole CNT4. The second electrode CE12 of the first capacitor C1 may be connected to the source electrode S1 of the first transistor ST1 and the source electrode S3 of the third transistor ST3. In addition, the region of the gate electrode DT_G of the driving transistor DT that overlaps with the second gate layer GTL2 may be equivalent to the first electrode CE21 of the second capacitor C2.

[0207] The second electrode CE12 of the first capacitor C1 , the drain electrode D1 and the source electrode S1 of the first transistor ST1 , and the drain electrode D3 and the source electrode S3 of the third transistor ST3 may be conductorized by thermally treating the second active layer ACTL2 of the oxide substrate.

[0208] For example, the second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 can be conductively connected by hydrogen transferred from the third interlayer insulating film ILD3. Here, the third interlayer insulating film ILD3 can cover the second gate insulating film GI2 and the third gate layer GTL3 on the second active layer ACTL2. For example, the third interlayer insulating film ILD3 may include a silicon oxide film SiOx or a silicon nitride film SiNx having a relatively high hydrogen content. The hydrogen contained in the silicon oxide film SiOx or the silicon nitride film SiNx can be diffused to the second active layer ACTL2 through a heat treatment process, and the second electrode CE12 of the first capacitor C1, the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3 can be conductively connected.

[0209] The inorganic film pattern PTN may be disposed at a lower portion of the second electrode CE12 of the first capacitor C1. For example, the inorganic film pattern PTN may be disposed to overlap the second electrode CE12 of the first capacitor C1 between the second interlayer insulating film ILD2 and the second active layer ACTL2.

[0210] The second electrode CE12 of the first capacitor C1 can obtain hydrogen from the third interlayer insulating film ILD3 during the heat treatment process, and can further obtain hydrogen from the inorganic film pattern PTN. For example, the inorganic film pattern PTN may include a silicon oxide film SiOx or a silicon nitride film SiNx having a relatively high hydrogen content. The hydrogen content of the inorganic film pattern PTN may be higher than the hydrogen content of the second gate insulating film GI2 covering the second active layer ACTL2 or the second interlayer insulating film ILD2 configured at the lower part of the second active layer ACTL2. Therefore, the conductivity of the second electrode CE12 of the first capacitor C1 may be higher than the conductivity of the second active layer ACTL2 that does not overlap with the inorganic film pattern PTN. For example, the conductivity of the second electrode CE12 of the first capacitor C1 may be higher than the conductivity of the drain electrode D1 and the source electrode S1 of the first transistor ST1, and the drain electrode D3 and the source electrode S3 of the third transistor ST3. Therefore, the display device 10 can remove the streaks caused by the conductivity deviation of multiple pixels, and the reliability of the display device 10 can be improved.

[0211] The embodiments of the present invention are described above with reference to the accompanying drawings. However, a person with ordinary knowledge in the technical field to which the present invention belongs should understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are examples in all aspects and are not intended to be limiting.

Claims

1. A display device, wherein: include: A first active layer is disposed on the substrate and is composed of a first material; a second active layer, disposed on the first active layer and composed of a second material different from the first material; a first gate layer, disposed on the second active layer; as well as an inorganic film pattern, arranged at a lower portion of the second active layer and overlapping a portion of the first gate layer, The second active layer includes a conductor portion disposed between a portion of the first gate layer and the inorganic film pattern, An upper surface and a side surface of the inorganic film pattern are covered by the second active layer.

2. The display device according to claim 1, wherein: The display device further includes a first gate insulating film for insulating the second active layer from the first gate layer. The inorganic film pattern has a higher hydrogen content than the first gate insulating film.

3. The display device according to claim 1, wherein: Also includes: a second gate layer, disposed on the first active layer; A first interlayer insulating film is disposed on the second gate layer; A third gate layer is arranged on the first interlayer insulating film; as well as a second interlayer insulating film, arranged on the third gate layer; The inorganic film pattern is arranged between the second interlayer insulating film and the conductor portion of the second active layer.

4. The display device according to claim 3, wherein: The inorganic film pattern has a higher hydrogen content than the second interlayer insulating film.

5. The display device according to claim 1, wherein: The conductivity of the conductor portion is higher than the conductivity of a region other than the conductor portion of the second active layer.

6. A display device, wherein: A display panel comprising a plurality of pixels having light emitting elements is provided for driving the display panel. The plurality of pixels respectively include: A driving transistor including an active region arranged in a first active layer composed of a first substance, and controlling a driving current flowing through the light emitting element; A first transistor including an active region configured in a second active layer composed of a second substance different from the first substance, selectively connecting a first node as a drain electrode of the driving transistor and a second node as a gate electrode of the driving transistor; A first scanning line is disposed on a first gate layer on the second active layer and is connected to a gate electrode of the first transistor; and The inorganic film pattern overlaps with the second active layer and the intersection area of ​​the first scanning line.

7. The display device according to claim 6, wherein: The inorganic film pattern is in direct contact with a lower portion of the second active layer, and the second active layer includes a conductor portion disposed between the first scan line and the inorganic film pattern.

8. The display device according to claim 7, wherein: The gate electrode of the driving transistor and the source electrode of the first transistor are electrically connected through the conductor portion of the second active layer.

9. The display device according to claim 7, wherein: The plurality of pixels further include: a second transistor that supplies a data voltage to a third node that is a source electrode of the driving transistor based on a voltage of a second scan line disposed at a second gate layer on the first active layer; and a first capacitor connected between the second scan line and the second node, A first electrode of the first capacitor is disposed on the second gate layer, and a second electrode of the first capacitor is disposed on the second active layer.

10. The display device according to claim 9, wherein: A gate electrode of the driving transistor and the second electrode of the first capacitor are electrically connected through the conductor portion of the second active layer.

11. The display device according to claim 9, wherein: The plurality of pixels further include a second capacitor connected between the second node and the driving voltage line. A first electrode of the second capacitor and a second electrode of the first capacitor are electrically connected via a portion of the conductive second active layer.

12. The display device according to claim 9, wherein: The plurality of pixels also include a first connecting electrode of a source-drain layer configured on the first gate layer, The first connection electrode is connected to the gate electrode of the driving transistor arranged in the second gate layer through a first contact hole, and is connected to the second active layer through a second contact hole.

13. The display device according to claim 9, wherein: The plurality of pixels further include: a third transistor, selectively supplying an initialization voltage to the second node; a fourth transistor selectively supplying a driving voltage to the third node; a fifth transistor that selectively connects the first node to a fourth node that is an anode electrode of the light emitting element; and A sixth transistor selectively supplies the initialization voltage to the fourth node.

14. The display device according to claim 13, wherein: The gate electrode of the third transistor is connected to the third scan line configured in the first gate layer, the gate electrodes of the fourth transistor and the fifth transistor are connected to the light emitting control line configured in the second gate layer, and the gate electrode of the sixth transistor is connected to the second scan line.

15. A display device, wherein: A display panel comprising a plurality of pixels having light emitting elements is provided for driving the display panel. The plurality of pixels respectively include: A driving transistor including an active region arranged in a first active layer composed of a first substance, and controlling a driving current flowing through the light emitting element; A first transistor including an active region configured in a second active layer composed of a second material different from the first material, connecting a first node as a drain electrode of the driving transistor and a second node as a gate electrode of the driving transistor based on a voltage of a first scanning line configured in a first gate layer on the second active layer; a first capacitor including a first electrode and a second electrode, wherein the first electrode corresponds to a portion of a second scanning line disposed on a second gate layer on the first active layer, and the second electrode is connected to the second node and disposed on the second active layer; and an inorganic film pattern, arranged at a lower portion of the second electrode of the first capacitor, The conductivity of the second electrode of the first capacitor is higher than the conductivity of the second active layer which does not overlap with the inorganic film pattern.

16. The display device according to claim 15, wherein: The conductivity of the second electrode of the first capacitor is higher than the conductivity of the source electrode of the first transistor.

17. The display device according to claim 15, wherein: The plurality of pixels also include a second connection electrode of the source-drain layer configured on the first gate layer, The second connection electrode is connected to the gate electrode of the driving transistor arranged in the second gate layer through the third contact hole, and is connected to the second electrode of the first capacitor arranged in the second active layer through the fourth contact hole.

18. The display device according to claim 15, wherein: Each of the plurality of pixels further includes a second transistor for supplying a data voltage to a third node, which is a source electrode of the driving transistor, based on a voltage of the second scan line.

19. The display device according to claim 18, wherein: The plurality of pixels further include a third transistor, respectively, selectively supplying an initialization voltage to the second node, The conductivity of the second electrode of the first capacitor is higher than the conductivity of the source electrode of the third transistor.

20. The display device according to claim 19, wherein: The plurality of pixels further include: a fourth transistor selectively supplying a driving voltage to the third node; a fifth transistor that selectively connects the first node to a fourth node that is an anode electrode of the light emitting element; and A sixth transistor selectively supplies the initialization voltage to the fourth node.

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