Semiconductor device structure

Abstract

The present invention provides a semiconductor device structure, which includes: a semiconductor substrate of a first conductivity type; an epitaxial structure of the first conductivity type, the epitaxial structure including at least two epitaxial unit layers, and at least two layers have different doping concentrations; a trench structure and a column structure of a second conductivity type formed in the trench structure. In the process of preparing the epitaxial structure, the present invention prepares an epitaxial structure including at least two epitaxial unit layers, and at least two layers of the epitaxial unit layers have different doping concentrations, and the morphology of the sidewall of the trench structure formed in the epitaxial structure can be changed based on the setting of the above-mentioned material layer, so that the morphology of the column structure formed in the trench structure can be improved according to actual needs, and the inclination between the sidewall and the bottom of the trench structure can be changed, that is, the inclination between the sidewall and the bottom of the column structure can be changed, thereby improving the problem of rapid change in capacitance caused by it.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device structure. Background Art

[0002] In modern life, electric energy is an economical, practical, clean and controllable energy source. Power devices are playing an increasingly important role in the transmission and conversion of electric energy. Among them, super junction devices have broken through the limitation of high withstand voltage and low resistance in traditional silicon-based high-voltage devices, and have achieved device characteristics of high withstand voltage and excellent conduction at the same time, which is a power device with great application prospects.

[0003] In the process of manufacturing super junction devices, alternating P-type and N-type regions are used to achieve charge balance, improve breakdown voltage and obtain lower on-resistance. In its preparation process, trench etching process is often required. In deep trench process super junction devices, the sidewall and bottom of the trench will form an inclination angle. For example, the P-type silicon pillar formed subsequently will have an inclination angle, causing a sharp change in device capacitance, which will cause electromagnetic oscillation of the circuit system and bring unfavorable factors to the application of super junction devices.

[0004] Therefore, it is necessary to propose a new semiconductor device structure to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device structure to solve the problems in the prior art where the inclination angle at the bottom of the pillar structure causes a sharp change in device capacitance, thereby causing electromagnetic oscillation of the circuit system.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a semiconductor device structure, the semiconductor device structure comprising:

[0007] a semiconductor substrate of a first conductivity type;

[0008] The epitaxial structure of the first conductivity type is formed on the semiconductor substrate and includes at least two epitaxial unit layers, at least two of the epitaxial unit layers have different doping concentrations;

[0009] a trench structure formed in the epitaxial structure;

[0010] A second conductive type pillar structure is formed in the trench structure.

[0011] Optionally, the semiconductor device structure further includes:

[0012] a body region formed in the epitaxial structure and located on top of the pillar structure;

[0013] A gate oxide layer, located on the epitaxial structure, and the gate oxide layer exposes a portion of the body region;

[0014] A gate layer, located on the surface of the gate oxide layer;

[0015] A source region, located in the body region and on a side of the gate oxide layer;

[0016] An interlayer dielectric layer, located on the surface and sidewall of the gate layer and exposing a portion of the source region;

[0017] A front metal electrode is located on the surface of the body region, the source region and the interlayer dielectric layer;

[0018] The back metal electrode is located at a side of the semiconductor substrate away from the epitaxial structure.

[0019] Optionally, the epitaxial structure includes a top structural layer, and the body region is formed in the top structural layer.

[0020] Optionally, the semiconductor device structure further includes a lead-out contact region, wherein the lead-out contact region is formed in the body region and is adjacent to the source region.

[0021] Optionally, the epitaxial structure includes an underlying structural layer, the underlying structural layer is formed on the semiconductor substrate, and the epitaxial unit layer is formed on the underlying structural layer.

[0022] Optionally, the concentration range of each epitaxial unit layer is between 1.9e 15 ~2.3e 15 cm -3 between.

[0023] Optionally, the concentration of each epitaxial unit layer changes linearly from the semiconductor substrate upwards.

[0024] Optionally, the concentration of each epitaxial unit layer increases in an arithmetic progression from the semiconductor substrate upwards.

[0025] Optionally, the angle between the sidewall and the bottom of the groove structure ranges from 87° to 90°.

[0026] Optionally, the depth of the trench structure is between 35 μm and 45 μm, and the thickness of each epitaxial unit layer is between 6 μm and 12 μm.

[0027] As described above, the present invention provides a semiconductor device structure. In the process of preparing an epitaxial structure, an epitaxial structure including at least two epitaxial unit layers is prepared, and at least two of the epitaxial unit layers have different doping concentrations. Through the above design, the morphology of the side wall of the trench structure formed in the epitaxial structure can be changed based on the setting of the above material layer, so that the morphology of the column structure formed in the trench structure can be improved according to actual needs, wherein the inclination between the side wall and the bottom of the trench structure can be changed, that is, the inclination between the side wall and the bottom of the column structure can be changed, thereby improving the problem of rapid change in capacitance caused thereby. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a flow chart of a method for preparing a semiconductor device structure provided in an embodiment of the present invention.

[0029] Figure 2 Shown is a schematic cross-sectional view of a semiconductor substrate provided in an embodiment of the present invention.

[0030] Figure 3 It is a cross-sectional schematic diagram showing the formation of the bottom structure layer and the epitaxial unit layer in an embodiment of the present invention.

[0031] Figure 4 It is a cross-sectional schematic diagram showing the formation of an epitaxial unit layer and a top structure layer in an embodiment of the present invention.

[0032] Figure 5 It is a cross-sectional schematic diagram showing the formation of a trench structure in an embodiment of the present invention.

[0033] Figure 6 It is another cross-sectional schematic diagram showing the formation of a trench structure in an embodiment of the present invention.

[0034] Figure 7 It is a schematic cross-sectional view showing the formation of a pillar structure in an embodiment of the present invention.

[0035] Figure 8 It is a cross-sectional schematic diagram showing the formation of a body region in an embodiment of the present invention.

[0036] Fig. 9 It shows a cross-sectional schematic diagram of forming a gate oxide layer, a gate layer, an interlayer dielectric layer, a source region, a lead-out contact region, a front metal electrode and a back metal electrode in an embodiment of the present invention.

[0037] Fig.10 It is a schematic cross-sectional view of a super junction device structure formed in a comparative example of the present invention.

[0038] FIG. 11( a ) and FIG. 11 ( b ) are graphs showing the capacitance of the superjunction device as a function of the drain-source voltage in the examples of the present invention and the comparative example.

[0039] Component number description

[0040] 101 Semiconductor Substrate

[0041] 102 Epitaxial structure

[0042] 103 underlying structure layer

[0043] 104, 105, 106, 107 epitaxial unit layer

[0044] 108 top structure layer

[0045] 109 Groove structure

[0046] 110 Column Structure

[0047] 111 Body Area

[0048] 112 Gate Oxide

[0049] 113 Gate layer

[0050] 114 interlayer dielectric layer

[0051] 115 Source Area

[0052] 116 Lead-out contact area

[0053] 117 Front metal electrode

[0054] 118 Back metal electrode

[0055] 201 Semiconductor substrate

[0056] 202 epitaxial layer

[0057] 203 Superjunction Trench

[0058] 204 Column Structure

[0059] Steps S1 to S4 DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0062] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0063] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0064] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0065] Embodiment 1:

[0066] like Figure 1-9 As shown, the present invention provides a method for preparing a semiconductor device structure, comprising the following steps:

[0067] providing a semiconductor substrate of a first conductivity type;

[0068] forming an epitaxial structure of a first conductivity type on the semiconductor substrate, wherein the epitaxial structure comprises at least two epitaxial unit layers, and at least two of the epitaxial unit layers have different doping concentrations;

[0069] forming a trench structure in the epitaxial structure;

[0070] A pillar structure of a second conductivity type is formed in the trench structure.

[0071] The method for preparing the semiconductor device structure of the present invention can be carried out according to the above sequence. Of course, it can also be replaced and improved according to conventional methods in the art. The preparation of the semiconductor device structure of the present invention will be described in detail below with reference to the accompanying drawings.

[0072] like Figure 1 S1 and Figure 2 As shown, a semiconductor substrate 101 of a first conductivity type is provided. Figure 2 : is a schematic cross-sectional view of the semiconductor substrate 101. The first conductivity type may be n-type or p-type. In this embodiment, n-type is selected. In one example, the semiconductor substrate 101 is an n-type silicon substrate. Of course, in other implementation cases, the semiconductor substrate 101 may also be a p-type silicon substrate or other semiconductor substrates. In addition, the semiconductor substrate 101 may be a single-layer material structure or a stacked structure composed of multiple material layers, which is selected based on actual conditions.

[0073] like Figure 1 S2 and Figure 3-4 As shown, an epitaxial structure 102 of a first conductivity type is formed on the semiconductor substrate 101. The epitaxial structure includes at least two epitaxial unit layers, for example, Figure 4 104, 105, 106, 107 in the epitaxial unit layer, and at least two layers in the epitaxial unit layer have different doping concentrations. In the present invention, by setting epitaxial unit layers with different doping concentrations to form an epitaxial structure, the morphology of the sidewalls of the trench structure subsequently formed in the epitaxial structure 102 can be changed based on the setting of the above-mentioned material layer, so that the morphology of the column structure formed in the trench structure can be improved according to actual needs. For example, the inclination between the sidewalls and the bottom of the trench structure can be changed, that is, the inclination between the sidewalls and the bottom of the column structure can be changed, and then the morphology of the trench structure and the column structure can be changed to improve the problem of rapid capacitance change caused by them. In one example, its formation method can be as follows Figure 3 , 4 As shown, an epitaxial unit layer 104 , an epitaxial unit layer 105 , an epitaxial unit layer 106 and an epitaxial unit layer 107 are epitaxially formed in sequence on the semiconductor substrate 101 , and each of the epitaxial unit layers can be formed by epitaxial growth.

[0074] As an example, the concentration range of each epitaxial unit layer is between 1.9e 15 ~2.3e 15 cm -3 The specific selection can be made according to the actual situation to meet the needs of super junction device preparation. For example, 2.0e 15 cm -3 , 2.1e 15 cm -3 , 2.2e 15 cm -3. Among them, doping can be performed while each of the epitaxial unit layers is being prepared, or doping can be performed after one epitaxial unit layer is prepared, and the next epitaxial unit layer is formed after doping is completed. When the doping concentrations of the two epitaxial unit layers are different, the doping concentrations of the other epitaxial unit layers can be the same or different. In addition, the material of the epitaxial unit layer includes but is not limited to silicon, forming silicon-doped epitaxial unit layers of different concentrations. In this embodiment, each epitaxial unit layer is selected to be n-type to constitute an n-type epitaxial structure 102. As an example, the thickness of each epitaxial unit layer is between 6μm-12μm, for example, it can be 8μm or 10μm.

[0075] As an example, the concentration of each epitaxial unit layer changes linearly from the semiconductor substrate 101 upward. For example, it can be increasing or decreasing from the semiconductor substrate 101 upward. By setting the concentration change of each epitaxial unit layer, the side wall of the subsequently formed trench structure can be changed. For example, the trench structure formed in the epitaxial structure with a single concentration generally presents an inverted trapezoid. Through the above design, the angle between the side wall of the trench structure and the bottom can be reduced while ensuring the straightness of the side wall of the trench structure. Fig. 9 As shown in α, the sidewall is even perpendicular to the bottom, thereby improving the problem of rapid changes in device capacitance caused by the inclined sidewall of the inverted trapezoid, alleviating the electromagnetic oscillation of the circuit system caused by this, and further facilitating the application of superjunction devices. In one example, the concentration of each layer of the epitaxial unit layer is linearly increased from the semiconductor substrate 101 upward, and can be optionally set to increase in an arithmetic progression. Based on the linear increase method, a basically vertical groove structure can be obtained. For example, the angle between the sidewall and the bottom of the groove structure ranges from 87° to 90°, that is, Fig. 9 The angle α is between 87° and 90°, where 87° and 90° are included. For example, the angle may be 88°, 88.5° or 89°.

[0076] As an example, the step of forming the epitaxial structure 102 further includes: forming a top structure layer 108 on the epitaxial unit layer at the top layer, and further, the structure such as the body region formed subsequently can be formed in the top structure layer 108. The material of the top structure layer 108 can be consistent with the material of each epitaxial unit layer, and the concentration can be set according to the device requirements. For example, the doping concentration can be adjusted according to the device requirements to prevent short circuits between the body regions 111. In addition, in an optional example, the step of forming the epitaxial structure 102 further includes: forming a bottom structure layer 103 on the semiconductor substrate 101, and then forming each epitaxial unit layer on the bottom structure layer 103. In a further optional example, the bottom of the groove structure formed subsequently stops in the bottom structure layer 103, that is, the bottom of the groove structure is higher than the lower surface of the bottom structure layer 103 and lower than the upper surface of the bottom structure layer 103. The thickness of the bottom structure layer 103 can be set to be greater than the layer with the largest thickness among the epitaxial unit layers, and the material can be consistent with the material of the epitaxial unit layers. Of course, when the bottom structure layer 103 and the top structure layer 108 are not included in the formation process of the epitaxial structure 102, the bottom of the trench structure can be stopped in any of the epitaxial unit layers, preferably in the bottom epitaxial unit layer. In addition, the body region and other structures formed subsequently can also be directly prepared in the top epitaxial unit layer.

[0077] like Figure 1 S3 and Figure 5-6 As shown, a trench structure 109 is formed in the epitaxial structure 102. For example, a dry etching process can be used. In one example, the present invention is used to dope the epitaxial unit layers of the same material with different concentrations to improve the sidewall formation of the trench structure, so that the trench structure of the present invention can be formed by etching using a conventional trench etching process for a single epitaxial structure, thereby simplifying the process design. Figure 5 and Figure 6 It is a cross-sectional schematic diagram after the trench structure 109 is formed. Figure 6 The schematic cross-sectional view of the completed trench structure 109 is shown. Based on the design of the epitaxial structure 102 of the present invention, the inclination of the sidewall of the trench structure 109 relative to the bottom can be reduced. For example, in one example, the cross-sectional shape of the trench structure 109 is an inverted trapezoid. Further, the cross-sectional shape of the trench structure 109 is a rectangle. Optionally, the angle between the sidewall and the bottom of the trench structure ranges from 87° to 90°, and can be 88°, 88.5° or 89°.

[0078] As an example, the depth of the trench structure is between 35 μm and 45 μm, for example, 38 μm, 40 μm or 42 μm; the thickness of each epitaxial unit layer is between 6 μm and 12 μm, for example, 8 μm or 10 μm.

[0079] like Figure 1 S4 and Figure 7 As shown, a column structure 110 of a second conductive type is formed in the trench structure 109. The second conductive type may be n-type or p-type. In this embodiment, the first conductive type is selected as n-type and the second conductive type is selected as p-type. The material of the column structure 110 includes silicon. Optionally, there are multiple column structures 110, and the multiple column structures 110 have the same width and are arranged at equal intervals in the epitaxial structure 102. In actual super junction devices, hundreds to thousands of column structures are generally arranged in an array with equal intervals. In one example, the width of the column structure 110 and the spacing between the column structures 110 have an important influence on the withstand voltage and other performances of the super junction device. The column structures 110 are designed to have the same width and the same spacing, that is, to have a uniform pitch size. In an optional example, in the array in which the column structures 110 are arranged, the spacing between the column structures 110 is set to be greater than the width of the column structure 110. For example, the width can be set to 5 microns, and the spacing can be set to 6 microns.

[0080] As an example, Figure 8-9 As shown, after the column structure is formed, the following steps are also included:

[0081] First, if Figure 8 As shown, a body region 111 is formed by ion implantation at the top of the column structure 110. As an example, a patterned photoresist layer is used as an ion implantation mask to perform local ion implantation at the top region of the column structure 110, and the body region 111 of the second conductivity type (such as p-type) is formed. In addition, in an optional example, an annealing process can be applied after the ion implantation process to adjust the impurity distribution and diffusion range and repair the lattice damage caused by the ion implantation.

[0082] Then, if Fig. 9 As shown, a gate oxide layer 112 is formed on the epitaxial structure 102, and the gate oxide layer 112 exposes a portion of the body region 111. As an example, a thermal oxide layer can be formed on the upper surface of the epitaxial structure 102 by a furnace process, and a patterned gate oxide layer 112 can be formed by photolithography and etching processes. Optionally, the thickness of the gate oxide layer 112 is between 50-150nm, for example, 80nm, 100nm, 120nm, etc. can be selected.

[0083] Next, continue to refer to Fig. 9 As shown, a gate layer 113 is formed on the gate oxide layer 112; as an example, a polysilicon material layer is first deposited on the gate oxide layer 112 by chemical vapor deposition, and then a patterned polysilicon gate is formed by photolithography and etching to form the gate layer 113. It should be pointed out that the process of forming the gate oxide layer 112 and the gate layer 113 can also be to first form a thermal oxide layer, deposit a polysilicon material layer on the thermal oxide layer, and then define a patterned photoresist mask layer by photolithography, and etch the polysilicon material layer and the thermal oxide layer in sequence, and finally form the gate oxide layer 112 and the gate layer 113. Optionally, the thickness of the gate layer 113 is between 300-500nm, for example, it can be selected to be 350nm, 400nm, 450nm, etc.

[0084] Next, continue to refer to Fig. 9 As shown, a source region 115 is formed in the body region 111 by ion implantation, and the source region 115 is formed on the side of the gate oxide layer 112; as an example, the source region 115 is of the first conductivity type (such as n-type), and the source region 115 can also be locally ion implanted on the body region 111 through a patterned photoresist layer as an ion implantation mask, and finally the source region 115 is formed.

[0085] Next, continue to refer to Fig. 9 As shown, an interlayer dielectric layer 114 is formed on the surface and sidewall of the gate layer 113, and the interlayer dielectric layer 114 exposes a portion of the source region 115. As an example, the interlayer dielectric layer 114 may be a silicon dioxide layer, a silicon nitride layer, or a combination of the two. The process of forming the interlayer dielectric layer 114 may be to first deposit a dielectric material layer on the surface and sidewall of the body region 111, the source region 115, and the gate layer 113, and then remove the dielectric material layer on the body region 111 and the source region 115 by etching, and finally obtain the interlayer dielectric layer 114 covering and wrapping the gate layer 113 and the sidewall of the gate oxide layer 112.

[0086] Next, continue to refer to Fig. 9 As shown, a front metal electrode 117 is formed on the surface of the body region 111, the source region 115 and the interlayer dielectric layer 114. As an example, the material constituting the front metal electrode 117 includes a metal material such as aluminum, gold, silver or copper. The method of forming the front metal electrode 117 includes physical vapor deposition or chemical vapor deposition. Optionally, after the metal is deposited, a pattern such as a metal connection can also be defined by photolithography.

[0087] Finally, continue to refer to Fig. 9As shown, a back metal electrode 118 is formed on the side of the semiconductor substrate 101 away from the epitaxial junction 102. The method for forming the back metal electrode 118 is the same as the method for forming the front metal electrode 117. Optionally, before forming the back metal electrode 118 on the semiconductor substrate 101, the step of thinning and grinding the semiconductor substrate 101 is also included to obtain the substrate thickness required by the device.

[0088] As an example, after forming the body region 111, the step of forming the lead-out contact region 116 in the body region 111 is also included, and the lead-out contact region 116 is adjacent to the source region 115. As an example, the lead-out contact region 116 has the second conductivity type, such as p-type, and optionally, the doping concentration of the lead-out contact region 116 is greater than the doping concentration of the body region 111, and the lead-out contact region 116 is in contact with the formed front metal electrode 117 to improve contact characteristics.

[0089] It should be pointed out that in order to clearly describe the steps of the preparation method, the steps are numbered in this embodiment, but this does not limit the specific implementation order of the steps of the preparation method described in the present invention. Those skilled in the art can adjust the implementation order according to actual conditions.

[0090] Embodiment 2

[0091] like Fig. 9 See Figure 1-8 As shown, the present invention further provides a semiconductor device structure, which is preferably prepared by the preparation process of the semiconductor device structure in the first embodiment of the present invention. Of course, it can also be prepared by other processes. The description of the corresponding structure in this embodiment can refer to the first embodiment, and will not be repeated here. The semiconductor device structure includes:

[0092] A semiconductor substrate 101 of a first conductivity type;

[0093] The first conductivity type may be n-type or p-type. In this embodiment, n-type is selected. In one example, the semiconductor substrate 101 is an n-type silicon substrate. Of course, in other implementation cases, the semiconductor substrate 101 may also be a p-type silicon substrate or other semiconductor substrates. In addition, the semiconductor substrate 101 may be a single-layer material structure or a stacked structure composed of multiple material layers, which is selected according to actual conditions.

[0094] The epitaxial structure 102 of the first conductivity type is formed on the semiconductor substrate 101, and the epitaxial structure 102 includes at least two epitaxial unit layers, for example, 104, 105, 106, and 107, and at least two of the epitaxial unit layers have different doping concentrations;

[0095] In the present invention, by setting epitaxial unit layers with different doping concentrations to form an epitaxial structure, the morphology of the side walls of the trench structure subsequently formed in the epitaxial structure 102 can be changed based on the setting of the above-mentioned material layer, so that the morphology of the column structure formed in the trench structure can be improved according to actual needs. For example, the inclination between the side walls and the bottom of the trench structure can be changed, that is, the inclination between the side walls and the bottom of the column structure can be changed, and then the problem of rapid changes in capacitance caused by them can be improved by changing the morphology of the trench structure and the column structure.

[0096] As an example, the concentration range of each epitaxial unit layer is between 1.9e 15 ~2.3e 15 cm -3 The specific selection can be made according to the actual situation to meet the needs of super junction device preparation. For example, 2.0e 15 cm -3 , 2.1e 15 cm -3 , 2.2e 15 cm -3 . In the case where the doping concentrations of two epitaxial unit layers are different, the doping concentrations of the other epitaxial unit layers may be the same or different. In addition, the material of the epitaxial unit layer includes but is not limited to silicon, forming epitaxial unit layers with different concentrations of silicon doping. In this embodiment, each epitaxial unit layer is selected to be n-type to form an n-type epitaxial structure 102. As an example, the thickness of each epitaxial unit layer is between 6μm-12μm, for example, it can be 8μm or 10μm.

[0097] A trench structure 109 formed in the epitaxial structure 102;

[0098] A second conductivity type pillar structure 110 is formed in the trench structure 109 .

[0099] A column structure 110 of a second conductive type is formed in the trench structure 109. The second conductive type may be n-type or p-type. In this embodiment, the first conductive type is selected as n-type and the second conductive type is selected as p-type. The material of the column structure 110 includes silicon. Optionally, there are multiple column structures 110, and the multiple column structures 110 have the same width and are arranged at equal intervals in the epitaxial structure 102. In actual super junction devices, hundreds to thousands of column structures are generally arranged in an array with equal intervals. In one example, the width of the column structure 110 and the spacing between the column structures 110 have an important influence on the withstand voltage and other performances of the super junction device. The column structures 110 are designed to have the same width and the same spacing, that is, to have a uniform pitch size. In an optional example, in the array in which the column structures 110 are arranged, the spacing between the column structures 110 is set to be greater than the width of the column structure 110. For example, the width can be set to 5 microns, and the spacing can be set to 6 microns.

[0100] As an example, the semiconductor device structure further includes:

[0101] A body region 111 formed in the epitaxial structure 102 and located on the top of the pillar structure 110;

[0102] A gate oxide layer 112 is located on the epitaxial structure 102 , and the gate oxide layer 112 exposes a portion of the body region 111 ;

[0103] A gate layer 113 is located on the surface of the gate oxide layer 112;

[0104] A source region 115 , located in the body region 111 and on a side of the gate oxide layer 112 ;

[0105] An interlayer dielectric layer 114 is located on the surface and sidewall of the gate layer 113 and exposes a portion of the source region 115;

[0106] A front metal electrode 117 is located on the surface of the body region 111 , the source region 115 and the interlayer dielectric layer 114 ;

[0107] The back metal electrode 118 is located on a side of the semiconductor substrate 101 away from the epitaxial structure 102 .

[0108] As an example, the epitaxial structure includes a top structural layer 108 , and the body region is formed in the top structural layer 108 .

[0109] As an example, the epitaxial structure includes an underlying structural layer 103 , wherein the underlying structural layer 103 is formed on the semiconductor substrate 101 , and the epitaxial unit layer is formed on the underlying structural layer 103 .

[0110] As an example, the step of forming the epitaxial structure 102 further includes: forming a top structure layer 108 on the epitaxial unit layer at the top layer, and further, the structure such as the body region formed subsequently can be formed in the top structure layer 108. The material of the top structure layer 108 can be consistent with the material of each epitaxial unit layer, and the concentration can be set according to the device requirements. For example, the doping concentration can be adjusted according to the device requirements to prevent short circuits between the body regions 111. In addition, in an optional example, the step of forming the epitaxial structure 102 further includes: forming a bottom structure layer 103 on the semiconductor substrate 101, and then forming each epitaxial unit layer on the bottom structure layer 103. In a further optional example, the bottom of the groove structure formed subsequently stops in the bottom structure layer 103, that is, the bottom of the groove structure is higher than the lower surface of the bottom structure layer 103 and lower than the upper surface of the bottom structure layer 103. The thickness of the bottom structure layer 103 can be set to be greater than the layer with the largest thickness among the epitaxial unit layers, and the material can be consistent with the material of the epitaxial unit layers. Of course, when the bottom structure layer 103 and the top structure layer 108 are not included in the formation process of the epitaxial structure 102, the bottom of the trench structure can be stopped in any of the epitaxial unit layers, preferably in the bottom epitaxial unit layer. In addition, the body region and other structures formed subsequently can also be directly prepared in the top epitaxial unit layer.

[0111] As an example, the semiconductor device structure further includes a lead-out contact region 116 , which is formed in the body region 111 and is adjacent to the source region 115 .

[0112] As an example, the concentration range of each epitaxial unit layer is between 1.9e 15 ~2.3e 15 cm -3 between.

[0113] As an example, the concentration of each epitaxial unit layer changes linearly from the semiconductor substrate upward.

[0114] As an example, the angle between the sidewall and the bottom of the groove structure ranges from 87° to 90°, and may be 88°, 88.5° or 89°.

[0115] As an example, the concentration of each epitaxial unit layer changes linearly from the semiconductor substrate 101 upward. For example, it can be increasing or decreasing from the semiconductor substrate 101 upward. By setting the concentration change of each epitaxial unit layer, the side wall of the subsequently formed trench structure can be changed. For example, the trench structure formed in the epitaxial structure with a single concentration generally presents an inverted trapezoid. Through the above design, the angle between the side wall of the trench structure and the bottom can be reduced while ensuring the straightness of the side wall of the trench structure. Fig. 9 As shown in α, the sidewall is even perpendicular to the bottom, thereby improving the problem of rapid changes in device capacitance caused by the inclined sidewall of the inverted trapezoid, alleviating the electromagnetic oscillation of the circuit system caused by this, and further facilitating the application of superjunction devices. In one example, the concentration of each layer of the epitaxial unit layer is linearly increased from the semiconductor substrate 101 upward, and can be optionally set to increase in an arithmetic progression. Based on the linear increase method, a basically vertical groove structure can be obtained. For example, the angle between the sidewall and the bottom of the groove structure ranges from 87° to 90°, that is, Fig. 9 The medium α is between 87°-90° and can be 88°, 88.5° or 89°.

[0116] As an example, the depth of the trench structure is between 35 μm and 45 μm, for example, 38 μm, 40 μm or 42 μm; the thickness of each epitaxial unit layer is between 6 μm and 12 μm, for example, 8 μm or 10 μm.

[0117] Comparative Example

[0118] like Fig.10As shown, the present invention also provides a pair of ratios, in which an epitaxial layer 202 is formed on a semiconductor substrate 201, a super junction trench 203 is formed in the epitaxial layer 202, and a pillar structure 204 is formed in the super junction trench 203, wherein the epitaxial layer 202 has a first conductivity type, the pillar structure 204 has a second conductivity type, and other structures can be set to be consistent with the embodiments of the present invention. In this comparative example, it is difficult to ensure that the width of the etched trench of the deep trench etching (etching of the super junction trench 203) is consistent from top to bottom, showing the characteristics of being wide at the top and narrow at the bottom, that is, the etching has a large angle. Referring to FIG11 , a graph showing the variation of capacitance of a super junction device with drain-source voltage is plotted, wherein the dotted circle in FIG11( a) represents a schematic diagram of the above-mentioned variation of a super junction device having a groove with a large inclination angle formed by a single epitaxial layer in the comparative example, and the dotted circle in FIG11( b) represents a schematic diagram of the above-mentioned variation of a super junction device formed by an epitaxial structure designed by the present invention. It can be seen from the figure that the drastic variation of capacitance in the comparative example will cause electromagnetic oscillation of the circuit system, bringing adverse factors to the application of super junction devices; however, the above-mentioned situation is significantly improved by adopting the solution of the present invention.

[0119] In summary, the present invention provides a super junction device structure. In the process of preparing an epitaxial structure, an epitaxial structure including at least two epitaxial unit layers is prepared, and at least two of the epitaxial unit layers have different doping concentrations. Through the above design, the morphology of the side wall of the trench structure formed in the epitaxial structure can be changed based on the setting of the above material layer, so that the morphology of the column structure formed in the trench structure can be improved according to actual needs, wherein the inclination between the side wall and the bottom of the trench structure can be changed, that is, the inclination between the side wall and the bottom of the column structure can be changed, and then the morphology of the trench structure and the column structure can be changed to improve the problem of sharp changes in capacitance caused by them.

[0120] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor device structure, characterized in that: The semiconductor device structure comprises: a semiconductor substrate of a first conductivity type; The epitaxial structure of the first conductivity type is formed on the semiconductor substrate and includes at least two epitaxial unit layers, at least two of the epitaxial unit layers have different doping concentrations, and the doping concentrations of the epitaxial unit layers decrease in sequence from the semiconductor substrate upward; A trench structure is formed in the epitaxial structure; the concentration change of each epitaxial unit layer is used to change the side wall of the formed trench structure and reduce the angle between the side wall and the bottom of the trench structure; A second conductive type pillar structure is formed in the trench structure.

2. The semiconductor device structure according to claim 1, characterized in that: The semiconductor device structure also includes: a body region formed in the epitaxial structure and located on top of the pillar structure; A gate oxide layer, located on the epitaxial structure, and the gate oxide layer exposes a portion of the body region; A gate layer, located on the surface of the gate oxide layer; A source region, located in the body region and on a side of the gate oxide layer; An interlayer dielectric layer, located on the surface and sidewall of the gate layer and exposing a portion of the source region; A front metal electrode is located on the surface of the body region, the source region and the interlayer dielectric layer; The back metal electrode is located at a side of the semiconductor substrate away from the epitaxial structure.

3. The semiconductor device structure according to claim 2, characterized in that: The epitaxial structure includes a top structural layer, and the body region is formed in the top structural layer.

4. The semiconductor device structure according to claim 2, characterized in that: The semiconductor device structure further includes a lead-out contact region formed in the body region and adjacent to the source region.

5. The semiconductor device structure according to claim 1, characterized in that: The epitaxial structure comprises an underlying structural layer, wherein the underlying structural layer is formed on the semiconductor substrate, and the epitaxial unit layer is formed on the underlying structural layer.

6. The semiconductor device structure according to claim 1, characterized in that: The concentration range of each epitaxial unit layer is between 1.9e 15 ~2.3e 15 cm -3 between.

7. The semiconductor device structure according to any one of claims 1 to 6, characterized in that: The angle between the sidewall and the bottom of the groove structure ranges from 87° to 90°.

8. The semiconductor device structure according to claim 7, characterized in that: The depth of the trench structure is between 35 μm and 45 μm, and the thickness of each epitaxial unit layer is between 6 μm and 12 μm.

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