Semiconductor Structure and Method for Forming the Semiconductor Structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure. The structure includes: a substrate; a gate structure located on the substrate; a dielectric structure located on the substrate, the dielectric structure covering the gate structure; a first conductive plug located within the dielectric structure, the first conductive plug being located on one or both sides of the gate structure; an opening located within the dielectric structure, the opening exposing the gate structure; and a first dielectric layer located at the top of the opening, the first dielectric layer closing the opening. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] As the technology node of semiconductor processes continues to decrease, the size of semiconductor structures becomes smaller and smaller, and the space on both sides of the gate structure also needs to be reduced to increase the density of semiconductor structure units. However, the thinning of the sidewalls between the gate structure and the via plug increases the parasitic capacitance between the gate structure and the via plug, reduces the read / write speed, and increases the interference to the data of the memory cell during read / write operations.

[0003] To reduce the parasitic capacitance and improve the read / write speed, fabricating an air gap between the gate structure and the via plug is a very effective method.

[0004] However, the existing methods for fabricating air gaps still need to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure to improve the method for fabricating an air gap and the performance of the semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; a dielectric structure located on the substrate, the dielectric structure covering the gate structure; a first conductive plug located within the dielectric structure, the first conductive plug being located on one side or both sides of the gate structure; an opening located within the dielectric structure, the opening exposing the gate structure; a first dielectric layer located at the top of the opening, the first dielectric layer closing the opening into a sealed cavity.

[0007] Optionally, the opening includes a first opening, the first opening being located between the first conductive plug and the gate structure.

[0008] Optionally, it further includes: a first dielectric layer located at the top of the first opening, the first dielectric layer closing the first opening into a first sealed cavity.

[0009] Optionally, the aspect ratio range of the first opening is: 5 to 20.

[0010] Optionally, the opening further includes a second opening, the second opening being located within the third dielectric layer, the second opening exposing a part of the top surface of the gate structure.

[0011] Optionally, it further includes: a first dielectric layer located within the second opening, the first dielectric layer closing the second opening into a second sealed cavity.

[0012] Optionally, the aspect ratio of the second opening ranges from 10 to 30.

[0013] Optionally, the dielectric structure includes a second dielectric layer and a third dielectric layer located on the second dielectric layer. The second dielectric layer is located on the sidewall surface of the gate structure, and the third dielectric layer is located on the top surface of the gate structure.

[0014] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the gate structure is located within the second dielectric layer.

[0015] Optionally, the dielectric constant of the gate dielectric layer material is greater than 3.7. The material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0016] Optionally, it further includes: a transition layer located on the substrate, the gate dielectric layer is located on the surface of the transition layer; a work function layer located on the gate dielectric layer, and the gate layer is located on the surface of the work function layer.

[0017] Optionally, it further includes: a second conductive plug located within the dielectric structure, and the second conductive plug is electrically connected to the top of the gate structure.

[0018] Optionally, it further includes: a fourth dielectric layer located on the top surface of the dielectric structure and the top surface of the first dielectric layer; a first metal layer located within the fourth dielectric layer, and the first metal layer is electrically connected to the second conductive plug.

[0019] Optionally, it further includes: source / drain doping regions located within the substrate on both sides of the gate structure; the first conductive plug is electrically connected to the source / drain doping regions.

[0020] Optionally, the substrate includes a base and a plurality of fin structures located on the base; the gate structure spans across the plurality of fin structures.

[0021] Optionally, the material of the first dielectric layer includes a dielectric material, and the dielectric material includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0022] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a gate structure, a sacrificial sidewall, and a dielectric structure on the substrate, where the sacrificial sidewall is located on the sidewall surface of the gate structure, and the dielectric structure is located on the substrate and on the surface of the sacrificial sidewall; forming a first conductive plug in the dielectric structure, where the first conductive plug is located on one side or both sides of the gate structure; removing the sacrificial sidewall, and forming an opening in the dielectric structure, where the opening exposes the gate structure; forming a first dielectric layer on the top of the opening, and the first dielectric layer seals the opening into a closed cavity.

[0023] Optionally, the dielectric structure includes a second dielectric layer, and the second dielectric layer is located on the sidewall surface of the gate structure.

[0024] Optionally, the opening includes a first opening, the first opening is located between the first conductive plug and the gate structure, and the first opening is located in the second dielectric layer.

[0025] Optionally, it further includes: forming a first dielectric layer on the top of the first opening, and the first dielectric layer seals the first opening into a first closed cavity.

[0026] Optionally, the aspect ratio range of the first opening is: 5 to 20.

[0027] Optionally, the dielectric structure further includes: a third dielectric layer located on the surface of the second dielectric layer.

[0028] Optionally, the opening further includes a second opening, the second opening is located in the third dielectric layer, and the second opening exposes the top surface of the sacrificial sidewall and a part of the top surface of the gate structure.

[0029] Optionally, it further includes: forming a first dielectric layer in the second opening, and the first dielectric layer seals the second opening into a second closed cavity.

[0030] Optionally, the aspect ratio range of the second opening is: 10 to 30.

[0031] Optionally, the process for forming the first dielectric layer includes a chemical vapor deposition process.

[0032] Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0033] Optionally, the dielectric constant of the gate dielectric layer material is greater than 3.7, the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0034] Optionally, the method for forming the gate structure includes: forming a dummy gate structure on a substrate; forming sacrificial sidewalls on the sidewalls of the dummy gate structure; forming a second dielectric layer on the substrate, the second dielectric layer exposing the top surface of the dummy gate structure and the top surface of the sacrificial sidewalls; removing the dummy gate structure to form a gate opening in the second dielectric layer; and forming a gate structure in the gate opening.

[0035] Optionally, it further includes: a transition layer located on the substrate, the gate dielectric layer being located on the surface of the transition layer; a work function layer located on the gate dielectric layer, the gate layer being located on the surface of the work function layer.

[0036] Optionally, it further includes: forming a protective layer on the top surface of the gate structure; and removing the protective layer while removing the sacrificial sidewalls.

[0037] Optionally, the method for forming the protective layer includes: after forming the gate structure, performing a re-etching on the gate layer to form a groove in the second dielectric layer; and forming the protective layer in the groove.

[0038] Optionally, the material of the protective layer is the same as the material of the sacrificial sidewalls.

[0039] Optionally, the material of the protective layer includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0040] Optionally, before removing the sacrificial sidewalls, it further includes: forming a second conductive plug in the dielectric structure, the second conductive plug being electrically connected to the top of the gate structure.

[0041] Optionally, after forming the first dielectric layer, it further includes: forming a fourth dielectric layer on the top surface of the dielectric structure and the top surface of the first dielectric layer; and forming a first metal layer in the fourth dielectric layer, the first metal layer being electrically connected to the second conductive plug.

[0042] Optionally, before forming the dielectric structure on the substrate, it further includes: forming source / drain doping regions in the substrate on both sides of the gate structure; the first conductive plug being electrically connected to the source / drain doping regions.

[0043] Optionally, the substrate includes a substrate and a plurality of fin structures located on the substrate; the gate structure straddles the plurality of fin structures.

[0044] Optionally, the process for removing the sacrificial sidewalls includes one or a combination of more of a dry etching process or a wet etching process.

[0045] Optionally, the material of the first dielectric layer includes a dielectric material, and the dielectric material includes one or a combination of more than one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0046] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0047] For the semiconductor structure of the technical solution of the present invention, the first dielectric layer closes the opening into a sealed cavity, and the sealed cavity has a small dielectric constant, so that the parasitic capacitance of the semiconductor structure is reduced, thereby improving the performance of the semiconductor structure.

[0048] Further, the opening includes a first opening located between the first conductive plug and the gate structure. The first dielectric layer closes the first opening into a first sealed cavity, and the first sealed cavity has a small dielectric constant, so that the parasitic capacitance between the first conductive plug and the gate structure is reduced, thereby improving the performance of the semiconductor structure.

[0049] Further, the opening further includes a second opening that exposes a part of the top surface of the gate structure. The first dielectric layer closes the second opening into a second sealed cavity, and the second sealed cavity has a small dielectric constant, so that when a first metal layer is formed in a fourth dielectric layer on the top surface of the dielectric structure subsequently, the parasitic capacitance between the first metal layer and the gate structure is reduced, thereby improving the performance of the semiconductor structure.

[0050] For the method of forming a semiconductor structure of the technical solution of the present invention, a first conductive plug is first formed in a dielectric structure. The first conductive plug is located on one or both sides of the gate structure. Then, the sacrificial sidewall is removed to form an opening in the dielectric structure, and the opening exposes the gate structure. Then, a first dielectric layer is formed on the top of the opening. The first dielectric layer closes the first opening into a sealed cavity, and the sealed cavity has a small dielectric constant, so that the parasitic capacitance of the semiconductor structure is reduced. The sealed cavity formed by this method has a good isolation effect, avoiding the situation that when the sealed cavity is formed first and then the first conductive plug is formed, the material of the first conductive plug penetrates into the sealed cavity and affects the isolation effect of the sealed cavity.

[0051] Further, the opening includes a first opening located between the first conductive plug and the gate structure. The first dielectric layer seals the first opening to form a first sealed cavity with a relatively small dielectric constant, thereby reducing the parasitic capacitance between the first conductive plug and the gate structure and improving the performance of the semiconductor structure. The first sealed cavity formed by the method has a good isolation effect, avoiding the situation where the material of the first conductive plug penetrates into the first sealed cavity when the sealed cavity is formed first and then the first conductive plug is formed, which affects the isolation effect of the first sealed cavity.

[0052] Further, the opening further includes a second opening. A first dielectric layer is formed in the second opening, and the first dielectric layer seals the second opening to form a second sealed cavity with a relatively small dielectric constant, thereby reducing the parasitic capacitance between the first metal layer formed in the fourth dielectric layer and the gate structure subsequently and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figures 1 to 3 is a schematic cross-sectional structure diagram of the formation process of a semiconductor structure in an embodiment;

[0054] Figures 4 to 14 is a schematic cross-sectional structure diagram of the formation process of a semiconductor structure in an embodiment of the present invention;

[0055] Figures 15 to 18 is a schematic cross-sectional structure diagram of the formation process of a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] As described in the background art, the existing methods for preparing air gaps still need to be improved. Specific embodiments are now combined for analysis and explanation.

[0057] Figures 1 to 3 is a schematic structure diagram of the formation process of a semiconductor structure in an embodiment.

[0058] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 has fin structures 101; a dummy gate structure 103 is formed on the substrate 100; an initial spacer 104 is formed on the sidewalls of the dummy gate structure 103; source / drain doping regions 102 are formed in the fin structures 101 on both sides of the gate structure 103; a first dielectric layer 105 is formed on the substrate 100, and the gate structure 103 is located within the first dielectric layer 105.

[0059] Please refer to Figure 2 , the initial spacer 104 is removed, and an opening (not shown) is formed in the first dielectric layer 105; a spacer 106 is formed in the opening, and the spacer 106 seals the opening to form a sealed cavity.

[0060] Please refer to Figure 3 , remove the dummy gate structure 103, and form a gate opening (not shown) in the first dielectric layer 105; form a gate structure 107 in the gate opening; after forming the gate structure 107, form a second dielectric layer 108 on the first dielectric layer 105; form a gate plug 109 in the second dielectric layer 108, and the gate plug 109 is electrically connected to the top of the gate structure 107; form source / drain plugs 110 in the first dielectric layer 105 and the second dielectric layer 108, and the source / drain plugs 110 are electrically connected to the source / drain doping regions 102.

[0061] During the formation process of the semiconductor structure, after forming the sidewall 106, the sidewall 106 closes the opening into a sealed cavity, and the sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the formed source / drain plugs 110 and the gate structure 107 is reduced.

[0062] However, as the size of the semiconductor structure is further reduced, the distance between the source / drain plugs 110 and the gate structure 107 is also getting smaller and smaller. When forming the source / drain plugs 110, it is necessary to etch the first dielectric layer 105 and the second dielectric layer 108 to form grooves in the first dielectric layer 105 and the second dielectric layer 108. Due to the small distance between the source / drain plugs 110 and the gate structure 107, during the etching process of the first dielectric layer 105 and the second dielectric layer 108, over-etching may occur, so that the grooves communicate with the sealed cavity, and the material of the source / drain plugs formed in the grooves subsequently will also fill into the sealed cavity, thereby increasing the parasitic capacitance of the semiconductor structure and affecting the performance of the semiconductor structure.

[0063] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure. By first forming a first conductive plug in the dielectric structure, the first conductive plug is located on one side or both sides of the gate structure, then removing the sacrificial sidewall, forming a first opening in the dielectric structure, the first opening is located between the gate structure and the first conductive plug, and then forming a first dielectric layer on the top of the first opening, the first dielectric layer closes the first opening into a first sealed cavity, and the first sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first conductive plug and the gate structure is reduced. The first sealed cavity formed by the method has a good isolation effect, avoiding the situation that when the first sealed cavity is formed first and then the first conductive plug is formed, the material of the first conductive plug penetrates into the first sealed cavity and affects the isolation effect of the first sealed cavity.

[0064] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0065] Figures 4 to 14 It is a schematic cross-sectional structure diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0066] Please refer to Figure 4 , a substrate is provided.

[0067] The substrate includes: a substrate 200; fin structures 201 located on the substrate 200; an isolation layer (not shown) located on the surface of the substrate 200 and the sidewall surfaces of several fin structures 201, and the top surface of the isolation layer is lower than the top surface of the fin structures 201.

[0068] In this embodiment, the material of the substrate 200 is single-crystalline silicon; the material of the fin structures 201 includes single-crystalline silicon.

[0069] In other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, silicon on insulator or germanium on insulator; the fin structures may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, silicon on insulator or germanium on insulator.

[0070] The material of the isolation layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride and silicon carbonitride. In this embodiment, the material of the isolation layer includes silicon oxide.

[0071] In other embodiments, the substrate is a planar substrate.

[0072] Please refer to Figure 5 , a gate structure 203, a sacrificial sidewall 204 and a dielectric structure are formed on the substrate. The gate structure 203 straddles the several fin structures 201, the sacrificial sidewall 204 is located on the sidewall surface of the gate structure 203, and the dielectric structure is located on the substrate and on the surface of the sacrificial sidewall 204.

[0073] In this embodiment, it further includes: source / drain doping regions 202 are formed in the fin structures 201 on both sides of the gate structure 203.

[0074] The gate structure 203 includes a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer.

[0075] In this embodiment, the gate structure 203 further includes: a transition layer (not shown) located on the substrate, the gate dielectric layer is located on the surface of the transition layer; a work function layer (not shown) located on the gate dielectric layer, and the gate layer is located on the surface of the work function layer.

[0076] The dielectric constant of the gate dielectric layer material is greater than 3.7. The material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten. The material of the transition layer includes a dielectric material, and the dielectric material includes silicon oxide. The material of the work function layer includes an N-type work function material or a P-type work function material. The N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0077] The method for forming the gate structure 203 includes: forming a dummy gate structure (not shown) on a substrate; forming a sacrificial sidewall 204 on the sidewalls of the dummy gate structure; forming a second dielectric layer 205 on the substrate, where the second dielectric layer 205 exposes the top surface of the dummy gate structure and the top surface of the sacrificial sidewall 204; removing the dummy gate structure to form a gate opening (not shown) in the second dielectric layer 205; and forming a gate structure 203 in the gate opening.

[0078] The material of the sacrificial sidewall 204 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. The material of the second dielectric layer 205 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0079] In this embodiment, the material of the sacrificial sidewall 204 includes silicon nitride; the material of the second dielectric layer 205 includes silicon oxide.

[0080] The dielectric structure includes a second dielectric layer 205, and the second dielectric layer 205 is located on the sidewall surface of the gate structure 203.

[0081] In this embodiment, the dielectric structure further includes a third dielectric layer on the second dielectric layer 205. For details, please refer to Figure 6 .

[0082] Please refer to Figure 6 , and a protective layer 206 is formed on the top surface of the gate structure 203.

[0083] The protective layer 206 is used to protect the top surface of the gate structure 203 from being damaged by subsequent processes to the gate structure 203.

[0084] The method for forming the protective layer 206 includes: after forming the gate structure 203, etching back the gate layer to form a groove (not shown) in the second dielectric layer 205; forming a protective material layer (not shown) in the groove and on the second dielectric layer 205; planarizing the protective material layer until the surface of the second dielectric layer 205 is exposed, and forming the protective layer 206 on the top surface of the gate structure 203.

[0085] The material of the protective layer 206 is the same as that of the sacrificial sidewall 204. The material of the protective layer 206 is the same as that of the sacrificial sidewall 204, so that when the sacrificial sidewall 204 is removed, the protective layer 206 can also be removed together, thus saving the process flow.

[0086] The material of the protective layer 206 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the protective layer 206 includes silicon nitride.

[0087] In other embodiments, the protective layer may not be formed.

[0088] Please continue to refer to Figure 6 , a third dielectric layer 207 is formed on the surface of the second dielectric layer 205, the top surface of the sacrificial sidewall 204, and the surface of the protective layer 206.

[0089] The material of the third dielectric layer 207 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. The process for forming the third dielectric layer 207 includes a chemical vapor deposition process, an atomic layer deposition process, or a heat treatment process.

[0090] In this embodiment, the material of the third dielectric layer 207 includes silicon oxide; the process for forming the third dielectric layer 207 includes a chemical vapor deposition process.

[0091] In this embodiment, the third dielectric layer 207 and the second dielectric layer 205 together form the dielectric structure, providing structural support for the first conductive plug and the second conductive plug formed in the dielectric structure subsequently, and also being used for electrical isolation between the first conductive plug, the second conductive plug, and the gate structure 203.

[0092] In other embodiments, the dielectric structure may not include the third dielectric layer.

[0093] Please refer to Figure 7 and Figure 8 , Figure 8 For Figure 7 omit the top view of the dielectric structure,Figure 7 is Figure 8 A schematic cross-sectional structure diagram along the direction of the section line AA'. A first conductive plug 208 is formed in the dielectric structure, and the first conductive plug 208 is located on one or both sides of the gate structure 203.

[0094] The first conductive plug 208 is electrically connected to the source / drain doping region 202.

[0095] The method for forming the first conductive plug 208 includes: forming a first groove (not shown) in the dielectric structure, the first groove exposing the surface of the source / drain doping region 202; forming a plug material layer (not shown) in the first groove and on the top surface of the dielectric structure; planarizing the plug material layer until the surface of the dielectric structure is exposed, thereby forming the first conductive plug 208.

[0096] The material of the first conductive plug 208 includes a metal, and the metal includes one or a combination of more of copper, tungsten, aluminum, and titanium nitride.

[0097] In this embodiment, when forming the first conductive plug 208, it further includes: forming a second conductive plug 209 in the third dielectric layer 207, the second conductive plug 209 being electrically connected to the top of the gate structure 203.

[0098] The method for forming the second conductive plug 209 includes: forming a second groove (not shown) in the third dielectric layer 207 and the protective layer 206, the second groove exposing the top surface of the gate structure 203; forming a plug material layer (not shown) in the second groove and on the top surface of the third dielectric layer 207; planarizing the plug material layer until the surface of the third dielectric layer 207 is exposed, thereby forming the second conductive plug 209.

[0099] The material of the second conductive plug 209 includes a metal, and the metal includes one or a combination of more of copper, tungsten, aluminum, and titanium nitride.

[0100] In other embodiments, the second conductive plug may not be formed.

[0101] Please refer to Figure 9 and Figure 10 , Figure 10 is Figure 9 a top view of Figure 9 is Figure 10 A schematic cross-sectional structure diagram along the direction of the section line BB'. The sacrificial sidewall 204 is removed, and a first opening 211 is formed in the dielectric structure. The first opening 211 is located between the first conductive plug 208 and the gate structure 203, and the first opening 211 is located in the second dielectric layer 205.

[0102] The first opening 211 is used to form a first dielectric layer in the first opening 211 subsequently. The first dielectric layer seals the first opening 211 into a first sealed cavity. The first sealed cavity has a relatively small dielectric constant, thereby reducing the parasitic capacitance between the first conductive plug 208 and the gate structure 203.

[0103] The aspect ratio range of the first opening 211 is: 5 to 20. For the first opening 211 with such an aspect ratio range, a first dielectric layer is formed in the first opening 211 subsequently. The first dielectric layer seals the first opening 211 into a first sealed cavity. If the aspect ratio is too small, it is not easy for the first dielectric layer to be deposited on the top of the first opening 211 to seal the first opening 211 into a first sealed cavity. If the aspect ratio is too large, it is more difficult to form the first opening 211.

[0104] In this embodiment, during the process of forming the first opening 211, a second opening 210 is also formed in the third dielectric layer 207. The second opening 210 exposes the top surface of the sacrificial sidewall 204 and a part of the top surface of the gate structure 203.

[0105] The method for forming the first opening 211 includes: forming a patterned mask layer on the third dielectric layer 207. The patterned mask layer exposes the surface of the third dielectric layer 207 on the top of the sacrificial sidewall 204 and the surface of the third dielectric layer 207 on a part of the top of the gate structure 203; etching the third dielectric layer 207 using the patterned mask layer as a mask until the top surface of the gate structure 203 is exposed, and forming a second opening 210 in the third dielectric layer 207. The second opening 210 exposes the top surface of the sacrificial sidewall 204; removing the sacrificial sidewall 204 exposed by the second opening 210, and forming a first opening 211 in the second dielectric layer 205.

[0106] The patterned mask layer covers the top surface of the second conductive plug 209.

[0107] In this embodiment, when removing the sacrificial sidewall 204, the protective layer 206 exposed by the second opening 210 is also removed.

[0108] Removing the protective layer 206 on the top surface of the gate bond 203. The dielectric constant of the protective layer 206 is relatively large. Subsequently, a first dielectric layer is formed in the second opening 210. The first dielectric layer seals the second opening 210 into a second sealed cavity. Subsequently, when forming a first metal layer on the top surface of the first dielectric layer, the degree of reduction of the dielectric constant between the first metal layer and the gate structure 203 is relatively large, thereby being able to reduce the parasitic capacitance between the first metal layer and the gate structure 203, which is beneficial to the improvement of the performance of the semiconductor structure.

[0109] The process of removing the sacrificial sidewall 204 includes one or a combination of dry etching processes and wet etching processes.

[0110] Please refer to Figure 11 and Figure 12 , Figure 12 is Figure 11 a top view of Figure 11 is Figure 12 a schematic cross-sectional structure along the direction of the section line CC'. A first dielectric layer 212 is formed on the top of the first opening 211, and the first dielectric layer 212 seals the first opening 211 into a first sealed cavity.

[0111] The material of the first dielectric layer 212 includes a dielectric material, and the dielectric material includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. The process of forming the first dielectric layer 212 includes a chemical vapor deposition process, a heat treatment process, or an atomic layer deposition process.

[0112] In this embodiment, the material of the first dielectric layer 212 includes silicon oxide; the process of forming the first dielectric layer 212 includes a chemical vapor deposition process, and the deposition rate of the chemical vapor deposition process is relatively fast, so that the first dielectric layer 212 can be formed on the top of the first opening 211. The first dielectric layer 212 seals the first opening 211 into a first sealed cavity, and the first sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first conductive plug 208 and the gate structure 203 is reduced.

[0113] The method for forming the semiconductor structure is as follows: first, a first conductive plug 208 is formed in the dielectric structure, and the first conductive plug 208 is located on one side or both sides of the gate structure 203. Then, the sacrificial sidewall 204 is removed, and a first opening 211 is formed in the dielectric structure. The first opening 211 is located between the gate structure 203 and the first conductive plug 208. Then, a first dielectric layer 212 is formed on the top of the first opening 211, and the first dielectric layer 212 seals the first opening 211 into a first sealed cavity. The first sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first conductive plug 208 and the gate structure 203 is reduced. The first sealed cavity formed by this method has a good isolation effect, avoiding the situation that when the first sealed cavity is formed first and then the first conductive plug 208 is formed, the material of the first conductive plug 208 penetrates into the first sealed cavity and affects the isolation effect of the first sealed cavity.

[0114] In this embodiment, a first dielectric layer 212 is formed in the second opening 210, and the first dielectric layer 212 fills the second opening 210.

[0115] In other embodiments, the first dielectric layer is located on top of the second opening, and the first dielectric layer seals the second opening to form a second sealed cavity, and the first dielectric layer seals the first opening to form a first sealed cavity.

[0116] Please refer to Figure 13 and Figure 14 , Figure 14 is Figure 13 a top view of Figure 13 is Figure 14 a schematic cross-sectional structure diagram along the direction of the section line DD'. A fourth dielectric layer 214 is formed on the top surface of the dielectric structure and the top surface of the first dielectric layer 212; a first metal layer 213 is formed in the fourth dielectric layer 214, and the first metal layer 213 is electrically connected to the second conductive plug 209.

[0117] The material of the first metal layer 213 includes a metal, and the metal includes one or a combination of copper, tungsten, aluminum, and titanium nitride.

[0118] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to Figure 13 and Figure 14 , including:

[0119] a substrate;

[0120] a gate structure 203 located on the substrate;

[0121] a dielectric structure located on the substrate, and the dielectric structure covers the gate structure 203;

[0122] a first conductive plug 208 located in the dielectric structure, and the first conductive plug 208 is located on one side or both sides of the gate structure 203;

[0123] a first opening (not shown) located in the dielectric structure, and the first opening exposes the sidewall surface of the gate structure 203, and the first opening is located between the first conductive plug 208 and the gate structure 203;

[0124] a first dielectric layer 212 located on top of the first opening, and the first dielectric layer 212 seals the first opening to form a first sealed cavity.

[0125] In this embodiment, it further includes: a second opening (not shown) located in the dielectric structure, and the second opening exposes a part of the top surface of the gate structure 203.

[0126] In this embodiment, it further includes: a first dielectric layer 212 located in the second opening.

[0127] In this embodiment, the aspect ratio of the first opening ranges from 5 to 20.

[0128] In this embodiment, the dielectric structure includes a second dielectric layer 205 and a third dielectric layer 207 located on the second dielectric layer 205. The second dielectric layer 205 is located on the sidewall surface of the gate structure 203, and the third dielectric layer 207 is located on the top surface of the gate structure 203.

[0129] In this embodiment, the gate structure 203 includes a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer; the gate structure 203 is located within the second dielectric layer 205.

[0130] In this embodiment, the dielectric constant of the gate dielectric layer material is greater than 3.7. The material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0131] In this embodiment, the gate structure 203 further includes: a transition layer (not shown) located on the substrate, the gate dielectric layer is located on the surface of the transition layer; a work function layer (not shown) located on the gate dielectric layer, and the gate layer is located on the surface of the work function layer.

[0132] In this embodiment, it further includes: a second conductive plug 209 located within the dielectric structure, and the second conductive plug 209 is electrically connected to the top of the gate structure 203.

[0133] In this embodiment, it further includes: source / drain doping regions 202 located within the substrate on both sides of the gate structure 203; the first conductive plug 208 is electrically connected to the source / drain doping regions 202.

[0134] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 located on the substrate 200; the gate structure 203 straddles the plurality of fin structures 201.

[0135] In this embodiment, the material of the first dielectric layer 212 includes a dielectric material, and the dielectric material includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0136] In this embodiment, it further includes: a fourth dielectric layer 214 located on the top surface of the dielectric structure and the top surface of the first dielectric layer 212; a first metal layer 213 located within the fourth dielectric layer 214, and the first metal layer 213 is electrically connected to the second conductive plug 209.

[0137] In the semiconductor structure, the first dielectric layer 212 seals the first opening to form a first sealed cavity. The first sealed cavity has a relatively small dielectric constant, thereby reducing the parasitic capacitance between the first conductive plug 208 and the gate structure 203, and thus improving the performance of the semiconductor structure.

[0138] Figures 15 to 18 It is a schematic cross-sectional structure diagram of the process of forming a semiconductor structure in another embodiment of the present invention.

[0139] Please refer to Figure 15 and Figure 16 , Figure 15 is Figure 9 a schematic structure diagram based on Figure 16 is Figure 10 a schematic structure diagram based on Figure 16 is Figure 15 a top view of Figure 16 is Figure 15 a schematic cross-sectional structure diagram along the section line EE'. A first dielectric layer 312 is formed in the second opening 210. The first dielectric layer 312 seals the second opening 210 to form a second sealed cavity, and the first dielectric layer 312 seals the first opening 211 to form a first sealed cavity.

[0140] In this embodiment, the aspect ratio range of the second opening 210 is: 10 - 30.

[0141] For the second opening 210 with the aspect ratio within the above range, a first dielectric layer is subsequently formed in the second opening 210, and the first dielectric layer seals the second opening 210 to form a first sealed cavity. If the aspect ratio is too small, it is not easy for the first dielectric layer to be deposited on the top of the second opening 210 to seal the second opening 210 into a first sealed cavity. If the aspect ratio is too large, it is more difficult to form the second opening 210.

[0142] The material of the first dielectric layer 312 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. The process for forming the first dielectric layer 312 includes chemical vapor deposition process, heat treatment process, or atomic layer deposition process.

[0143] In this embodiment, the material of the first dielectric layer 312 includes silicon oxide; the process for forming the first dielectric layer 312 includes a chemical vapor deposition process, and the deposition rate of the chemical vapor deposition process is relatively fast, so that the first dielectric layer 312 can be formed in the second opening 210. The first dielectric layer 312 seals the second opening 210 into a second sealed cavity, and at the same time, the first dielectric layer seals the first opening 211, thereby reducing the parasitic capacitance between the first conductive plug 208 and the gate structure 203; the second sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first metal layer formed in the fourth dielectric layer and the gate structure 203 is reduced, thereby improving the performance of the semiconductor structure.

[0144] Please refer to Figure 17 and Figure 18 , Figure 18 is Figure 17 a top view of Figure 17 is Figure 18 a schematic cross-sectional structure diagram along the direction of the section line FF'. A fourth dielectric layer 314 is formed on the top surface of the dielectric structure and the top surface of the first dielectric layer 312; a first metal layer 313 is formed in the fourth dielectric layer 314, and the first metal layer 313 is electrically connected to the second conductive plug 209.

[0145] The material of the first metal layer 313 includes a metal, and the metal includes one or a combination of copper, tungsten, aluminum, and titanium nitride.

[0146] The first dielectric layer 312 seals the second opening 210 into a second sealed cavity, and the second sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first metal layer 313 and the gate structure 203 is reduced, thereby improving the performance of the semiconductor structure.

[0147] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to Figure 17 and Figure 18 , including:

[0148] a substrate;

[0149] a gate structure 203 located on the substrate;

[0150] a dielectric structure located on the substrate, and the dielectric structure covers the gate structure 203;

[0151] a first conductive plug 208 located in the dielectric structure, and the first conductive plug 208 is located on one side or both sides of the gate structure 203;

[0152] A first opening (not shown) located within the dielectric structure, the first opening exposing the sidewall surface of the gate structure 203, the first opening being located between the first conductive plug 208 and the gate structure 203;

[0153] A first dielectric layer 312 located at the top of the first opening, the first dielectric layer 312 enclosing the first opening into a first sealed cavity.

[0154] In this embodiment, it further includes: a second opening (not shown) located within the dielectric structure, the second opening exposing a portion of the top surface of the gate structure 203.

[0155] In this embodiment, it further includes: a first dielectric layer 312 located within the second opening, the first dielectric layer 312 enclosing the second opening into a second sealed cavity.

[0156] In this embodiment, the aspect ratio range of the second opening is: 10 - 30.

[0157] In this embodiment, the aspect ratio range of the first opening is: 5 - 20.

[0158] In this embodiment, the dielectric structure includes a second dielectric layer 205 and a third dielectric layer 207 located on the second dielectric layer 205, the second dielectric layer 205 being located on the sidewall surface of the gate structure 203, and the third dielectric layer 207 being located on the top surface of the gate structure 203.

[0159] In this embodiment, the gate structure 203 includes a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer; the gate structure 203 is located within the second dielectric layer 205.

[0160] In this embodiment, the dielectric constant of the gate dielectric layer material is greater than 3.7, the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

[0161] In this embodiment, the gate structure 203 further includes: a transition layer (not shown) located on the substrate, the gate dielectric layer being located on the surface of the transition layer; a work function layer (not shown) located on the gate dielectric layer, and the gate layer being located on the surface of the work function layer.

[0162] In this embodiment, it further includes: a second conductive plug 209 located within the dielectric structure, the second conductive plug 209 being electrically connected to the top of the gate structure 203.

[0163] In this embodiment, it further includes: source / drain doping regions 202 located within the substrate on both sides of the gate structure 203; the first conductive plug 208 is electrically connected to the source / drain doping regions 202.

[0164] In this embodiment, the substrate includes a base 200 and a plurality of fin structures 201 located on the base 200; the gate structure 203 straddles the plurality of fin structures 201.

[0165] In this embodiment, the material of the first dielectric layer 312 includes a dielectric material, and the dielectric material includes one or a combination of more than one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

[0166] In this embodiment, it further includes: a fourth dielectric layer 314 located on the top surface of the dielectric structure and the top surface of the first dielectric layer 312; a first metal layer 313 located in the fourth dielectric layer 314, and the first metal layer 313 is electrically connected to the second conductive plug 209.

[0167] In the semiconductor structure, the first dielectric layer 312 closes the first opening into a first sealed cavity, and the first sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first conductive plug 208 and the gate structure 203 is reduced; the first dielectric layer 312 closes the second opening into a second sealed cavity, and the second sealed cavity has a relatively small dielectric constant, so that the parasitic capacitance between the first metal layer 313 and the gate structure 203 is reduced, thereby improving the performance of the semiconductor structure.

[0168] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A gate structure located on the substrate; A dielectric structure located on the substrate, the dielectric structure covering the gate structure, the dielectric structure including a second dielectric layer and a third dielectric layer located on the second dielectric layer; A first conductive plug located within the dielectric structure, the first conductive plug located on one or both sides of the gate structure; An opening located within the dielectric structure, the opening exposing the gate structure, the opening including a first opening and a second opening, the first opening located between the first conductive plug and the gate structure, the second opening located within the third dielectric layer, the second opening exposing a portion of the top surface of the gate structure; A first dielectric layer located on top of the second opening and on top of the first opening, the first dielectric layer enclosing the first opening into a first sealed cavity, the first dielectric layer enclosing the second opening into a second sealed cavity.

2. The semiconductor structure according to claim 1, wherein The aspect ratio range of the first opening is: 5 to 20.

3. The semiconductor structure according to claim 1, wherein The aspect ratio range of the second opening is: 10 to 30.

4. The semiconductor structure according to claim 1, wherein, The second dielectric layer is located on the sidewall surface of the gate structure, and the third dielectric layer is located on the top surface of the gate structure.

5. The semiconductor structure according to claim 4, wherein The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the gate structure is located within the second dielectric layer.

6. The semiconductor structure according to claim 5, wherein, The dielectric constant of the gate dielectric layer material is greater than 3.7, the material of the gate dielectric layer includes hafnium oxide or aluminum oxide; the material of the gate layer includes a metal, and the metal includes tungsten.

7. The semiconductor structure according to claim 5, wherein, Further comprising: A transition layer located on the substrate, the gate dielectric layer being located on the surface of the transition layer; A work function layer located on the gate dielectric layer, the gate layer being located on the surface of the work function layer.

8. The semiconductor structure according to claim 1, wherein Further comprising: A second conductive plug located within the dielectric structure, the second conductive plug being electrically connected to the top of the gate structure.

9. The semiconductor structure according to claim 8, wherein Further comprising: A fourth dielectric layer located on the top surface of the dielectric structure and on the top surface of the first dielectric layer; A first metal layer located within the fourth dielectric layer, the first metal layer being electrically connected to the second conductive plug.

10. The semiconductor structure according to claim 1, wherein Further comprising: Source / drain doping regions located within the substrate on both sides of the gate structure; the first conductive plug is electrically connected to the source / drain doping regions.

11. The semiconductor structure according to claim 1, wherein, The substrate includes a base and a plurality of fin structures located on the base; the gate structure straddles the plurality of fin structures.

12. The semiconductor structure according to claim 1, wherein, The material of the first dielectric layer includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

13. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a gate structure, a sacrificial sidewall, and a dielectric structure on the substrate, the sacrificial sidewall being located on the sidewall surface of the gate structure, the dielectric structure being located on the substrate and on the surface of the sacrificial sidewall, the dielectric structure including a second dielectric layer and a third dielectric layer located on the surface of the second dielectric layer; Forming a first conductive plug within the dielectric structure, the first conductive plug being located on one or both sides of the gate structure; Remove the sacrificial sidewall to form an opening within the dielectric structure, the opening exposing the gate structure. The opening includes a first opening and a second opening. The first opening is located between the first conductive plug and the gate structure, and the second opening is within the third dielectric layer, the second opening exposing a portion of the top surface of the gate structure. Form a first dielectric layer on top of the second opening and on top of the first opening. The first dielectric layer seals the first opening into a first sealed cavity and seals the second opening into a second sealed cavity.

14. The method for forming a semiconductor structure according to claim 13, wherein, The second dielectric layer is located on the sidewall surface of the gate structure.

15. The method for forming a semiconductor structure as described in claim 13, wherein, The aspect ratio range of the first opening is: 5 - 20.

16. The method for forming a semiconductor structure according to claim 13, wherein, The aspect ratio range of the second opening is: 10 - 30.

17. The method for forming a semiconductor structure according to claim 13, wherein The process of forming the first dielectric layer includes a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 13, wherein, The gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.

19. The method for forming a semiconductor structure as described in claim 18, wherein, The dielectric constant of the gate dielectric layer material is greater than 3.

7. The material of the gate dielectric layer includes hafnium oxide or aluminum oxide. The material of the gate layer includes a metal, and the metal includes tungsten.

20. The method for forming a semiconductor structure according to claim 18, wherein, The method of forming the gate structure includes: forming a dummy gate structure on a substrate; forming sacrificial sidewalls on the sidewalls of the dummy gate structure; forming a second dielectric layer on the substrate, the second dielectric layer exposing the top surface of the dummy gate structure and the top surface of the sacrificial sidewalls; removing the dummy gate structure to form a gate opening within the second dielectric layer; forming a gate structure within the gate opening.

21. The method for forming a semiconductor structure according to claim 18, wherein, Further included is: A transition layer located on the substrate, and the gate dielectric layer is located on the surface of the transition layer; A work function layer located on the gate dielectric layer, and the gate layer is located on the surface of the work function layer.

22. The method for forming a semiconductor structure according to claim 18, wherein, Further included is: Form a protective layer on the top surface of the gate structure; When removing the sacrificial sidewall, the protective layer is also removed.

23. The method for forming a semiconductor structure according to claim 22, wherein, The method of forming the protective layer includes: after forming the gate structure, etch back the gate layer to form a groove within the second dielectric layer; form the protective layer within the groove.

24. The method for forming a semiconductor structure according to claim 23, wherein, The material of the protective layer is the same as the material of the sacrificial sidewall.

25. The method for forming a semiconductor structure according to claim 24, wherein, The material of the protective layer includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

26. The method for forming a semiconductor structure according to claim 13, wherein, Before removing the sacrificial sidewall, further included is: forming a second conductive plug within the dielectric structure, the second conductive plug being electrically connected to the top of the gate structure.

27. The method for forming a semiconductor structure according to claim 26, wherein, After forming the first dielectric layer, further included is: forming a fourth dielectric layer on the top surface of the dielectric structure and on the top surface of the first dielectric layer; forming a first metal layer within the fourth dielectric layer, the first metal layer being electrically connected to the second conductive plug.

28. The method for forming a semiconductor structure according to claim 13, wherein Before forming the dielectric structure on the substrate, further included is: forming source / drain doping regions within the substrate on both sides of the gate structure; the first conductive plug being electrically connected to the source / drain doping regions.

29. The method for forming a semiconductor structure according to claim 13, wherein, The substrate includes a substrate and a plurality of fin structures located on the substrate; the gate structure straddles the plurality of fin structures.

30. The method for forming a semiconductor structure according to claim 13, wherein, The process of removing the sacrificial sidewall includes one or a combination of more of a dry etching process or a wet etching process.

31. The method for forming a semiconductor structure according to claim 13, wherein, The material of the first dielectric layer includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride.

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