BOOST type switching power supply voltage regulator and control method thereof

Abstract

The present invention discloses a boost-type switching power supply voltage regulator and its control method. The voltage regulator includes an input terminal IN, an output terminal OUT, a control terminal CT, an inductor L1, a switch transistor NM1, a first P-type channel MOS field-effect transistor PM1, a second P-type channel MOS field-effect transistor PM2, a capacitor C1, a resistor divider network, an error amplifier EA, and a voltage comparator COMP. The boost-type switching power supply voltage regulator and its control method proposed in the present invention can address the output voltage limitations of traditional boost-type switching power supply voltage regulator structures and improve circuit stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits and relates to a switching power supply circuit, in particular to a BOOST type switching power supply voltage regulator and a control method thereof. Background Art

[0002] A switching power supply voltage regulator is a topology commonly used in power supply designs, generating an adjustable, stable output voltage. Its structure allows for manual adjustment of the output voltage, and its stable loop, formed by a voltage divider sampling network, error amplifier, and pulse-width modulator, makes it widely used in power supply modules. The performance of a switching power supply voltage regulator significantly impacts the entire circuit.

[0003] Switching power supply voltage regulators typically fall into two categories: buck and boost. Buck regulators, also known as step-down regulators, require their output voltage to be lower than their input voltage for them to function properly and stably. Boost regulators, also known as step-up regulators, require their output voltage to be higher than their input voltage for them to function properly and stably.

[0004] Take the traditional buck-type switching power supply voltage regulator circuit as an example: when the switch is on, the circuit's input charges the inductor and also provides current to the load at the output. When the switch is off, because the inductor's current cannot change suddenly, the inductor's polarity changes and provides current to the load at the output. Based on the buck-type switching power supply voltage regulator circuit diagram, ignoring the diode voltage drop, we can briefly list the approximate equations for the switch on and off: ton=T·D,toff=T·(1-D); where T is the switching time period of the switch tube, and D is the corresponding duty cycle. Since the current in the inductor does not change suddenly when the switching state of the switch tube changes, the solution of the equation can be obtained: V OUT =V IN D. It can be seen that under this structure, the output voltage that can be obtained by adjusting the duty cycle of the switch tube is less than or equal to the input voltage. At the same time, the feedback loop composed of the voltage divider network and error amplifier connected to the output terminal ensures the stability of the output voltage.

[0005] Take the traditional BOOST-type switching power supply voltage circuit as an example: when the switch is on, the circuit's input charges the inductor. When the switch is off, because the inductor's current cannot change suddenly, the inductor's polarity changes and, together with the circuit's input, provides current to the load. Based on the schematic diagram of the BOOST-type switching power supply voltage circuit structure, ignoring the diode's forward voltage drop, we can briefly list the approximate equations for the switch on and off: ton = T·D, toff = T·(1-D); where T is the switching period of the switch tube, and D is the corresponding duty cycle. Since the current in the inductor does not change suddenly when the switching state of the switch tube changes, solving the equation yields: It can be seen that under this structure, the output voltage that can be obtained by adjusting the duty cycle of the switching tube is greater than or equal to the input voltage. At the same time, the feedback loop composed of the voltage divider network and the error amplifier connected to the input end ensures the stability of the output voltage.

[0006] In practical applications, the ability to accurately output an adjustable and stable output voltage is a fundamental requirement of a switching regulator and a key factor in determining the feasibility of a power supply circuit using this structure. However, the output voltage of both buck-type and boost-type switching power supply voltage regulators has an adjustable voltage range, which undoubtedly presents a significant limitation in practical applications and significantly impacts subsequent structural design.

[0007] In view of this, there is an urgent need to design a new switching power supply voltage regulator to overcome at least some of the above-mentioned defects of the existing switching power supply voltage regulator. Summary of the Invention

[0008] The present invention provides a BOOST type switching power supply voltage regulator and a control method thereof, which can solve the output voltage value limitation existing in the traditional BOOST type switching power supply voltage regulator structure and improve the stability of the circuit.

[0009] In order to solve the above technical problems, according to one aspect of the present invention, the following technical solution is adopted:

[0010] A BOOST type switching power supply voltage regulator, the voltage regulator comprising:

[0011] Input terminal IN, used for providing input voltage;

[0012] The output terminal OUT is used to provide an output voltage;

[0013] The inductor L1 has its same-name end connected to the input terminal IN, and is used to provide current to the load together with the voltage at the input terminal IN after the switch tube NM1 is turned off;

[0014] The switch tube NM1 is connected between the opposite-polarity terminal of the inductor L1 and the ground;

[0015] The first P-channel MOS field effect transistor PM1 has its substrate and drain connected together, and is used to replace the diode and reduce the voltage loss caused by the diode conduction voltage drop through synchronous rectification technology;

[0016] The second P-type channel MOS field effect transistor PM2 has its substrate and source connected together, and is used to act as an equivalent resistor to reduce the voltage when the output voltage needs to be lower than the input voltage;

[0017] A first P-type channel MOS field effect transistor PM1 and a second P-type channel MOS field effect transistor PM2 are connected in series between the opposite-polarity terminal of the inductor L1 and the output terminal OUT;

[0018] Capacitor C1 is connected between the output terminal OUT and ground, and is used to provide current to the load when the switch tube NM1 is turned on;

[0019] A resistor divider network is connected between the output terminal OUT and ground;

[0020] an error amplifier EA having the output of the resistor divider network and a reference voltage VREF1 as inputs;

[0021] A pulse width modulator (PWM) takes the output of the error amplifier EA and a sawtooth wave Vt with a period of T as inputs. The output of the pulse width modulator (PWM) is connected to the gate of the switch tube NM1 and is used to adjust the duty cycle of the output voltage of the pulse width modulator according to the reference voltage VREF1, thereby adjusting the ratio of the on-time and off-time within the cycle of the switch tube NM1, and ultimately adjusting the output current and output voltage.

[0022] a voltage comparator COMP having an input terminal IN and an output terminal OUT as inputs, wherein the output of the voltage comparator COMP is connected to the gate of the second P-channel MOS field effect transistor PM2;

[0023] The control terminal CT is used to control the conduction of the first P-type channel MOS field effect transistor PM1, so that the first P-type channel MOS field effect transistor PM1 can be turned off and on when the switch tube is turned on and off respectively.

[0024] As an embodiment of the present invention, the resistor divider network includes a first resistor R1 and a second resistor R2 connected in series.

[0025] As an implementation manner of the present invention, the switch transistor NM1 is an N-type channel MOS field effect transistor.

[0026] As an embodiment of the present invention, when the switch tube NM1 is turned on, the control terminal CT outputs a high level to turn off the first P-type channel MOS field effect transistor PM1; when the switch tube NM1 is turned off, the control terminal CT outputs a low level to turn on the first P-type channel MOS field effect transistor PM1; thereby reducing the loss caused by the conduction voltage drop of the diode D1.

[0027] As an embodiment of the present invention, a voltage comparator COMP having an input voltage at the input terminal IN and an output voltage at the output terminal OUT as inputs and a second P-type channel MOS field effect transistor PM2 whose gate is controlled by the output of the voltage comparator COMP are used to complete the voltage reduction operation when the output voltage value of the output terminal OUT is lower than the input voltage value of the input terminal IN.

[0028] As an embodiment of the present invention, if it is necessary to increase or decrease the output voltage value of the output terminal OUT within an adjustment range greater than the input voltage value of the input terminal IN, a corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network;

[0029] The error amplifier EA and the pulse width modulator PWM adjust the duty cycle of the square wave output of the pulse width modulator PWM according to the current output voltage divided voltage sampling value and the reference voltage value, so that the on-time of the switch tube is adjusted; thereby, the charging time of the inductor L1 is changed. In this way, the power that the inductor L1 can provide to the load during the off-time of the switch tube is also changed accordingly, resulting in a corresponding change in the output voltage of the output terminal OUT;

[0030] When the output voltage of the output terminal OUT is divided by the resistor voltage divider network and the divided voltage value is equal to the reference voltage value VREF1, the feedback loop is stable, and the output voltage of the output terminal OUT is further kept stable.

[0031] As an embodiment of the present invention, if it is necessary to increase or decrease the output voltage value of the output terminal OUT within an adjustment range smaller than the input voltage value of the input terminal IN, a corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network;

[0032] The error amplifier EA and the pulse width modulator PWM will reduce the duty cycle of the square wave output of the pulse width modulator PWM according to the current larger output voltage divided voltage sampling value and the reference voltage value, shortening the on-time of the switch tube. This in turn shortens the charging time of the inductor L1. As a result, during the off-time of the switch tube, the power that the inductor L1 can provide to the load is also reduced, causing the output voltage of the output terminal OUT to drop.

[0033] When the output voltage of the output terminal OUT drops to be equal to the input voltage of the input terminal IN, the voltage comparator COMP, which takes the input voltage of the input terminal IN and the output voltage of the output terminal IN as inputs, detects this situation and outputs a high level to the gate of the second P-type channel MOS field effect transistor PM2, so that the second P-type channel MOS field effect transistor PM2 is pinched off;

[0034] At this time, although the switch tube remains off, the input terminal IN is directly connected to the source of PM2 through the PN junction formed by the source and substrate of the first P-type channel MOS field effect transistor PM1, but it cannot be conducted to the output terminal OUT through the NP junction formed by the substrate connected to the source and the drain. The only way to pass through PM2 is to transmit through the channel of PM2;

[0035] After the second P-type channel MOS field effect transistor PM2 is cut off, the output voltage at the output terminal OUT will become lower due to the path from the load to ground. When the divided output voltage sample value of the output terminal OUT is less than the reference voltage value, the error amplifier EA and the pulse width modulator PWM will output a square wave to the gate of the switch tube. Then the inductor L1 will start charging and discharging again. In the first cycle of the switch tube resuming conduction and shutting down, when the switch tube is turned off, the voltage value at the opposite end of the inductor L1 is equal to the voltage value of the inductor L1 plus the voltage value of the input terminal IN. This voltage value reaches the source of the second P-type channel MOS field effect transistor PM2 through the turned-on first P-type channel MOS field effect transistor PM1, thereby causing the second P-type channel MOS field effect transistor PM2 to operate in the saturation region, which is equivalent to a resistor completing the voltage reduction work.

[0036] The output voltage of the output terminal OUT will change accordingly, causing the feedback loop to continue to adjust; eventually, when the divided voltage sampling value of the output voltage of the output terminal OUT is equal to the reference voltage value, the feedback loop is stable, and a stable output voltage value OUT is further obtained, and the voltage value is lower than the input voltage value of the input terminal IN.

[0037] According to another aspect of the present invention, the following technical solution is adopted: a control method of the above-mentioned BOOST type switching power supply voltage regulator, the control method comprising:

[0038] When the switch tube NM1 is turned on, the control terminal CT outputs a high level to turn off the first P-type channel MOS field effect transistor PM1; when the switch tube NM1 is turned off, the control terminal CT outputs a low level to turn on the first P-type channel MOS field effect transistor PM1, thereby reducing the loss caused by the conduction voltage drop of the diode D1;

[0039] A voltage comparator COMP having an input voltage at the input terminal IN and an output voltage at the output terminal OUT as inputs and a second P-channel MOS field effect transistor PM2 whose gate is controlled by the output of the voltage comparator COMP are used to complete the voltage reduction operation when the output voltage value of the output terminal OUT is lower than the input voltage value of the input terminal IN.

[0040] As an embodiment of the present invention, if it is necessary to increase or decrease the output voltage value of the output terminal OUT within an adjustment range greater than the input voltage value of the input terminal IN, a corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network;

[0041] The error amplifier EA and the pulse width modulator PWM adjust the duty cycle of the square wave output of the pulse width modulator PWM according to the current output voltage divided voltage sampling value and the reference voltage value, so that the on-time of the switch tube is adjusted; thereby, the charging time of the inductor L1 is changed. In this way, the power that the inductor L1 can provide to the load during the off-time of the switch tube is also changed accordingly, resulting in a corresponding change in the output voltage of the output terminal OUT;

[0042] When the output voltage of the output terminal OUT is divided by the resistor voltage divider network and the divided voltage value is equal to the reference voltage value VREF1, the feedback loop is stable, and the output voltage of the output terminal OUT is further kept stable.

[0043] As an embodiment of the present invention, if it is necessary to increase or decrease the output voltage value of the output terminal OUT within an adjustment range smaller than the input voltage value of the input terminal IN, a corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network;

[0044] The error amplifier EA and the pulse width modulator PWM will reduce the duty cycle of the square wave output of the pulse width modulator PWM according to the current larger output voltage divided voltage sampling value and the reference voltage value, shortening the on-time of the switch tube. This in turn shortens the charging time of the inductor L1. As a result, during the off-time of the switch tube, the power that the inductor L1 can provide to the load is also reduced, causing the output voltage of the output terminal OUT to drop.

[0045] When the output voltage of the output terminal OUT drops to be equal to the input voltage of the input terminal IN, the voltage comparator COMP, which takes the input voltage of the input terminal IN and the output voltage of the output terminal IN as inputs, detects this situation and outputs a high level to the gate of the second P-type channel MOS field effect transistor PM2, so that the second P-type channel MOS field effect transistor PM2 is pinched off;

[0046] At this time, although the switch tube remains off, the input terminal IN is directly connected to the source of PM2 through the PN junction formed by the source and substrate of the first P-type channel MOS field effect transistor PM1, but it cannot be conducted to the output terminal OUT through the NP junction formed by the substrate connected to the source and the drain. The only way to pass through PM2 is to transmit through the channel of PM2;

[0047] After the second P-type channel MOS field effect transistor PM2 is cut off, the output voltage at the output terminal OUT will become lower due to the path from the load to ground. When the divided output voltage sample value of the output terminal OUT is less than the reference voltage value, the error amplifier EA and the pulse width modulator PWM will output a square wave to the gate of the switch tube. Then the inductor L1 will start charging and discharging again. In the first cycle of the switch tube resuming conduction and shutting down, when the switch tube is turned off, the voltage value at the opposite end of the inductor L1 is equal to the voltage value of the inductor L1 plus the voltage value of the input terminal IN. This voltage value reaches the source of the second P-type channel MOS field effect transistor PM2 through the turned-on first P-type channel MOS field effect transistor PM1, thereby causing the second P-type channel MOS field effect transistor PM2 to operate in the saturation region, which is equivalent to a resistor completing the voltage reduction work.

[0048] The output voltage of the output terminal OUT will change accordingly, causing the feedback loop to continue to adjust; eventually, when the divided voltage sampling value of the output voltage of the output terminal OUT is equal to the reference voltage value, the feedback loop is stable, and a stable output voltage value OUT is further obtained, and the voltage value is lower than the input voltage value of the input terminal IN.

[0049] The beneficial effect of the present invention is that the BOOST type switching power supply voltage regulator and the control method thereof proposed in the present invention can solve the output voltage value limitation of the traditional BOOST type switching power supply voltage regulator structure.

[0050] When the voltage at output terminal OUT is required to be lower than the voltage at input terminal IN, VREF1 is first set to the desired output voltage. Through the feedback loop, the duty cycle D of the pulse width modulator (PWM)'s output square wave is reduced to zero. This effectively connects output terminal OUT to input terminal IN, resulting in the voltage at output terminal OUT being equal to the voltage at input terminal IN. The voltage comparator COMP then detects that the voltage at the output terminal is equal to the voltage at the input terminal and outputs a high level to the gate of PM2, causing PM2 to operate in its saturation region, effectively acting as a resistor and completing the voltage reduction process from input terminal IN to output terminal OUT. At this point, due to the participation of PM2, a new feedback relationship is established, and the output voltage at output terminal OUT, which is lower than the input voltage at input terminal IN, can also be stabilized through the feedback loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1This is a schematic diagram of the circuit structure of a traditional BUCK type switching power supply voltage regulator.

[0052] Figure 2 This is a schematic diagram of the circuit structure of a traditional BOOST type switching power supply voltage regulator.

[0053] Figure 3 FIG. 1 is a schematic diagram of the topology structure of a medium-sized switching power supply voltage regulator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0055] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0056] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments described. The same or similar existing technical means and some technical features of the embodiments are mutually replaced within the scope of the description and protection of the present invention.

[0057] It should be noted that relational terms such as "first" and "second" in the present invention are used solely to distinguish one entity or operation from another and do not imply any actual relationship or order between the entities or operations. The diagrams provided herein are merely schematic illustrations of the basic concepts of the present invention. The diagrams only show components relevant to the present invention and are not drawn to reflect the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may be more complex.

[0058] The description of the steps in each embodiment in the specification is only for the convenience of explanation, and the implementation method of this application is not limited by the order of implementation of the steps.

[0059] The term "connection" as used in this specification includes both direct connection and indirect connection, such as connection through active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices that are well known to those skilled in the art and can achieve the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0060] Figure 2 This is a schematic diagram of a traditional BOOST type switching power supply voltage regulator circuit structure; please refer to Figure 2Assuming the output voltage and output current have already been established, when switch NM1 is turned on, input IN is connected to ground via inductor L1 and switch NM1. In other words, input IN charges inductor L1 for a duration of TD, where T is the period of the sawtooth wave Vt and D is the duty cycle of the pulse width modulator's square wave output. During this period, the polarity of the inductor's like-signal terminal is positive and the opposite-signal terminal is negative. When switch NM1 is turned off, the inductor's current cannot change suddenly, and the output voltage at output OUT is greater than the input voltage at input IN. Therefore, at the moment the switch is turned off, the inductor current remains unchanged, but its polarity changes: the like-signal terminal becomes negative and the opposite-signal terminal becomes positive. At this point, the inductor acts as a power source in the same direction as input OUT, supplying power to output OUT together with input IN. Therefore, the output voltage at output OUT is higher than the input voltage at input IN.

[0061] The conventional BOOST type switching power supply voltage regulator circuit structure has the function of adjusting the output voltage of the output terminal OUT through a feedback loop, which is also the basic function of the switching power supply voltage regulator.

[0062] Specifically, if a lower output voltage than the current output voltage value at output terminal OUT is desired within the adjustment range, a corresponding reference voltage VREF1 can be set based on the desired output voltage value and the resistor divider network. The error amplifier EA and pulse width modulator PWM will reduce the duty cycle of the pulse width modulator PWM's output voltage based on the voltage-divided sample value of the current larger output voltage and the reference voltage value, thereby shortening the on-time of the switch tube. This, in turn, shortens the charging time of inductor L1. Consequently, during the off-time of the switch tube, the energy that inductor L1 can provide to the load is also reduced, causing the output voltage at output terminal OUT to drop. When the output voltage at output terminal OUT, after being divided by the resistor divider network, equals the reference voltage VREF1, the feedback loop stabilizes, further stabilizing the output voltage at output terminal OUT.

[0063] Specifically, if a higher output voltage than the current output voltage value at the output terminal OUT is desired within the adjustment range, a corresponding reference voltage VREF1 can be set based on the desired output voltage value and the resistor divider network. The error amplifier EA and the pulse width modulator PWM will increase the duty cycle of the square wave output of the pulse width modulator PWM based on the current smaller output voltage divided voltage sample value and the reference voltage value, thereby lengthening the on-time of the switch tube. This in turn prolongs the charging time of the inductor L1. Consequently, during the off-time of the switch tube, the amount of energy that the inductor L1 can provide to the load also increases, causing the output voltage at the output terminal OUT to rise. When the output voltage at the output terminal OUT, after being divided by the resistor divider network, equals the reference voltage VREF1, the feedback loop stabilizes, further stabilizing the output voltage at the output terminal OUT.

[0064] Specifically, if the output voltage at output terminal OUT needs to be lower than the input voltage at input terminal IN, the aforementioned operating method sets a corresponding reference voltage VREF1 based on the desired output voltage and the resistor divider network. The error amplifier and pulse width modulator (PWM) reduce the duty cycle of the square wave output of the PWM based on the current larger output voltage's divided voltage sample value and the reference voltage, shortening the on-time of the switch. This, in turn, shortens the charging time of inductor L1. Consequently, during the switch's off period, the energy inductor L1 can provide to the load is also reduced, causing the output voltage at output terminal OUT to drop. However, when the duty cycle of the PWM square wave output reaches 0, the switch is disconnected, and input terminal IN is directly connected to output terminal OUT via inductor L1 and diode D1. At this point, the output voltage at output terminal OUT equals the input voltage at input terminal IN minus the conduction voltage of diode D1, and the switching regulator loses its regulation capability.

[0065] When the required output voltage at the output terminal OUT is lower than the input voltage, the traditional BOOST type switching power supply voltage regulator fails, indicating that the traditional BOOST type switching power supply voltage regulator has an output voltage limitation, which will undoubtedly affect the design of subsequent structures in practical applications and have a significant impact.

[0066] Figure 3 A schematic diagram of a BOOST topology structure provided by an embodiment of the present invention; see Figure 3 The present invention discloses a BOOST type switching power supply voltage regulator, which includes: an input terminal IN, an output terminal OUT, a control terminal CT, an inductor L1, a switch tube NM1, a first P-type channel MOS field effect transistor PM1, a second P-type channel MOS field effect transistor PM2, a capacitor C1, a resistor divider network, an error amplifier EA and a voltage comparator COMP.

[0067] The input terminal IN is used to provide an input voltage; the output terminal OUT is used to provide an output voltage. The same-name end of the inductor L1 is connected to the input terminal IN, and is used to provide current to the load together with the voltage at the input terminal IN after the switch tube NM1 is turned off.

[0068] The switching transistor NM1 is connected between the opposite-polarity terminal of the inductor L1 and ground, and functions as a switching transistor in the circuit. By adjusting the ratio of the on-time to the off-time within a single cycle of NM1, the output voltage at the output terminal is adjusted. In one embodiment, the switching transistor NM1 is an N-type channel MOS field-effect transistor.

[0069] The substrate and drain of the first P-type channel MOS field-effect transistor PM1 are connected together, replacing a diode and reducing voltage loss due to the diode's conduction voltage drop through synchronous rectification. The substrate and source of the second P-type channel MOS field-effect transistor PM2 are connected together, acting as an equivalent resistor to reduce the voltage when the output voltage needs to be lower than the input voltage. The first and second P-type channel MOS field-effect transistors PM1 and PM2 are connected in series between the opposite-signal terminals of inductor L1 and the output terminal OUT.

[0070] Capacitor C1 is connected between the output terminal OUT and ground to provide current to the load when the switch NM1 is turned on. A resistor divider network is connected between the output terminal OUT and ground. In one embodiment, the resistor divider network includes a first resistor R1 and a second resistor R2 connected in series.

[0071] The error amplifier EA takes the output of the resistor divider network and a reference voltage, VREF1, as inputs. The pulse-width modulator PWM takes the output of the error amplifier EA and a sawtooth waveform, Vt, with a period of T, as inputs. The output of the PWM is connected to the gate of the switching transistor NM1. It adjusts the duty cycle of the PWM's output voltage based on the reference voltage, VREF1, thereby adjusting the ratio of the on-time to the off-time within the switching transistor NM1 cycle, ultimately adjusting the output current and output voltage.

[0072] The voltage comparator COMP has an input terminal IN and an output terminal OUT as inputs, and the output of the voltage comparator COMP is connected to the gate of the second P-type channel MOS field effect transistor PM2.

[0073] The control terminal CT is used to control the conduction of the first P-type channel MOS field effect transistor PM1, so that the first P-type channel MOS field effect transistor PM1 can be turned off and on respectively when the switch tube is turned on and off.

[0074] The present invention also discloses a control method for the BOOST type switching power supply voltage regulator, the control method comprising:

[0075] When the switch tube NM1 is turned on, the control terminal CT outputs a high level to turn off the first P-type channel MOS field effect transistor PM1; when the switch tube NM1 is turned off, the control terminal CT outputs a low level to turn on the first P-type channel MOS field effect transistor PM1, thereby reducing the loss caused by the conduction voltage drop of the diode D1;

[0076] A voltage comparator COMP having an input voltage at the input terminal IN and an output voltage at the output terminal OUT as inputs and a second P-channel MOS field effect transistor PM2 whose gate is controlled by the output of the voltage comparator COMP are used to complete the voltage reduction operation when the output voltage value of the output terminal OUT is lower than the input voltage value of the input terminal IN.

[0077] Unlike conventional boost-type switching power supply voltage regulators, the present invention utilizes synchronous rectification technology, replacing the conventional diode D1 with a P-channel MOS field-effect transistor PM1 whose gate is controlled by a control terminal CT. When the switch NM1 is on, the control terminal CT outputs a high level, turning PM1 off; when the switch NM1 is off, the control terminal CT outputs a low level, turning PM1 on. This operation reduces losses caused by the conduction voltage drop of diode D1. Furthermore, a voltage comparator COMP, which uses the input voltage at the input terminal IN and the output voltage at the output terminal OUT as inputs, and a P-channel MOS field-effect transistor PM2, whose gate is controlled by the output of the voltage comparator COMP, are used to step down the voltage when the output voltage at the output terminal OUT falls below the input voltage at the input terminal IN.

[0078] In one embodiment, if the output voltage value at the output terminal OUT needs to be increased or decreased within an adjustment range greater than the input voltage value at the input terminal IN, a corresponding reference voltage VREF1 is set based on the desired output voltage value and the resistor divider network. The error amplifier EA and the pulse width modulator PWM adjust the duty cycle of the square wave output of the pulse width modulator PWM based on the current output voltage divided voltage sampling value and the reference voltage value, thereby adjusting the on-time of the switch tube. This in turn changes the charging time of the inductor L1, thereby correspondingly changing the electrical energy that the inductor L1 can provide to the load during the off-time of the switch tube, resulting in a corresponding change in the output voltage of the output terminal OUT. When the output voltage of the output terminal OUT, after being divided by the resistor divider network, equals the reference voltage VREF1, the feedback loop becomes stable, further stabilizing the output voltage of the output terminal OUT.

[0079] In one embodiment, if the output voltage value at the output terminal OUT needs to be increased or decreased within an adjustment range less than the input voltage value at the input terminal IN, the required output voltage value and the corresponding reference voltage VREF1 set by the resistor divider network are used. The error amplifier EA and the pulse width modulator PWM reduce the duty cycle of the square wave output of the pulse width modulator PWM based on the currently larger output voltage divided voltage sample value and the reference voltage value, thereby shortening the on-time of the switch. This in turn shortens the charging time of the inductor L1. Consequently, during the off-time of the switch, the energy that the inductor L1 can provide to the load is correspondingly reduced, resulting in a decrease in the output voltage at the output terminal OUT.

[0080] When the output voltage of the output terminal OUT drops to equal the input voltage of the input terminal IN, the voltage comparator COMP, which takes the input voltage of the input terminal IN and the output voltage of the output terminal IN as input, detects this situation and outputs a high level to the gate of the P-type channel MOS field effect transistor PM2, causing PM2 to be pinched off. At this time, although the switch tube remains off, the input terminal can directly pass through the PN junction formed by the source and substrate of PM1 to the source of PM2, but it cannot pass through the NP junction formed by the substrate connected to the source and the drain to the output terminal OUT. The only way to pass through PM2 is to transmit through the channel of PM2.

[0081] After PM2 is disconnected, the output voltage at output terminal OUT drops due to the load-to-ground path. When the divided-down sampled output voltage at output terminal OUT falls below the reference voltage, the error amplifier EA and pulse-width modulator PWM output a square wave to the gate of the switching transistor. This restarts the charging and discharging of inductor L1. During the first cycle in which the switching transistor resumes on and off, when the switching transistor is off, the voltage at the opposite-terminal terminal of inductor L1 is equal to the voltage of inductor L1 plus the voltage at input terminal IN. This voltage reaches the source of PM2 through the on-state PM1, causing PM2 to operate in its saturation region, effectively performing a voltage reduction operation like a resistor. Consequently, the output voltage at output terminal OUT changes accordingly, causing the feedback loop to continue adjusting. Ultimately, when the divided-down sampled output voltage at output terminal OUT equals the reference voltage, the feedback loop stabilizes, resulting in a stable output voltage OUT that is lower than the input voltage at input terminal IN.

[0082] As described above, the topology proposed by the present invention utilizes a P-type channel MOS field-effect transistor operating in the saturation region to step down the voltage at low output voltage, thereby achieving an output voltage lower than the input voltage. This output voltage can also be adjusted by setting a reference voltage VREF1. This overcomes the limited output voltage adjustment range of conventional boost-type switching power supply voltage regulators.

[0083] In summary, the BOOST type switching power supply voltage regulator proposed in the present invention can solve the output voltage value limitation of the traditional BOOST type switching power supply voltage regulator structure.

[0084] When the voltage at output terminal OUT is required to be lower than the voltage at input terminal IN, VREF1 is first set to the desired output voltage. Through the feedback loop, the duty cycle D of the pulse width modulator (PWM)'s output square wave is reduced to zero. This effectively connects output terminal OUT to input terminal IN, resulting in the voltage at output terminal OUT being equal to the voltage at input terminal IN. The voltage comparator COMP then detects that the voltage at the output terminal is equal to the voltage at the input terminal and outputs a high level to the gate of PM2, causing PM2 to operate in its saturation region, effectively acting as a resistor and completing the voltage reduction process from input terminal IN to output terminal OUT. At this point, due to the participation of PM2, a new feedback relationship is established, and the output voltage at output terminal OUT, which is lower than the input voltage at input terminal IN, can also be stabilized through the feedback loop.

[0085] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-described embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. Variations and changes to the embodiments disclosed here are possible, and the replacement of the embodiments and various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the present invention. Other variations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A BOOST type switching power supply voltage regulator, characterized in that: The voltage regulator comprises: Input terminal IN, used for providing input voltage; The output terminal OUT is used to provide an output voltage; The inductor L1 has its same-name end connected to the input terminal IN, and is used to provide current to the load together with the voltage at the input terminal IN after the switch tube NM1 is turned off; The switch tube NM1 is connected between the opposite-polarity terminal of the inductor L1 and the ground; A first P-channel MOS field effect transistor PM1, whose substrate and drain are connected together, is used to reduce the voltage loss caused by the diode conduction voltage drop through synchronous rectification technology; The second P-type channel MOS field effect transistor PM2 has its substrate and source connected together, and is used to act as an equivalent resistor to reduce the voltage when the output terminal voltage needs to be lower than the input terminal voltage; the first P-type channel MOS field effect transistor PM1 and the second P-type channel MOS field effect transistor PM2 are connected in series between the opposite-polarity terminal of the inductor L1 and the output terminal OUT; Capacitor C1 is connected between the output terminal OUT and ground, and is used to provide current to the load when the switch tube NM1 is turned on; A resistor divider network is connected between the output terminal OUT and ground; an error amplifier EA having the output of the resistor divider network and a reference voltage VREF1 as inputs; A pulse width modulator (PWM) takes the output of the error amplifier EA and a sawtooth wave Vt with a period of T as input. The output of the PWM is connected to the gate of the switch NM1 to adjust the duty cycle of the PWM output voltage according to the reference voltage VREF1, thereby adjusting the ratio of the on-time to the off-time within the cycle of the switch NM1, and ultimately adjusting the output current and output voltage. a voltage comparator COMP having an input terminal IN and an output terminal OUT as inputs, wherein the output of the voltage comparator COMP is connected to the gate of the second P-channel MOS field effect transistor PM2; The control terminal CT is used to control the conduction of the first P-type channel MOS field effect transistor PM1, so that the first P-type channel MOS field effect transistor PM1 can be turned off and on when the switch tube NM1 is turned on and off respectively; When the switch tube NM1 is turned on, the control terminal CT outputs a high level to turn off the first P-type channel MOS field effect transistor PM1; when the switch tube NM1 is turned off, the control terminal CT outputs a low level to turn on the first P-type channel MOS field effect transistor PM1, thereby reducing the loss caused by the conduction voltage drop of the diode; If the output voltage value of the output terminal OUT needs to be increased or decreased within an adjustment range smaller than the input voltage value of the input terminal IN, the corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network; The error amplifier EA and the pulse width modulator PWM will reduce the duty cycle of the square wave output of the pulse width modulator PWM according to the current larger output voltage divided voltage sampling value and the reference voltage value, shortening the on-time of the switch tube. This in turn shortens the charging time of the inductor L1. As a result, during the off-time of the switch tube, the power that the inductor L1 can provide to the load is also reduced, causing the output voltage of the output terminal OUT to drop. When the output voltage of the output terminal OUT drops to be equal to the input voltage of the input terminal IN, the voltage comparator COMP, which takes the input voltage of the input terminal IN and the output voltage of the output terminal OUT as input, detects this situation and outputs a high level to the gate of the second P-type channel MOS field effect transistor PM2, so that the second P-type channel MOS field effect transistor PM2 is pinched off; At this time, although the switch tube NM1 remains off, the input terminal IN is directly connected to the source of PM2 through the PN junction formed by the source and substrate of the first P-channel MOS field effect transistor PM1, but it cannot be conducted to the output terminal OUT through the NP junction formed by the substrate connected to the source and the drain. The only way to pass through PM2 is to transmit through the channel of PM2; After the second P-type channel MOS field effect transistor PM2 is cut off, the output voltage of the output terminal OUT will become lower due to the path from the load to the ground. When the divided output voltage sample value of the output terminal OUT is less than the reference voltage value, the error amplifier EA and the pulse width modulator PWM will output a square wave to the gate of the switching tube; then the inductor L1 begins to charge and discharge again. In the first cycle in which the switching tube resumes conduction and shutdown, when the switching tube is turned off, the voltage value at the opposite end of the inductor L1 is equal to the voltage value of the inductor L1 plus the voltage value of the input terminal IN. The voltage value at the opposite end of the inductor L1 reaches the source of the second P-type channel MOS field effect transistor PM2 through the turned-on first P-type channel MOS field effect transistor PM1, thereby causing the second P-type channel MOS field effect transistor PM2 to operate in the saturation region, which is equivalent to completing the voltage reduction work of a resistor; The output voltage of the output terminal OUT will change accordingly, causing the feedback loop to continue to adjust; eventually, when the divided voltage sampling value of the output voltage of the output terminal OUT is equal to the reference voltage value, the feedback loop is stable, and a stable output voltage value is further obtained, which is lower than the input voltage value of the input terminal IN.

2. The BOOST type switching power supply voltage regulator according to claim 1, wherein: The resistor divider network includes a first resistor R1 and a second resistor R2 connected in series.

3. The BOOST type switching power supply voltage regulator according to claim 1, wherein: The switch tube NM1 is an N-type channel MOS field effect tube.

4. The BOOST type switching power supply voltage regulator according to claim 1, wherein: A voltage comparator COMP having an input voltage at the input terminal IN and an output voltage at the output terminal OUT as inputs and a second P-channel MOS field effect transistor PM2 whose gate is controlled by the output of the voltage comparator COMP are used to complete the voltage reduction operation when the output voltage value of the output terminal OUT is lower than the input voltage value of the input terminal IN.

5. The BOOST type switching power supply voltage regulator according to claim 1, wherein: If the output voltage value of the output terminal OUT needs to be increased or decreased within an adjustment range greater than the input voltage value of the input terminal IN, the corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network; The error amplifier EA and the pulse width modulator PWM adjust the duty cycle of the square wave output of the pulse width modulator PWM according to the current output voltage divided voltage sampling value and the reference voltage value, so that the on-time of the switch tube is adjusted; thereby, the charging time of the inductor L1 is changed. In this way, the power that the inductor L1 can provide to the load during the off-time of the switch tube is also changed accordingly, resulting in a corresponding change in the output voltage of the output terminal OUT; When the output voltage of the output terminal OUT is divided by the resistor voltage divider network and the divided voltage value is equal to the reference voltage value VREF1, the feedback loop is stable, and the output voltage of the output terminal OUT is further kept stable.

6. A control method for a BOOST type switching power supply voltage regulator according to any one of claims 1 to 5, characterized in that: The control method includes: When the switch tube NM1 is turned on, the control terminal CT outputs a high level to turn off the first P-channel MOS field effect transistor PM1; When the switch tube NM1 is turned off, the control terminal CT outputs a low level to turn on the first P-channel MOS field effect transistor PM1, thereby reducing the loss caused by the conduction voltage drop of the diode; A voltage comparator COMP having an input voltage at the input terminal IN and an output voltage at the output terminal OUT as inputs and a second P-channel MOS field effect transistor PM2 whose gate is controlled by the output of the voltage comparator COMP are used to complete the voltage reduction operation when the output voltage value of the output terminal OUT is lower than the input voltage value of the input terminal IN.

7. The control method according to claim 6, characterized in that: If the output voltage value of the output terminal OUT needs to be increased or decreased within an adjustment range greater than the input voltage value of the input terminal IN, the corresponding reference voltage VREF1 is set according to the required output voltage value and the resistor divider network; The error amplifier EA and the pulse width modulator PWM adjust the duty cycle of the square wave output of the pulse width modulator PWM according to the current output voltage divided voltage sampling value and the reference voltage value, so that the on-time of the switch tube is adjusted; thereby, the charging time of the inductor L1 is changed. In this way, the power that the inductor L1 can provide to the load during the off-time of the switch tube is also changed accordingly, resulting in a corresponding change in the output voltage of the output terminal OUT; When the output voltage of the output terminal OUT is divided by the resistor voltage divider network and the divided voltage value is equal to the reference voltage value VREF1, the feedback loop is stable, and the output voltage of the output terminal OUT is further kept stable.

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