Display device

Abstract

A display device is provided, and includes a plurality of pixels and a power converter configured to receive a first power supply voltage and an external input voltage and to provide a gamma voltage to a first output terminal. The power converter includes a target power supply voltage generator circuit configured to generate a target power supply voltage, a first gamma voltage generator circuit configured to generate a first gamma voltage, a second gamma voltage generator circuit configured to generate a second gamma voltage, a first gap controller configured to generate the second gamma voltage based on the first power supply voltage, a reference target power supply voltage, and a reference gamma voltage during a period when a display mode is switched, and a first selector configured to selectively output the first gamma voltage or the second gamma voltage according to the display mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0048133, filed on April 21, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to display devices, and more particularly to a display device having multiple switchable modes. Background Art

[0004] With the development of information technology, display devices play an increasingly important role as a connection medium between users and information. Accordingly, the use of display devices such as liquid crystal display devices, organic light emitting display devices and / or plasma display devices has increased.

[0005] The driving frequency of the pixels of the display device can be changed according to the display mode. For example, in general image display, the pixels can be driven at a relatively high frequency. On the other hand, in the case of standby mode where only minimal information (e.g., the time of day) is displayed, the pixels can be driven at a relatively low frequency.

[0006] When driving pixels at low frequencies, various solutions have been devised to reduce power consumption of display devices. However, when these solutions are applied, a side effect may occur during the process of changing the driving frequency, which may result in brightness deviation due to rapid voltage or current changes. Summary of the Invention

[0007] Embodiments of the present disclosure are directed to a display device that minimizes brightness deviation that may occur when switching display modes.

[0008] In addition, embodiments of the present disclosure may provide a display device capable of further reducing power consumption in a low-power display mode.

[0009] The embodiments of the present disclosure are not limited to the embodiments described above, and other technical changes, modifications, or substitutions not described herein will be clearly understood by those skilled in the art through the following description.

[0010] A display apparatus according to an embodiment of the disclosure includes: a plurality of pixels; a target power voltage generator circuit configured to generate a target power voltage corresponding to a first power voltage based on an external input voltage; a first gamma voltage generator circuit configured to generate a first gamma voltage based on the external input voltage; a second gamma voltage generator circuit configured to generate a second gamma voltage based on the target power voltage, the first gamma voltage, and the first power voltage; a first gap controller configured to generate the second gamma voltage based on the first power voltage, a reference target power voltage, and a reference gamma voltage during a period in which a display mode is switched to display a frame of the plurality of pixels at a different driving frequency; and a first selector configured to selectively output any one of the first gamma voltage and the second gamma voltage to a first output terminal according to the display mode.

[0011] As an embodiment, the target power voltage generator circuit can include: a first amplifier including a first input terminal inputting the external input voltage, a second input terminal inputting a feedback voltage of the target power voltage, and an output terminal outputting the target power voltage; and a first voltage divider circuit configured to output the feedback voltage of the target power voltage to the second input terminal of the first amplifier.

[0012] As an embodiment, the first gamma voltage generator circuit can include: a second amplifier including a first input terminal inputting the external input voltage, a second input terminal inputting a feedback voltage of the first gamma voltage, and an output terminal outputting the first gamma voltage; and a second voltage divider circuit configured to output the feedback voltage of the first gamma voltage to the second input terminal of the second amplifier.

[0013] As an embodiment, the second gamma voltage generator circuit can include: a first resistor including a first terminal connected to an output terminal of the target power voltage generator circuit and a second terminal connected to a first node; a second resistor including a first terminal connected to the first node and a second terminal connected to a second node; a third resistor including a first terminal connected to an output terminal of the first gamma voltage generator circuit and a second terminal connected to a third node; a fourth resistor including a first terminal connected to the first power voltage and a second terminal connected to the third node; and a third amplifier including a first input terminal connected to the first node, a second input terminal connected to the third node, and an output terminal outputting the second gamma voltage.

[0014] As an embodiment, all resistance values of the first resistor, the second resistor, the third resistor, and the fourth resistor can be the same, and the third amplifier can output the second gamma voltage based on a difference between the first power voltage and the target power voltage and the first gamma voltage.

[0015] As an example, the third amplifier can be turned on during a period in which the plurality of pixels display a frame in a first display mode at a first driving frequency, and can be turned off during a period in which the display mode switches between the first display mode and a second display mode in which the plurality of pixels display a frame at a second driving frequency less than the first driving frequency.

[0016] As an example, the third amplifier can be turned on during a period of the second display mode, or turned off during a period of the second display mode.

[0017] As an example, the third amplifier can be turned off after at least one frame displayed after a period in which the display mode switches from the first display mode to the second display mode.

[0018] As an example, the first gap controller can generate the second gamma voltage based on a difference between the reference target power supply voltage and the reference gamma voltage and the first power supply voltage.

[0019] As an example, the first gap controller can be turned off during a period in which the plurality of pixels display a frame in a first display mode at a first driving frequency or during a period in which the plurality of pixels display a frame in a second display mode at a second driving frequency less than the first driving frequency, and the first gap controller can be turned on during a period in which the display mode switches between the first display mode and the second display mode.

[0020] As an example, the first selector can receive a first selection signal indicating a first display mode in which a frame is displayed at a first driving frequency or a second selection signal indicating a second display mode in which a frame is displayed at a second driving frequency less than the first driving frequency, and when the first selector receives the first selection signal, the first selector can output the second gamma voltage to the first output terminal, and when the first selector receives the second selection signal, the first selector can output the first gamma voltage to the first output terminal.

[0021] As an example, the first selector can include a multiplexer including a first input terminal connected to an output terminal of the second gamma voltage generator circuit and an output terminal of the first gap controller, a second input terminal connected to an output terminal of the first gamma voltage generator circuit, a third input terminal to which the first selection signal or the second selection signal is applied, and an output terminal from which the first gamma voltage or the second gamma voltage is output.

[0022] A power converter according to an embodiment of the disclosure includes: a first input terminal configured to receive an external input voltage; a second input terminal configured to receive a first power voltage for a plurality of pixels; a first output terminal configured to provide a gamma voltage for controlling the plurality of pixels; a target power voltage generator circuit configured to generate a target power voltage corresponding to the first power voltage based on the external input voltage; a first gamma voltage generator circuit configured to generate a first gamma voltage based on the external input voltage; a second gamma voltage generator circuit configured to generate a second gamma voltage based on the target power voltage, the first gamma voltage, and the first power voltage; a first gap controller configured to generate the second gamma voltage based on the first power voltage, a reference target power voltage, and a reference gamma voltage during a period in which a display mode is switched to display a frame of the plurality of pixels at a different driving frequency; a first selector configured to selectively output any one of the first gamma voltage and the second gamma voltage to the first output terminal according to the display mode; a first reference voltage generator circuit configured to generate a first reference voltage based on the external input voltage; a second reference voltage generator circuit configured to generate a second reference voltage based on the target power voltage, the first reference voltage, and the first power voltage; a second gap controller configured to generate the second reference voltage based on the first power voltage, the reference target power voltage, and a reference voltage during a period in which the display mode is switched; and a second selector configured to selectively output any one of the first reference voltage and the second reference voltage to a second output terminal of the power converter according to the display mode.

[0023] As an embodiment, the first reference voltage generator circuit can include: a fourth amplifier including a first input terminal into which the external input voltage is input, a second input terminal into which a feedback voltage of the first reference voltage is input, and an output terminal outputting the first reference voltage; and a third voltage divider circuit configured to output the feedback voltage of the first reference voltage to the second input terminal of the fourth amplifier.

[0024] As an embodiment, the second reference voltage generator circuit can include: a fifth resistor including a first terminal connected to an output terminal of the target power voltage generator circuit and a second terminal connected to a fourth node; a sixth resistor including a first terminal connected to the fourth node and a second terminal connected to a fifth node; a seventh resistor including a first terminal connected to an output terminal of the first reference voltage generator circuit and a second terminal connected to a sixth node; an eighth resistor including a first terminal connected to the first power voltage and a second terminal connected to the sixth node; and a fifth amplifier including a first input terminal connected to the fourth node, a second input terminal connected to the sixth node, and an output terminal outputting the second reference voltage.

[0025] As an example, all resistance values of the fifth resistor, the sixth resistor, the seventh resistor, and the eighth resistor can be the same, and the fifth amplifier can output the second reference voltage based on a difference between the first supply voltage and the target supply voltage and the first reference voltage.

[0026] As an example, the fifth amplifier can be turned on during a period in which the plurality of pixels display a first display mode of a frame at a first driving frequency, and can be turned off during a period in which the display mode switches between a second display mode of the frame at a second driving frequency less than the first driving frequency and the first display mode.

[0027] As an example, the fifth amplifier can be turned on during a period of the second display mode, or turned off during a period of the second display mode.

[0028] As an example, the second gap controller can generate the second reference voltage based on a difference between the reference target supply voltage and the reference voltage and the first supply voltage.

[0029] As an example, the second gap controller can be turned off during a period in which the plurality of pixels display a first display mode of a frame at a first driving frequency or during a period in which the plurality of pixels display a second display mode of the frame at a second driving frequency less than the first driving frequency, and can be turned on during a period in which the display mode switches between the first display mode and the second display mode.

[0030] Specific details of other embodiments include those described in the detailed description and drawings.

[0031] As described above, embodiments of the disclosure can provide a display apparatus that minimizes luminance deviation that can occur when a display mode is switched.

[0032] In addition, embodiments of the disclosure can provide a display apparatus capable of further reducing power consumption in a low power display mode.

[0033] Effects according to embodiments are not limited by the details shown and various alternative effects include those described in this specification. BRIEF DESCRIPTION OF DRAWINGS

[0034] Embodiments of the disclosure will become more fully understood from the detailed description and accompanying drawings, in which:

[0035] Figure 1 is a block diagram for describing a display apparatus according to an embodiment of the disclosure;

[0036] Figure 2 is a circuit diagram for describing a pixel according to an embodiment of the disclosure;

[0037] Figure 3 is a timing diagram for describing an embodiment of driving a pixel according to a first driving frequency;

[0038] Figure 4 is a timing diagram for describing a data write period of a pixel according to an embodiment of the disclosure;

[0039] Figure 5 is a timing diagram for describing an embodiment of driving a pixel according to a second driving frequency;

[0040] Figure 6 is a timing diagram for describing a bias period of a pixel according to an embodiment of the disclosure;

[0041] Figure 7 is a block diagram for describing a data driver according to an embodiment of the disclosure;

[0042] Figure 8 is a block diagram for describing a gray voltage generator according to an embodiment of the disclosure;

[0043] Figure 9 is a timing diagram for describing a problem that occurs when a first power voltage is changed during a period of switching a display mode;

[0044] Figure 10 is a block diagram for describing a power converter according to an embodiment of the disclosure;

[0045] Figure 11 is an equivalent circuit diagram of a power converter according to an embodiment of the disclosure;

[0046] Figure 12 is a circuit diagram illustrating an embodiment in which the power converter shown in Figure 11 operates during a period of a first display mode;

[0047] Figure 13 is a circuit diagram illustrating an embodiment in which the power converter shown in Figure 11 operates during a switching period of a display mode;

[0048] Figure 14 is a circuit diagram illustrating an embodiment in which the power converter shown in Figure 11 operates during a period of a second display mode;

[0049] Figure 15 is a timing diagram for describing an opening time point and a closing time point of the third amplifier and the fifth amplifier shown in Figures 11 to 14 ;

[0050] Figure 16 is a timing diagram for describing a period in which the third amplifier and the fifth amplifier shown in Figure 15A timing diagram of an embodiment of applying black data during a period in which a display mode of the display device is switched from a first display mode to a second display mode;

[0051] Figure 17 It shows Figure 15 and Figure 16 A timing diagram of an enlarged view of A in the graph shown in ; and

[0052] Figure 18 is a block diagram for describing a power converter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Refer to the following when making and attaching Figure 1 The exemplary embodiments and methods of operation of the present disclosure will become apparent from the detailed description of the embodiments below. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various forms. The present embodiment is provided as an example so that the present disclosure will be thorough and complete and those skilled in the art to which the present disclosure belongs can fully understand the scope of the present disclosure. The scope of the present disclosure is limited only by the scope of the appended claims.

[0054] When adding reference numerals to components of each drawing, even if the same or similar components are shown in different drawings, the same or similar components may be given the same or similar reference numerals as much as possible. In addition, when describing the present disclosure, when it is determined that the detailed description of the relevant configuration or function may obscure the main points of the present disclosure, its repeated detailed description may be omitted.

[0055] When describing the components of the present disclosure, terms such as first, second, etc. may be used. These terms are only used to distinguish a component from other components, and the nature, direction, order, quantity, etc. of the corresponding components are not limited by these terms. When a component is described as being "connected" or "coupled" to another component, the component can be directly connected to or coupled to the other component. However, it will be understood that another component can be "interposed" between each component, or each component can be "connected" or "coupled" through another component. Unless the context clearly indicates otherwise, the singular also includes the plural.

[0056] Figure 1 is a diagram for describing a display device according to an embodiment of the present disclosure.

[0057] Reference Figure 1 , the display device 1 may include a timing controller 10 , a data driver 20 , a scan driver 30 , an emission driver 40 , a display unit 50 , and a power supply 60 .

[0058] The timing controller 10 can generate a signal for the display device 1 by receiving an external input signal for each of the image frames from an external processor. For example, the timing controller 10 can provide a gray value and a control signal to the data driver 20. Also, the timing controller 10 can provide a clock signal, a scan start signal, and the like to the scan driver 30. Also, the timing controller 10 can provide a clock signal, a light emission stop signal, and the like to the emission driver 40.

[0059] The timing controller 10 can render a gray value to correspond to a specification of the display device 1. For example, the external processor can provide a red gray value, a green gray value, and a blue gray value for each unit dot. However, when the display unit 50 has a structure in which adjacent unit dots can share a pixel, the pixel does not necessarily correspond one-to-one to each gray value, and rendering of the gray value is used. When the pixel corresponds one-to-one to each gray value, rendering of the gray value can not be necessary. The rendered or unrendered gray value can be provided to the data driver 20. For frame display, the timing controller 10 can provide a control signal suitable for each specification to the data driver 20 and the scan driver 30.

[0060] The power supply 60 can receive a first external input voltage VBAT, and convert the first external input voltage VBAT to provide a data driving voltage AVDD to the data driver 20. For example, the power supply 60 can receive the first external input voltage VBAT from a battery or the like, and step up the first external input voltage VBAT to generate the data driving voltage AVDD, which is a voltage higher than the first external input voltage VBAT.

[0061] The power supply 60 can receive a first external input voltage VBAT, and convert the first external input voltage VBAT to provide a first power voltage VDD and a second power voltage VSS to the display unit 50. For example, when the display device 1 operates in a first display mode as described below with reference to FIG. 2, the power supply 60 can provide the first power voltage VDD and the second power voltage VSS to the display unit 50. Here, the first power voltage VDD and the second power voltage VSS can mean a driving voltage for the pixel PXij included in the display unit 50 to emit light. Figure 3 Figure 4

[0062] The power supply 60 can be configured by, for example, a power management integrated chip (PMIC). The power supply 60 can be configured by, for example, an external DC / DC IC.

[0063] ​​​The data driver 20 can generate data voltages to be supplied to the data lines DL1, DL2, …, DLj, …, and DLm using the grayscale values and the control signals received from the timing controller 10. For example, the data driver 20 can sample the grayscale values by using a clock signal, and can apply data voltages corresponding to the grayscale values to the data lines DL1, DL2, …, DLj, …, and DLm in units of a pixel row (e.g., pixels connected to the same scan line). Here, m and j can be natural numbers.

[0064] The data driver 20 can receive a data driving voltage AVDD from the power supply 60, and generate a scan driving voltage VGH for controlling the display unit 50 by using the data driving voltage AVDD.

[0065] The data driver 20 can receive a second external input voltage VCI, and can generate a gamma voltage and a reference voltage for controlling the display unit 50 based on the second external input voltage VCI. This will be described later with reference to FIG. 2. Figures 7 to 14 This will be described.

[0066] The data driver 20 can be configured by, for example, a separate IC. As another example, the data driver 20 can be configured by an IC integrated with the timing controller 10.

[0067] When the display apparatus 1 operates in the second display mode as described later with reference to FIG. 2, Figure 5 and Figure 6 The data driver 20 can receive the data driving voltage AVDD and convert the data driving voltage AVDD to supply a first power supply voltage VDD and a second power supply voltage VSS to the display unit 50 instead of the power supply 60 when the display apparatus 1 operates in the second display mode as described later with reference to FIG. 2. At this time, the power supply voltage supplied by the data driver 20 can be the same as or less than the power supply voltage supplied by the power supply 60.

[0068] The scan driver 30 can receive a clock signal, a scan start signal, etc. from the timing controller 10 to generate scan signals to be supplied to the scan lines GIL1, GWNL1, GWPL1, GBL1, …, GILi, GWNLi, GWPLi, GBLi, …, GILn, GWNLn, GWPLn, and GBLn. Here, n and i can be natural numbers.

[0069] The scan driver 30 can include a plurality of sub scan drivers. For example, a first sub scan driver can provide scan signals for the scan lines GIL1,..., GILi,..., and GILn, a second sub scan driver can provide scan signals for the scan lines GWNL1,..., GWNLi,..., and GWNLn, a third sub scan driver can provide scan signals for the scan lines GWPL1,..., GWPLi,..., and GWPLn, and a fourth sub scan driver can provide scan signals for the scan lines GBL1,..., GBLi,..., and GBLn. Each of the sub scan drivers can include a plurality of scan stages connected in the form of a shift register. For example, the scan signals can be generated in a method in which a pulse of an on level of a scan start signal supplied to a scan start line is sequentially transferred to a next scan stage.

[0070] For another example, the first sub scan driver and the second sub scan driver can be integrated to provide scan signals for the scan lines GIL1, GWNL1,..., GILi, GWNLi,..., GILn, and GWNLn, and the third sub scan driver and the fourth sub scan driver can be integrated to provide scan signals for the scan lines GWPL1, GBL1,..., GWPLi, GBLi,..., GWPLn, and GBLn. For example, a previous scan line of the nth scan line GWNLn, i.e., the (n-1)th scan line can be connected to the same electrical node as the nth scan line GILn. Also, for example, a next scan line of the nth scan line GWPLn, i.e., the (n+1)th scan line can be connected to the same electrical node as the nth scan line GBLn.

[0071] At this time, the first sub scan driver and the second sub scan driver can supply scan signals having pulses of a first polarity to the scan lines GIL1, GWNL1,..., GILi, GWNLi,..., GILn, and GWNLn. Also, the third sub scan driver and the fourth sub scan driver can supply scan signals having pulses of a second polarity to the scan lines GWPL1, GBL1,..., GWPLi, GBLi,..., GWPLn, and GBLn. The first polarity and the second polarity can be opposite polarities.

[0072] Hereinafter, a polarity can mean a logic level of a pulse. For example, when a pulse is a first polarity, the pulse can have a high level. At this time, the pulse of the high level can be referred to as an up pulse. When the up pulse is supplied to a gate electrode of an N-type transistor, the N-type transistor can be turned on. That is, the up pulse can be an on level with respect to the N-type transistor. Here, it is assumed that a voltage of a sufficiently low level is applied to a source electrode of the N-type transistor compared to the gate electrode. For example, the N-type transistor can be an N-type metal oxide semiconductor (NMOS).

[0073] Further, when the pulse is the second polarity, the pulse can have a low level. At this time, the pulse of the low level can be referred to as a falling pulse. When the falling pulse is supplied to the gate electrode of the P-type transistor, the P-type transistor can be turned on. That is, the falling pulse can be a turn-on level with respect to the P-type transistor. Here, it is assumed that a voltage of a sufficiently high level is applied to the source electrode of the P-type transistor compared to the gate electrode. For example, the P-type transistor can be a P-type metal oxide semiconductor (PMOS).

[0074] The scan driver 30 can generate a scan signal using the scan driving voltage VGH. For example, a scan signal of a high level can be configured by the scan driving voltage VGH. That is, a case where the scan driving voltage VGH is output from the scan stage can be described as outputting a scan signal of a high level. For another example, the scan stage does not directly output the scan driving voltage VGH, and the scan driving voltage VGH can be used as an internal control voltage.

[0075] The emission driver 40 can receive a clock signal, an emission stop signal, and the like from the timing controller 10 to generate an emission signal to be supplied to the emission lines EL1, EL2, …, ELi, …, and ELn. For example, the emission driver 40 can sequentially supply the emission lines EL1, EL2, …, ELi, …, and ELn with an emission signal of a pulse having an off level. For example, the emission driver 40 can be configured in the form of a shift register, and can generate an emission signal in a method of sequentially transferring a pulse of an off level of the emission stop signal to a next emission stage under the control of a clock signal.

[0076] The display unit 50 includes the pixels PXij. For example, the pixel PXij can be connected to the corresponding data line DLj, the scan lines GILi, GWNLi, GWPLi, and GBLi, and the emission line ELi.

[0077] Figure 2 is a diagram for describing a pixel according to an embodiment of the disclosure.

[0078] Referring to Figure 2 The pixel PXij according to an embodiment of the disclosure includes the transistors T1, T2, T3, T4, T5, T6, and T7, the storage capacitor Cst, and the light emitting diode LD.

[0079] The first transistor T1 can be referred to as a driving transistor. The first electrode of the first transistor T1 can be connected to the first electrode of the second transistor T2, the second electrode of the first transistor T1 can be connected to the first electrode of the third transistor T3, and the gate electrode of the first transistor T1 can be connected to the second electrode of the third transistor T3.

[0080] The second transistor T2 can be referred to as a scan transistor. The first electrode of the second transistor T2 can be connected to the first electrode of the first transistor T1, the second electrode of the second transistor T2 can be connected to the data line DLj, and the gate electrode of the second transistor T2 can be connected to the scan line GWPLi.

[0081] The third transistor T3 can be referred to as a diode-connected transistor. The first electrode of the third transistor T3 can be connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3 can be connected to the gate electrode of the first transistor T1, and the gate electrode of the third transistor T3 can be connected to the scan line GWNLi.

[0082] The fourth transistor T4 can be referred to as a gate initialization transistor. The first electrode of the fourth transistor T4 can be connected to the second electrode of the storage capacitor Cst, the second electrode of the fourth transistor T4 can be connected to the initialization line VINTL, and the gate electrode of the fourth transistor T4 can be connected to the scan line GILi.

[0083] The fifth transistor T5 can be referred to as a first light-emitting transistor. The first electrode of the fifth transistor T5 can be connected to the first power supply line VDDL, the second electrode of the fifth transistor T5 can be connected to the first electrode of the first transistor T1, and the gate electrode of the fifth transistor T5 can be connected to the light-emitting line ELi.

[0084] The sixth transistor T6 can be referred to as a second light-emitting transistor. The first electrode of the sixth transistor T6 can be connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6 can be connected to the anode of the light-emitting diode LD, and the gate electrode of the sixth transistor T6 can be connected to the light-emitting line ELi. Although a light-emitting diode is illustrated here as an example of an emission element, it is to be understood that any emission element can be used in alternative embodiments.

[0085] The seventh transistor T7 can be referred to as an anode initialization transistor. The first electrode of the seventh transistor T7 can be connected to the anode of the light-emitting diode LD, the second electrode of the seventh transistor T7 can be connected to the initialization line VINTL, and the gate of the seventh transistor T7 can be connected to the scan line GBLi.

[0086] The storage capacitor Cst can charge a charge corresponding to a difference between voltages respectively applied to two electrodes, or discharge a charged charge. The first electrode of the storage capacitor Cst can be connected to the first power supply line VDDL, and the second electrode of the storage capacitor Cst can be connected to the gate electrode of the first transistor T1.

[0087] An anode of the light emitting diode LD can be connected to a second electrode of the sixth transistor T6, and a cathode of the light emitting diode LD can be connected to a second power supply line VSSL. A voltage applied to the second power supply line VSSL can be set to be lower than a voltage applied to the first power supply line VDDL. The light emitting diode LD can be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0088] The transistors T1, T2, T5, T6, and T7 can be P-type transistors. The P-type transistors are collectively referred to as transistors whose amount of conduction increases when a voltage difference between a gate electrode and a source electrode increases in a negative direction. Channels of the transistors T1, T2, T5, T6, and T7 can be configured of polysilicon. The polysilicon transistor can be a low temperature polysilicon (LTPS) transistor. The polysilicon transistor has a high electron mobility, and thus has a fast driving characteristic. However, the disclosure is not limited thereto, and according to an embodiment, the transistors T1, T2, T5, T6, and T7 can be, for example, N-type oxide semiconductor transistors, rather than P-type polysilicon transistors.

[0089] The transistors T3 and T4 can be N-type transistors. The N-type transistors are collectively referred to as transistors whose amount of conduction increases when a voltage difference between a gate electrode and a source electrode increases in a positive direction. Channels of the transistors T3 and T4 can be configured of oxide semiconductor. The oxide semiconductor transistor can be processed at a low temperature and has a low charge mobility, compared to polysilicon. Thus, the oxide semiconductor transistor has a small leakage current amount generated in an off state, compared to the polysilicon transistor. However, the disclosure is not limited thereto, and according to an embodiment, the transistors T3 and T4 can be P-type polysilicon transistors, rather than oxide semiconductor transistors.

[0090] According to an embodiment, the seventh transistor T7 can be configured of an N-type oxide semiconductor transistor, rather than a polysilicon transistor. At this time, one of the scan lines GWNLi and GILi can be connected to a gate electrode of the seventh transistor T7 by replacing the scan line GBLi.

[0091] The transistors T1, T2, T3, T4, T5, T6, and T7 can be configured in various forms, such as a thin film transistor (TFT), a field effect transistor (FET), and / or a bipolar junction transistor (BJT).

[0092] The pixel PXij according to an embodiment of the present disclosure includes a first transistor T1 having a first connection terminal coupled to a first power supply line VDDL, a control terminal coupled to a storage capacitor Cst, and a second connection terminal coupled to a light emitting diode LD; a second transistor T2 having a first connection terminal coupled to a data line DLj, a control terminal coupled to a scan line GWPLi, and a second connection terminal coupled to the first connection terminal of the first transistor T1; and a third transistor T3 having a first connection terminal coupled to the control terminal of the first transistor T1 and a control terminal coupled to a display mode dependent scan line GWNLi.

[0093] That is, the first display mode of Figure 3 and Figure 4 is compared with the second display mode of Figure 5 and Figure 6 , and the scan line GWNLi carries a display mode dependent signal GWNi. Further, the scan line GILi carries a display mode dependent signal GIi.

[0094] The third transistor T3 can have a second connection terminal coupled to the second connection terminal of the first transistor T1. The pixel PXij can have a fourth transistor T4 having a control terminal coupled to the display mode dependent scan line GILi and a second connection terminal coupled to an initialization line VINTL. The pixel PXij can have a fifth transistor T5 having a first connection terminal coupled to the first power supply line VDDL, a control terminal coupled to a light emitting line ELi, and a second connection terminal coupled to the first connection terminal of the first transistor T1. The pixel PXij can have a sixth transistor T6 having a first connection terminal coupled to the second connection terminal of the first transistor T1, a control terminal coupled to the light emitting line ELi, and a second connection terminal coupled to the light emitting diode LD.

[0095] The pixel PXij can have a seventh transistor T7 having a first connection terminal coupled to the second connection terminal of the fourth transistor T4, a control terminal coupled to a scan line GBLi, and a second connection terminal coupled to the second connection terminal of the sixth transistor T6.

[0096] Figure 3 is a diagram for describing an embodiment in which the pixel is driven according to a first driving frequency.

[0097] The display device 1 can be in a first display mode when the display unit 50 displays a frame at a first driving frequency. In addition, the display device 1 can be in a second display mode when the display unit 50 displays a frame at a second driving frequency less than the first driving frequency.

[0098] In the first display mode, the display device 1 can display image frames at 20 Hz or more, for example, 60 Hz. In this case, the power supply 60 can supply the first power supply voltage VDD and the second power supply voltage VSS to the display unit 50.

[0099] The second display mode can be a low-power display mode or a standby mode. For example, in the standby mode, image frames can be displayed at less than 20 Hz (for example, 1 Hz). For example, a case in which only time and date are displayed in the "always-on display mode" among common modes can correspond to the second display mode. In this case, in order to reduce power consumption, the data driver 20, not the power supply 60, can supply the first power supply voltage VDD and the second power supply voltage VSS to the display unit 50.

[0100] In the first display mode, one period 1T can include a plurality of image frames. One period 1T can be an arbitrarily defined period, and is a period defined for comparison with the second display mode. One period 1T can mean the same time interval in the first display mode and the second display mode.

[0101] In the first display mode, each of the image frames can include a data write period WP and a light emission period EP.

[0102] Hereinafter, a method of driving a pixel PXij for any one of the image frames in one period 1T will be described. Since the same driving method can be applied to other image frames within one period 1T, a repeated description will be omitted. Figure 4 A method of driving a pixel PXij for any one of the image frames in one period 1T will be described. Since the same driving method can be applied to other image frames within one period 1T, a repeated description will be omitted.

[0103] Figure 4 is a diagram for describing a data write period of a pixel according to an embodiment of the disclosure.

[0104] As described above, one image frame in the first display mode can include a data write period WP and a light emission period EP. However, since the data write period WP and the light emission period EP of the present embodiment are for a specific pixel PXij or a specific pixel row (such as pixels connected to the same scan line), the data write period and the light emission period of another pixel connected to another scan line can be different from the data write period and the light emission period of the pixel PXij.

[0105] First, a light emission signal Ei of an off level (for example, a high level) can be supplied to the light emission line ELi during the data write period WP. Accordingly, the fifth transistor T5 and the sixth transistor T6 can be turned off during the data write period WP.

[0106] Next, the signal GIi having the first pulse of the on level (e.g., high level) is supplied to the scan line GILi. Accordingly, the fourth transistor T4 is turned on, and the gate electrode of the first transistor Tl and the initialization line VINTL are connected to each other. Accordingly, the voltage of the gate electrode of the first transistor Tl is initialized to the initialization voltage of the initialization line VINTL, and is held by the storage capacitor Cst. The initialization voltage of the initialization line VINTL can be, for example, a voltage sufficiently lower than the first power supply voltage VDD of the first power supply line VDDL. The initialization voltage can be, for example, a voltage of a level similar to that of the second power supply voltage VSS of the second power supply line VSSL.

[0107] Next, the signals GWPi and GWNi having the first pulse of the on level are supplied to the scan lines GWPLi and GWNLi, respectively, and the corresponding second transistor T2 and third transistor T3 are turned on. Accordingly, the data voltage applied to the data line DLj is written to the storage capacitor Cst through the second transistor T2, the first transistor Tl, and the third transistor T3. However, the data voltage at this time is the data voltage of the previous pixel, and is not used for the emission of the pixel PXij, but is used for applying the on bias voltage to the first transistor Tl. When the on bias voltage is applied before the actual data voltage is written to the first transistor Tl, the hysteresis phenomenon can be improved.

[0108] Next, the signal GBi having the first pulse of the on level (e.g., low level) is supplied to the scan line GBLi, and the seventh transistor T7 is turned on. Thus, the voltage applied to the anode of the light emitting diode LD is initialized.

[0109] At this time, the signal GIi having the second pulse of the on level (e.g., high level) is supplied to the scan line GILi, and the driving process described above is performed again. That is, the on bias voltage is applied to the first transistor Tl again, and the voltage applied to the anode of the light emitting diode LD is initialized.

[0110] By repeating the process described above, when the signals GWPi and GWNi having the third pulse of the on level are supplied to the scan lines GWPLi and GWNLi, respectively, the data voltage of the pixel PXij is written to the storage capacitor Cst. At this time, the data voltage written to the storage capacitor Cst is a voltage reflecting the decrease in the threshold voltage of the first transistor Tl.

[0111] Finally, when the light emission signal Ei becomes an on level (e.g., a low level), the fifth transistor T5 and the sixth transistor T6 are turned on. Accordingly, a drive current path connected to the first power supply line VDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light emitting diode LD, and the second power supply line VSSL is formed, and then a drive current flows. The drive current corresponds to the data voltage stored in the storage capacitor Cst. Specifically, the drive current can be proportional to the square of the difference between the first power supply voltage VDD and the data voltage, and the data voltage can be determined by a gamma voltage and / or a reference voltage. Since the drive current flows through the first transistor T1, a decrease in the threshold voltage of the first transistor T1 is reflected. Accordingly, since the decrease in the threshold voltage reflected in the data voltage stored in the storage capacitor Cst and the decrease in the threshold voltage reflected in the drive current cancel each other out, a drive current corresponding to the data voltage can flow regardless of the threshold voltage value of the first transistor T1.

[0112] According to the amount of the drive current, the light emitting diode LD emits light at a target luminance.

[0113] In this embodiment, each of the scan signals includes three pulses, but in other embodiments, each of the scan signals can include two or four or more pulses. In still another embodiment, each of the scan signals can be configured to include one pulse. In this case, the process of applying an on bias voltage to the first transistor T1 is omitted.

[0114] Figure 5 is a diagram for describing an embodiment in which a pixel is driven according to a second drive frequency.

[0115] In the second display mode, one subframe in one period 1T includes a data write period WP and a light emission period EP, and each of the other subframes in one period 1T includes a bias period BP and a light emission period EP.

[0116] Since the third transistor T3 and the fourth transistor T4 of the pixel PXij remain in an off state in the other subframes during one period 1T, the storage capacitor Cst maintains the same data voltage during a plurality of subframes. In particular, since the third transistor T3 and the fourth transistor T4 can be configured by an oxide semiconductor transistor, a leak current can be minimized.

[0117] Thus, the pixel PXij can display the same image during one period 1T based on a data voltage supplied during a data write period WP of one image frame (1 frame) during one period 1T.

[0118] Figure 6 is a diagram for describing a bias period of a pixel according to an embodiment of the disclosure.

[0119] Referring to Figure 6 In the bias period BP, the scan signal GIi and GWNi of the cutoff level (e.g., low level) are supplied. Thus, as described above, in the bias period BP, the data voltage written to the storage capacitor Cst is constant.

[0120] However, in the bias period BP and the data write period WP, the same emission signal Ei and the scan signals GWPi and GBi are supplied. At this time, the reference data voltage can be applied to the data line DLj. This is to make the emission waveform of the light emitting diode LD similar to each other between a plurality of subframes of one period 1T so that the user does not recognize flicker during low frequency driving.

[0121] Referring to Figures 1 to 6 The described pixel PXij is one embodiment applicable to high frequency driving and low frequency driving. The following described embodiments can also be applied to a pixel having another circuit capable of high frequency driving and low frequency driving. For example, all of the transistors of the pixel can be configured only by P-type transistors. In this case, since the scan driver can include only a sub-scan driver for P-type transistors, the configuration of the scan driver can be simplified. For example, the transistors of the pixel need not include the light emitting transistor. In this case, the emission driver can be unnecessary.

[0122] Figure 7 is a diagram for describing a data driver according to an embodiment of the disclosure.

[0123] Referring to Figure 7 The data driver 20 according to an embodiment of the disclosure can include a power converter 21, a gray voltage generator 22, a shift register 23, a sample latch 24, a hold latch 25, a digital-to-analog converter 26, and an output buffer 27.

[0124] The power converter 21 can receive a data driving voltage AVDD and convert the data driving voltage AVDD to provide a scan driving voltage VGH for control of the pixel PXij to an output terminal. The scan driving voltage VGH can be provided to the scan driver 30.

[0125] In an embodiment, when the display device 1 operates in the second display mode, the power converter 21 can receive a data driving voltage AVDD and convert the data driving voltage AVDD to generate a first power voltage VDD and a second power voltage VSS. At this time, the first power voltage VDD and the second power voltage VSS can be provided to the display unit 50 by the power converter 21. In addition, the first power voltage VDD can be fed back to the power converter 21.

[0126] The power converter 21 can receive the first power supply voltage VDD and the second external input voltage VCI, and provide a gamma voltage VREG for control of the pixel PXij to the output terminal based on the first power supply voltage VDD and the second external input voltage VCI. The gamma voltage VREG can be provided to the grayscale voltage generator 22.

[0127] Here, the magnitude of the gamma voltage VREG can change according to the display mode (e.g., the first display mode and the second display mode). For example, the gamma voltage of the first display mode can be greater than the gamma voltage of the second display mode.

[0128] The power converter 21 can receive the first power supply voltage VDD and the second external input voltage VCI, and provide a reference voltage VREF for control of the pixel PXij to the output terminal based on the first power supply voltage VDD and the second external input voltage VCI. The reference voltage VREF can be provided to the grayscale voltage generator 22.

[0129] Here, the magnitude of the reference voltage VREF can change according to the display mode (e.g., the first display mode and the second display mode).

[0130] The grayscale voltage generator 22 can generate a grayscale voltage GV using the gamma voltage VREG. Since the grayscale voltage GV generated by the grayscale voltage generator 22 is used for display of an image frame, it is necessary to provide a grayscale voltage GV corresponding to the color of the pixel. Accordingly, the grayscale voltage generator 22 can include a first color grayscale voltage generator, a second color grayscale voltage generator, and a third color grayscale voltage generator. Here, for example, the first color can be red, the second color can be green, and the third color can be blue.

[0131] The data signal DCD received from the timing controller 10 can include a source start pulse SSP, a source shift clock SSC, a grayscale value GD, a source output enable signal SOE, and the like.

[0132] The shift register 23 can sequentially generate a sampling signal while shifting the source start pulse SSP at every period 1T of the source shift clock SSC. The number of the sampling signals can correspond to the number of the data lines DL1, …, DLj, …, and DLm. For example, the number of the sampling signals can be the same as the number of the data lines DL1, …, DLj, …, and DLm. For another example, when the display device 1 further includes a demultiplexer between the data driver 20 and the data lines DL1, …, DLj, …, and DLm, the number of the sampling signals can be less than the number of the data lines DL1, …, DLj, …, and DLm. For the convenience of description, it is assumed below that the demultiplexer is not present.

[0133] The sample latch 24 can include a number of sample latch units corresponding to the number of the data lines DL1,..., DLj,..., and DLm, and sequentially receive the gradation values GD for the image frame from the timing controller 10. The sample latch 24 can store the gradation values GD sequentially received from the timing controller 10 in the corresponding sample latch units in response to the sample signals sequentially supplied from the shift register 23.

[0134] The hold latch 25 can include a number of hold latch units corresponding to the number of the data lines DL1,..., DLj,..., and DLm. When the source output enable signal SOE is input, the hold latch 25 can store the gradation values GD stored in the sample latch units in the hold latch units.

[0135] The digital-to-analog converter 26 can include a number of digital-to-analog conversion units corresponding to the number of the data lines DL1,..., DLj,..., and DLm. For example, the number of the digital-to-analog conversion units can be the same as the number of the data lines DL1,..., DLj,..., and DLm. Each of the digital-to-analog conversion units can apply a gradation voltage GV corresponding to the gradation value GD stored in the corresponding hold latch unit to the corresponding data line.

[0136] The output buffer 27 can include buffer units BUF1 to BUFm. For example, each of the buffer units BUF1 to BUFm can be an operational amplifier. Each of the buffer units BUF1 to BUFm can be configured in the form of a voltage follower to apply the output of the digital-to-analog conversion unit to the corresponding data line. For example, the inverting terminal of each of the buffer units BUF1 to BUFm can be connected to its output terminal, and the non-inverting terminal can be connected to the output terminal of the digital-to-analog conversion unit. The output of the buffer units BUF1,..., BUFj,..., and BUFm can be a data voltage.

[0137] For example, an output terminal of the mth buffer unit BUFm can be connected to the mth data line DLm, and the mth buffer unit BUFm can receive a buffer power voltage and a ground power voltage GND. At this time, the buffer power voltage can be a data driving voltage AVDD. The buffer power voltage can determine an upper limit of an output voltage (i.e., a data voltage) of the mth buffer unit BUFm. In addition, the ground power voltage GND can determine a lower limit of the output voltage of the mth buffer unit BUFm. According to the configuration of the mth buffer unit BUFm, a voltage other than the buffer power voltage and the ground power voltage GND can be further applied to the mth buffer unit BUFm. The other voltage can be a control voltage that determines a slew rate of the mth buffer unit BUFm. The control voltage is different from the buffer power voltage and the ground power voltage GND in that the control voltage is not a voltage that determines the upper limit or the lower limit of the output voltage of the mth buffer unit BUFm.

[0138] Figure 8 is a diagram for describing a gray voltage generator according to an embodiment of the disclosure.

[0139] Referring to Figure 8 , an exemplary first color gray voltage generator 22R is illustrated. Other color gray voltage generators can be configured substantially the same as the first color gray voltage generator 22R, and thus a repeated description will be omitted. However, selection values stored in a selection value provider of the other color gray voltage generators can be different from selection values stored in the selection value provider 221 of the first color gray voltage generator 22R.

[0140] The first color gray voltage generator 22R can include a selection value provider 221, a gray voltage output unit 222, resistor strings RS1 to RS11, multiplexers MX1 to MX12, and resistors R1 to R10.

[0141] The selection value provider 221 can provide selection values for the multiplexers MX1 to MX12 according to an input maximum luminance value DBVI. The selection values according to the input maximum luminance value DBVI can be pre-stored in a storage element, for example, an element such as a register.

[0142] Hereinafter, for convenience of description, there are a total of 256 grays from a 0th gray (e.g., a minimum gray) to a 255th gray (e.g., a maximum gray), but there can be more grays when a gray value is expressed with 8 bits or more. The minimum gray is the darkest gray, and the maximum gray can be the brightest gray.

[0143] The maximum luminance value can be a luminance value of light emitted from the pixel corresponding to the maximum gray scale. For example, the maximum luminance value can be a luminance value of a white line generated by causing the pixel of the first color forming one dot to emit corresponding to the 255th gray scale, causing the pixel of the second color to emit corresponding to the 255th gray scale, and causing the pixel of the third color to emit corresponding to the 255th gray scale. The unit of the luminance value can be nits.

[0144] Accordingly, the pixel PXij can partially or spatially display a dark or bright image frame, but the maximum luminance of the image frame is limited to the maximum luminance value. The maximum luminance value can be manually set by a user's manipulation of the display device 1, or can be automatically set by an algorithm associated with an illuminance sensor or the like. At this time, the set maximum luminance value is referred to as an input maximum luminance value DBVI. The first color gray scale voltage generator 22R can be configured to directly receive the input maximum luminance value DBVI from an external processor, or can be configured to receive the input maximum luminance value DBVI through the timing controller 10.

[0145] For example, although the maximum and minimum values can vary depending on the product, the maximum value of the maximum luminance value can be 1200 nits, and the minimum value can be 4 nits. Even if the gray scale values are the same, when the input maximum luminance value DBVI changes, the first color gray scale voltage generator 22R provides different gray scale voltages, and thus the luminance of the emission of the pixel also varies.

[0146] The resistor string RS1 can generate an intermediate voltage of a gamma voltage VREG applied to the first high voltage terminal VH1 and a reference voltage VREF applied to the first low voltage terminal VL1. Here, the gamma voltage VREG can be greater than the reference voltage VREF. The multiplexer MX1 can select one of the intermediate voltages provided from the resistor string RS1 according to a selection value of a selection signal, and output a voltage VT. The multiplexer MX2 can select one of the intermediate voltages provided from the resistor string RS1 according to a selection value, and output a 255th gray scale voltage RGV255.

[0147] The resistor string RS11 can generate an intermediate voltage of the voltage VT and the 255th gray scale voltage RGV255. The multiplexer MX12 can select one of the intermediate voltages provided from the resistor string RS11 according to a selection value of a selection signal, and output a 203rd gray scale voltage RGV203.

[0148] The resistor string RS10 can generate an intermediate voltage of the voltage VT and the 203rd gray scale voltage RGV203. The multiplexer MX11 can select one of the intermediate voltages provided from the resistor string RS10 according to a selection value of a selection signal, and output a 151st gray scale voltage RGV151.

[0149] The resistor string RS9 can generate intermediate voltages of the voltage VT and the 151st gray voltage RGV151. The multiplexer MX10 can select one of the intermediate voltages supplied from the resistor string RS9 in accordance with a selection value of a selection signal, and output the 87th gray voltage RGV87.

[0150] The resistor string RS8 can generate intermediate voltages of the voltage VT and the 87th gray voltage RGV87. The multiplexer MX9 can select one of the intermediate voltages supplied from the resistor string RS8 in accordance with a selection value of a selection signal, and output the 51st gray voltage RGV51.

[0151] The resistor string RS7 can generate intermediate voltages of the voltage VT and the 51st gray voltage RGV51. The multiplexer MX8 can select one of the intermediate voltages supplied from the resistor string RS7 in accordance with a selection value of a selection signal, and output the 35th gray voltage RGV35.

[0152] The resistor string RS6 can generate intermediate voltages of the voltage VT and the 35th gray voltage RGV35. The multiplexer MX7 can select one of the intermediate voltages supplied from the resistor string RS6 in accordance with a selection value of a selection signal, and output the 23rd gray voltage RGV23.

[0153] The resistor string RS5 can generate intermediate voltages of the voltage VT and the 23rd gray voltage RGV23. The multiplexer MX6 can select one of the intermediate voltages supplied from the resistor string RS5 in accordance with a selection value of a selection signal, and output the 11th gray voltage RGV11.

[0154] The resistor string RS4 can generate intermediate voltages of the gamma voltage VREG and the 11th gray voltage RGV11. The multiplexer MX5 can select one of the intermediate voltages supplied from the resistor string RS4 in accordance with a selection value of a selection signal, and output the seventh gray voltage RGV7.

[0155] The resistor string RS3 can generate intermediate voltages of the gamma voltage VREG and the seventh gray voltage RGV7. The multiplexer MX4 can select one of the intermediate voltages supplied from the resistor string RS3 in accordance with a selection value of a selection signal, and output the first gray voltage RGV1.

[0156] The resistor string RS2 can generate intermediate voltages of the gamma voltage VREG and the first gray voltage RGV1. The multiplexer MX3 can select one of the intermediate voltages supplied from the resistor string RS2 in accordance with a selection value of a selection signal, and output the 0th gray voltage RGV0.

[0157] The 0th, 1st, 7th, 11th, 23rd, 35th, 51st, 87th, 151st, 203rd, and 255th gray scales described above can be referred to as reference gray scales. In addition, the gray scale voltages RGV0, RGV1, RGV7, RGV11, RGV23, RGV35, RGV51, RGV87, RGV151, RGV203, and RGV255 generated from the multiplexers MX2 to MX12 can be referred to as reference gray scale voltages. The number of reference gray scales and the number of gray scales corresponding to the reference gray scales can be set differently according to products. Hereinafter, for convenience of description, the 0th, 1st, 7th, 11th, 23rd, 35th, 51st, 87th, 151st, 203rd, and 255th gray scales are described as reference gray scales.

[0158] The gray scale voltage output unit 222 can divide the reference gray scale voltages RGV0, RGV1, RGV7, RGV11, RGV23, RGV35, RGV51, RGV87, RGV151, RGV203, and RGV255 to generate the first color gray scale voltages RGV0 to RGV255. For example, the gray scale voltage output unit 222 can divide the reference gray scale voltages RGV1 and RGV7 to generate the first color gray scale voltages RGV2 to RGV6.

[0159] Figure 9 is a graph for describing a problem that occurs when the first power voltage is changed during a period in which the display mode is switched.

[0160] Referring to Figure 1 and Figure 9 , Figure 9 the graph shown in Figure 9 may show a transition period in which the display mode is switched from the first display mode in which an image frame is displayed at 60 Hz to the second display mode which is a low-power display mode (or in which an image frame is displayed at 1 Hz) and a part of the period of the second display mode. Hereinafter, for convenience, the present embodiment will be described on the basis of a case in which the display mode is switched from the first display mode to the second display mode.

[0161] When the first power voltage VDD1 is constant regardless of the switching of the display mode, when the display mode is switched from the first display mode to the second display mode, in order to reduce power consumption, the second power voltage VSS, the data driving voltage AVDD, etc. can be reduced according to the characteristics of the display mode after the switching, and thus the gamma voltage VREG can also be reduced.

[0162] At this time, the main reason why the gamma voltage VREG decreases during the period when the display mode is switched from the first display mode to the second display mode is because the second power voltage VSS and the data drive voltage AVDD, etc. are decreased.

[0163] During the period of the second display mode, the gap between the gamma voltage VREG and the first power voltage VDD1 is maintained so that the drive current flows to generate the luminance used in the pixel PXij. To this end, the gamma voltage VREG can be increased or decreased according to the ripple of the first power voltage VDD1 so that the gap is maintained.

[0164] In the case where the first power voltage VDD2 is also decreased when the display mode is switched from the first display mode to the second display mode, since the gamma voltage VREG' is decreased to a smaller value according to the decreased first power voltage VDD2, the power consumption can be further decreased, and the gap between the gamma voltage VREG' and the first power voltage VDD2 is gradually decreased during the period when the display mode is switched from the first display mode to the second display mode.

[0165] As the gap between the gamma voltage VREG' and the first power voltage VDD2 is gradually decreased, the drive current flowing through the pixel PXij is not constant either. In addition, the pixel PXij does not emit light with the used luminance, and a luminance deviation occurs in the switching period of the display mode.

[0166] This is because, since the drive current is affected by the difference between the first power voltage VDD and the data voltage and is determined by the data voltage from the gamma voltage, when the gamma voltage is greatly changed, the drive current is greatly changed.

[0167] Since the user perceives the luminance deviation occurring when the display mode is switched, there is a problem that the user feels a sense or a difference.

[0168] Although not shown, differently from Figure 9 When the display mode is switched from the second display mode to the first display mode, the decreased first power voltage VDD2 is increased again, and the gamma voltage VREG' is increased to a larger value according to the increased first power voltage VDD2. Therefore, there is a problem that the gap between the gamma voltage VREG' and the first power voltage VDD2 is not necessarily maintained constant (in this case, the size of the gap is gradually increased) during the period when the display mode is switched from the second display mode to the first display mode.

[0169] Therefore, the gap between the gamma voltage and the first power voltage is maintained constant in order to prevent the luminance difference that can occur during the period when the display mode is switched, while the first power voltage is decreased to decrease the power.

[0170] Figure 10 is a diagram for describing a power converter according to an embodiment of the disclosure.

[0171] Referring to Figure 10 , the power converter 21 according to an embodiment of the disclosure can receive a first power voltage VDD supplied to a pixel and a second external input voltage VCI, provide a gamma voltage for control of the pixel to a first output terminal, and provide a reference voltage to a second output terminal. Here, the first output terminal and the second output terminal can refer to the first high voltage terminal VH1 and the first low voltage terminal VL1 described above with reference to Figure 8 .

[0172] The power converter 21 can include a target power voltage generator 211, a first gamma voltage generator 212, a second gamma voltage generator 213, a first gap controller 214, a first reference voltage generator 215, a second reference voltage generator 216, a second gap controller 217, a first selector 218, a second selector 219, etc.

[0173] The target power voltage generator 211 can generate a target power voltage corresponding to the first power voltage VDD based on the second external input voltage VCI. Here, the target power voltage can refer to a voltage used for the pixel PXij to emit light.

[0174] The first gamma voltage generator 212 can generate a first gamma voltage based on the second external input voltage VCI. Here, the first gamma voltage can refer to a high-level voltage used to generate a gray voltage GV when the display device 1 operates in the second display mode.

[0175] The second gamma voltage generator 213 can generate a second gamma voltage based on the target power voltage, the first gamma voltage, and the first power voltage VDD. Here, the second gamma voltage can refer to a high-level voltage used to generate a gray voltage GV when the display device 1 operates in the first display mode.

[0176] The first gap controller 214 can generate the second gamma voltage based on the first power voltage VDD, a preset reference target power voltage, and a reference gamma voltage during a period when the display mode in which the pixel displays a frame at a driving frequency is switched. Here, the reference target power voltage and the reference gamma voltage can be used to maintain a gap between the gamma voltage and the first power voltage VDD during the period when the display mode is switched, can be determined in advance through experiments, and can be stored in a memory present inside or outside the first gap controller 214.

[0177] Here, the output terminal of the second gamma voltage generator 213 and the output terminal of the first gap controller 214 can be electrically connected to the same node and configured as one output terminal. The one output terminal can be electrically connected to the first selector 218.

[0178] At this time, the first gap controller 214 can be turned on and operated only during a period when the display mode is switched, so that the second gamma voltage output from the second gamma voltage generator 213 and the second gamma voltage output from the first gap controller 214 are not simultaneously input to the first selector 218.

[0179] The first selector 218 can be electrically connected to the output terminal of the second gamma voltage generator 213 and the output terminal of the first gap controller 214 at which the output terminals are connected to the same node to each other, and can be electrically connected to the output terminal of the first gamma voltage generator 212.

[0180] The first selector 218 can selectively output one of the first gamma voltage and the second gamma voltage to the first output terminal (or the first high voltage terminal VH1) of the power converter 21 according to the display mode. For example, when the display device 1 operates in the first display mode, the first selector 218 can output the second gamma voltage to the first output terminal (or the first high voltage terminal VH1) of the power converter 21. For another example, when the display device 1 operates in the second display mode, the first selector 218 can output the first gamma voltage to the first output terminal (or the first high voltage terminal VH1) of the power converter 21.

[0181] The first reference voltage generator 215 can generate a first reference voltage based on the second external input voltage VCI. Here, the first reference voltage can refer to a low-level voltage used to generate the gray voltage GV when the display device 1 operates in the second display mode.

[0182] The second reference voltage generator 216 can generate a second reference voltage based on the target power voltage, the first reference voltage, and the first power voltage VDD. Here, the second reference voltage can refer to a low-level voltage used to generate the gray voltage GV when the display device 1 operates in the first display mode.

[0183] The second gap controller 217 can generate a second reference voltage based on the first power voltage VDD, a preset reference target power voltage, and a reference voltage during a period when the display mode is switched. Here, the preset reference target power voltage and the reference voltage can be determined in advance through experiments similarly to the above-described reference target power voltage and the reference gamma voltage, and can be stored in a memory present inside or outside the second gap controller 217.

[0184] Here, the output terminal of the second reference voltage generator 216 and the output terminal of the second gap controller 217 can be electrically connected to the same node and configured as one output terminal. The one output terminal can be electrically connected to the second selector 219.

[0185] At this time, as with the first gap controller 214, the second gap controller 217 can be turned on and operated only during a period in which the display mode is switched, so that the second reference voltage output from the second reference voltage generator 216 and the second reference voltage output from the second gap controller 217 are not simultaneously input to the second selector 219.

[0186] The second selector 219 can be electrically connected to the output terminal of the second reference voltage generator 216 and the output terminal of the second gap controller 217 at which the output terminals are connected to the same node as each other, and can be electrically connected to the output terminal of the first reference voltage generator 215.

[0187] The second selector 219 can selectively output one of the first reference voltage and the second reference voltage to the second output terminal (or the first low voltage terminal VL1) of the power converter 21 according to the display mode.

[0188] Figure 11 is an equivalent circuit diagram of a power converter according to an embodiment of the disclosure.

[0189] Referring to Figure 11 The target power voltage generator 211 can include a first amplifier AMP1 and a first voltage divider VDV1.

[0190] The first amplifier AMP1 can include a first input terminal to which a second external input voltage VCI is input, a second input terminal to which a feedback voltage of a target power voltage NVDD is input, and an output terminal from which the target power voltage NVDD is output. Here, the first input terminal of the first amplifier AMP1 can be an inverting terminal, and the second input terminal of the first amplifier AMP1 can be a non-inverting terminal.

[0191] The first voltage divider VDV1 can output the feedback voltage of the target power voltage NVDD to the second input terminal of the first amplifier AMP1. The first voltage divider VDV1 can be configured by a plurality of resistors, and a wire extending from a node Na connected with the plurality of resistors can be electrically connected to the second input terminal of the first amplifier AMP1. At this time, the voltage of the node Na can be the feedback voltage of the target power voltage NVDD, and the voltage of the node Na can be input to the second input terminal of the first amplifier AMP1.

[0192] The first gamma voltage generator 212 can include a second amplifier AMP2 and a second voltage divider VDV2.

[0193] The second amplifier AMP2 can include a first input terminal to which a second external input voltage VCI is input, a second input terminal to which a feedback voltage of the first gamma voltage VREG1 is input, and an output terminal from which the first gamma voltage VREG1 is output.

[0194] The second voltage divider VDV2 can output the feedback voltage of the first gamma voltage VREG1 to the second input terminal of the second amplifier AMP2. Like the first voltage divider VDV1, the second voltage divider VDV2 can be configured by a plurality of resistors, and a wire extending from a node Nb to which the plurality of resistors are connected can be electrically connected to the second input terminal of the second amplifier AMP2. At this time, the voltage of the node Nb can be the feedback voltage of the first gamma voltage VREG1.

[0195] The second gamma voltage generator 213 can include a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a third amplifier AMP3.

[0196] The first resistor R1 can include a first terminal connected to the output terminal of the target power supply voltage generator 211, and a second terminal. Specifically, the first terminal of the first resistor R1 can be connected to the output terminal of the first amplifier AMP1, and the second terminal of the first resistor R1 can be connected to the first node N1.

[0197] The second resistor R2 can include a first terminal connected to the first node N1 and a second terminal connected to the second node N2.

[0198] The third resistor R3 can include a first terminal connected to the output terminal of the first gamma voltage generator 212, and a second terminal. Specifically, the first terminal of the third resistor R3 can be connected to the output terminal of the second amplifier AMP2, and the second terminal of the third resistor R3 can be connected to the third node N3.

[0199] The fourth resistor R4 can include a first terminal connected to the first power supply voltage VDD and a second terminal connected to the third node N3.

[0200] Here, the respective resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can be different values, and can be the same value. Hereinafter, for convenience, the present embodiment will be described under the assumption that the respective resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are all the same value.

[0201] The third amplifier AMP3 can include a first input terminal connected to the first node N1, a second input terminal connected to the third node N3, and an output terminal from which the second gamma voltage VREG2 is output. Here, the first input terminal of the third amplifier AMP3 can be an inverting terminal, and the second input terminal of the third amplifier AMP3 can be a non-inverting terminal.

[0202] The first gap controller 214 can include a first operation circuit COM1 that performs an operation using a pre-stored reference target power voltage NVDD_SET, a reference gamma voltage VREG_SET, and the first power voltage VDD.

[0203] The first selector 218 can receive a selection signal SEL indicating a display mode, and output either of the first gamma voltage VREG1 and the second gamma voltage VREG2 to the first output terminal (or the first high voltage terminal VH1) according to the display mode indicated by the selection signal SEL.

[0204] Specifically, the first selector 218 can receive a first selection signal indicating a first display mode in which a frame is displayed at a first driving frequency or a second selection signal indicating a second display mode in which a frame is displayed at a second driving frequency less than the first driving frequency. Here, the first selection signal and the second selection signal can be pulse-type signals. A pulse of the first selection signal can have a first polarity, a high level, and a digital value 1. A pulse of the second selection signal can have a second polarity, a low level, and a digital value 0. However, the disclosure is not limited thereto, and the pulse of each of the first selection signal and the second selection signal can be set differently from the above-described example according to experiments or products.

[0205] As an embodiment, when the first selector 218 receives the first selection signal, the second gamma voltage VREG2 can be output to the first output terminal (or the first high voltage terminal VH1).

[0206] As another embodiment, when the first selector 218 receives the second selection signal, the first gamma voltage VREG1 can be output to the first output terminal (or the first high voltage terminal VH1).

[0207] The first selector 218 can include a first multiplexer MUX1. The first multiplexer MUX1 can include a first input terminal connected to the output terminal of the second gamma voltage generator 213 and the output terminal of the first gap controller 214, a second input terminal connected to the output terminal of the first gamma voltage generator 212, a third input terminal to which the first selection signal or the second selection signal is applied, and an output terminal from which the first gamma voltage VREG1 or the second gamma voltage VREG2 is output.

[0208] For a specific example, the first input terminal of the first multiplexer MUX1 is connected to the second node N2, the second input terminal of the first multiplexer MUX1 is connected to the output terminal of the second amplifier AMP2, the third input terminal of the first multiplexer MUX1 receives a selection signal, and the first gamma voltage VREG1 or the second gamma voltage VREG2 is output at the output terminal of the first multiplexer MUX1. At this time, the output terminal of the first multiplexer MUX1 can refer to the first output terminal (or the first high voltage terminal VH1) of the power converter 21.

[0209] As described above, the first selector 218 can be implemented as the first multiplexer MUX1, but is not limited thereto, and the first selector 218 can include a plurality of switches instead of the first multiplexer MUX1.

[0210] The first reference voltage generator 215 can include a fourth amplifier AMP4 and a third voltage divider VDV3.

[0211] The fourth amplifier AMP4 can include a first input terminal inputting a second external input voltage VCI, a second input terminal inputting a feedback voltage of the first reference voltage VREF1, and an output terminal outputting the first reference voltage VREF1. Here, the first input terminal of the fourth amplifier AMP4 can be an inverting terminal, and the second input terminal of the fourth amplifier AMP4 can be a non-inverting terminal.

[0212] The third voltage divider VDV3 can output the feedback voltage of the first reference voltage VREF1 to the second input terminal of the fourth amplifier AMP4. Like the first voltage divider VDV1 and the second voltage divider VDV2, the third voltage divider VDV3 can be configured by a plurality of resistors, and a wire extending from a node Nc to which the plurality of resistors are connected can be electrically connected to the second input terminal of the fourth amplifier AMP4. At this time, the voltage of the node Nc can be the feedback voltage of the first reference voltage VREF1.

[0213] The second reference voltage generator 216 can include a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a fifth amplifier AMP5.

[0214] The fifth resistor R5 can include a first terminal connected to the output terminal of the target power voltage generator 211, and a second terminal. Specifically, the first terminal of the fifth resistor R5 can be connected to the output terminal of the first amplifier AMP1, and the second terminal of the fifth resistor R5 can be connected to the fourth node N4.

[0215] The sixth resistor R6 can include a first terminal connected to the fourth node N4 and a second terminal connected to the fifth node N5.

[0216] The seventh resistor R7 can include a first terminal connected to an output terminal of the first reference voltage generator 215 and a second terminal. Specifically, the first terminal of the seventh resistor R7 can be connected to the output terminal of the fourth amplifier AMP4, and the second terminal of the seventh resistor R7 can be connected to the sixth node N6.

[0217] The eighth resistor R8 can include a first terminal connected to the first power supply voltage VDD and a second terminal connected to the sixth node N6.

[0218] Here, the respective resistance values of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 can be different values, and can be the same value. Hereinafter, for convenience, the present embodiment will be described under the assumption that the respective resistance values of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are all the same value.

[0219] The fifth amplifier AMP5 can include a first input terminal connected to the fourth node N4, a second input terminal connected to the sixth node N6, and an output terminal from which the second reference voltage VREF2 is output. Here, the first input terminal of the fifth amplifier AMP5 can be an inverting terminal, and the second input terminal of the fifth amplifier AMP5 can be a non-inverting terminal.

[0220] The second gap controller 217 can include a second operation circuit COM2 that performs an operation using the pre-stored reference target power supply voltage NVDD_SET, the reference voltage VREF_SET, and the first power supply voltage VDD.

[0221] Like the first selector 218, the second selector 219 can receive a selection signal SEL indicating a display mode, and output either one of the first reference voltage VREF1 and the second reference voltage VREF2 to the second output terminal (or the first low voltage terminal VL1) according to the display mode indicated by the selection signal SEL.

[0222] For example, when the second selector 219 receives a first selection signal, the second reference voltage VREF2 can be output to the second output terminal (or the first low voltage terminal VL1). For another example, when the second selector 219 receives a second selection signal, the first reference voltage VREF1 can be output to the second output terminal (or the first low voltage terminal VL1).

[0223] The second selector 219 can include a second multiplexer MUX2. The second multiplexer MUX2 can include a first input terminal, a second input terminal, a third input terminal, and an output terminal.

[0224] For a specific example, the first input terminal of the second multiplexer MUX2 is connected to the fifth node N5, the second input terminal of the second multiplexer MUX2 is connected to the output terminal of the fourth amplifier AMP4, the third input terminal of the second multiplexer MUX2 receives a selection signal, and the output terminal of the second multiplexer MUX2 outputs the first gamma voltage VREG1 or the second gamma voltage VREG2. At this time, the output terminal of the second multiplexer MUX2 can refer to the second output terminal (or the first low voltage terminal VL1) of the power converter 21.

[0225] As described above, the second selector 219 can include a plurality of switches instead of the second multiplexer MUX2.

[0226] Figure 12 is a graph illustrating an embodiment of the power converter shown in Figure 11 FIG. 4 is a graph illustrating an embodiment of the power converter shown in FIG. 1, which operates during a period of the first display mode.

[0227] Referring to Figure 12 During the first display mode in which the pixels display a frame at the first driving frequency, the third amplifier AMP3 can be turned on. For example, when power for driving the third amplifier AMP3 is supplied, the third amplifier AMP3 can be turned on.

[0228] At this time, when all resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are the same, the third amplifier AMP3 can output the second gamma voltage VREG2 based on a difference between the first power voltage VDD and the target power voltage NVDD and the first gamma voltage VREG1. For example, the second gamma voltage VREG2 can be calculated by Equation 1 below.

[0229] [Equation 1]

[0230] VREG2 = VREG1 + (VDD - NVDD)

[0231] In the first display mode in which the pixels display a frame at the first driving frequency, the fifth amplifier AMP5 can be turned on similarly to the third amplifier AMP3.

[0232] And at this time, when all resistance values of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are the same, the fifth amplifier AMP5 can output the second reference voltage VREF2 based on a difference between the first power voltage VDD and the target power voltage NVDD and the first reference voltage VREF1. For example, the second reference voltage VREF2 can be calculated by Equation 2 below.

[0233] [Equation 2]

[0234] VREF2 = VREF1 + (VDD - NVDD)

[0235] During the period of the first display mode, the first gap controller 214 can be turned off and does not need to operate. Also, during the period of the first display mode, the second gap controller 217 can also be turned off and does not need to operate.

[0236] Here, in the case of the first display mode, since the first selection signal is input to each of the first selector 218 and the second selector 219, the first selector 218 can output the second gamma voltage VREG2 output from the third amplifier AMP3 to the first output terminal (or the first high voltage terminal VH1), and the second selector 219 can output the second reference voltage VREF2 output from the fifth amplifier AMP5 to the second output terminal (or the first low voltage terminal VL1).

[0237] Figure 13 is shown in FIG. 1. Figure 11 FIG. 2 is a diagram of an embodiment of the power converter shown in FIG. 1 operating during a switching period of a display mode.

[0238] Referring to Figure 13 , the switching period of the display mode can be a period in which the display mode is switched between the first display mode and the second display mode, and can refer to a period in which the display mode is switched from the first display mode to the second display mode, or a period in which the display mode is switched from the second display mode to the first display mode.

[0239] As an embodiment, during a period in which the display mode is switched between the second display mode in which the pixels display a frame at a second driving frequency less than the first driving frequency and the first display mode, the third amplifier AMP3 can be turned off, and the first gap controller 214 can be turned on.

[0240] This prevents the second gamma voltage VREG2 output from the first gap controller 214 and the second gamma voltage VREG2 output from the third amplifier AMP3 from being simultaneously input to the first selector 218, thereby preventing erroneous operation.

[0241] The first gap controller 214 that is turned on can generate the second gamma voltage VREG2 based on a difference between the reference target power voltage and the reference gamma voltage and the first power voltage VDD. For example, the second gamma voltage VREG2 can be calculated by Equation 3 below.

[0242] [Equation 3]

[0243] VREG2 = VDD + (VREG_SET - NVDD_SET)

[0244] Here, NVDD_SET can refer to the reference target power voltage, and VREG_SET can refer to the reference gamma voltage. Each of the reference target power voltage and the reference gamma voltage can be a predetermined constant, and can be a digital value. The second gamma voltage VREG2 can vary according to the first power voltage VDD. Ultimately, a gap between the first power voltage VDD and the second gamma voltage VREG2 can be maintained during a period in which the display mode is switched.

[0245] Similarly to the operation of the third amplifier AMP3, during a period in which the display mode is switched between the second display mode in which a frame is displayed at the second driving frequency that is less than the first driving frequency and the first display mode, the fifth amplifier AMP5 can be turned off, and the second gap controller 217 can be turned on.

[0246] This prevents the second reference voltage VREF2 output from the second gap controller 217 and the second reference voltage VREF2 output from the fifth amplifier AMP5 from being simultaneously input to the second selector 219, thereby preventing an erroneous operation.

[0247] The second gap controller 217 that is turned on can generate the second reference voltage VREF2 based on a difference between the reference target power voltage and the reference voltage and the first power voltage VDD. For example, the second reference voltage VREF2 can be calculated by Equation 4 below.

[0248] [Equation 4]

[0249] VREF2 = VDD + (VREF_SET - NVDD_SET)

[0250] Here, NVDD_SET can refer to the reference target power voltage, and VREF_SET can refer to a preset reference voltage. Each of the reference target power voltage and the preset reference voltage can be a predetermined constant, and can be a digital value. The second reference voltage VREF2 varies according to the first power voltage VDD.

[0251] Here, in a period in which the display mode is switched, since the display mode has not yet been completely switched, the selection signal corresponding to the display mode before the switching can be applied to each of the first selector 218 and the second selector 219, and can be maintained. As Figure 13 As shown in FIG. 6, in a period in which the display mode is switched from the first display mode to the second display mode, the first selection signal can be continuously input to each of the first selector 218 and the second selector 219.

[0252] However, since the first gap controller 214 and the second gap controller 217 are turned on and operated, and the third amplifier AMP3 and the fifth amplifier AMP5 are turned off and not operated, during the period in which the display mode is switched, the first selector 218 can output the second gamma voltage VREG2 output from the first gap controller 214 to the first output terminal, and the second selector 219 can output the second reference voltage VREF2 output from the second gap controller 217 to the second output terminal (or the first low voltage terminal VL1).

[0253] Figure 14 is a view illustrating an embodiment of the power converter shown in FIG. 6, which is operated during a period of the second display mode. Figure 11

[0254] Referring to Figure 14 , the third amplifier AMP3 and / or the fifth amplifier AMP5 can be turned off during a period of the second display mode. In addition, the first gap controller 214 and / or the second gap controller 217 can be turned off during a period of the second display mode. At this time, the second gamma voltage VREG2 and / or the second reference voltage VREF2 need not be generated.

[0255] In this case, the first selector 218 can receive the second selection signal and output the first gamma voltage VREG1 output from the first gamma voltage generator 212 to the first output terminal (or the first high voltage terminal VH1), and the second selector 219 can receive the second selection signal and output the first reference voltage VREF1 output from the first reference voltage generator 215 to the second output terminal (or the first low voltage terminal VL1).

[0256] As described above, when the third amplifier AMP3 and / or the fifth amplifier AMP5 are turned off during a period of the second display mode, since the first gamma voltage VREG1 and the first reference voltage VREF1 are determined based on the second external input voltage VCI, regardless of the first power voltage VDD, power consumption is reduced.

[0257] ​The display apparatus 1 can also apply a second gamma voltage VREG2 reflecting the first power voltage VDD and a second reference voltage VREF2 to the second display mode so as to display an image (or frame) of higher luminance in the second display mode. In this case, the third amplifier AMP3 and / or the fifth amplifier AMP5 can be turned on during a period of the second display mode.

[0258] The turning-on and turning-off points of time of the third amplifier AMP3 and / or the fifth amplifier AMP5 are adjusted for the effects of reducing power consumption and displaying an image of excellent image quality in the second display mode.

[0259] Figure 15 is a graph for describing Figures 11 to 14 the turning-on and turning-off points of time of the third amplifier and the fifth amplifier shown in FIG.

[0260] Referring to Figure 15 In the case of the first display mode, the display apparatus 1 displays an image frame at, for example, 60 Hz, and in the case of the second display mode, the display apparatus 1 displays an image frame at, for example, 1 Hz. Accordingly, a period in which a pulse of the vertical synchronization period V_SYNC occurs can be shorter in the first display mode than in the second display mode.

[0261] The period in which the pulse of the vertical synchronization period V_SYNC occurs can correspond to one frame.

[0262] When the display mode is switched from the first display mode to the second display mode, the third amplifier AMP3 turned on in the first display mode can be turned off after at least one frame displayed after a transition period in which the display mode is switched from the first display mode to the second display mode.

[0263] Referring to Figure 15 For example, the third amplifier AMP3 can be turned off after a first frame displayed initially in the second display mode is displayed.

[0264] Although not shown, for another example, the third amplifier AMP3 can be turned off during a transition period in which the display mode is switched from the first display mode to the second display mode.

[0265] Although not shown, for yet another example, the third amplifier AMP3 can be turned off immediately after a transition period in which the display mode is switched from the first display mode to the second display mode elapses.

[0266] When an instruction signal for switching the display mode from the first display mode to the second display mode is received, the third amplifier AMP3 turned off can be turned on during a period of the second display mode.

[0267] Similarly to the third amplifier AMP3, the fifth amplifier AMP5 turned on in the first display mode can be turned off after at least one frame displayed after a transition period when the display mode is switched from the first display mode to the second display mode. Referring to Figure 15 , for example, the fifth amplifier AMP5 can be turned off after a first frame to be displayed initially in the second display mode is displayed.

[0268] When the display mode is switched from the second display mode to the first display mode, the third amplifier AMP3 and / or the fifth amplifier AMP5 can be turned on before a transition period when the display mode is switched from the second display mode to the first display mode.

[0269] Figure 16 is a graph for describing an embodiment of applying black data during a period when the display mode of Figure 15 is switched from the first display mode to the second display mode.

[0270] Referring to Figure 16 , during a transition period when the display mode is switched from the first display mode to the second display mode, black data (or a black frame) can be applied to the data lines DL1, DL2, …, DLj, …, and DLm. The black data can refer to data that causes the pixels PXij included in the display unit 50 not to emit light, and a gray level corresponding to the black data can be a minimum gray level, i.e., a darkest gray level.

[0271] Since the black data is applied during a transition period when the display mode is switched from the first display mode to the second display mode, it is possible to prevent a user from recognizing a luminance change that can occur when the display mode is switched.

[0272] When the black data is applied, in a case where a gray level corresponding to the black data is slightly higher than the minimum gray level, flicker can occur in the display unit 50 during a transition period when the display mode is switched from the first display mode to the second display mode.

[0273] In this case, a gap between the first power voltage VDD and the second gamma voltage VREG2 is maintained, thereby preventing the occurrence of flicker in the display unit 50.

[0274] During a transition period when the display mode is switched from the second display mode to the first display mode, it is not necessary to insert the black data.

[0275] Figure 17 is a zoomed-in view of A in the graph shown in Figure 15 and Figure 16

[0276] Referring to Figure 17 ​, A is a magnified view of a transition period of the display mode. According to an embodiment of the disclosure, even if the first power voltage VDD is reduced to further reduce power consumption in a second display mode that is a low-power display mode, a gap between the first power voltage VDD and the second gamma voltage VREG2 can be maintained during a transition period of the display mode and during the first display mode and the second display mode. Since the gap is always maintained, a driving current flowing through the pixel PXij is also maintained constant, thereby preventing a luminance deviation that occurs when the display mode is changed.

[0277] Figure 18 is a diagram for describing a power converter according to another embodiment of the disclosure.

[0278] Referring to Figure 18 , a power converter 21' according to another embodiment of the disclosure is similar to the power converter 21 shown in Figure 10 in that the power converter 21' includes a target power voltage generator 211, a first gamma voltage generator 212, a second gamma voltage generator 213, a first gap controller 214, a first reference voltage generator 215, a second reference voltage generator 216, a second gap controller 217, a first selector 218, and a second selector 219. Thus, the description thereof is omitted below.

[0279] However, Figure 17 the power converter 21' shown in Figure 10 differs from the power converter 21 shown in

[0280] The first switch SW1 can be closed so that the second gamma voltage generator 213 and the first selector 218 are electrically connected during the first display mode. In addition, the first switch SW1 can be opened so that the second gamma voltage generator 213 and the first selector 218 are electrically separated during a transition period of switching the display mode.

[0281] The second switch SW2 can be closed so that the first gap controller 214 and the first selector 218 are electrically connected during the transition period of switching the display mode. In addition, the second switch SW2 can be opened so that the first gap controller 214 and the first selector 218 are electrically separated during a period of the first display mode or during a period of the second display mode.

[0282] The third switch SW3 can be closed to electrically connect the second reference voltage generator 216 and the second selector 219 during the first display mode. Also, the third switch SW3 can be opened to electrically separate the second reference voltage generator 216 and the second selector 219 during the transition period of switching the display mode.

[0283] The fourth switch SW4 can be closed to electrically connect the second gap controller 217 and the second selector 219 during the transition period of switching the display mode. Also, the fourth switch SW4 can be opened to electrically separate the second gap controller 217 and the second selector 219 during the period of the first display mode or during the period of the second display mode.

[0284] As described above, during the transition period of switching the display mode, the second gamma voltage VREG2 output from each of the second gamma voltage generator 213 and the first gap controller 214 is prevented from being simultaneously input to the first selector 218, and the second reference voltage VREF2 output from each of the second reference voltage generator 216 and the second gap controller 217 is prevented from being simultaneously input to the second selector 219. Accordingly, incorrect operation can be prevented.

[0285] As described above, embodiments of the present disclosure can provide a display apparatus that minimizes luminance deviation when switching a display mode.

[0286] Also, embodiments of the present disclosure can provide a display apparatus that can further reduce power consumption in a low power display mode.

[0287] Although exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art to which the present disclosure pertains that the embodiments can be implemented in other specific forms without changing the technical spirit and scope of the present disclosure. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and are not restrictive.

Claims

1. A display device comprising: Multiple pixels; as well as a power converter configured to receive a first power voltage supplied to the plurality of pixels and an external input voltage, and provide a gamma voltage for controlling the plurality of pixels to a first output terminal, The power converter comprises: a target power supply voltage generator circuit configured to generate a target power supply voltage corresponding to the first power supply voltage based on the external input voltage; a first gamma voltage generator circuit configured to generate a first gamma voltage based on the external input voltage; a second gamma voltage generator circuit configured to generate a second gamma voltage based on the target power voltage, the first gamma voltage, and the first power voltage; a first gap controller configured to generate the second gamma voltage based on the first power voltage, a reference target power voltage, and a reference gamma voltage during a period in which a display mode is switched to display a frame of the plurality of pixels at a different driving frequency; and A first selector is configured to selectively output any one of the first gamma voltage and the second gamma voltage to the first output terminal according to the display mode.

2. The display device according to claim 1, wherein The target power supply voltage generator circuit comprises: a first amplifier including: a first input terminal for inputting the external input voltage, a second input terminal for inputting a feedback voltage of the target power supply voltage, and an output terminal for outputting the target power supply voltage; and A first voltage divider circuit is configured to output the feedback voltage of the target power supply voltage to the second input terminal of the first amplifier.

3. The display device according to claim 1, wherein The first gamma voltage generator circuit includes: a second amplifier including: a first input terminal to which the external input voltage is input, a second input terminal to which a feedback voltage of the first gamma voltage is input, and an output terminal to output the first gamma voltage; and A second voltage divider circuit is configured to output the feedback voltage of the first gamma voltage to the second input terminal of the second amplifier.

4. The display device according to claim 1, wherein The second gamma voltage generator circuit includes: a first resistor including a first terminal connected to an output terminal of the target power supply voltage generator circuit and a second terminal connected to a first node; a second resistor including a first terminal connected to the first node and a second terminal connected to a second node; a third resistor including a first terminal connected to the output terminal of the first gamma voltage generator circuit and a second terminal connected to a third node; a fourth resistor including a first terminal connected to the first power supply voltage and a second terminal connected to the third node; and The third amplifier includes a first input terminal connected to the first node, a second input terminal connected to the third node, and an output terminal outputting the second gamma voltage.

5. The display device according to claim 4, wherein All resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor are the same as each other, and The third amplifier outputs the second gamma voltage based on a difference between the first power voltage and the target power voltage and the first gamma voltage. The display device according to claim 4 , wherein: The third amplifier is turned on during a period of a first display mode in which the plurality of pixels display frames at a first driving frequency, and is turned off during a period in which the display mode is switched between a second display mode in which the plurality of pixels display frames at a second driving frequency less than the first driving frequency and the first display mode.

7. The display device according to claim 6, wherein: The third amplifier is turned on during the period of the second display mode or turned off during the period of the second display mode, and the third amplifier is turned off after at least one frame displayed after the period in which the display mode is switched from the first display mode to the second display mode.

8. The display device according to claim 1, wherein The first gap controller generates the second gamma voltage based on the difference between the reference target power supply voltage and the reference gamma voltage and the first power supply voltage, and the first gap controller is turned off during a period of a first display mode in which the plurality of pixels display frames at a first driving frequency or during a period of a second display mode in which the plurality of pixels display frames at a second driving frequency less than the first driving frequency, and is turned on during a period in which the display mode switches between the first display mode and the second display mode.

9. The display device according to claim 1, wherein The first selector receives a first selection signal indicating a first display mode in which frames are displayed at a first driving frequency or a second selection signal indicating a second display mode in which frames are displayed at a second driving frequency lower than the first driving frequency, When the first selector receives the first selection signal, the first selector outputs the second gamma voltage to the first output terminal, and When the first selector receives the second selection signal, the first selector outputs the first gamma voltage to the first output terminal.

10. The display device according to claim 9, wherein The first selector includes a multiplexer, the multiplexer including: a first input terminal connected to the output terminal of the second gamma voltage generator circuit and the output terminal of the first gap controller; a second input terminal connected to the output terminal of the first gamma voltage generator circuit; a third input terminal, to which the first selection signal or the second selection signal is applied; and an output terminal, from which the first gamma voltage or the second gamma voltage is output.

Images