Pixel and display device comprising the same

Abstract

The present invention relates to a pixel and a display device including the same. The pixel includes a driving transistor including a semiconductor layer and a gate electrode; and a compensation transistor connected to the gate electrode and the semiconductor layer of the driving transistor, wherein the compensation transistor includes a first sub-transistor including a first gate electrode receiving a first scan signal having a first voltage level during a period, and a second sub-transistor connected in parallel to the first sub-transistor and including a second gate electrode receiving a second scan signal having a second voltage level which is an inverted level of the first voltage level during the same period.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0049482, filed with the Korean Intellectual Property Office on April 23, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to pixels and display devices including such pixels. Background Technology

[0004] Display devices such as flat panel displays (FPDs) are electronic devices used to view content (e.g., still / moving images). FPD devices are lighter, thinner, and use less power than traditional cathode ray tube (CRT) devices. A display device includes multiple pixels, each pixel comprising a display element and pixel circuitry for controlling electrical signals transmitted to the display element. The pixel circuitry may include one or more transistors. The transistors may include compensation transistors and drive transistors. However, in some cases, the compensation transistor is the cause of a recoil voltage at the gate node of the drive transistor, which results in a perceived image retention. Therefore, there is a need to improve the quality of images generated by display devices that include pixel circuitry. Summary of the Invention

[0005] At least one exemplary embodiment of this disclosure provides a display device capable of preventing image retention.

[0006] According to an exemplary embodiment of the present disclosure, a pixel includes: a driving transistor including a semiconductor layer and a gate electrode; and a compensation transistor connected to the gate electrode and the semiconductor layer of the driving transistor. The compensation transistor includes: a first sub-transistor including a first gate electrode that receives a first scan signal having a first voltage level during a time period; and a second sub-transistor connected in parallel to the first sub-transistor and including a second gate electrode that receives a second scan signal having a second voltage level that is inversely related to the first voltage level during the same time period.

[0007] The first sub-transistor can be a P-channel thin-film transistor, and the second sub-transistor can be an N-channel thin-film transistor.

[0008] The pixel may further include: a first scan line that transmits a first scan signal to a first sub-transistor and is connected to the first sub-transistor; and a second scan line that transmits a second scan signal to a second sub-transistor and is connected to the second sub-transistor, wherein the first scan line and the second scan line extend in parallel, and a driving transistor is located between the first scan line and the second scan line.

[0009] The pixel can further include a first node electrode connecting the semiconductor layer of the first sub transistor and the gate electrode of the driving transistor to each other, and a second node electrode connecting the semiconductor layer of the second sub transistor and the gate electrode of the driving transistor to each other.

[0010] The pixel can further include a capacitor overlapping the driving transistor.

[0011] The pixel can further include a data line and a driving voltage line disposed on the same layer as the first node electrode.

[0012] The driving transistor can include a P-channel thin film transistor.

[0013] Each of the first and second sub transistors can include a semiconductor layer including silicon.

[0014] The first sub transistor can include a semiconductor layer including silicon, and the second sub transistor can include a semiconductor layer having an oxide.

[0015] The pixel can further include an initialization transistor connected to the gate electrode of the driving transistor and an initialization voltage line.

[0016] The initialization transistor can include a semiconductor layer including an oxide.

[0017] According to an exemplary embodiment of the disclosure, a pixel includes a driving transistor including a semiconductor layer and a gate electrode, and a compensation transistor connected to the gate electrode and the semiconductor layer of the driving transistor. The compensation transistor includes a first sub transistor including a first gate electrode receiving a first scan signal having a first voltage level during a period and a second gate electrode receiving a second scan signal having a second voltage level which is an inversion of the first voltage level during the same period, and a second sub transistor connected in series to the first sub transistor and including a third gate electrode receiving the first scan signal.

[0018] The pixel can further include a first scan line connected to the first gate electrode of the first sub transistor and the third gate electrode of the second sub transistor, and a second scan line connected to the second gate electrode of the first sub transistor.

[0019] The second gate electrode can be disposed on a lower layer of the first gate electrode, and the third gate electrode can be disposed on the same layer as the first gate electrode.

[0020] The pixel can further include a capacitor overlapping the driving transistor.

[0021] The pixel can further include a node electrode connecting the semiconductor layer of the compensation transistor and the gate electrode of the driving transistor to each other, and a data line and a driving voltage line disposed on the same layer as the node electrode.

[0022] According to an example embodiment of the disclosure, a display device includes a plurality of pixels, and each of the plurality of pixels includes: a driving transistor including a semiconductor layer and a gate electrode; and a compensation transistor connected to the gate electrode and the semiconductor layer of the driving transistor. The compensation transistor includes: a first sub-transistor including a first gate electrode receiving a first scan signal having a first voltage level during a time period; and a second sub-transistor including a second gate electrode receiving a second scan signal having a second voltage level which is an inversion of the first voltage level during the same time period.

[0023] The first sub-transistor and the second sub-transistor can be connected in parallel, the first sub-transistor can be a P-channel thin film transistor, and the second sub-transistor can be an N-channel thin film transistor.

[0024] The first sub-transistor can include a semiconductor layer including silicon, and the second sub-transistor can include a semiconductor layer including an oxide.

[0025] The display device can further include a third gate electrode receiving the first scan signal during the same time period, wherein the third gate electrode can be disposed on a lower layer of the second gate electrode and disposed on the same layer as the first gate electrode.

[0026] According to an example embodiment of the disclosure, a pixel includes a driving transistor and a compensation transistor. The compensation transistor is connected to a gate electrode of the driving transistor. The compensation transistor includes a first sub-transistor and a second sub-transistor. The first sub-transistor includes a first gate electrode receiving a first scan signal having a first logic level during a first time period of a frame period and receiving a second scan signal having a second logic level different from the first logic level during a second time period of the frame period. The second sub-transistor is connected in parallel to the first sub-transistor and includes a second gate electrode receiving the second scan signal having the second logic voltage level during the first time period and having the first logic level during the second time period.

[0027] In an example embodiment, the driving transistor further includes a semiconductor layer, and the compensation transistor is further connected to the semiconductor layer of the driving transistor.

[0028] In an example embodiment, one of the sub-transistors is a P-channel thin film transistor, and the other of the sub-transistors is an N-channel thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other aspects, features, and elements of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1is a schematic perspective view of a display device illustrating exemplary embodiments according to the present disclosure;

[0031] Figure 2 is a schematic cross-sectional view of a display device illustrating exemplary embodiments according to the present disclosure;

[0032] Figure 3 is an equivalent circuit diagram of a pixel illustrating exemplary embodiments according to the present disclosure;

[0033] Figure 4 is a timing diagram of the driving of a pixel according to exemplary embodiments of the present disclosure Figure 3

[0034] Figure 5 is an equivalent circuit diagram of a pixel illustrating exemplary embodiments according to the present disclosure;

[0035] Figure 6 is a timing diagram of the driving of a pixel according to exemplary embodiments of the present disclosure Figure 5

[0036] is a plan view of a portion of a pixel circuit illustrating exemplary embodiments according to the present disclosure Figure 7A Figure 5

[0037] Figure 7B is an enlarged plan view of a portion of a display device illustrating exemplary embodiments according to the present disclosure along lines IIa-IIa' and IIb-IIb' of Figure 7A

[0038] Figure 8A is an equivalent circuit diagram of a pixel illustrating exemplary embodiments according to the present disclosure; Figure 8B Figure 7B is a plan view of a pixel circuit illustrating exemplary embodiments according to the present disclosure

[0039] Figure 9 is an enlarged plan view of a portion of a display device illustrating exemplary embodiments according to the present disclosure along lines III-III' of

[0040] Figure 10 Figure 9 is a plan view of a pixel circuit illustrating exemplary embodiments according to the present disclosure

[0041] Figure 10A is an enlarged plan view of a portion of a display device illustrating exemplary embodiments according to the present disclosure along lines III-III' of Figure 10

[0042] is a cross-sectional view of a display device illustrating exemplary embodiments according to the present disclosure along lines III-III' of Figure 11 Figure 10A

[0043] Figure 12 ​​​​​​​​is an equivalent circuit diagram of a pixel illustrating exemplary embodiments according to the present disclosure;

[0044] Figure 13 is a plan view of a pixel circuit illustrating exemplary embodiments according to the present disclosure; Figure 12

[0045] Figure 13A is an enlarged plan view of a portion of the pixel circuit of Figure 13

[0046] Figure 14A and Figure 14B is a cross-sectional view of the display device taken along lines IVa-IVa' and IVb-IVb' of Figure 13A

[0047] Figure 15 is a schematic plan view of a display panel illustrating exemplary embodiments according to the present disclosure. DETAILED DESCRIPTION

[0048] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Throughout the drawings and the specification, like reference numerals refer to like elements. In this regard, the present disclosure can have different forms and is not necessarily limited to the description set forth herein. Accordingly, a number of exemplary embodiments will be described below by referencing the drawings to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0049] As the present disclosure allows for various changes and numerous embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. Reference will be made to drawings that will aid in understanding the present disclosure, the advantages thereof, and the objects that are achieved by the implementation of the present disclosure. However, the present disclosure can be embodied in many different forms and is not necessarily limited to the example embodiments set forth herein.

[0050] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms can be only used to distinguish one element from another.

[0051] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. ​​​

[0052] It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, or elements, but do not preclude the presence or addition of one or more other features, integers, steps, or elements.

[0053] It will be understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly on the other layer, region, or element, or intervening layers, regions, or elements can also be present. For example, an intervening layer, region, or element can be present.

[0054] The size of the components in the drawings can be exaggerated for the purpose of explanation. In other words, since the size and thickness of the components in the drawings can be exaggerated for the purpose of explanation, the following embodiments are not necessarily limited thereto.

[0055] In the disclosure, an expression such as "A and / or B" indicates A, B, or A and B. Also, an expression such as "at least one of A and B" indicates A, B, or A and B.

[0056] In the following embodiments, a description that a line "extends in a first direction or a second direction" includes a case where the line extends in a straight line, and includes a case where the line extends in a zigzag shape or a curve along the first direction or the second direction.

[0057] In the following embodiments, when an element is referred to as "on" another element, it is understood that the element is directly on the other element, and when an element is referred to as "on" a plane, it is understood that the element is observed from the top, and when an element is referred to as "in a cross section", it is understood that the element is cut vertically and observed from the side. In the following embodiments, when elements "overlap" each other, the elements overlap each other "on a plane" and "in a cross section".

[0058] In the following embodiments, when X and Y are connected to each other, the connection can include an electrical connection, a functional connection, and a direct connection between X and Y. Here, X and Y can refer to objects (for example, devices, apparatuses, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Thus, such a connection is not necessarily limited to a specific connection, for example, a connection in the drawings or the detailed description, and can include a connection other than the above-described connection.

[0059] For example, when X and Y are electrically connected to each other, one or more devices (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) can be present between X and Y to allow an electrical connection between X and Y.

[0060] In embodiments, the term "on" regarding device states can refer to the active state of the device, and the term "off" can refer to the inactive state of the device. The term "on" used relative to a signal received by the device can refer to a signal used to activate the device, and the term "off" can refer to a signal used to deactivate the device. The device can be activated based on a high-level voltage or a low-level voltage. For example, a P-channel transistor is activated based on a low-level voltage, and an N-channel transistor is activated based on a high-level voltage. Therefore, it should be interpreted that the "on" voltages applied to the P-channel transistor and the N-channel transistor are opposite to each other (low to high).

[0061] Figure 1 This is a schematic perspective view of a display device according to exemplary embodiments of the present disclosure. Figure 2 This is a schematic cross-sectional view of a display device according to exemplary embodiments of the present disclosure, and can be compared with... Figure 1 The section cut by line I-I' corresponds to the section cut by line I-I'.

[0062] The display device according to one or more embodiments can be implemented as an electronic device such as a smartphone, mobile phone, smartwatch, navigation device, gaming device, television (TV), car head unit, portable computer, tablet computer, personal multimedia player (PMP), or personal digital assistant (PDA). Furthermore, the electronic device can be a flexible device.

[0063] Display device 1 includes a display area DA for displaying an image and a peripheral area PA surrounding the display area DA. Display device 1 can provide a specific image by using light emitted from pixels arranged in the display area DA.

[0064] The shape of the display device 1 can vary. For example, the shape may include a rectangle with two pairs of parallel sides. When the shape of the display device 1 is rectangular, either pair of sides may be larger than the other pair. For ease of discussion, it is assumed that the shape of the display device 1 is a rectangle comprising a pair of long sides and a pair of short sides. However, embodiments of the display device 1 are not limited to this shape. The direction in which the short sides extend is a first direction (e.g., the x-direction), the direction in which the long sides extend is a second direction (e.g., the y-direction), and the direction perpendicular to the above extension directions is a third direction (e.g., the z-direction). In an exemplary embodiment, the display device 1 has a non-rectangular shape. The non-rectangular shape may be, for example, a circle, an ellipse, a partially circular polygon, or a polygon other than a square.

[0065] When the display area DA is planar, the display area DA can have the following characteristics: Figure 1 The rectangular shape shown is used. In an exemplary embodiment, the shape of the display area DA is a polygon such as a triangle, pentagon, hexagon, circle, ellipse, or an atypical shape.

[0066] The peripheral area PA is an area around the display area DA, and can be of a type of a non-display area in which pixels are not disposed. The display area DA can be completely surrounded by the peripheral area PA. The peripheral area PA can include a pad (e.g., a conductive element). Various wiring for transmitting an electrical signal to the display area DA, a printed circuit board, or a driver IC chip can be attached to the pad.

[0067] Hereinafter, an organic light emitting display device is used as the display device 1 according to an embodiment, but embodiments of the disclosure are not limited to this specific type of display device. In exemplary embodiments, the display device 1 can be an inorganic light emitting display (or inorganic EL display) device or a quantum dot light emitting display device.

[0068] Reference Figure 2 The display device 1 includes a display panel 10, an input sensing layer 40 disposed on the display panel 10, and an optical functional layer 50 disposed on the input sensing layer 40. The display panel 10, the input sensing layer 40, and the optical functional layer 50 can be covered by a window 60. For example, the window 60 can be made of a transparent material such as glass or plastic.

[0069] The display panel 10 can display an image. The display panel 10 includes pixels disposed in a display area DA. Each pixel can include a display element. The display element can be connected to a pixel circuit. The display element can include an organic light emitting diode or a quantum dot organic light emitting diode.

[0070] The input sensing layer 40 can obtain coordinate information according to an external input (e.g., a touch event). For example, the input sensing layer 40 can determine a location within the display panel 10 that is touched by a user. The input sensing layer 40 can include a sensing electrode (or touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 can be disposed on the display panel 10. The input sensing layer 40 can detect an external input in a mutual capacitance manner and / or a self-capacitance manner.

[0071] The input sensing layer 40 can be directly formed on the display panel 10 or can be separately formed. The input sensing layer 40 can be coupled to the display panel 10 by using an adhesive layer such as an optically clear adhesive. For example, the input sensing layer 40 can be continuously formed after a process of forming the display panel 10. The input sensing layer 40 can be a part of the display panel 10. In exemplary embodiments, an adhesive layer is not disposed between the input sensing layer 40 and the display panel 10. Figure 2It is shown that the input sensing layer 40 is disposed between the display panel 10 and the optical function layer 50. However, in an exemplary embodiment, the input sensing layer 40 is disposed on the optical function layer 50. For example, the input sensing layer 40 can be disposed between the window 60 and the optical function layer 50.

[0072] The optical function layer 50 can include an anti-reflection layer. The anti-reflection layer can reduce the reflectance of light (external light) incident to the display panel 10 from the outside through the window 60. In an exemplary embodiment, the anti-reflection layer includes a retarder (or wave plate) and a polarizer. In an exemplary embodiment, the retarder transmits a beam of light and changes its polarization state without attenuating, deviating, or shifting the light beam. In an exemplary embodiment, the polarizer is a light filter that allows light waves of a specific polarization to pass through while blocking light waves of other polarizations. The retarder can be of a film type or a liquid crystal coating type, and can include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer can also be of a film type or a liquid crystal coating type. The polarizer of the film type can include a stretchable synthetic resin film, and the polarizer of the liquid crystal coating type can include liquid crystals arranged in a specific arrangement. The retarder and the polarizer can further include a protective film. The retarder and the polarizer themselves or the protective film can be a base layer of the anti-reflection layer.

[0073] In an exemplary embodiment, the anti-reflection layer includes a black matrix and a color filter. The color filter can be arranged by considering colors of light emitted from pixels, respectively. In an exemplary embodiment, the anti-reflection layer includes a destructive interference structure. The destructive interference structure can include a first reflection layer and a second reflection layer arranged at different layers. First reflected light and second reflected light respectively reflected from the first reflection layer and the second reflection layer destructively interfere with each other, and the reflectance of the external light can be accordingly reduced.

[0074] In an exemplary embodiment, the optical function layer 50 includes a lens layer (e.g., a lens). The lens layer can improve the output efficiency of light emitted from the display panel 10 or can reduce chromatic aberration. The lens layer can include a layer having a convex lens shape or a concave lens shape and / or can include layers having different refractive indexes. The optical function layer 50 can include both the anti-reflection layer and the lens layer, or can include either one of the anti-reflection layer and the lens layer.

[0075] In an embodiment, the optical function layer 50 is continuously formed after a process of forming the display panel 10 and / or the input sensing layer 40. In an embodiment, when the optical function layer 50 is continuously formed, an adhesive layer is not disposed between the optical function layer 50 and the display panel 10 and / or the input sensing layer 40.

[0076] Figure 3 is an equivalent circuit diagram of a pixel of a display panel 10 illustrating an exemplary embodiment according to the inventive concept. Figure 4 is a diagram showing Figure 3a timing chart of driving of a pixel.

[0077] Referring to Figure 3 The pixel P1 includes an organic light emitting diode OLED as a display element and a pixel circuit PC1 connected to the organic light emitting diode OLED. The pixel circuit PC1 can include first to seventh transistors T1 to T7, and a first terminal of each of the first to seventh transistors T1 to T7 can be a source terminal or a drain terminal, and a second terminal of each of the first to seventh transistors T1 to T7 can be different from the first terminal, according to the type (p-type or n-type) and / or operating condition of the transistor. For example, when the first terminal is the source terminal, the second terminal can be the drain terminal. In an embodiment, the first to seventh transistors T1 to T7 can be implemented by P-channel multi-oxide semiconductor field effect transistors (MOSFETs) or P-channel metal-oxide-semiconductor (PMOS) transistors.

[0078] The pixel circuit PC1 is connected to a first scan line SL1 that transmits a first scan signal GW, a second scan line SL2 that transmits a second scan signal GI, a third scan line SL3 that transmits a third scan signal GB, an emission control line EL that transmits an emission control signal EM, and a data line DL that transmits a data signal DATA.

[0079] The pixel circuit PC1 is further connected to a driving voltage line PL and first and second initialization voltage lines VL1 and VL2. The driving voltage line PL transmits a driving voltage ELVDD to the first transistor T1. The first initialization voltage line VL1 can transmit an initialization voltage Vint to a gate terminal of the first transistor T1. The second initialization voltage line VL2 can transmit the initialization voltage Vint to the organic light emitting diode OLED.

[0080] The first transistor T1 includes a gate terminal connected to a second node N2, a first terminal connected to a first node N1, and a second terminal connected to a third node N3. The first transistor T1 functions as a driving transistor and receives the data signal DATA according to a switching operation of the second transistor T2, thus providing a driving current to the organic light emitting diode OLED.

[0081] The second transistor T2 (a switching transistor) includes a gate terminal connected to the first scan line SL1, a first terminal connected to the data line DL, and a second terminal connected to the first node N1 (or the first terminal of the first transistor T1). The second transistor T2 can be turned on in response to the first scan signal GW transmitted through the first scan line SL1, and can perform a switching operation of transmitting the data signal DATA transmitted to the data line DL to the first node N1.

[0082] The third transistor T3 (a compensation transistor) includes a gate terminal connected to the first scan line SL1, a first terminal connected to the second node N2 (or the gate terminal of the first transistor T1), and a second terminal connected to the third node N3 (or the second terminal of the first transistor T1). The third transistor T3 can be turned on in response to the first scan signal GW transmitted through the first scan line SL1, and can diode-connect the first transistor T1 to compensate for the threshold voltage of the first transistor T1. The third transistor T3 can have a structure in which at least two transistors are connected in series. For example, Figure 3 The third transistor T3 shown in FIG. 1B can be implemented by a pair of transistors connected in series.

[0083] The fourth transistor T4 (a first initialization transistor) includes a gate terminal connected to the second scan line SL2, a first terminal connected to the first initialization voltage line VL1, and a second terminal connected to the second node N2. The fourth transistor T4 can be turned on in response to the second scan signal GI transmitted through the second scan line SL2, and transmit the initialization voltage Vint to the gate terminal of the first transistor T1, thereby initializing the gate voltage of the first transistor T1. The fourth transistor T4 can have a structure in which at least two transistors are connected in series. For example, Figure 3 The fourth transistor T4 shown in FIG. 1B can be implemented by a pair of transistors connected in series.

[0084] The fifth transistor T5 (a first emission control transistor) includes a gate terminal connected to the emission control line EL, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first node N1. The sixth transistor T6 (a second emission control transistor) includes a gate terminal connected to the emission control line EL, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM transmitted through the emission control line EL, and thus a driving current flows in the organic light emitting diode OLED.

[0085] The seventh transistor T7 (second initialization transistor) includes a gate terminal connected to the third scan line SL3, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to the second initialization voltage line VL2. The seventh transistor T7 can be turned on in response to the third scan signal GB transmitted through the third scan line SL3, and can initialize the voltage of the pixel electrode of the organic light emitting diode OLED by transmitting the initialization voltage Vint to the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 can not be formed. In an exemplary embodiment, the seventh transistor T7 is omitted. When the seventh transistor T7 is omitted, the second initialization voltage line VL2 can be directly connected to the organic light emitting diode OLED.

[0086] The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the driving voltage line PL.

[0087] The organic light emitting diode OLED can include the pixel electrode and a common electrode facing the pixel electrode. The common electrode can receive the common voltage ELVSS. In an exemplary embodiment, the driving voltage ELVDD is higher than the common voltage ELVSS. The organic light emitting diode OLED emits a specific color of light after receiving the driving current from the first transistor T1, and thus an image can be displayed. The common electrode can be shared by the pixel P1 and one or more pixels as the pixel P1.

[0088] Reference Figure 4 During one frame or frame period, the pixel P1 is driven in the first time period t1, the second time period t2, and the third time period t3. The display panel 10 can include several rows of pixels. Each row can be sequentially driven during the frame period so that one frame of image data is output to the display panel 10 during the frame period. During one horizontal period 1H, the first scan signal GW and the second scan signal GI can be applied as a turn-on voltage. Here, the term "turn-on voltage" can refer to the on voltage of a transistor, and can be a voltage having a low level. Although not shown in FIG. 1, the third scan signal GB can be applied as a turn-on voltage having a low level with the same timing. In an exemplary embodiment, only one row of pixels is driven during one horizontal period 1H. Figure 4

[0089] ​The first time period t1 is a period in which the second node N2 connected to the gate terminal of the first transistor T1 is initialized and an on bias (e.g., a bias voltage or current) is applied to the gate terminal of the first transistor T1. In the first time period t1, the second scan signal GI having a low level is transmitted to the second scan line SL2, and the fourth transistor T4 is turned on accordingly. The voltage of the second node N2 (i.e., the voltage of the gate terminal of the first transistor T1) is initialized by the initialization voltage Vint supplied from the first initialization voltage line VL1.

[0090] The second time period t2 is a threshold voltage compensation and data write period. In the second time period t2, the first scan signal GW having a low level is transmitted to the first scan line SL1, and the second transistor T2 is turned on accordingly. The data signal DATA supplied from the data line DL is transmitted to the first node N1. When the second transistor T2 is turned on, the third transistor T3 is simultaneously turned on to diode-connect the first transistor T1, and a compensation voltage (e.g., a threshold voltage of the first transistor T1) compensated in the data signal DATA is applied to the second node N2 (i.e., the gate terminal of the first transistor T1). Accordingly, the driving voltage ELVDD and the compensation voltage are applied to both ends of the capacitor Cst, respectively, and a charge corresponding to a voltage difference between both ends of the capacitor Cst is stored in the capacitor Cst.

[0091] In the exemplary embodiment, the emission control signal EM transmitted to the emission control line EL during the first time period t1 and the second time period t2 has a constant high level, and the level of the emission control signal EM is transitioned from the high level to the low level in the third time period t3. The third time period t3 is an emission period in which the organic light emitting diode OLED emits light. In the third time period t3, the fifth transistor T5 and the sixth transistor T6 are turned on. A driving current corresponding to the charge stored in the capacitor Cst is supplied to the organic light emitting diode OLED through the first transistor T1, and thus, the organic light emitting diode OLED emits light.

[0092] When the second time period t2 changes to the third time period t3, the third transistor T3, which has been turned on, is turned off, and thus, the voltage of the second node N2 (e.g., the voltage V G of the gate terminal of the first transistor T1) can change due to a parasitic capacitance C gs generated between the gate terminal of the third transistor T3 and the first terminal. G The change in the voltage V G of the gate terminal of the first transistor T1 is referred to as a kickback voltage ΔV KB . When the pixel P1 displays black and then displays white, a residual image can be perceived in the image due to the kickback voltage ΔV KB .

[0093] Since the kickback voltage ΔV KB is proportional to the size of the parasitic capacitance C gs , it is necessary to reduce the kickback voltage ΔV gs by reducing the parasitic capacitance C KB of the third transistor T3 to reduce the residual image.

[0094] Figure 5 is an equivalent circuit diagram of a pixel illustrating an exemplary embodiment according to the inventive concept. Figure 6 is a timing chart for driving of the pixel of Figure 5 .

[0095] Referring to Figure 5 , the pixel P2 includes an organic light emitting diode OLED as a display element and a pixel circuit PC2 connected to the organic light emitting diode OLED. The pixel circuit PC2 includes first to seventh transistors T1, T2, T3A, T4, T5, T6, T7, and a first terminal of each of the first to seventh transistors T1, T2, T3A, T4, T5, T6, T7 can be a source terminal or a drain terminal and a second terminal of each of the first to seventh transistors T1, T2, T3A, T4, T5, T6, T7 can be different from the first terminal according to the type (p-type or n-type) of the transistor and the operating condition. For example, when the first terminal is the source terminal, the second terminal can be the drain terminal.

[0096] In an embodiment, a 3-2 transistor T32 of the third transistor T3A among the first to seventh transistors T1, T2, T3A, T4, T5, T6, T7 can be implemented by an N-channel MOSFET or an N-channel metal oxide semiconductor (NMOS) transistor, and the remaining transistors among the first to seventh transistors T1, T2, T3A, T4, T5, T6, T7 can each be implemented by a PMOS transistor.

[0097] The pixel circuit PC2 can be connected to a first scan line SL1 transmitting a first scan signal GW, a second scan line SL2 transmitting a second scan signal GI, a third scan line SL3 transmitting a third scan signal GB, a fourth scan line SL4 transmitting a fourth scan signal GWn, an emission control line EL transmitting an emission control signal EM, and a data line DL transmitting a data signal DATA.

[0098] The pixel circuit PC2 can also be connected to a driving voltage line PL and first and second initialization voltage lines VL1 and VL2. The driving voltage line PL can transmit a driving voltage ELVDD to the first transistor T1. The first initialization voltage line VL1 can transmit an initialization voltage Vint to the gate terminal of the first transistor T1. The second initialization voltage line VL2 can transmit the initialization voltage Vint to the organic light emitting diode OLED.

[0099] The first transistor T1 includes a gate terminal connected to the second node N2, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The first transistor T1 functions as a driving transistor and provides a driving current to the organic light emitting diode OLED by receiving a data signal DATA according to a switching operation of the second transistor T2.

[0100] The second transistor T2 (a switching transistor) includes a gate terminal connected to the first scan line SL1, a first terminal connected to the data line DL, and a second terminal connected to the first node N1 (or the first terminal of the first transistor). The second transistor T2 can be turned on in response to a first scan signal GW transmitted through the first scan line SL1 and can perform a switching operation of transmitting a data signal DATA transmitted to the data line DL to the first node N1.

[0101] The third transistor T3A (a compensation transistor) can include two sub-transistors connected in parallel. For example, as shown in FIG. 1B, the third transistor T3A includes a 3-1 transistor T31 as a first sub-transistor and a 3-2 transistor T32 as a second sub-transistor. The 3-1 transistor T31 can be a PMOS transistor, and the 3-2 transistor T32 can be an NMOS transistor. Figure 5

[0102] The 3-1 transistor T31 includes a gate terminal connected to the first scan line SL1, a first terminal connected to the second node N2 (or the gate terminal of the first transistor T1), and a second terminal connected to the third node N3 (or the second terminal of the first transistor T1). The 3-2 transistor T32 includes a gate terminal connected to the fourth scan line SL4, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The 3-1 transistor T31 can be turned on in response to a first scan signal GW transmitted through the first scan line SL1, and the 3-2 transistor T32 can be turned on in response to a fourth scan signal GWn transmitted through the fourth scan line SL4. In an exemplary embodiment, the fourth scan signal GWn is an inverted signal of the first scan signal GW. The 3-1 transistor T31 and the 3-2 transistor T32 can be turned on at the same time and can diode-connect the first transistor T1. ​

[0103] The fourth transistor T4 can include two sub-transistors connected in series. For example, as shown in FIG. 4A, the fourth transistor T4 includes a 4-1 transistor T41 as a first sub-transistor and a 4-2 transistor T42 as a second sub-transistor. The 4-1 transistor T41 and the 4-2 transistor T42 can each be a PMOS transistor. Figure 5

[0104] The 4-1 transistor T41 includes a gate terminal connected to the second scan line SL2, a first terminal connected to a second terminal of the 4-2 transistor T42, and a second terminal connected to the second node N2. The 4-2 transistor T42 includes a gate terminal connected to the second scan line SL2, a first terminal connected to the first initialization voltage line VL1, and a second terminal connected to the first terminal of the 4-1 transistor T41. The 4-1 transistor T41 and the 4-2 transistor T42 can be simultaneously turned on in response to a second scan signal GI transmitted through the second scan line SL2, and transmit the initialization voltage Vint to the gate terminal of the first transistor T1, thereby initializing the gate voltage of the first transistor T1.

[0105] The fifth transistor T5 (first emission control transistor) includes a gate terminal connected to an emission control line EL, a first terminal connected to a driving voltage line PL, and a second terminal connected to the first node N1. The sixth transistor T6 (second emission control transistor) includes a gate terminal connected to the emission control line EL, a first terminal connected to the third node N3, and a second terminal connected to a pixel electrode of the organic light emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to an emission control signal EM transmitted through the emission control line EL, and thus a driving current flows in the organic light emitting diode OLED.

[0106] The seventh transistor T7 (second initialization transistor) includes a gate terminal connected to a third scan line SL3, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to a second initialization voltage line VL2. The seventh transistor T7 can be turned on in response to a third scan signal GB transmitted through the third scan line SL3, and can initialize the voltage of the pixel electrode of the organic light emitting diode OLED by transmitting the initialization voltage Vint to the pixel electrode of the organic light emitting diode OLED. In an exemplary embodiment of the disclosure, the seventh transistor T7 is omitted. For example, when the seventh transistor T7 is omitted, the second initialization voltage line VL2 can be directly connected to the organic light emitting diode OLED.

[0107] The capacitor Cst includes a first electrode connected to the second node N2, and a second electrode connected to the driving voltage line PL. ​

[0108] The organic light emitting diode OLED can include a pixel electrode and a common electrode facing the pixel electrode, and the common electrode can receive a common voltage ELVSS. The organic light emitting diode OLED emits light of a specific color after receiving a driving current from the first transistor T1, and thus an image can be displayed. The common electrode can be shared by the pixel P2 and pixels as the pixel P2. The common voltage ELVSS can be lower than the driving voltage ELVDD. The initialization voltage Vint can be a voltage identical to the common voltage ELVSS or a voltage lower than the common voltage ELVSS.

[0109] Reference Figure 6 During one frame or frame period, the pixel P2 is driven in a first time period t1, a second time period t2, and a third time period t3. The first scan signal GW, the second scan signal GI, and the fourth scan signal GWn can be applied as an on voltage during one horizontal period 1H. The on voltage of the first scan signal GW and the second scan signal GI can be a voltage having a low level, and the on voltage of the fourth scan signal GWn can be a voltage having a high level.

[0110] The first time period t1 is an initialization period in which a second node N2 connected to a gate terminal of the first transistor T1 is initialized and an on bias (e.g., a bias current or voltage) is applied to the gate terminal of the first transistor T1. In the first time period t1, the second scan signal GI having a low level is transmitted to the second scan line SL2, and the fourth transistor T4 is correspondingly turned on. The voltage of the second node N2 (e.g., the voltage of the gate terminal of the first transistor T1) is initialized by the initialization voltage Vint supplied from the first initialization voltage line VL1.

[0111] The second time period t2 is a threshold voltage compensation and data write period. In the second time period t2, the first scan signal GW having a low level is transmitted to the first scan line SL1, and the fourth scan signal GWn having a high level is simultaneously transmitted to the fourth scan line SL4. Accordingly, the second transistor T2, the 3-1 transistor T31, and the 3-2 transistor T32 can be simultaneously turned on.

[0112] The data signal DATA supplied from the data line DL is transmitted to the first node N1 through the second transistor T2. The turned-on 3-1 transistor T31 and 3-2 transistor T32 diode-connect the first transistor T1, and a compensation voltage (e.g., a compensation voltage of the first transistor T1 compensated in the data signal DATA) is applied to the second node N2 (i.e., the gate terminal of the first transistor T1). Accordingly, the driving voltage ELVDD and the compensation voltage are applied to both ends of the capacitor Cst, respectively, and a charge corresponding to a voltage difference between both ends of the capacitor Cst is stored in the capacitor Cst.

[0113] In an exemplary embodiment, the emission control signal EM transmitted to the emission control line EL has a constant high level in the first time period t1 and the second time period t2, and the level of the emission control signal EM transitions from the high level to the low level in the third time period t3. The third time period t3 is an emission period in which the organic light emitting diode OLED emits light. In the third time period t3, the fifth transistor T5 and the sixth transistor T6 are turned on. The driving current corresponding to the charge stored in the capacitor Cst is supplied to the organic light emitting diode OLED through the first transistor T1, and thus the organic light emitting diode OLED emits light.

[0114] In an exemplary embodiment, the third transistor T3A of the pixel P2 has a structure in which the 3-1 transistor T31 as a PMOS and the 3-2 transistor T32 as an NMOS are connected in parallel. When the second time period t2 changes to the third time period t3, the turned-on 3-1 transistor T31 and 3-2 transistor T32 are turned off, respectively. When the 3-1 transistor T31 and 3-2 transistor T32 are turned off, the kickback voltage ΔV gs(T31) generated at the gate terminal of the first transistor T1 due to the parasitic capacitance C KB(GW) of the 3-1 transistor T31 is canceled (eliminated). Accordingly, when the pixel P2 displays black and then displays white (or vice versa), the kickback voltage ΔV gs(T32) at the second node N2 (e.g., the gate terminal of the first transistor T1) is reduced (or becomes zero), and thus a residual image perceived in an image can be reduced. KB(GWn) KB

[0115] Figure 7A is a plan view of a pixel circuit PC2 according to an exemplary embodiment of the present disclosure. Figure 5 is a plan view of a pixel circuit PC2 according to an exemplary embodiment of the present disclosure. Figure 7B is an enlarged plan view of a part of Figure 7A is an enlarged plan view of a part of Figure 8A and Figure 8B are cross-sectional views taken along lines​​Figure 7B a cross-sectional view taken along the lines IIa-IIa' and IIb-IIb' of FIG. 1A. Figure 7A corresponding to Figure 5 a plan view of the pixel P2. Hereinafter, a description will be provided with reference to Figure 7A to Figure 8B provided.

[0116] Figure 5 The first to seventh transistors T1, T2, T3A, T4, T5, T6, T7 of FIG. 1A can each be implemented by a thin film transistor (TFT). Hereinafter, the first to seventh transistors T1, T2, T3A, T4, T5, T6, T7 will be referred to as first to seventh thin film transistors T1, T2, T3A, T4, T5, T6, T7. The third thin film transistor T3A can include two sub-transistors connected in parallel. For example, the third thin film transistor T3A can include a 3-1 thin film transistor T31 as a first sub-thin film transistor and a 3-2 thin film transistor T32 as a second sub-thin film transistor. The fourth thin film transistor T4 can include two sub-transistors connected in series. For example, the fourth thin film transistor T4 can include a 4-1 thin film transistor T41 as a first sub-thin film transistor and a 4-2 thin film transistor T42 as a second sub-thin film transistor.

[0117] Figure 5 The gate terminal, the first terminal, and the second terminal of the transistor of the pixel circuit PC2 of FIG. 1A can correspond to the gate electrode, the source region, and the drain region of each thin film transistor of FIG. 1A, respectively. The source region and the drain region can be the source electrode and the drain electrode of the thin film transistor according to other embodiments. Figure 7A

[0118] The semiconductor layer ACT can be formed on the substrate 100. In an exemplary embodiment, a buffer layer 111 can be disposed on the substrate 100, and the semiconductor layer ACT can be disposed on the buffer layer 111. Some regions of the semiconductor layer ACT can form the semiconductor layers of the first to seventh thin film transistors T1 to T7, respectively.

[0119] The substrate 100 can include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 can include a polymer resin such as polyether sulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0120] The substrate 100 can have a multi-layer structure. For example, as Figure 8A ​As shown in the middle, the substrate 100 can have a structure in which the first base layer 101, the first barrier layer 102, the second base layer 103, and the second barrier layer 104 are sequentially stacked. The first base layer 101 and the second base layer 103 can include the polymer resin described above. The first barrier layer 102 and the second barrier layer 104 can be layers for preventing the penetration of external impurities, and can be one or more layers of an inorganic material such as silicon nitride SiN x or silicon oxide SiO x .

[0121] The buffer layer 111 can increase the uniformity (or consistency) of the upper surface of the substrate 100, and can include an oxide layer such as SiO x , a nitride layer such as SiN x , or SiON.

[0122] The semiconductor layer ACT can include a silicon semiconductor. For example, the semiconductor layer ACT can include low temperature polysilicon (LTPS).

[0123] The semiconductor layers of the first to seventh thin film transistors T1, T2, T3A, T4, T5, T6, T7 can each include source regions S1 to S7, drain regions D1 to D7, and channel regions between the source regions S1 to S7 and the drain regions D1 to D7. Figure 8A and Figure 8B Examples of the channel region C1 of the first thin film transistor T1, the channel region C31 of the 3-1 thin film transistor T31, and the channel region C32 of the 3-2 thin film transistor T32 are shown.

[0124] The channel region can be a region overlapping the gate electrode. The source region and the drain region can be regions doped with impurities around the channel region. According to an embodiment, the positions of the source region and the drain region can vary. In an embodiment, the source region and the drain region of the 3-2 thin film transistor T32 of the third transistor T3A among the first to seventh thin film transistors T1, T2, T3A, T4, T5, T6, T7 can be doped with nitrogen (N) as a group 5 element, and the source regions and the drain regions of the other thin film transistors can be doped with boron (B) as a group 3 element. For example, the material for doping the drain region D1 of the first thin film transistor T1 and the source region S6 of the sixth thin film transistor T6 connected to the drain region D32 of the 3-2 thin film transistor T32 can be different from the material for doping the drain region D32 of the 3-2 thin film transistor T32. Accordingly, the 3-2 thin film transistor T32 can be implemented by an NMOS transistor, and the other thin film transistors can each be implemented by a PMOS transistor.

[0125] The first gate insulating layer 112 can be provided on the semiconductor layer ACT, and the gate electrode G1 of the first thin film transistor T1, the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, and the emission control line EL can be provided on the first gate insulating layer 112. The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, and the emission control line EL can extend in a first direction (for example, an x direction) and can be spaced apart from each other.

[0126] The first gate insulating layer 112 can include SiO2, SiN x , SiON, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0127] The gate electrode G1 of the first thin film transistor T1 can overlap the semiconductor layer ACT and have an isolated pattern.

[0128] The region of the first scan line SL1 that overlaps the channel region of the second thin film transistor T2 can be the gate electrode G2 of the second thin film transistor T2, and the region of the first scan line SL1 that overlaps the channel region of the 3-1 thin film transistor T31 can be the gate electrode G31 of the 3-1 thin film transistor T31. The region of the fourth scan line SL4 that overlaps the channel region of the 3-2 thin film transistor T32 can be the gate electrode G32 of the 3-2 thin film transistor T32. The region of the second scan line SL2 that overlaps the channel region of the fourth thin film transistor T4 can be the gate electrodes G41 and G42 of the fourth thin film transistor T4. The region of the third scan line SL3 that overlaps the channel region of the seventh thin film transistor T7 can be the gate electrode G7 of the seventh thin film transistor T7. The regions of the emission control line EL that overlap the channel regions of the fifth thin film transistor T5 and the sixth thin film transistor T6 can be the gate electrode G5 of the fifth thin film transistor T5 and the gate electrode G6 of the sixth thin film transistor T6, respectively.

[0129] The gate electrode G1 of the first thin film transistor T1, the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, and the emission control line EL can each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), and can each be one layer or multiple layers including at least one material.

[0130] The second gate insulating layer 113 can be provided on the gate electrode G1 of the first thin film transistor T1, the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, and the emission control line EL. The second gate insulating layer 113 can include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0131] The first initialization voltage line VL1, the second initialization voltage line VL2, and the electrode voltage line HL can be provided on the second gate insulating layer 113. The electrode voltage line HL, and the first initialization voltage line VL1 and the second initialization voltage line VL2 can extend in a first direction (e.g., an x direction), and can be provided apart from each other.

[0132] In an exemplary embodiment, the electrode voltage line HL covers at least a portion of the gate electrode G1 of the first thin film transistor T1. The electrode voltage line HL can function as an upper electrode Cst2 of the capacitor Cst. In an exemplary embodiment, the electrode voltage line HL completely covers the gate electrode G1.

[0133] A lower electrode Cst1 of the capacitor Cst can be integrally formed with the gate electrode G1 of the first thin film transistor T1. For example, the gate electrode G1 of the first thin film transistor T1 can function as the lower electrode Cst1 of the capacitor Cst. First and second openings SOP1 and SOP2 can be formed in an upper electrode Cst2 of the capacitor Cst.

[0134] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 can each include at least one selected from the group consisting of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu, and can be one or more layers.

[0135] An interlayer insulating layer 114 is provided on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The interlayer insulating layer 114 can include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2.

[0136] The data line DL, the drive voltage line PL, first and second node electrodes 1174a and 1174b, and connection electrodes 1173a, 1173b, and 1175 can be provided on the interlayer insulating layer 114. The data line DL and the drive voltage line PL can extend in a second direction (e.g., a y direction), and can be provided apart from each other.

[0137] The data line DL, the drive voltage line PL, the first node electrode 1174a and the second node electrode 1174b, and the connection electrodes 1173a, 1173b, and 1175 can include a conductive material such as Mo, Al, Cu, and Ti, and can each be one or more layers. In an embodiment, the data line DL, the drive voltage line PL, the first node electrode 1174a and the second node electrode 1174b, and the connection electrodes 1173a, 1173b, and 1175 each have a multilayer structure of Ti / Al / Ti.

[0138] The data line DL can be electrically connected to the source region S2 of the second thin-film transistor T2 through a contact hole 1154 formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. In an exemplary embodiment, a portion of the data line DL is a source electrode that contacts the source region S2.

[0139] The drive voltage line PL can be electrically connected to the upper electrode Cst2 of the capacitor Cst through a contact hole 1158 formed in the interlayer insulating layer 114. Thus, the electrode voltage line HL can have the same voltage level (constant voltage) as the drive voltage line PL. Further, the drive voltage line PL can be electrically connected to the source region S5 of the fifth thin-film transistor T5 through a contact hole 1155 formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114.

[0140] As shown in Figure 7A and Figure 8A The first node electrode 1174a can electrically connect the gate electrode G1 of the first thin-film transistor T1 to the source region S31 of the 3-1 thin-film transistor T31 and the drain region D41 of the 4-1 thin-film transistor T41 through a first opening SOP1 formed in the upper electrode Cst2 of the capacitor Cst. One end of the first node electrode 1174a can be electrically connected to the gate electrode G1 of the first thin-film transistor T1 through a contact hole 1157a formed in the second gate insulating layer 113 and the interlayer insulating layer 114. The other end of the first node electrode 1174a can be electrically connected to the source region S31 of the 3-1 thin-film transistor T31 through a contact hole 1156a formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114.

[0141] As shown in Figure 7A and Figure 8BAs shown in FIG. 11, the second node electrode 1174b can electrically connect the gate electrode G1 of the first thin-film transistor T1 to the source region S32 of the 3-2 thin-film transistor T32 through the second opening SOP2 formed in the upper electrode Cst2 of the capacitor Cst. One end of the second node electrode 1174b can be electrically connected to the gate electrode G1 of the first thin-film transistor T1 through the contact hole 1157b formed in the second gate insulating layer 113 and the interlayer insulating layer 114. The other end of the second node electrode 1174b can be electrically connected to the source region S32 of the 3-2 thin-film transistor T32 through the contact hole 1156b formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114.

[0142] The connection electrode 1173a can electrically connect the first initialization voltage line VL1 and the source region S42 of the 4-2 thin-film transistor T42 through the contact hole 1151a formed in the interlayer insulating layer 114 and the contact hole 1152a formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114, respectively. The connection electrode 1173b can electrically connect the second initialization voltage line VL2 and the drain region D7 of the seventh thin-film transistor T7 through the contact hole 1151b formed in the interlayer insulating layer 114 and the contact hole 1152b formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114, respectively.

[0143] The connection electrode 1175 can be electrically connected to the drain electrode D6 of the sixth thin-film transistor T6 through the contact hole 1153 formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. The sixth thin-film transistor T6 can be electrically connected to the pixel electrode 210 of the organic light-emitting diode OLED through the connection electrode 1175.

[0144] The planarization layer 115 can be disposed on the data line DL, the driving voltage line PL, the first node electrode 1174a and the second node electrode 1174b, and the connection electrodes 1173a, 1173b, and 1175, and the organic light-emitting diode OLED can be disposed on the planarization layer 115.

[0145] Figure 7A A structure of one pixel circuit PC2 is illustrated. In an embodiment, the pixels P2 having the same pixel circuit PC2 are arranged in a first direction (e.g., an x direction) and a second direction (e.g., a y direction). In this embodiment, the first initialization voltage line VL1, the second scan line SL2, the second initialization voltage line VL2, and the third scan line SL3 are shared by two pixel circuits PC2 adjacent to each other in the second direction (e.g., the y direction).

[0146] That is, the first initialization voltage line VL1 and the second scan line SL2 can be electrically connected to the second direction (e.g., the y-direction) shown in the attached figure. Figure 7A The seventh thin-film transistor of the different pixel circuit PC2 is located adjacent to the upper side of the pixel circuit PC2. Therefore, the second scan signal GI transmitted to the second scan line SL2 can be transmitted as a third scan signal to the seventh thin-film transistor of the different pixel circuit PC2. As described, the second initialization voltage line VL2 and the third scan line SL3 can be electrically connected to the seventh thin-film transistor of the different pixel circuit PC2 in the second direction (e.g., the y-direction) shown in the figure. Figure 7A The fourth thin-film transistor of the different pixel circuit PC2 is located adjacent to the lower side of the pixel circuit PC2. Therefore, the third scan signal GB transmitted to the third scan line SL3 can be transmitted as a second scan signal to the fourth thin-film transistor of the different pixel circuit PC2.

[0147] The planarization layer 115 may have a flat upper surface to ensure that the pixel electrode 210 is flat. The planarization layer 115 may be a single layer or multiple layers comprising organic materials. The planarization layer 115 may include general polymers such as benzocyclobutene (BCB), PI, hexamethyldisilane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof.

[0148] In an exemplary embodiment, the planarization layer 115 comprises an inorganic material. The planarization layer 115 may include SiO2, SiN, etc. x The materials used are SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2. When the planarization layer 115 comprises an inorganic material, chemical planarization polishing can be performed. In an exemplary embodiment, the planarization layer 115 comprises both organic and inorganic materials.

[0149] like Figure 8A and Figure 8B As shown, the organic light-emitting diode (OLED) includes a pixel electrode 210, a common electrode 230, and an intermediate layer 220 including an emission layer disposed between the pixel electrode 210 and the common electrode 230.

[0150] The pixel electrode 210 can be electrically connected to the connection electrode 1175 through the contact hole 1163 formed in the planarization layer 115, and the connection electrode 1175 can be electrically connected to the sixth thin film transistor T6 through the contact hole 1153 formed in the first gate insulating layer 112, the second gate insulating layer 113 and the interlayer insulating layer 114.

[0151] The pixel electrode 210 can be a transparent (semi-transparent) electrode or a reflective electrode. In some embodiments, the pixel electrode 210 can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 can have a stack structure of ITO / Ag / ITO.

[0152] The pixel defining layer 116 can be disposed on the planarization layer 115 and can define an emission area of the pixel P2 by exposing a portion of the pixel electrode 210. The pixel defining layer 116 can cover edges of the pixel electrode 210. In an exemplary embodiment, an upper surface between opposite sides of the pixel electrode 210 is not covered by the pixel defining layer 116. The pixel defining layer 116 can include an organic insulating material such as polyimide (PI), polyamide, an acrylic resin, benzocyclobutene (BCB) resin, hexamethyldisilane (HMDSO), or a phenol resin.

[0153] The intermediate layer 220 can include an emission layer. The emission layer can include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer can include a low molecular weight or a high molecular weight organic material. As shown in FIGS. 1 and 2, the organic light emitting diode OLED can further include a first functional layer and / or a second functional layer on and under the emission layer. The first functional layer and / or the second functional layer can include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL). The intermediate layer 220 can be disposed to correspond to the pixel electrode 210, respectively. However, embodiments of the present disclosure are not limited thereto, and at least some of the layers included in the intermediate layer 220 can be integrally formed over the pixel electrode 210. Figure 8A and Figure 8B As shown in FIGS. 1 and 2, for convenience, only the emission layer of the intermediate layer 220 is shown. The organic light emitting diode OLED can further include a first functional layer and / or a second functional layer on and under the emission layer. The first functional layer and / or the second functional layer can include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL). The intermediate layer 220 can be disposed to correspond to the pixel electrode 210, respectively. However, embodiments of the present disclosure are not limited thereto, and at least some of the layers included in the intermediate layer 220 can be integrally formed over the pixel electrode 210.

[0154] The common electrode 230 can be a transparent electrode or a reflective electrode. In some embodiments, the common electrode 230 can be a transparent or semi-transparent electrode, and can include a metal thin film including Li, Ca, LiF, Al, Ag, Mg, or a compound thereof and having a low work function. Further, a transparent conductive oxide (TCO) layer including ITO, IZO, ZnO, or In2O3 can be further formed on the metal thin film. The common electrode 230 can be integrally formed to correspond to the pixel electrode 210.

[0155] Although not shown, a thin film encapsulation layer (not shown) or a sealing substrate (not shown) can be disposed on the common electrode 230. The thin film encapsulation layer can cover the display area DA and extend to the outside of the display area DA. Such a thin film encapsulation layer can include at least one inorganic encapsulation layer including an inorganic material and at least one organic encapsulation layer including an organic material. In some embodiments, the thin film encapsulation layer can have a structure in which a first inorganic encapsulation layer / organic encapsulation layer / second inorganic encapsulation layer are stacked. The sealing substrate (not shown) can face the substrate 100, and in the peripheral area PA, the sealing substrate can be coupled to the substrate 100 by a sealing member such as a sealant or a frit. In addition, a spacer for preventing indentation in a mask can be disposed on the pixel definition layer 116.

[0156] Figure 9 is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. Structures identical to those of the pixel circuit PC2 of Figure 5 will not be described in detail, and differences between them will be mainly described.

[0157] Referring to Figure 9 , the pixel P3 includes an organic light emitting diode OLED as a display element and a pixel circuit PC3 connected to the organic light emitting diode OLED. The pixel circuit PC3 includes first to seventh transistors T1, T2, T3B, T4, T5, T6, T7. In an embodiment, the first to seventh transistors T1, T2, T3B, T4, T5, T6, T7 are each implemented by a PMOS transistor. Figure 9 The pixel P3 of Figure 6 may be driven in a driving timing of

[0158] The pixel circuit PC3 can be connected to a first scan line SL1 that transmits a first scan signal GW, a second scan line SL2 that transmits a second scan signal GI, a third scan line SL3 that transmits a third scan signal GB, a fourth scan line SL4 that transmits a fourth scan signal GWn, an emission control line EL that transmits an emission control signal EM, and a data line DL that transmits a data signal DATA. The pixel circuit PC3 can also be connected to a driving voltage line PL and first and second initialization voltage lines VL1 and VL2.

[0159] The third transistor T3B (a compensation transistor) can include two sub-transistors connected in series. For example, the third transistor T3B can include a 3-1 transistor T31' as a first sub-transistor and a 3-2 transistor T32' as a second sub-transistor.

[0160] 3-1 transistor T31' includes a first gate terminal G31a connected to the first scan line SL1, a second gate terminal G31b connected to the fourth scan line SL4, a first terminal connected to the second node N2, and a second terminal connected to a first terminal of the 3-2 transistor T32'. The 3-2 transistor T32' includes a gate terminal G32 connected to the first scan line SL1, a first terminal connected to the second terminal of the 3-1 transistor T31', and a second terminal connected to the third node N3.

[0161] The first gate terminal G31a of the 3-1 transistor T31' can receive the first scan signal GW through the first scan line SL1, and the second gate terminal G31b can receive the fourth scan signal GWn through the fourth scan line SL4. In an exemplary embodiment, the fourth scan signal GWn is an inverted voltage of the first scan signal GW. The fourth scan signal GWn can be applied with the same timing as the first scan signal GW. The gate terminal G32 of the 3-2 transistor T32' can receive the first scan signal GW through the first scan line SL1. The 3-1 transistor T31' and the 3-2 transistor T32' can be turned on at the same time, and can diode-connect the first transistor T1.

[0162] In an embodiment, the 3-1 thin film transistor T31' adjacent to the gate terminal of the first transistor T1 among the 3-1 thin film transistor T31' and the 3-2 transistor T32' of the third transistor T3B of the pixel P3 can include a pair of gate terminals. Signals that are inverted from each other can be transmitted to the gate terminals of the 3-1 thin film transistor T31', respectively. The third transistor T3B can be driven similarly to the third transistor T3A of the pixel P2 of Figure 5 and Figure 6 When the second time period t2 changes to the third time period t3, the kickback voltage generated at the gate terminal of the first transistor T1 due to the parasitic capacitance C g1s(T31') between the first gate terminal G31a and the source region of the 3-1 transistor T31' can be offset (canceled) by the kickback voltage generated at the gate terminal of the first transistor T1 due to the parasitic capacitance C g2s(T31') between the second gate terminal G31b and the source region of the 3-1 transistor T31'. Accordingly, when the pixel P3 displays black and then displays white (or vice versa), the afterimage perceived in the image can be reduced due to the reduction (or becoming zero) of the kickback voltage at the gate terminal of the first transistor T1.

[0163] Figure 10 is a plan view of a pixel circuit PC3 of Figure 9 according to an exemplary embodiment of the present disclosure. Figure 10A is an enlarged plan view of a portion of Figure 10 according to an exemplary embodiment of the present disclosure.Figure 11 It is along Figure 10A The cross-sectional view taken from line III-III'. Figure 10 It can correspond to Figure 9 A plan view of the pixel circuit PC3. Referencing below... Figure 10 , Figure 10A and Figure 11 Provide a description, but focus primarily on the description with Figure 7A floor plan and Figure 8B The cross-sectional diagrams show different structures.

[0164] Figure 9 The first to seventh transistors T1, T2, T3B, T4, T5, T6, and T7 can each be implemented as thin-film transistors. In the following text, the first to seventh transistors T1, T2, T3B, T4, T5, T6, and T7 will be referred to as the first to seventh thin-film transistors T1, T2, T3B, T4, T5, T6, and T7. The third thin-film transistor T3B may include two sub-transistors connected in series. For example, the third thin-film transistor T3B may include a 3-1 transistor T31' as the first sub-transistor and a 3-2 transistor T32' as the second sub-transistor. The fourth thin-film transistor T4 may include two sub-thin-film transistors connected in series. For example, the fourth thin-film transistor T4 may include a 4-1 transistor T41 as the first sub-transistor and a 4-2 transistor T42 as the second sub-transistor.

[0165] A buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may have a structure in which a first buffer layer 111a and a second buffer layer 111b are stacked. For example, the second buffer layer 111b may be disposed on top of the first buffer layer 111a. In an exemplary embodiment, the first buffer layer 111a and the second buffer layer 111b comprise different materials. For example, the first buffer layer 111a may comprise materials such as SiN. x Silicon nitride. The second buffer layer 111b may include materials such as SiO2. x Silica.

[0166] When the first buffer layer 111a comprises silicon nitride, hydrogen can be included during the formation of the silicon nitride, and thus, the carrier mobility of the semiconductor layer ACT formed on the buffer layer 111a can be improved. The electrical characteristics of the thin-film transistor can be improved accordingly. Furthermore, the semiconductor layer ACT can comprise silicon material. This can improve the interfacial adhesion between the silicon-complementing semiconductor layer ACT and the second buffer layer 111b comprising silicon oxide, and further improve the electrical characteristics of the thin-film transistor.

[0167] The fourth scan line SL4 can be provided between the substrate 100 and the semiconductor layer ACT, for example, between the first buffer layer 111a and the second buffer layer 111b. In an exemplary embodiment, the fourth scan line SL4 is provided between the substrate 100 and the first buffer layer 111a.

[0168] The fourth scan line SL4 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and / or Cu.

[0169] The semiconductor layer ACT can be formed on the buffer layer 111. Some regions of the semiconductor layer ACT can form semiconductor layers of the first thin film transistor T1 to the seventh thin film transistor T7, respectively. The semiconductor layer ACT can include a silicon semiconductor. For example, the semiconductor layer ACT can include LTPS.

[0170] The semiconductor layers of the first thin film transistor T1 to the seventh thin film transistor T7 can include source regions S1 to S7, drain regions D1 to D7, and channel regions between the source regions S1 to S7 and the drain regions D1 to D7, respectively. Figure 11 The channel region C31 of the 3-1 thin film transistor T31' and the channel region C32 of the 3-2 thin film transistor T32' are shown. The first thin film transistor T1 to the seventh thin film transistor T7 can each be implemented by a PMOS transistor.

[0171] The first gate insulating layer 112 can be provided on the semiconductor layer ACT, and the gate electrode G1 of the first thin film transistor T1, the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emission control line EL can be provided on the first gate insulating layer 112.

[0172] As Figure 11As illustrated in FIG. 3-1, the 3-1 thin film transistor T31' can include a first gate electrode G31a as a top gate electrode, a second gate electrode G31b as a bottom gate electrode, and a semiconductor layer including a source region S31, a channel region C31, and a drain region D31. The second gate electrode G31b of the 3-1 thin film transistor T31' can be disposed between the substrate 100 and the semiconductor layer, for example, between the first buffer layer 111a and the second buffer layer 111b. In an exemplary embodiment, the second gate electrode G31b of the 3-1 thin film transistor T31' is disposed between the substrate 100 and the first buffer layer 111a. In an exemplary embodiment, the second gate electrode G31b of the 3-1 thin film transistor T31' is part of the fourth scan line SL4. In an exemplary embodiment, the second gate electrode G31b overlaps the channel region C31 of the 3-1 thin film transistor T31'. The second gate electrode G31b can partially overlap the channel region C31. The region that protrudes from the first scan line SL1 and overlaps the channel region C31 of the 3-1 thin film transistor T31' can be the first gate electrode G31a of the 3-1 thin film transistor T31'.

[0173] The 3-2 thin film transistor T32' includes a gate electrode G32 and a semiconductor layer including a source region S32, a channel region C32, and a drain region D32. In an exemplary embodiment, the region of the first scan line SL1 that overlaps the channel region C32 of the 3-2 thin film transistor T32' is the gate electrode G32 of the 3-2 thin film transistor T32'.

[0174] The second gate insulating layer 113 can be disposed on the gate electrode G1 of the first thin film transistor T1, the first scan line SL1, the second scan line SL2, the third scan line SL3, and the emission control line EL.

[0175] Hereinafter, although not illustrated in FIG. 3-1, a description will be provided with reference to FIGS. 3-2 and 3-3. Figure 11 Figure 8A and Figure 8B

[0176] The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 can be disposed on the second gate insulating layer 113.

[0177] In an exemplary embodiment, the electrode voltage line HL covers at least a portion of the gate electrode G1 of the first thin film transistor T1. In an exemplary embodiment, the electrode voltage line HL completely covers the gate electrode G1. The electrode voltage line HL can function as an upper electrode Cst2 of the capacitor Cst. A lower electrode Cst1 of the capacitor Cst can be integrally formed with the gate electrode G1. The gate electrode G1 of the first thin film transistor T1 can function as the lower electrode Cst1 of the capacitor Cst. An opening SOP can be formed in the upper electrode Cst2 of the capacitor Cst.

[0178] ​​The interlayer insulating layer 114 can be disposed on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The data line DL, the driving voltage line PL, the node electrode 1174, and the connection electrodes 1173a, 1173b, and 1175 can be disposed on the interlayer insulating layer 114.

[0179] The node electrode 1174 can electrically connect the gate electrode G1 of the first thin-film transistor T1 to the source region S31 of the 3-1 thin-film transistor T31' and the drain region D41 of the 4-1 thin-film transistor T41 through an opening SOP formed in the upper electrode Cst2 of the capacitor Cst. One end of the node electrode 1174 can be electrically connected to the gate electrode G1 of the first thin-film transistor T1 through a contact hole 1157 formed in the second gate insulating layer 113 and the interlayer insulating layer 114. The other end of the node electrode 1174 can be electrically connected to the source region S31 of the 3-1 thin-film transistor T31' through a contact hole 1156 formed in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114.

[0180] The planarization layer 115 can be disposed on the data line DL, the driving voltage line PL, the node electrode 1174, and the connection electrodes 1173a, 1173b, and 1175, and the organic light emitting diode OLED can be disposed on the planarization layer 115.

[0181] Reference Figure 10 The first initialization voltage line VL1, the second scan line SL2, the second initialization voltage line VL2, and the third scan line SL3 can be shared by two pixel circuits PC3 adjacent to each other in the second direction (for example, the y direction).

[0182] That is, the first initialization voltage line VL1 and the second scan line SL2 can be electrically connected to the seventh thin-film transistor of a different pixel circuit PC3 adjacent to the upper side of the pixel circuit PC3 of Equation 1 in the second direction (for example, the y direction) shown in the drawings. Accordingly, the second scan signal GI transmitted to the second scan line SL2 can be transmitted to the seventh thin-film transistor of the different pixel circuit PC3 as a third scan signal. Likewise, the second initialization voltage line VL2 and the third scan line SL3 can be electrically connected to the fourth thin-film transistor of a different pixel circuit PC3 adjacent to the lower side of the pixel circuit PC3 of Equation 1 in the second direction (for example, the y direction) shown in the drawings. Accordingly, the third scan signal GB transmitted to the third scan line SL3 can be transmitted to the fourth thin-film transistor of the different pixel circuit PC3 as a second scan signal. Figure 10 Figure 10

[0183] Figure 12 ​​is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. In the following, the same structures as the structure of the pixel circuit PC2 of Figure 5 will not be described in detail, and the differences between them will mainly be described.

[0184] Referring to Figure 12 , the pixel P4 includes an organic light emitting diode OLED as a display element and a pixel circuit PC4 connected to the organic light emitting diode OLED. The pixel circuit PC4 includes first to seventh transistors T1, T2, T3C, T4', T5, T6, T7, a first capacitor Cst, and a second capacitor Cbt. In an embodiment, the third transistor T3C and the fourth transistor T4' of the first to seventh transistors T1, T2, T3C, T4', T5, T6, T7 are each implemented by an NMOS transistor, and the other transistors of the first to seventh transistors T1, T2, T3C, T4', T5, T6, T7 are implemented by PMOS transistors. Figure 12 The pixel P4 of Figure 6 may be driven with the driving timing of

[0185] The pixel circuit PC4 can be connected to a first scan line SL1 that transmits a first scan signal GW, a second scan line SL2' that transmits a second scan signal GIn, a third scan line SL3 that transmits a third scan signal GB, a fourth scan line SL4 that transmits a fourth scan signal GWn, an emission control line EL that transmits an emission control signal EM, and a data line DL that transmits a data signal DATA. The pixel circuit PC4 can also be connected to a driving voltage line PL and first and second initialization voltage lines VL1 and VL2.

[0186] The third transistor T3C (compensation transistor) can include two sub-transistors connected in parallel. For example, the third transistor T3C can include a 3-1 transistor T31" as a first sub-transistor and a 3-2 transistor T32" as a second sub-transistor. The 3-1 transistor T31" can be a PMOS transistor, and the 3-2 transistor T32" can be an NMOS transistor.

[0187] 3-1 transistor T31" includes a gate terminal connected to a first scan line SL1, a first terminal connected to a second node N2, and a second terminal connected to a third node N3. 3-2 transistor T32" includes a gate terminal connected to a fourth scan line SL4, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. 3-1 transistor T31" can be turned on in response to a first scan signal GW transmitted through the first scan line SL1, and 3-2 transistor T32" can be turned on in response to a fourth scan signal GWn transmitted through the fourth scan line SL4. In an exemplary embodiment, the fourth scan signal GWn is an inverted signal of the first scan signal GW. 3-1 transistor T31" and 3-2 transistor T32" can be turned on at the same time to diode-connect the first transistor T1.

[0188] The fourth transistor T4' (first initialization transistor) includes a gate terminal connected to a second scan line SL2', a first terminal connected to a first initialization voltage line VL1, and a second terminal connected to the second node N2. The fourth transistor T4' can be turned on in response to a second scan signal GIn transmitted through the second scan line SL2', and can transmit the first initialization voltage Vint1 to the gate terminal of the first transistor T1, thereby initializing the gate voltage of the first transistor T1. In an exemplary embodiment, the second scan signal GIn is an inverted signal of the first scan signal GW.

[0189] The seventh transistor T7 (second initialization transistor) includes a gate terminal connected to a third scan line SL3, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to a second initialization voltage line VL2. The seventh transistor T7 can be turned on in response to a third scan signal GB transmitted through the third scan line SL3, and transmit the second initialization voltage Vint2 to the pixel electrode of the organic light emitting diode OLED, thereby initializing the voltage of the pixel electrode of the organic light emitting diode OLED. In an exemplary embodiment of the present disclosure, the seventh transistor T7 is omitted.

[0190] The first capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to a driving voltage line PL. The first capacitor Cst can store and hold a voltage corresponding to a difference between the driving voltage line PL and the both ends of the gate terminal of the first transistor T1, and thus can hold a voltage applied to the gate terminal of the first transistor T1.

[0191] The second capacitor Cbt includes a third electrode connected to the gate terminal of the first scan line SL1 and the second transistor T2, and a fourth electrode connected to the first electrode of the first capacitor Cst and the gate terminal of the first transistor T1. When the first scan signal GW of the first scan line SL1 has a voltage for turning off the second transistor T2, the second capacitor Cbt can be a boost capacitor, and can reduce a voltage (black voltage) for displaying black by increasing the voltage of the second node N2.

[0192] In an example embodiment of the present disclosure, at least one of the first to seventh transistors T1, T2, T3C, T4', T5, T6, T7 includes a semiconductor layer including an oxide, and the other transistors of the first to seventh transistors T1, T2, T3C, T4', T5, T6, T7 include a semiconductor layer including silicon. For example, the first transistor T1 directly affecting the brightness of the display device can include a semiconductor layer having high reliability and including polysilicon, and thus, a high-resolution display device can be implemented.

[0193] Since the oxide semiconductor has high carrier mobility and low leakage current, the voltage can not be significantly decreased even with long driving time. That is, since the color of the image can not greatly change according to the voltage drop even when operating at a low frequency, the display device can operate at a low frequency. In an example embodiment of the present disclosure, because the oxide semiconductor has small leakage current, at least one of the 3-1 transistor T31" connected to the gate terminal of the first transistor T1 and the fourth transistor T4' uses the oxide semiconductor to prevent the leakage current from flowing to the gate terminal of the first transistor T1. The use of the oxide semiconductor can also reduce power consumption.

[0194] In an example embodiment of the present disclosure, the 3-1 transistor T31" including a semiconductor layer including silicon and embodied as a PMOS transistor can be connected in parallel to the 3-2 transistor T32" including a semiconductor layer including an oxide and embodied as an NMOS transistor. The third transistor T3C can be connected in parallel to the fourth transistor T4' in the pixel P2 of Figure 5 and Figure 6 be driven similarly to the third transistor T3A of the pixel P2. That is, since the kickback voltage generated at the gate terminal of the first transistor T1 due to the parasitic capacitance C gs(T32") of the 3-2 transistor T32" is canceled (eliminated) by the kickback voltage generated at the gate terminal of the first transistor T1 due to the parasitic capacitance C gs(T31") of the 3-1 transistor T31". Thus, when the pixel P4 displays black and then displays white (or vice versa), the afterimage perceived in the image can be reduced due to the decrease (or becoming zero) of the kickback voltage at the gate terminal of the first transistor T1.

[0195] Figure 13 is a plan view of a pair of pixel circuits arranged in the same row adjacent to each other according to an example embodiment of the present disclosure. Figure 13A is an enlarged plan view of a part of Figure 13 according to an example embodiment of the present disclosure. Figure 14A and Figure 14B are cross-sectional views taken along lines IVa-IVa' and IVb-IVb' of Figure 13A Figure 13 may correspond to Figure 12 a plan view of the pixel circuit PC4 of Figure 13 to Figure 14B will be provided below, but structures different from those in the plan view of Figure 7A and the cross-sectional view of Figure 8B will mainly be described.

[0196] Figure 13 The pixel circuit of the pixel arranged in the left pixel area PA1 can be symmetrical to the pixel circuit of the pixel arranged horizontally in the right pixel area PA2.

[0197] In an embodiment, the first transistor T1, the second transistor T2, the 3-1 transistor T31", the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are each a thin film transistor including a silicon semiconductor. The 3-2 transistor T32" and the fourth transistor T4' can each be a thin film transistor including an oxide semiconductor. Hereinafter, they will be described as first to seventh thin film transistors T1, T2, T3C, T4', T5, T6, T7. The third thin film transistor T3C can include two sub-transistors (e.g., thin film transistors) connected in parallel. For example, the third thin film transistor T3C can include the 3-1 transistor T31" as a first sub-transistor and the 3-2 transistor T32" as a second sub-transistor.

[0198] A buffer layer 111 can be provided over a substrate 100. A first semiconductor layer AS (see Figure 13A ) can be provided over the buffer layer 111. Some regions of the first semiconductor layer AS can respectively form semiconductor layers of the first thin film transistor T1, the second thin film transistor T2, the 3-1 thin film transistor T31", the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7. The first semiconductor layer AS can include a silicon semiconductor. For example, the first semiconductor layer AS can include LTPS. The semiconductor layers of the first thin film transistor T1, the second thin film transistor T2, the 3-1 thin film transistor T31", the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 can be connected to each other and can be curved into various shapes.

[0199] ​The semiconductor layers of the first thin-film transistor T1, the second thin-film transistor T2, the 3-1 thin-film transistor T31", the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 can each include a source region S1, S2, S31", S5, S6, S7, a drain region D1, D2, D31", D5, D6, D7, and a channel region therebetween. The source and drain regions can be doped with impurities and can include P-type impurities. Figure 14A The channel region C1 of the first thin-film transistor T1 and the channel region C31" of the 3-1 thin-film transistor T31" are shown.

[0200] The first gate insulating layer 112 can be disposed on the first semiconductor layer AS.

[0201] The first scan line SL1, the third scan line SL3, and the emission control line EL can each extend in a first direction (e.g., the x-direction) on the first gate insulating layer 112. On the first gate insulating layer 112, the gate electrode G1 of the first thin-film transistor T1 can be disposed and can have an isolated pattern. The first scan line SL1 can include a pair of branch 1-1 scan line SL1a and 1-2 scan line SL1b, while the first thin-film transistor T1 is between the 1-1 scan line SL1a and the 1-2 scan line SL1b.

[0202] An area of the 1-1 scan line SL1a that overlaps with the channel region of the second thin-film transistor T2 (where the 1-1 scan line SL1a is disposed on the upper side of the first thin-film transistor T1) can be the gate electrode G2 of the second thin-film transistor T2. An area of the 1-2 scan line SL1b that overlaps with the channel region of the 3-1 thin-film transistor T31" (where the 1-2 scan line SL1b is disposed on the lower side of the first thin-film transistor T1) can be the gate electrode G31" of the 3-1 thin-film transistor T31". In an exemplary embodiment, an area of the third scan line SL3 that overlaps with the channel region of the seventh thin-film transistor T7 is the gate electrode G7 of the seventh thin-film transistor T7. Areas of the emission control line EL that overlap with the channel regions of the fifth thin-film transistor T5 and the sixth thin-film transistor T6 can be the gate electrode G5 of the fifth thin-film transistor T5 and the gate electrode G6 of the sixth thin-film transistor T6, respectively. In an exemplary embodiment, a portion of the 1-1 scan line SL1a is the third electrode CE3 of the second capacitor Cbt.

[0203] The first scan line SL1, the third scan line SL3, and the emission control line EL can each include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, or Cu, and can be a single layer or multiple layers including one or more materials.

[0204] The second gate insulating layer 113a can be provided over the first scan line SL1, the third scan line SL3, and the emission control line EL.

[0205] The electrode voltage line HL, the first initialization voltage line VL1, the lower scan line 143 of the second scan line SL2', and the lower scan line 145 of the fourth scan line SL4 can be provided over the second gate insulating layer 113a.

[0206] The electrode voltage line HL can cover at least part of the gate electrode G1 of the first thin film transistor T1. In an example embodiment, the electrode voltage line HL covers the entire gate electrode G1. The electrode voltage line HL can function as the second electrode CE2 of the first capacitor Cst.

[0207] In an example embodiment, the first capacitor Cst overlaps with the first thin film transistor T1. The first capacitor Cst includes the first electrode CE1 and the second electrode CE2. The gate electrode G1 of the first thin film transistor T1 can function as the control electrode and the first electrode CE1 of the first capacitor Cst. The second electrode CE2 of the first capacitor Cst can overlap with the first electrode CE1 of the first capacitor Cst, with the second gate insulating layer 113a between the second electrode CE2 and the first electrode CE1.

[0208] The second electrode CE2 of the first capacitor Cst can include a first opening SOP1 and a second opening SOP2. The first opening SOP1 and the second opening SOP2 formed by the removed portions of the second electrode CE2 can have a closed shape.

[0209] The electrode voltage line HL, the first initialization voltage line VL1, the lower scan line 143 of the second scan line SL2', and the lower scan line 145 of the fourth scan line SL4 can each include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, or Cu, and can be a single layer or a plurality of layers including one or more of the above materials.

[0210] The first interlayer insulating layer 114a can be provided over the second gate insulating layer 113a.

[0211] The second semiconductor layer AO (see FIG. 1) including an oxide semiconductor can be provided over the first interlayer insulating layer 114a. Figure 13A) can be provided. Some regions of the second semiconductor layer AO can form a semiconductor layer of the 3-2 thin film transistor T32" and the fourth thin film transistor T4', respectively. The second semiconductor layer AO can include a Zn-oxide-based material, such as Zn-oxide, In-Zn-oxide, or Ga-In-Zn-oxide. In some embodiments, the second semiconductor layer AO can include an In-Ga-Zn-O (IGZO) semiconductor, an In-Sn-Zn-O (ITZO) semiconductor, or an In-Ga-Sn-Zn-O (IGTZO) semiconductor in which a metal such as indium (In), gallium (Ga), or tin (Sn) is included in ZnO.

[0212] The semiconductor layers of the 3-2 thin film transistor T32" and the fourth thin film transistor T4' can include a channel region, a source region S32" and S4' and a drain region D32" and D4' on both ends of the respective channel regions. Figure 14B The channel region C32" of the 3-2 thin film transistor T32" is illustrated. The source regions S32" and S4' and the drain regions D32" and D4' of the 3-2 thin film transistor T32" and the fourth thin film transistor T4' can be formed by adjusting the carrier concentration of the oxide semiconductor and making them conductive. For example, the source regions S32" and S4' and the drain regions D32" and D4' of the 3-2 thin film transistor T32" and the fourth thin film transistor T4' can be formed by increasing the carrier concentration using a plasma treatment of a hydrogen-based gas, a fluorine-based gas, or a combination thereof.

[0213] A portion of the second semiconductor layer AO can be a fourth electrode CE4 of the second capacitor Cbt. The fourth electrode CE4 can extend from the semiconductor layer of the 3-2 thin film transistor T32" or the semiconductor layer of the fourth thin film transistor T4'. That is, the fourth electrode CE4 can include an oxide semiconductor, and can be provided over the first interlayer insulating layer 114a. In an exemplary embodiment, the fourth electrode CE4 of the second capacitor Cbt overlaps with the third electrode CE3. In a plan view, the second capacitor Cbt can be provided between the 3-2 thin film transistor T32" and the fourth thin film transistor T4'.

[0214] The third gate insulating layer 113b can be provided over the second semiconductor layer AO, and over the third gate insulating layer 113b, the upper scan line 163 of the second scan line SL2' and the upper scan line 165 of the fourth scan line SL4 can extend in a first direction (e.g., the x-direction). The upper scan line 163 of the second scan line SL2' can overlap with at least a portion of the lower scan line 143. The upper scan line 165 of the fourth scan line SL4 can overlap with at least a portion of the lower scan line 145. That is, the second scan line SL2' and the fourth scan line SL4 can be two conductive layers provided in different layers.

[0215] AsFigure 13A As illustrated in FIG. 12, the region of the lower scan line 143 of the second scan line SL2' overlapping with the second semiconductor layer AO can be a lower gate electrode G4a of the fourth thin film transistor T4'. The region of the upper scan line 163 of the second scan line SL2' overlapping with the second semiconductor layer AO can be an upper gate electrode G4b of the fourth thin film transistor T4'. Further, the region of the lower scan line 145 of the fourth scan line SL4 overlapping with the second semiconductor layer AO can be a lower gate electrode G32a of the 3-2 thin film transistor T32". The region of the upper scan line 165 of the fourth scan line SL4 overlapping with the second semiconductor layer AO can be an upper gate electrode G32b of the 3-2 thin film transistor T32". That is, the 3-2 thin film transistor T32" and the fourth thin film transistor T4' can have a dual gate structure in which a control electrode is provided above and below a semiconductor layer.

[0216] The upper gate electrode G32b of the 3-2 thin film transistor T32" and the upper gate electrode G4b of the fourth thin film transistor T4' can each be a single layer or a multilayer including at least one of Mo, Cu, and Ti.

[0217] The second interlayer insulating layer 114b can cover the 3-2 thin film transistor T32" and the fourth thin film transistor T4'. On the second interlayer insulating layer 114b, the second initialization voltage line VL2, the first and second node electrodes 1174c and 1174d, and the connection electrodes 1176, 1177, 1178, 1179, and 1180 can be provided.

[0218] The second initialization voltage line VL2 can be connected to the drain region D7 of the seventh thin film transistor T7 through a contact hole 1181 formed in the first gate insulating layer 112, the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b.

[0219] As Figure 13A and Figure 14AAs shown, the first node electrode 1174c can electrically connect the gate electrode G1 of the first thin-film transistor T1 to the source region S31" of the 3-1 thin-film transistor T31" through the first opening SOP1 formed in the second electrode CE2 of the capacitor Cst. One end of the first node electrode 1174c can be electrically connected to the gate electrode G1 of the first thin-film transistor T1 through the contact hole 1157c formed in the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b. The other end of the first node electrode 1174c can be electrically connected to the source region S31" of the 3-1 thin-film transistor T31" through the contact hole 1156c formed in the first gate insulating layer 112, the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b.

[0220] like Figure 13A and Figure 14B As shown, the second node electrode 1174d can electrically connect the gate electrode G1 of the first thin-film transistor T1 to the source region S32" of the 3-2 thin-film transistor T32" through the second opening SOP2 formed in the second electrode CE2 of the capacitor Cst. One end of the second node electrode 1174d can be electrically connected to the gate electrode G1 of the first thin-film transistor T1 through the contact hole 1157d formed in the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b. The other end of the second node electrode 1174d can be electrically connected to the source region S32" of the 3-2 thin-film transistor T32" through the contact hole 1156d formed in the third gate insulating layer 113b and the second interlayer insulating layer 114b.

[0221] The connection electrode 1176 can be electrically connected to the first initialization voltage line VL1 through contact holes 1182 formed in the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b. The connection electrode 1176 can be electrically connected to the source region S4' of the fourth thin-film transistor T4' through contact holes 1183 formed in the third gate insulating layer 113b and the second interlayer insulating layer 114b.

[0222] The connecting electrode 1177 can be electrically connected to the drain region D6 of the sixth thin film transistor T6 through contact holes 1184 formed in the first gate insulating layer 112, the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b.

[0223] One end of the connection electrode 1178 can be electrically connected to the drain region D31" of the 3-1 thin film transistor T31" through a contact hole 1185 formed in the first gate insulating layer 112, the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b. The other end of the connection electrode 1178 can be electrically connected to the drain region D32" of the 3-2 thin film transistor T32" through a contact hole 1186 formed in the third gate insulating layer 113b and the second interlayer insulating layer 114b.

[0224] One end of the connection electrode 1179 can be electrically connected to the second electrode CE2 of the first capacitor Cst through a contact hole 1187 formed in the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b. The other end of the connection electrode 1179 can be electrically connected to the source region S5 of the fifth thin film transistor T5 through a contact hole 1188 formed in the first gate insulating layer 112, the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b.

[0225] The connection electrode 1180 can be electrically connected to the source region S2 of the second thin film transistor T2 through a contact hole 1189 formed in the first gate insulating layer 112, the second gate insulating layer 113a, the first interlayer insulating layer 114a, the third gate insulating layer 113b, and the second interlayer insulating layer 114b.

[0226] The first gate insulating layer 112, the second gate insulating layer 113a, and the third gate insulating layer 113b can each include an inorganic material such as an oxide or a nitride. For example, the first gate insulating layer 112, the second gate insulating layer 113a, and the third gate insulating layer 113b can each include at least one of SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2.

[0227] The first interlayer insulating layer 114a and the second interlayer insulating layer 114b can each include an inorganic material such as an oxide or a nitride. For example, the first interlayer insulating layer 114a and the second interlayer insulating layer 114b can each include at least one of SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2.

[0228] The second initialization voltage line VL2, the first node electrode 1174c and the second node electrode 1174d, and the connection electrodes 1176, 1177, 1178, 1179, and 1180 can each include a highly conductive material such as a metal and a conductive oxide. For example, the second initialization voltage line VL2, the first node electrode 1174c and the second node electrode 1174d, and the connection electrodes 1176, 1177, 1178, 1179, and 1180 can each be a single layer or a multi-layer including at least one of Al, Cu, and Ti.

[0229] The fourth electrode CE4 of the second capacitor Cbt can be connected to the second node electrode 1174d, and can be electrically connected to the first gate electrode G1.

[0230] The first planarization layer 115a can be disposed on the second interlayer insulating layer 114b, and the data line DL and the driving voltage line PL can be disposed on the first planarization layer 115a.

[0231] The data line DL can be electrically connected to the source region S2 of the second thin-film transistor T2 when the data line DL is electrically connected to the connection electrode 1180 through the contact hole 1191 formed in the first planarization layer 115a.

[0232] The driving voltage line PL can be electrically connected to the source region S5 of the fifth thin-film transistor T5 when the driving voltage line PL is electrically connected to the connection electrode 1179 through the contact hole 1192 formed in the first planarization layer 115a. The driving voltage line PL can cover the second semiconductor layer AO, and can block light that can enter from above the substrate 100.

[0233] The data line DL and the driving voltage line PL can each be a single layer or a multi-layer including at least one of Al, Cu, and Ti.

[0234] The second planarization layer 115b can be disposed on the first planarization layer 115a, and the organic light emitting diode OLED can be disposed on the second planarization layer 115b. A pixel electrode of the organic light emitting diode OLED can be electrically connected to the drain region D6 of the sixth thin-film transistor T6 through at least one of the connection electrodes 1177 and 1193 thereunder. The connection electrode 1193 can be electrically connected to the connection electrode 1177 through a contact hole formed in the second planarization layer 115b.

[0235] The first planarization layer 115a and the second planarization layer 115b can each include an organic material such as acrylic, BCB, PI, or HMDSO. Alternatively, the first planarization layer 115a and the second planarization layer 115b can each include an inorganic material. The first planarization layer 115a and the second planarization layer 115b can each include a single layer or multiple layers. A pixel definition layer can be disposed on the second planarization layer 115b.

[0236] Referring to Figure 13 , the 1-1 scan line SL1a and the third scan line SL3 can be shared by two pixel circuits PC4 adjacent to each other in a second direction (e.g., a y direction).

[0237] That is, the 1-1 scan line SL1a can be electrically connected to a seventh thin-film transistor of a different pixel circuit PC4 adjacent to an upper side of the pixel circuit PC4 of Figure 13 in the second direction (e.g., the y direction) shown in the drawings. Accordingly, the first scan signal GW transmitted to the 1-1 scan line SL1a can be transmitted to the seventh thin-film transistor of the different pixel circuit PC4 as a third scan signal. Likewise, the third scan line SL3 can be electrically connected to a second thin-film transistor of a different pixel circuit PC4 adjacent to a lower side of the pixel circuit PC4 of Figure 13 in the second direction (e.g., the y direction) shown in the drawings. Accordingly, the third scan signal GB transmitted to the third scan line SL3 can be transmitted to the second thin-film transistor of the different pixel circuit PC4 as a first scan signal.

[0238] Figure 15 is a schematic plan view of a display panel according to an exemplary embodiment of the inventive concept.

[0239] Referring to Figure 15 , the pixels P can be arranged in a display area DA of the display panel 10. The pixels P can be arranged in various forms such as a stripe arrangement, a five-bank arrangement, and a mosaic arrangement, and thus can display an image. Each pixel P can include an organic light emitting diode (OLED) as a display element, and the organic light emitting diode (OLED) can be connected to a pixel circuit. Each pixel P can emit, for example, red light, green light, blue light, or white light from the organic light emitting diode (OLED).

[0240] In the display area DA, the first to fourth scan lines, the emission control line, the first initialization voltage line, and the second initialization voltage line can be spaced apart from each other and arranged in a row direction. Further, in the display area DA, the data lines and the driving voltage lines can be spaced apart from each other and arranged in a column direction.

[0241] The first scan driving circuit SDRV1 and the second scan driving circuit SDRV2, the emission control driving circuit EDRV, and the data driving circuit DDRV can be disposed outside the display area DA. The first scan driving circuit SDRV1 and the second scan driving circuit SDRV2 are connected to the first to fourth scan lines and transmit scan signals. The emission control driving circuit EDRV is connected to the emission control line EL and transmits an emission control signal. The data driving circuit DDRV is connected to the data line DL and transmits a data signal. A main voltage line (not shown) for supplying an initialization voltage Vint, a driving voltage ELVDD, and a common voltage ELVSS can be further disposed outside the display area DA.

[0242] The first scan driving circuit SDRV1 can be connected to a scan line connected to a gate electrode of a thin film transistor of the pixel P of the display area DA turned on according to a first voltage. The second scan driving circuit SDRV2 can be connected to a scan line connected to a gate electrode of a thin film transistor of the pixel P of the display area DA turned on according to a second voltage. The first voltage can be a voltage having a high level, and the second voltage can be an inverted voltage (i.e., a voltage having a low level) of the first voltage.

[0243] In an embodiment, the pixel P is a pixel P2 of Figure 5 The first scan driving circuit SDRV1 can be connected to the first to third scan lines SL1 to SL3, and the second scan driving circuit SDRV2 can be connected to the fourth scan line SL4.

[0244] In an embodiment, the pixel P is a pixel P3 of Figure 9 The first scan driving circuit SDRV1 can be connected to the first to third scan lines SL1 to SL3, and the second scan driving circuit SDRV2 can be connected to the fourth scan line SL4.

[0245] In an embodiment, the pixel P is a pixel P4 of Figure 12 The first scan driving circuit SDRV1 can be connected to the first and third scan lines SL1 and SL3, and the second scan driving circuit SDRV2 can be connected to the second and fourth scan lines SL2' and SL4.

[0246] The controller CON (e.g., a control circuit) can receive input image data and an input control signal for controlling display of the input image data from an external graphic controller (not shown). The controller CON can generate a control signal in response to the input control signal, and can transmit the generated control signal to the first scan driving circuit SDRV1, the second scan driving circuit SDRV2, the emission control driving circuit EDRV, and the data driving circuit DDRV.

[0247] The first scan driving circuit SDRV1, the second scan driving circuit SDRV2, and the emission control driving circuit EDRV can be directly disposed on the substrate. The data driving circuit DDRV can be disposed on a flexible printed circuit board (FPCB) that is electrically connected to pads disposed on one side of the substrate. In an exemplary embodiment, the data driving circuit DDRV is directly disposed on the substrate in a chip on glass (COG) manner or a chip on plastic (COP) manner.

[0248] As described above, according to at least one exemplary embodiment of the present disclosure, the occurrence of residual images can be prevented, and thus the display apparatus can provide a higher quality image.

[0249] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A pixel comprising: a drive transistor including a semiconductor layer and a gate electrode; a switching transistor connected to a first terminal of the semiconductor layer and a data line; and a compensation transistor connected to a second terminal of the semiconductor layer and the gate electrode of the drive transistor, wherein the compensation transistor includes: a first sub-transistor including a first gate electrode that receives a first scan signal having a first voltage level during a first period; and a second sub-transistor connected in parallel to the first sub-transistor and including a second gate electrode that receives a second scan signal having a second voltage level that is an inversion of the first voltage level during the first period, wherein, in the first period, the switching transistor, the first sub-transistor, and the second sub-transistor are simultaneously turned on, and an organic light emitting diode of the pixel does not emit light, and wherein, in a second period after the first period, the switching transistor, the first sub-transistor, and the second sub-transistor are simultaneously turned off, and the organic light emitting diode emits light. the first sub-transistor is a P-channel thin film transistor, and the second sub-transistor is an N-channel thin film transistor.

2. The pixel of claim 1, wherein, 3. The pixel according to claim 1, further comprising: a first scan line that transmits the first scan signal to the first sub-transistor and is connected to the first sub-transistor; and a second scan line that transmits the second scan signal to the second sub-transistor and is connected to the second sub-transistor, wherein the first scan line and the second scan line extend in parallel, and the drive transistor is between the first scan line and the second scan line.

4. The pixel according to claim 1, further comprising: a first node electrode that connects a semiconductor layer of the first sub-transistor and the gate electrode of the drive transistor to each other; and a second node electrode that connects a semiconductor layer of the second sub-transistor and the gate electrode of the drive transistor to each other.

5. The pixel according to claim 4, further comprising: a capacitor that overlaps the drive transistor.

6. The pixel according to claim 4, further comprising: the data line and a drive voltage line are provided on the same layer as the first node electrode. the drive transistor is a P-channel thin film transistor. each of the first sub-transistor and the second sub-transistor includes a semiconductor layer including silicon. the first sub-transistor includes a semiconductor layer including silicon, and the second sub-transistor includes a semiconductor layer including an oxide.

7. The pixel of claim 4, wherein, 10. The pixel according to claim 9, further comprising:

8. The pixel of claim 1, wherein, an initialization transistor connected to the gate electrode of the drive transistor and an initialization voltage line.

9. The pixel of claim 1, wherein, the initialization transistor includes a semiconductor layer including an oxide.

12. A pixel comprising: a drive transistor including a semiconductor layer and a gate electrode; 11. The pixel of claim 10, wherein, a switching transistor connected to a first terminal of the semiconductor layer and a data line; and a compensation transistor connected to a second terminal of the semiconductor layer and the gate electrode of the drive transistor, wherein the compensation transistor includes: ​ ​ ​ ​ a first sub-transistor including a first gate electrode receiving a first scan signal having a first voltage level during a first period and a second gate electrode receiving a second scan signal which is an inversion of the first voltage level during the first period; and a second sub-transistor connected in series to the first sub-transistor and including a third gate electrode receiving the first scan signal, wherein, in the first period, the switch transistor, the first sub-transistor, and the second sub-transistor are simultaneously turned on, and an organic light emitting diode of the pixel does not emit light, and wherein, in a second period after the first period, the switch transistor, the first sub-transistor, and the second sub-transistor are simultaneously turned off, and the organic light emitting diode emits light.

13. The pixel according to claim 12, further comprising: a first scan line connected to the first gate electrode of the first sub-transistor and the third gate electrode of the second sub-transistor; and a second scan line connected to the second gate electrode of the first sub-transistor. the second gate electrode is disposed on a lower layer of the first gate electrode, and 14. The pixel of claim 13, wherein, the third gate electrode is disposed on the same layer as the first gate electrode.

15. The pixel according to claim 12, further comprising: a capacitor overlapping the drive transistor.

16. The pixel according to claim 12, further comprising: a node electrode connecting the semiconductor layer of the compensation transistor and the gate electrode of the drive transistor to each other; and the data line and a drive voltage line are disposed on the same layer as the node electrode. each of the plurality of pixels includes: a drive transistor including a semiconductor layer and a gate electrode; 17. A display device comprising a plurality of pixels, wherein, a switch transistor connected to a first terminal of the semiconductor layer and a data line; and a compensation transistor connected to a second terminal of the semiconductor layer and the gate electrode of the drive transistor, wherein the compensation transistor includes: a first sub-transistor including a first gate electrode receiving a first scan signal having a first voltage level during a first period; and a second sub-transistor including a second gate electrode receiving a second scan signal having a second voltage level which is an inversion of the first voltage level during the first period, wherein, in the first period, the switch transistor, the first sub-transistor, and the second sub-transistor are simultaneously turned on, and an organic light emitting diode of the pixel does not emit light, and wherein, in a second period after the first period, the switch transistor, the first sub-transistor, and the second sub-transistor are simultaneously turned off, and the organic light emitting diode emits light. the first sub-transistor and the second sub-transistor are connected in parallel, the first sub-transistor is a P-channel thin film transistor, and the second sub-transistor is an N-channel thin film transistor.

18. The display device of claim 17, wherein, the first sub-transistor includes a semiconductor layer including silicon, and the second sub-transistor includes a semiconductor layer including an oxide.

20. The display device according to claim 17, further comprising:

19. The display device of claim 18, wherein, ​ ​ a third gate electrode receiving the first scan signal during the first time period, wherein the third gate electrode is disposed on an upper layer of the second gate electrode and is disposed on the same layer as the first gate electrode.

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