Patterning method

Abstract

The present disclosure relates to a method of providing patterning of a bottom layer to form a first set of trenches and a second set of trenches in the bottom layer. The method is based on a combination of two litho-etch (LE) patterning processes aided by a spacer-assisted (SA) technique. Accordingly, the inventive method can be referred to as a "SALELE" patterning process. The method uses one or more first upper blocks formed by a tone inversion approach, an upper memory layer that allows first memory of upper trenches and subsequent memory of second upper blocks; and a lower memory layer that allows first memory of first lower trenches and one or more first lower blocks and subsequent memory of second lower trenches and one or more second lower blocks.

Description

Technical Field

[0001] The present invention relates to a patterning method. Background Technology

[0002] Photolithography and etching processes (“litho-etch”) are commonly used in semiconductor device fabrication, for example, to form trenches, openings, or other patterns in layers such as hard mask layers, dielectric layers, metal layers, or semiconductor layers. Patterns such as trench patterns can be defined (i.e., exposed and developed) in a resist layer by photolithography and then transferred to the underlying layer by etching. The minimum critical size (CD) of patterning based on photolithography-etch depends on the wavelength of light used to expose the resist. Therefore, extreme ultraviolet lithography (EUVL) enables patterns with a reduced CD compared to current technologies based on, for example, 193i.

[0003] In spacer-assisted multiple patterning techniques such as SADP or SAQP (also known as self-aligned multiple patterning), raster-patterned layers of core axes and spacers can be used to form a sub-lithographic, tightly pitched line pattern in the underlying layer. Multiple patterning can be combined with blocking techniques to enable the formation of discontinuous or broken lines.

[0004] EP 3618103 discloses a patterning method based on a combination of two photolithography-etching processes supplemented with spacer-assisted (SA) technology. This method can therefore be referred to as the "SALELE" patterning process. The two LE processes allow for the patterning of two sets of alternating trenches in the target layer. Using two LE processes allows for the formation of relatively tight pitch patterns by combining two loose pitch patterns. Simultaneously, the addition of the spacer-assisted technology makes it possible to ensure at least a minimum spacing between adjacent trenches in the target layer. By using blocking patterns, discontinuous trenches with small tip-to-tip spacing can be formed.

[0005] While existing patterning methods offer a path toward increasingly aggressive target CD, more aggressive target CD implies greater sensitivity to process variability, particularly to edge placement error (EPE). Summary of the Invention

[0006] In view of this, the object of the present invention is to provide a patterning method that enables the formation of groove patterns, including discontinuous grooves, and reduces sensitivity to process variations, particularly improving EPE margin. Further and alternative objectives may be understood from the following.

[0007] According to a first aspect of the present invention, a patterning method is provided, comprising:

[0008] A lower memory layer is formed on top of the bottom layer, and an auxiliary blocking mask layer is formed on the lower memory layer;

[0009] A blocking opening is formed in the auxiliary blocking mask layer;

[0010] A first upper barrier is formed in the blocking opening;

[0011] An upper memory layer is formed above the lower memory layer and the first upper barrier;

[0012] The upper memory layer is patterned using photolithography and etching to form upper trenches in the upper memory layer, wherein at least a subset of the upper trenches is interrupted by a corresponding first upper barrier.

[0013] Sidewall spacers are formed along the sidewalls of the upper groove;

[0014] The lower memory layer is patterned to form a first lower trench in the lower memory layer. The patterning includes etching while the patterned upper memory layer, sidewall spacers and a first upper barrier are masking the lower memory layer. At least one subset of the first lower trench is interrupted by a corresponding first lower barrier, which is formed by a corresponding portion of the first lower memory layer masked by the corresponding first upper barrier.

[0015] The patterned upper memory layer is patterned using photolithography and etching to form a second upper barrier from the remaining portion of the upper memory layer, and

[0016] Patterning the patterned lower memory layer to form a second lower trench in the patterned lower memory layer, the patterning including:

[0017] An auxiliary trench mask stack is formed above the lower memory layer, and the auxiliary trenches are patterned therein by photolithography and etching; and

[0018] While the patterned lower memory layer is masked by the patterned auxiliary trench mask stack, the spacer line and the second upper barrier and the first upper barrier mask the first lower barrier, the patterned lower memory layer is etched, wherein at least a subset of the second lower trench is interrupted by the corresponding second lower barrier, the corresponding second lower barrier being formed by the corresponding second lower memory layer portion masked by the corresponding second upper barrier.

[0019] The method also includes patterning a first set of grooves below the first lower groove and a second set of grooves below the second lower groove in the underlying layer.

[0020] The method of this invention allows for patterning of a substrate to form a first set of trenches and a second set of trenches within the substrate. The method is based on an advantageous combination of two photolithography-etching (LE) patterning processes supplemented with spacer-assisted (SA) technology. Accordingly, the method of this invention may be referred to as the "SALELE" patterning process and has advantages corresponding to those of the SALELE process described above. Compared to conventional SADP and SAQP techniques, the method of this invention particularly allows for greater flexibility in the shape of the trench patterns. Furthermore, this method enables the formation of trench patterns with a smaller CD (cathode) than that provided by conventional pure photolithography patterning techniques.

[0021] Furthermore, using LE (Leaf Lens) for patterning the upper groove and for patterning the second lower groove allows for the formation of a relatively tight pitch pattern by combining two loose pitch patterns. This can be particularly advantageous when combined with EUVL, which is otherwise a technique prone to random failures if used to directly form aggressively scaled patterns. Loose printing also offers corresponding advantages in the 193i application.

[0022] The method of this invention uses a stack comprising two memory layers: a lower memory layer above (e.g., on the bottom layer) a bottom layer in which a first set of trenches and a second set of trenches are formed, and an upper memory layer above (e.g., on the lower memory layer). Each of the lower and upper memory layers is provided for memorizing (corresponding) patterns. As the method proceeds, each memory layer is used multiple times to facilitate trench formation in the bottom layer. The upper memory layer allows for the memorization of upper trenches first, followed by the memorization of upper barriers. Since the upper barriers are formed by patterning the already patterned upper memory layer, the upper barriers can be self-aligned relative to the first set of lower trenches and thus reliably aligned with the second set of lower trenches. The lower memory layer allows for the memorization of first lower trenches and one or more first lower barriers, followed by the memorization of second lower trenches and one or more second lower barriers.

[0023] Compared to what can be achieved by directly “printing” photolithographically defined discontinuous trenches into the memory layer, using barriers (e.g., first and second upper barriers) to define trench breaks enables the formation of discontinuous trenches with smaller tip-to-tip spacing.

[0024] According to this method, the first upper barrier can be formed using a tone inversion method, that is, by filling the opening instead of printing the barrier "positively" in the layer (i.e., a "non-tone inversion" method). This allows for the definition of a smaller tip-to-tip spacing. It further allows for the use of trimming techniques to achieve an even smaller tip-to-tip spacing, as will be explained below.

[0025] Furthermore, the method of the present invention has the aforementioned advantages, combined with an improved margin for EPE that allows for reduced sensitivity to process variability, particularly during the patterning of the second lower trench.

[0026] Improved margin is facilitated at least in part by forming a first upper barrier above the lower memory layer and by also memorizing the first upper barrier as a first lower barrier below the first barrier. These "duotones," including the barrier (i.e., the first lower barrier below the first barrier representing two different shades), provide masking of the first lower barrier via the first upper barrier during the patterning of the second lower trench (within the already patterned lower memory layer). Therefore, even if auxiliary trenches in the auxiliary trench mask stack extend / overlap along the first lower trench above the first upper and first lower barriers, the first upper barrier can resist etching of the first lower barrier. Thus, trench interruptions of the first lower trench (memorized as the first lower barrier) can also be preserved after the second lower trench is formed.

[0027] Furthermore, according to the method of the present invention, sidewall spacers are present during the patterning of the first and second lower trenches.

[0028] The presence of the sidewall spacer line makes it possible to ensure at least a minimum spacing between the first and second lower trenches. Therefore, if an auxiliary trench in the auxiliary trench mask stack (by design or attributable to the EPE) extends above or overlaps the first lower trench, the spacer line portion extending along the exposed first lower trench can mask (and thus resist etching) the lower memory layer portion below this spacer line portion. Thus, the second lower trench can be etched in the lower memory layer through the overlapping auxiliary trenches, while the spacer line portion ensures that the first and second lower trenches are separated by the masked lower memory layer portion, for example, having a width determined by the linewidth of the spacer line.

[0029] As can be understood from the above discussion of the first aspect, the lower and upper memory layers represent different layers, each formed of a corresponding material. The material of the lower memory layer (“lower layer material”) and the material of the upper memory layer (“upper layer material”) can therefore be different. For example, the lower layer material can be a dielectric material, such as an oxide, nitride, or carbide. The upper layer material can be amorphous silicon (aSi).

[0030] The first upper barrier can be formed of a material different from each of the lower and upper layer materials (the barrier material). The barrier material can be a metallic material, such as a metal nitride, metal carbide, or metal oxide.

[0031] The bottom layer below the lower memory layer represents a layer different from both the lower and upper memory layers. The bottom layer can be formed of a material at least different from the material of the lower layers (“bottom layer material”). As will be further described below, the bottom layer can also be a memory layer (i.e., a “target memory layer”). The bottom / target layer material can, for example, be formed of any material discussed in conjunction with barrier materials.

[0032] The sidewall spacers can advantageously be formed of a material that is different from each of the upper layer material, the lower layer material, and the barrier material, and also different from the bottom layer material (“spacer material”). The sidewall spacers (“spacers”) can be formed of typical spacer materials, such as oxides or nitrides deposited by atomic layer deposition (ALD) (different from the lower and upper layer materials and the barrier material).

[0033] Different (corresponding material) memory layers allow for etching contrast during various layer patterning steps in the first method. In other words, during the patterning of a first layer of the first material (such as the lower memory layer) to form trenches therein, the first layer can be etched at a greater rate than a second layer or component of the second material that is also exposed to the etching process during that patterning. Thus, the first material (of the first layer) can be selectively etched or removed, i.e., removed at a greater rate than the second material (of the second layer or component).

[0034] The first part that masks the second part during etching means that the first part is above the second part (or conversely, the second part is below the first part), so that the first part can act as an etching mask and thus resist the etching of the second part.

[0035] The first component masking the second component means that the second component is at least masked by the first component, and may also be masked by other components between or above the first component. In other words, the first component can (possibly together with other intermediate or upper components) serve as an etching mask for the second component.

[0036] Accordingly, patterning of the lower memory layer may include etching the lower memory layer while the patterned upper memory layer, sidewall spacers, and first upper barrier act as an etching mask. The lower memory layer may be etched at a greater rate than the patterned upper memory layer, sidewall spacers, and first upper barrier.

[0037] Patterning of the patterned lower memory layer may include etching the patterned lower memory layer while the patterned auxiliary trench mask stack, the second upper barrier, and the spacers act as etch masks. As described above, during the patterning of the patterned lower memory layer, the first upper barrier may also act as an etch mask for the first lower barrier. The patterned lower memory layer may be etched at a greater rate than the patterned auxiliary trench mask stack (e.g., its mask material), the second upper barrier, the spacers, and the first upper barrier.

[0038] The upper memory layer can be formed on top of the first upper barrier and the patterned auxiliary barrier mask layer. Therefore, in subsequent patterning steps, the patterned auxiliary mask layer can exist as an intermediate layer between the upper and lower memory layers. Accordingly, an upper trench can be formed to extend through the upper memory layer and the intermediate layer. Furthermore, the upper barrier can be formed from the remaining portion of the upper memory layer and the remaining portion of the intermediate layer (i.e., the remaining portion of the patterned auxiliary barrier mask layer) below the upper memory layer portion. Maintaining the patterned auxiliary mask layer simplifies the process by reducing the number of process steps prior to forming the upper memory layer. Additionally, the intermediate layer increases the available mask budget during subsequent patterning steps. If the auxiliary mask layer is formed of the same material as the upper memory layer, the auxiliary mask layer and the upper memory layer can be formed together to create an upper memory layer with increased thickness. Accordingly, the aforementioned advantages can be achieved without increasing the complexity of the stack.

[0039] Alternatively, the patterned auxiliary barrier mask layer can be removed before forming the upper memory layer. Therefore, the upper memory layer can be formed above the first upper barrier and the lower memory layer. This allows for a reduction in the stack height, thereby facilitating the patterning step by reducing the aspect ratio of the trenches to be formed in the stack.

[0040] The first and second groups of trenches can be patterned simultaneously in the underlying layer. Alternatively, the first and second groups of trenches can be patterned sequentially. That is, the first group of trenches can be patterned in the underlying layer before the second group of trenches. This approach also allows for a reduction in the number of times layers beneath the underlying layer (such as an insulating layer) are exposed to the etchant.

[0041] Spacers can be formed using sidewall spacer layer formation processes, including conformally deposited spacer layers through etch-back. For example, the spacer layer can be conformally deposited (e.g., via ALD) to cover a patterned upper memory layer, the sidewalls of the upper trench, and the bottom surface. The spacer layer can then undergo top-down anisotropic etching (e.g., vertically biased dry etching), adapted to remove portions of the spacer layer from horizontally oriented surfaces, including the upper surface of the patterned upper memory layer and the lower surface of the upper trench, such that portions of the spacer layer remain on the upper trench sidewalls to form spacers. Sidewall spacer formation processes allow for reliable formation of spacers with uniform linewidth / thickness, thereby helping to reduce process variability.

[0042] Forming the first upper barrier may include depositing a barrier material on top of the auxiliary barrier mask layer and in the barrier opening, and removing the barrier material deposited outside the barrier opening, so that the barrier material remains in the barrier opening to form the first barrier.

[0043] Forming the first upper barrier may include:

[0044] A conformal barrier layer of barrier material is formed on top of the auxiliary barrier mask layer and is aligned with the sidewalls of the barrier opening, wherein the barrier material deposited on the sidewalls merges within the barrier opening, and

[0045] The conformal barrier layer is etched back, which removes the barrier material deposited outside the barrier opening and retains the barrier material inside the barrier opening to form the first upper barrier.

[0046] (For example, through atomic layer deposition, ALD) conformal layer deposition allows for reliable filling of small CD blocking openings. The CD of the blocking opening can thus be understood as the length dimension of the blocking opening. That is, the size of the blocking opening along the longitudinal direction of the upper trench or equivalently along the longitudinal direction of the first lower trench (both of which will be formed).

[0047] The barrier opening can be "closed" by merging the barrier material deposited on the sidewalls. This allows for a first upper barrier while not defining any gaps within the barrier opening. To reliably merge the barrier material within the barrier opening, a conformal barrier layer with a thickness at least half that of the trench opening CD can be formed.

[0048] Etching back of the conformal barrier layer may include subjecting the conformal barrier layer to anisotropic etching in a top-to-bottom direction.

[0049] Forming a blocking opening may include first patterning an initial blocking opening in an auxiliary blocking mask layer using photolithography and etching, and then forming a final blocking opening by forming a liner that conforms to the sidewalls of the initial blocking opening.

[0050] Therefore, by “trimming” or “shrinking” the initial blocking opening, the final blocking opening can be formed with a smaller CD.

[0051] The liner can be formed as a conformal liner. The (conformal) liner can be subjected to back etching (e.g., subjecting the conformally deposited liner to anisotropic etching in a top-down direction) to remove the liner portion from the horizontally oriented surface, thereby retaining the liner portion on the (vertically oriented) sidewall that initially blocked the opening.

[0052] The method may further include:

[0053] After the first lower trench is formed, an auxiliary barrier mask stack is formed, which includes mask material filling the upper trench and the first lower trench and also includes a resist layer.

[0054] Patterning of the patterned upper memory layer may include first patterning an auxiliary barrier mask stack using photolithography and etching to form an auxiliary barrier, and then patterning the patterned upper memory layer to form a second upper barrier, the patterning including etching while the auxiliary barrier masks the patterned upper memory layer.

[0055] During etching, the patterned upper memory layer is correspondingly masked by auxiliary barriers. The upper barriers can thus be formed from portions of the upper memory layer masked by the auxiliary barriers. Mask material from the auxiliary barrier mask stack can fill the upper and lower trenches, thereby covering the first lower barrier and the first upper barrier. The mask material can be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material can differ from the upper layer material, spacer material, and barrier material. Mask material can be deposited to form a planarized mask material layer that fills the trenches and covers the patterned upper memory layer. The mask material can include organic spin-coating materials such as SOCs.

[0056] The auxiliary trench mask stack can be formed on the lower memory layer and the second upper barrier.

[0057] The method may include removing the auxiliary trench mask stack before patterning the first and second sets of trenches in the underlying layer.

[0058] The auxiliary trench mask stack may include a mask material forming a planarization layer covering a second upper barrier, spacer lines, and a patterned lower memory layer. The auxiliary trench mask stack may further include a resist layer on top of the mask material. The mask material may be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material may be at least different from the spacer material, lower layer material, barrier material, and upper layer material. The mask material may be an organic spin-coating material such as SOC.

[0059] The auxiliary trenches may be formed to expose the upper surface portion of the lower memory layer between the first lower trenches. Patterning of the patterned lower memory layer may include etching a second lower trench in the lower memory layer through the auxiliary trenches.

[0060] At least one auxiliary trench of the auxiliary trench mask stack can extend above the first lower trench and above a first upper barrier located above the first lower barrier in the first lower trench. Therefore, the at least one auxiliary trench can expose the first upper barrier. Due to the presence of the first upper barrier, the patterned lower memory layer can still be etched to form the second lower trench without removing the trench interruption of the previous memory of the first lower trench (i.e., the first lower barrier therein). Furthermore, the presence of the spacer layer makes it possible to ensure that the second lower trench is separated from the first lower trench.

[0061] The trenches of at least one subset of the second lower trenches may be arranged alternately with the trenches of at least one subset of the first set of lower trenches. That is, in these subsets of trenches, the second lower trenches may be formed between a pair of first lower trenches, and vice versa.

[0062] Each trench of the at least one subset of the second lower trenches can be (only) spaced apart from the adjacent trenches of the at least one subset of the first lower trenches by a corresponding lower line formed by a corresponding third lower memory layer portion obscured by the corresponding sidewall spacer. Therefore, the minimum spacing between the first and second lower trenches can be determined by the linewidth of the spacer.

[0063] The patterning method of the first aspect can be advantageously combined with methods for forming interconnect structures. Therefore, according to the second aspect, a method for forming an interconnect structure is provided, comprising:

[0064] A target memory layer is formed on top of the insulating layer;

[0065] According to the method of the first aspect, a first group and a second group of trenches are formed in the target memory layer, wherein the bottom layer is the target memory layer;

[0066] After forming the first and second sets of trenches in the target memory layer, while the target memory layer masks the insulating layer, the first trench is etched in the insulating layer below the first set of trenches in the target memory layer, and the second trench is etched in the insulating layer below the second set of trenches in the target memory layer.

[0067] Conductive material is deposited in trenches within the insulating layer.

[0068] The second aspect of the method may also include:

[0069] Before the patterning of the patterned upper memory layer:

[0070] Forming a through-hole etch stack includes a mask material filling the upper and lower trenches and further includes a resist layer.

[0071] An opening is formed in the through-hole etch stack, which exposes the upper surface of the remaining portion of the upper memory layer.

[0072] The exposed upper surface of the upper memory layer is etched back to form an opening in the upper memory layer, and

[0073] The lower memory layer and the target memory layer are sequentially etched back through the opening in the upper memory layer to form an extended opening that runs through them;

[0074] The method also includes etching the insulating layer through the extended opening.

[0075] Thus, a (second) via opening or via can be formed in the insulating layer. The via opening can be self-aligned with the second set of trenches in the target memory layer due to this patterning method, and therefore also with the second trenches in the insulating layer.

[0076] An initial via opening can be formed by first etching through the extended opening in the insulating layer, which can then be deepened during the aforementioned etching of the (second) trench in the insulating layer to form the final via opening.

[0077] Conductive material can be deposited to fill the (final) via openings and trenches in the insulating layer.

[0078] The mask material for a through-hole etching stack can be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material can differ from the upper layer material, spacer material, barrier material, and lower layer material. The mask material can also differ from one or more of the materials of the lower layer material, target material layer, and insulating layer. The mask material can be deposited to form a planarized mask material layer that fills trenches and covers a patterned upper memory layer. The mask material can be an organic spin-coating material such as a SOC.

[0079] The exposed upper surface of the patterned upper memory layer can be etched back using an etching process adapted to etch the patterned upper memory layer at a rate greater than that of the mask material filling the upper trench and / or greater than that of the spacer material. This allows for improved etch margin during subsequent sequential etchback of the memory layer.

[0080] The exposed upper surface of the upper memory layer can be located between a pair of upper trenches, and the width of the openings in the via etch stack can exceed the spacing between the pair of upper trenches. This allows for loose printing of the openings within the via etch stack.

[0081] The method may further include:

[0082] Before the patterning of the patterned upper memory layer:

[0083] Forming a through-hole etch stack includes a mask material filling the lower and upper trenches and further includes a resist layer.

[0084] An opening is formed in the through-hole etch stack, which exposes the bottom surface of the selected first lower trench and the spacer layer portions on the opposite sides of the selected first lower trench.

[0085] The exposed bottom surface is etched back to form an opening in the target memory layer;

[0086] The method also includes etching the insulating layer through the opening in the target memory layer.

[0087] Thus, a (first) via opening or via can be formed in the insulating layer. The via opening can be self-aligned with the first set of trenches in the target memory layer due to this patterning method, and therefore also with the first trenches in the insulating layer.

[0088] An initial via opening can be formed by etching the insulating layer through the opening, which can then be deepened during the etching of the (first) trench in the insulating layer to form the final via opening.

[0089] After an opening is formed in the target memory layer, the insulating layer can be etched immediately through the opening. However, if a second via opening is also formed as described above, it is also possible to perform etching of the insulating layer simultaneously through the opening in the target memory layer (to form the first via opening) and through the extended opening (to form the second via opening).

[0090] Conductive material can be deposited to fill the (final) via openings and trenches in the insulating layer.

[0091] The mask material for a through-hole etching stack can be a single deposited mask material layer or a stack of two or more deposited mask material layers. The mask material can differ from the upper layer material, spacer material, barrier material, and lower layer material. The mask material can also differ from one or more of the target memory layer and insulating layer. The mask material can be deposited to form a planarized mask material layer that fills the trench and covers the patterned upper memory layer. The mask material can be an organic spin-coating material such as a SOC.

[0092] Forming openings in a through-hole etch stack can include etching the mask material using an etching process adapted to etch the mask material at a rate greater than that of the spacer material. This allows the openings to self-align with the first set of lower trenches. Attached Figure Description

[0093] The above and other objects, features, and advantages of the present invention will be better understood from the following illustrative and non-limiting detailed description with reference to the accompanying drawings. In the drawings, similar reference numerals will be used for similar elements unless otherwise stated.

[0094] Figure 1-28 The process flow of the patterning method was explained. Detailed Implementation

[0095] Now refer to Figure 1-28 A method for patterning a bottom layer is described. This method will be described in conjunction with patterning a target memory layer 12, which can then be used to pattern trenches in an insulating layer 10. The trenches in the insulating layer 10 may be filled with a conductive material, such as a metal, to form conductive lines at the interconnect level of an interconnect structure, for example, in a back-to-end (BEOL) process. However, it will be noted that this method has more general applicability for patterning trenches in any layer. For example, the layer 12 to be patterned may be a semiconductor layer or a metal layer.

[0096] refer to Figure 1 The diagram shows a portion of a structure that will undergo the processing steps of this patterning method, in perspective. This structure may extend laterally or horizontally beyond the shown portion. Unless otherwise specified, the extension of this portion through the shown plane of the structure is common throughout all the figures. Note that the relative dimensions of the elements shown, especially the relative thicknesses of the layers, are merely schematic and may differ from the physical structure for purposes of clarity. Figure 1 In this context, directions X and Y indicate the first and second horizontal directions, respectively, parallel to the main extension planes and main surfaces of each layer. Direction Z indicates the vertical direction, or equivalent to the bottom-up direction or the layer stacking direction, thus perpendicular to the main extension planes and main surfaces of each layer. As can be understood, terms such as “above,” “over,” “below,” “upper,” “bottom,” and “lower” should be understood as relative positions viewed in the vertical direction. The “width” of a trench or the “linewidth” of a component should be understood as referring to the dimension along the first horizontal direction X. For example, the “longitudinal” or “length” dimension of a trench should be understood as referring to the dimension along the second horizontal direction Y.

[0097] Figure 1 A stack of layers is depicted, comprising a bottom target memory layer 12 and a lower memory layer 14 in a bottom-up direction. The lower memory layer 14 may be formed on top of the bottom target memory layer 12, as shown. However, it is envisioned that an interface layer, such as an adhesive layer, may be provided between the memory layers 12 and 14. If an interface layer exists between the two memory layers 12 and 14, the interface layer may be patterned in the same steps as the upper layer (such as layer 14), or in the same steps as the lower layer (such as layer 12).

[0098] The target memory layer 12 can be such as a metal nitride, metal carbide, or metal oxide (e.g., TiN, W). x C y Al X O y Or Al x N y The lower memory layer 14 can be a layer of metallic material, such as oxides, nitrides, or carbides, for example, SiO2, SiCO, SiC, SiN, or SiCN. The memory layers 12 and 14 can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0099] As will be understood from the following text, memory layer 14 and another upper memory layer 20 that has not yet been formed can be used to "memorize" or "store" one or more portions of the final "target" pattern to be transferred to target memory layer 12 through patterning. The "target pattern" can then be transferred to insulating layer 10. Therefore, "memory layers" 12, 14, 20 can instead be referred to as "patterning layers" 12, 14, 20.

[0100] like Figure 1 As further shown, a stack can be formed on the insulating layer 10. The insulating layer 10 can be an oxide material, such as SiO2, or another conventional low-k dielectric. One or more interface layers 11 (e.g., interface layers and / or oxide capping layers) may optionally be present between the target memory layer 12 and the insulating layer 10.

[0101] An insulating layer 10 may be formed on a substrate 1, such as a semiconductor substrate. An active device layer comprising a semiconductor device such as a transistor may be fabricated on the main surface of the substrate 1. The active device layer may also be referred to as a front-end process portion (FEOL portion). The insulating layer 10 may be formed on (not shown) conductive structures such as conductive lines at lower interconnect levels, or on contact structures for devices such as source / drain or gate contacts of semiconductor devices, as known in the art.

[0102] Figure 1-6 The process steps for forming the first upper barrier 19 are explained. The first upper barrier 19 is used to define the trench interruption of the first set of target trenches, which will be patterned in the target memory layer 12.

[0103] An auxiliary barrier mask layer 16 is formed above the lower memory layer 14, or as shown, above the lower memory layer 14. The auxiliary barrier mask layer 16 may be, for example, an oxide (such as SiO2), a metal nitride, or a metal oxide (such as TiN, Al). x N y Al XO y TiO x or ZrO x Metallic materials such as α-Si, or nitrides or carbides (e.g., SiCO or SiN). Another example is a-Si. The auxiliary barrier mask layer 16 can be deposited, for example, by CVD, ALD or PVD.

[0104] exist Figure 2 In this embodiment, a barrier aperture mask stack 160 is formed over an auxiliary barrier mask layer 16. The barrier aperture mask stack 160 may include a mask material 162 and a resist layer 164 formed over the mask material 162. The mask material 162 may be, for example, an organic spin-coating material such as SOC. The barrier aperture mask stack 160 is patterned to form an auxiliary barrier aperture 161. The auxiliary barrier aperture 161 may first be formed in the resist layer 164 by photolithography and then transferred to the mask material 162 by etching. Although not shown, the auxiliary barrier aperture mask stack 160 may include additional layers under the resist layer 164, such as one or more anti-reflective coatings, such as SiOC layers and / or spin-coated glass layers. An alternative to the mask stack is that the resist layer may be formed directly on the auxiliary barrier mask layer 16.

[0105] like Figure 3 As further shown, while the patterned auxiliary barrier opening mask stack 160 subsequently masks the auxiliary barrier mask layer 16, a barrier opening 17 can be formed in the auxiliary barrier mask layer 16 by etching through the auxiliary barrier opening 161. The barrier opening 17 can be etched using a suitable etching process, such as dry etching, or reactive ion etching (RIE).

[0106] According to also Figure 3 As indicated in the variation, forming the blocking opening 17 may include first patterning an initial blocking opening 17' in an auxiliary blocking mask layer 16 using photolithography and etching. Subsequently, a final blocking opening 17' can be formed by "shrinking" the initial blocking opening 17' by forming a liner 16' conforming to the sidewalls of the initial blocking opening 17'. The liner 16' can be conveniently formed as a conformal liner by ALD deposition of the same material as the auxiliary blocking mask layer 16. The (conformal) liner may optionally undergo a top-down anisotropic etch-back or polishing step (e.g., chemical mechanical polishing - CMP) to remove a portion of the liner from the horizontally oriented surface, such that the liner portion on the (vertically oriented) sidewalls of the initial blocking opening remains unchanged. Thus, the liner material can be removed from the bottom surface of the blocking opening 17.

[0107] exist Figure 4In this process, a barrier material has been conformally deposited on the auxiliary barrier mask layer 16. The barrier material forms a conformal barrier layer that covers the auxiliary barrier mask layer 16 and fills the barrier opening 17. The barrier layer is conformal to the sidewalls of the barrier opening 17. The deposition thickness of the barrier material allows the barrier material deposited on the sidewalls to merge within the barrier opening 17.

[0108] The critical dimension (CD) of the blocking opening 17 may refer to the dimension of the blocking opening along the second horizontal direction Y. Given that the purpose of the blocking opening 17 is to allow the formation of a barrier, it is understood that it will further be used to define trench interruptions (i.e., defining trenches with a tip-to-tip configuration). Accordingly, depositing a barrier material with a thickness at least half that of the CD of the blocking opening 17 allows the barrier layer portions 18 deposited on the respective opposite sidewalls of the blocking opening 17 to merge, thereby closing the blocking opening 17.

[0109] The barrier material can typically be different from each of the underlying material and the (to be deposited) upper material. Barrier materials can be, for example, metal nitrides or metal oxides, such as TiN, TiOx, ZrOx, AlOx, and AlN. Ru represents another example. The barrier material can be deposited, for example, by ALD. To improve the mask budget during subsequent patterning steps, the barrier material can be selected to be a different material from the target memory layer 12.

[0110] exist Figure 5 In this process, the barrier layer has been etched back, causing the barrier material deposited outside the barrier opening 17 to be removed and the barrier material to remain in the barrier opening 17 to form the first upper barrier 19. The etch back can include dry etching, such as using RIE.

[0111] According to one variation, the first upper barrier 19 can be formed by depositing barrier material on the auxiliary barrier mask layer 16 and in the barrier opening 17 (e.g., in a non-conformal manner), and subsequently removing the barrier material deposited outside the barrier opening (e.g., by a top-down anisotropic etch-back (e.g., RIE) or polishing step (e.g., CMP)). Thus, the barrier material can be removed from the upper surface of the auxiliary barrier mask layer 16 but is retained in the barrier opening 17 to form the first upper barrier 19.

[0112] exist Figure 6 In this process, the auxiliary barrier mask layer 16 has been removed. The auxiliary barrier mask layer 16 can be removed by selectively etching it onto the first upper barrier 19. A suitable dry or wet etching process that provides sufficient selectivity can be used.

[0113] exist Figure 7 In the middle, an upper memory layer 20 is formed above the lower memory layer 14 and the first upper barrier 19. Figure 7In the diagram, the upper memory layer 20 is depicted with a flat upper surface. However, it should be noted that due to the presence of the first upper barrier 19, the upper surface of the upper memory layer 20 may exhibit a (slightly) varied morphology. If such a morphological variation is not desirable, the upper surface can be planarized, for example, by CMP, before subsequent process steps.

[0114] The upper memory layer 20 may be, for example, an a-Si layer, deposited by CVD, ALD, or PVD. A non-limiting example of the combination of materials for memory layers 12, 14, 20, and the first upper barrier 19 is: a target memory layer 12 of TiN, a lower memory layer 14 of SiN, an upper memory layer 20 of a-Si, and a first upper barrier 19 of TiN.

[0115] Figure 8-9 The process steps for patterning the upper memory layer 20 to form a set of upper trenches 22 within the upper memory layer 20 are explained. The upper trenches 22 are formed using photolithography and etching. For example... Figure 8 As shown, a (first) auxiliary trench mask stack 170, comprising a mask material 172 and a resist layer 178, is formed on top of the upper memory layer 20. The mask material 172 may be, for example, an organic spin-coating material such as SOC. As shown, the auxiliary trench mask stack 170 may also include additional layers 174, 176, 177 under the resist layer 178, such as one or more anti-reflective coatings, such as SiOC layers and / or spin-coated glass layers.

[0116] The auxiliary trench mask stack 170 is patterned to form auxiliary trenches 179. The auxiliary trenches 179 can first be formed in the resist layer 178 by photolithography, and then transferred to the mask material 172 by etching. Subsequently, while the patterned auxiliary trench mask stack 170 masks the upper memory layer 20, the upper trench 22 can be formed by etching through the auxiliary trenches 179 to the upper memory layer 20. The upper trench 22 can be etched using a suitable etching process, such as dry etching, such as reactive ion etching (RIE). For example, the etching chemicals containing bromine (e.g., HBr), chlorine (e.g., Cl2), or fluorine (e.g., SF6, CF4) can be tuned to achieve selective "a-Si etching," i.e., selective etching of a-Si relative to the auxiliary trench mask stack 170, for example, containing organic spin-coating materials such as SOC.

[0117] Figure 9The diagram illustrates an upper memory layer 20, patterned therein with upper trenches 22, after the removal of the auxiliary trench mask stack 170. For example, removing the auxiliary trench mask stack 170 may include "SOC etching," such as a RIE using oxygen-containing etching chemicals diluted with Ar or He, or N2 / H2-based etching chemicals. As shown, the upper trenches 22 can expose a portion of the upper surface of the lower memory layer 14. Each upper trench 22 is formed above the region of the target memory layer 12 (and insulating layer 10) where a first target trench 96 will be formed (see, for example...). Figure 27 As shown in the figure, the upper groove 22 can be formed to have various widths (along the first horizontal direction X) and various longitudinal dimensions (along the second horizontal direction Y). The upper groove 22 can extend parallel to the second horizontal direction Y.

[0118] As shown, the upper groove 22 may extend across and expose one or more first upper barriers 19. In turn, the first upper barriers 19 are formed along the upper groove 22. Thus, the first upper barriers 19 may define a groove interruption along the upper groove 22.

[0119] exist Figure 10 In this process, sidewall spacer lines 24 have been formed along the sidewalls of the upper trench 22. The spacer lines 24 can be formed from an ALD deposition material such as an oxide (e.g., SiO2) or an AlO2 material during the sidewall spacer deposition process. x or TiO x It is formed by metal oxide layers such as SiCO, SiN, AlN, AlON, and SiCN, or by carbides or nitrides such as SiCO, SiN, AlN, AlON, and SiCN. Figure 10 As shown, the spacer line 24 is conformal to the sidewall of each upper groove 22. In other words, the spacer line 24 can cover and extend along the sidewall of the upper groove 22. Figure 10 As further shown, spacer lines 24 can also be formed on the end walls of the upper groove 22 and the side walls of the first upper barrier 19. Such end wall spacer portions can thus connect the side wall spacer lines 24 formed on the opposing side walls of each respective upper groove 22.

[0120] exist Figure 11 In this configuration, the lower memory layer 14 has been patterned to form a first lower trench 26 therein. Patterning may include etching the lower memory layer 14 while the patterned upper memory layer 20, spacer 24, and first upper barrier 19 conceal the lower memory layer 14. In other words, patterning may include vertically etching back the upper surface portion of the lower memory layer 14 below or exposed within the upper trench 22 (i.e., the upper surface portion not concealed by the first upper barrier 19 or spacer 24). As shown, the lower trench 26 may expose the upper surface portion of the target memory layer 12.

[0121] from Figure 11 As can be seen, below each of the first upper barriers 19, a first lower barrier 28 has been formed by a corresponding first lower memory layer portion 14a, which is masked by the first upper barrier 19 during the etching of the lower memory layer 14. Therefore, the corresponding first lower memory layer portion 14a can be retained below each of the first upper barriers 19. Thus, at least one subset of the first lower trench 26 is interrupted by the corresponding first lower barrier 28.

[0122] Patterning of the lower memory layer 14 may include etching using an etching process (e.g., a dry etching process), thereby allowing the lower memory layer 14 to be etched at a greater rate than the upper memory layer 20, the spacer 24, and the first upper barrier 19. For example, fluorine-based chemicals (e.g., CHF3, CH3F, C4F8, CF4, CH2F2) may be used, optionally employing continuous wave plasma, plasma pulse, or cyclic processes (e.g., quasi-atomic layer etching), via RIE at a greater rate than that used for TiN, a-Si, and silicon or metal oxides (e.g., SiO2 or TiO2). x The rate of etching the SiN layer is achieved by each of the oxides such as ) and others.

[0123] After the lower memory layer 14 is patterned, the first upper barrier 19 and the upper groove 22 with spacer lines are thus "memorized" in the patterned lower memory layer 14.

[0124] The (first) via formation process for patterning (first) via openings aligned with the first set of target trenches 96 in the target memory layer 12 will now be described with reference to Figures 12-15 and 16-18, respectively, and the (second) via formation process for patterning (second) via openings aligned with the second set of target trenches 98 in the target memory layer 12. If the formation of the first and / or second via openings is not required, the relevant steps can be omitted. The method can then proceed to... Figure 19 .

[0125] Figure 12b The structure along Figure 12a The cross-section of line A-A' shown is illustrated. A (first) via-hole etch stack 44 has been formed on this structure. The via-hole etch stack 44 may include a mask material 46 filling the upper trench 22 and the first lower trench 26. The mask material 46 may form a planarization layer covering the patterned upper memory layer 20. The mask material 46 may be a SOC or other organic spin-coated layer. The via-hole etch stack 44 may also include a resist layer 48 formed on the mask material 46. Although not shown, the via-hole etch stack 44 may include additional mask material, such as one or more anti-reflective coatings (such as SiOC layers) and / or spin-coated glass layers, between the SOC layer and the resist layer 48.

[0126] An opening 50 has been formed in the via etch stack 44 by photolithography and etching. This opening is formed at a location above the "selected" first lower trench 26, below which a via opening is required. The opening 50 may extend through the via etch stack 44 to expose the bottom surface 12a of the selected first lower trench 26, which is formed, for example, by a portion of the upper surface of the target memory layer 12.

[0127] Etching the mask material 46 using an etching process adapted to etch it at a greater rate than that of the spacer 24 allows the opening 50 to self-align with respect to the spacer 24. The opening 50 can also self-align with respect to a selected first lower trench 26 by extension. Thus, a loose CD opening 50 can be defined in the resist layer 48 by photolithography and transferred into the mask material 46. During the etching of the mask material 46, the opening 50 can thus expose portions 24a of the spacer layer on opposite sides of the selected first lower trench 26. For example, as described above, organic spin-coating materials (such as SOC) can be etched at a greater rate than oxide spacers etched using SOC. After the opening 50 is formed, the resist layer 48 can be removed. Figure 12a , 12b An opening 50 is shown; however, it will be clear that any number of openings 50 can be formed depending on the desired number of through-hole openings.

[0128] exist Figure 13 In this process, the exposed bottom surface 12a has been etched back to form an opening 52 in the target memory layer 12. For example... Figure 14 As further shown, opening 52 can also be transferred to insulating layer 10 and any interface layer 11 (if present) by etching layer 10 / 11 through opening 52 in target memory layer 12. The depth of opening 52 in layer 10 / 11 may be only the initial depth at this stage and deepened in later stages, such as during the etching of trenches in insulating layer 10. Figure 15 The structure after removing the through-hole etch stack 44 is shown.

[0129] Figure 16b The structure along Figure 16a The cross-section of line B-B' is shown. A (second) via-hole etch stack 56 has been formed on this structure. The via-hole etch stack 56 may include a mask material 58 filling the upper trench 22 and the first lower trench 26. The mask material 58 may form a planarization layer covering the patterned upper memory layer 20. The mask material 58 may be a SOC or other organic spin-coating material. The via-hole etch stack 56 may further include a resist layer 60. Similar to the discussion of the via-hole etch stack 44, additional mask material (e.g., an anti-reflective coating) may be present in the via-hole etch stack 44.

[0130] An opening 62 has been formed in the via etch stack 56 by photolithography and etching. Reference will now be made to the opening 62 through which this cross-section extends. However, the following description applies accordingly to any other opening 62. The opening 62 is formed on the remaining portion of the patterned memory layer 12 (where the second lower trench is to be formed) at the location below which the via is required. The remaining portion of the patterned memory layer 12 may be located between a pair of upper trenches 22, as shown. The opening 62 may extend through the via etch stack 56 to expose the upper surface 20a of the remaining portion of the patterned memory layer 20. To maintain mask budget, etching of the mask material 58 can be stopped when the upper surface 20a is exposed.

[0131] exist Figure 17 In the patterned upper memory layer 20, the exposed upper surface 20a of the remaining portion has been etched back to form an opening 64 in the patterned upper memory layer 20. Therefore, the opening 64 can expose the upper surface portion 14c of the lower memory layer 14. The patterned upper memory layer 20 is etched using an etching process adapted to etch the patterned upper memory layer 20 at a greater rate than the mask material 58 and the spacers 24 (i.e., the spacers 24 of the spacer material), allowing the opening 64 to self-align relative to the spacers 24. Therefore, a loose CD opening 62 can be defined in the resist layer 60 by photolithography and transferred to the mask material 58. By extending, and as... Figure 17 As shown, the width of the opening 62 in the via etch stack 56 can exceed the spacing between a pair of upper trenches 22 on either side of the remaining portion of the patterned upper memory layer 20.

[0132] exist Figure 18 In this process, the patterned lower memory layer 14 and the target memory layer 12 have been sequentially etched back through the opening 64 in the patterned upper memory layer 20. This creates an extended opening that extends through the memory layers 14 and 12. As described above, if the opening 62 in the via etch stack 56 forms a loose CD opening, the etch back of the upper surface portion of the mask material 58 and the portion of the spacer layer 24 can also occur during the etching of the opening 64.

[0133] The bottom surface of the extended opening may be formed from a portion of the upper surface of the insulating layer 10 or the interface layer 11 (if present). Therefore, the extended opening has not yet been transferred to the lower layer to form the through-hole opening 67 (see...). Figure 28However, this can occur during subsequent patterning steps, such as during the patterning of the second lower trench 88 described below and / or during the etching of the trenches in the insulating layer 10. However, at this stage, at least an initial via opening 67 can also be etched in the insulating layer 10 (and / or any interface layer 11) for deepening in later stages, such as during the etching of the trenches in the insulating layer 10. The initial via opening 67 can be etched in layers 10 / 11 to the point where it intersects with the surface. Figure 14 The initial through-hole opening 52 shown has the same horizontal / depth. Figure 19 The structure after removing the through-hole etch stack 56 is shown.

[0134] Figure 20-22 The patterning of the (already) patterned upper memory layer 20 to form the second upper barrier 74 has been explained. These process steps can be performed after the above-mentioned through-hole opening patterning.

[0135] The second upper barrier 74 is formed using photolithography and etching. For example... Figure 20 As shown, an auxiliary barrier mask stack 66 is formed on the patterned upper memory layer 20, comprising a mask material 68 and a resist layer 70 forming a resist barrier. The mask material 68 may fill the upper trench 22 and the first lower trench 26. The mask material 68 may form a planarization layer covering the patterned upper memory layer 20. The mask material 68 may be a SOC or other organic spin coating. Similar to the discussion of via etch stacks 44 and 56, additional mask material (e.g., an anti-reflective coating) may be present in the auxiliary barrier mask stack 66.

[0136] By photolithographically patterning the resist block 70 in the resist layer and subsequently etching the mask material 68 while the resist block 70 masks the mask material 68, the auxiliary barrier mask stack 66 can be patterned to form a second mask block 72, such as... Figure 21 As shown. During the patterning of the auxiliary barrier mask stack 66, the mask material 68 can be etched back until the upper surface of the patterned upper memory layer 20 is exposed. Accordingly, the mask material 68 can be retained in the upper trench 22 and the first lower trench 26.

[0137] exist Figure 22In this process, while the patterned upper memory layer 20 is masked by the second mask barrier 72, the patterned upper memory layer 20 is etched. Therefore, the second upper barrier 74 can be formed from the remaining portions 20b of the patterned upper memory layer 20. The patterned upper memory layer 20 is etched using an etching process adapted to etch the upper memory layer 20 at a greater rate than the mask material 68, and the mask material 68 can also fill the trenches 22, 26 after the upper barrier 74 is formed. Correspondingly, the second mask barrier 72 can remain on the upper barrier 74. For example, the patterning of the patterned upper memory layer 20 can include using "a-Si etching," as described above.

[0138] After the second upper barrier 74 is formed, any remaining mask material 68 can be removed, for example, by using SOC etching.

[0139] Figure 23-26 The patterning of the (already) patterned upper memory layer 14 is explained to form the second lower trench 88 therein.

[0140] The second lower trench 88 is formed by photolithography and etching. For example... Figure 23 As shown, a (second) auxiliary trench mask stack 80, comprising a mask material 82 and a resist layer 84 above the mask material 82, is formed on a patterned lower memory layer 14. The mask material 82 may fill the first lower trench 26. The mask material 82 may further cover the second upper barrier 74. The mask material 82 may form a planarization layer. The mask material 82 may be a SOC or other organic spin-coating material. Similar to the discussion of the auxiliary trench mask stack 22, additional mask material (e.g., an anti-reflective coating 81) may be present in the auxiliary barrier mask stack 80.

[0141] The auxiliary trench mask stack 80 can be patterned to form auxiliary trenches by photolithographically patterning auxiliary trenches 86 in the resist layer 84, such as... Figure 23 As shown, and subsequently transferred to the mask material 82 by etching through the auxiliary trench 86 in the resist layer 84, as... Figure 24 As shown. During the patterning of the auxiliary trench mask stack 80, the mask material 82 may be etched back at least until the upper surface 14b of the patterned lower memory layer 14 is exposed, or further until the upper surface of the target memory layer 12 is exposed. The auxiliary trench 86 may be exposed and extend through the second upper barrier 74.

[0142] exist Figure 25In this process, while the patterned lower memory layer 14 is masked by the patterned auxiliary trench mask stack 80, the second upper barrier 74, and the spacer 24, the patterned lower memory layer 14 is etched to form the second lower trench 88. In other words, patterning may include back etching of the upper surface portion 14b of the patterned lower memory layer 14 exposed in the auxiliary trench 86 (i.e., not masked by the second upper barrier 74 and the spacer 77).

[0143] At each location in the patterned lower memory layer 14 below the second upper barrier 74, a corresponding second lower barrier 90 has been formed by the corresponding second lower memory layer portion 14c that was masked during etching. Therefore, at least one subset of the second lower trench 88 is interrupted by the corresponding second lower barrier 90.

[0144] Patterning of the patterned lower memory layer 14 may include selective etching of the patterned lower memory layer 14 (i.e., using an etching process adapted to etch the patterned lower memory layer 14 at a greater rate than the second upper barrier 74, spacer 24 and first upper barrier 19).

[0145] Figure 23-25 Reference numerals 86a-c and 86d-e in the accompanying drawings denote loose CD auxiliary trenches that extend / overlap not only over the remainder of the lower memory layer 14 in which the second lower trench 88 will be formed, but also over one or more first lower trenches 22. The auxiliary trench 86 may also extend accordingly over the first upper stop 19 and the first lower stop 28, as... Figure 25 As shown in the enlarged illustration, along the auxiliary trenches 86d, 86e. Due to the presence of the first upper barrier 19, each of the first lower barriers 28 exposed in the auxiliary trenches 86 can be accordingly masked during the selective etching of the patterned lower memory layer 14, and thus retained after the formation of the second lower trench 88 is completed. Furthermore, the spacer line 24 allows for ensuring a minimum spacing between the first and second lower trenches 26, 88.

[0146] exist Figure 26 In this configuration, the patterned auxiliary trench mask stack 80 has been removed from the structure (e.g., using SOC etching), thereby exposing the (twice) patterned lower memory layer 14, in which first and second lower trenches 26, 88 are formed. The second lower trenches 88 may be arranged alternately with the first lower trenches 26. As further shown, one or more second lower trenches 88 may be separated from adjacent first trenches 26 only by a lower line formed by a (wall-like) portion 14d of the patterned lower memory layer 14 retained beneath the spacer layer portion 24b. The linewidth of this lower line 14d matches or at least corresponds to the linewidth of the spacer line portion 24b.

[0147] exist Figure 27 In this process, the target memory layer 12 has been patterned to form a first set of "target" trenches 96 below the first lower trench 26, and a second set of "target" trenches 98 below the second lower trench 88. The patterning of the target memory layer 12 may include etching the target memory layer 12 while it is being masked by the (double-patterned) lower memory layer 14. In other words, the first set of trenches 96 can be formed by etching back the target memory layer 12 through the first lower trench 26, and the second set of trenches 98 can be formed by etching back the target memory layer 12 through the second lower trench 98. The bottom surfaces of the trenches 96 and 98 may be formed from the interface layer 11 or the upper surface of the insulating layer 10.

[0148] Below each first lower barrier 28, a first target barrier 93 has been formed by a corresponding first target memory layer portion 12a that was concealed by the first lower barrier 28 during the etching of the target memory layer 12. Therefore, the corresponding first lower memory layer portion 12a can remain below each first upper barrier 28. Accordingly, at least a subset of the first target trench 96 is interrupted by the corresponding first target barrier 93.

[0149] Below each second lower barrier 90, a second target barrier 94 has been formed by the corresponding second target memory layer portion 12b that was masked by the second lower barrier 90 during the etching of the target memory layer 12. Therefore, the corresponding second lower memory layer portion 12b can remain below each second lower barrier 90. Accordingly, at least a subset of the second target trench 98 is interrupted by the corresponding second target barrier 94.

[0150] As shown in the figure, the second target trench 98 can be separated from the adjacent first target trench 96 (only) by the lower line 97 formed by the third target memory layer portion 12c, which is masked by the corresponding lower line 14d during etching.

[0151] exist Figure 27 In this process, the target memory layer 12 is also masked by the upper obstruction 74 and the spacer 32. This can provide an increased mask budget during the patterning of the target memory layer 12. However, it is possible that one or more of these components have been removed before the patterning of the target memory layer 12.

[0152] After patterning the target memory layer 12, the first and second upper blocks 19, 74 and the spacer line 24 can be removed from the patterned target memory layer 12. Figure 28 The resulting structure is shown in the figure.

[0153] While the target memory layer 12 is (at least) patterned, masking layers 10 / 11 are simultaneously etched into the insulating layer 10 and interface layer 11, thereby forming a first insulating layer trench 100 below the first set of target trenches 96 and a second insulating layer trench 102 below the second set of target trenches 98. Thus, the trench pattern defined in the target memory layer 12 has been transferred to the insulating layer 10, including any discontinuous trenches. Etching of the trenches in the insulating layer can simultaneously create the final deepened via openings 52, 67, similar to a dual damascene process.

[0154] Although not shown, the patterned lower memory layer 14 may be removed before the trenches 100, 102 are formed. It is also possible to remove one or more of the first and second upper barriers 19, 74 and spacer 24 only after the trenches 100, 102 are formed.

[0155] As further illustrated, the trenches and via openings in the insulating layer 10 can be filled with a conductive material 104. However, as will be understood, the conductive material 104 may be deposited first after the target memory layer 12 (and the underlying memory layer 14) has been removed. The conductive material 104 may be one or more metals conventionally used to form metal lines and vias in BEOL processes, such as, for example, W, Cu, Al, Ru.

[0156] In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

[0157] For example, the method can continue to deposit another insulating layer on top of insulating layer 10 and the metal wires and vias therein. The above method steps can then be repeated to form higher interconnect layers. This can be repeated until the desired number of interconnect layers are formed.

[0158] According to another example, the step of removing the auxiliary blocking mask layer 16 (and optional liner 16') before forming the upper memory layer 20 can be omitted. Figure 5 Following the stage shown, the method can continue to form an upper memory layer 20 over the patterned auxiliary barrier mask layer 16 (and optional liner 16') and the first upper barrier 19. Therefore, in subsequent steps, the patterned auxiliary mask layer 16 can exist as an intermediate layer between the upper memory layer 20 and the lower memory layer 14. If the auxiliary barrier mask layer 16 is formed of a material different from the upper memory layer 20, then by referring to the upper memory layer 20 as a reference to the double stack of the patterned auxiliary barrier mask layer and the upper memory layer 20, the combination can be understood accordingly. Figure 7The process step 16 is described in the following figures. For example, trench 22 can be etched to extend through the double stack, and the second upper barrier 74 can be formed as a double barrier. As will be understood, depending on the material of the auxiliary barrier mask layer 16, the patterning of the upper trench 22 and the second upper barrier 74 may include switching from a first etch chemical (for etching the upper memory layer 20) to a second etch chemical (for etching the auxiliary barrier mask layer 16). However, if the auxiliary barrier mask layer 16 is formed of the same material as the upper memory layer 20 (e.g., a-Si), the process steps can be derived from the above. Figure 7 And in the manner shown and described in the accompanying figures.

[0159] Furthermore, in the above process flow, the first set of trenches 96 and the second set of trenches 98 are patterned simultaneously in the target memory layer 12. However, a sequential approach is also possible, wherein the first set of trenches 96 is patterned in the target memory layer 12 before the second set of trenches 98 is patterned in the target memory layer 12. According to the sequential approach, the first set of trenches 96 may be formed, for example, after the formation of the first lower trench 26 and before the formation of the patterned upper memory layer 20 to form the second upper barrier 74. The second set of trenches 98 may be formed after the formation of the second lower trench 88 in the patterned lower memory layer 14. If a via is to be formed during the first and / or second via formation process as described above, the first set of trenches 96 may be formed in the target memory layer 12, for example, before the via formation process.

Claims

1. A patterning method, comprising: A lower memory layer (14) is formed on top of the bottom layer (12) and an auxiliary blocking mask layer (16) is formed on top of the lower memory layer (14), and a blocking opening (17) is formed in the auxiliary blocking mask layer (16). A first upper barrier (19) is formed in the blocking opening (17); An upper memory layer (20) is formed on the lower memory layer (14) and the first upper barrier (19). The upper memory layer (20) is patterned using photolithography and etching to form upper trenches (22) in the upper memory layer (20), wherein at least a subset of the upper trenches (22) is interrupted by a corresponding first upper block (19); A sidewall spacer line (24) is formed along the sidewall of the upper groove (22). The lower memory layer (14) is patterned to form a first lower trench (26) in the lower memory layer (14). The patterning includes etching while the patterned upper memory layer (20), the sidewall spacer (24) and the first upper barrier (19) cover the lower memory layer (14). At least one subset of the first lower trench (26) is interrupted by a corresponding first lower barrier (28), which is formed by a corresponding portion (14a) of the first lower memory layer that is covered by the corresponding first upper barrier (19). The patterned upper memory layer (20) is patterned using photolithography and etching to form a second upper barrier (74) from the remaining upper memory layer portion (20b), and Patterning the patterned lower memory layer (14) to form a second lower trench (88) in the patterned lower memory layer (14), the patterning including: An auxiliary trench mask stack (80) is formed on the lower memory layer (14), and auxiliary trenches (86) are patterned therein by photolithography and etching. While the patterned lower memory layer (14) is masked by the patterned auxiliary trench mask stack (80), the sidewall spacer (24) and the second upper barrier (74) and the first upper barrier (19) masking the first lower barrier (28), the patterned lower memory layer (14) is etched, wherein at least a subset of the second lower trench (88) is interrupted by a corresponding second lower barrier (90), the corresponding second lower barrier (90) being formed by a corresponding second lower memory layer portion (14c) masked by the corresponding second upper barrier (74); The method further includes patterning a first set of grooves (96) below the first lower groove (26) and a second set of grooves (98) below the second lower groove (88) in the bottom layer (12).

2. The method as described in claim 1, characterized in that, Forming the first upper barrier (19) includes depositing a barrier material on the auxiliary barrier mask layer (16) and in the barrier opening (17), and removing the barrier material deposited outside the barrier opening (17) so that the barrier material remains in the barrier opening (17) to form the first upper barrier (19).

3. The method as described in any of the preceding claims, characterized in that, Forming the first upper barrier (19) includes: A conformal barrier layer of barrier material is formed on the auxiliary barrier mask layer (16) and is aligned with the sidewall of the barrier opening (17), wherein the barrier material deposited on the sidewall merges into the barrier opening (17), and The conformal barrier layer is etched back, such that the barrier material deposited outside the barrier opening (17) is removed and the barrier material remains in the barrier opening (17) to form the first upper barrier (19).

4. The method as described in claim 1 or 2, characterized in that, Forming the blocking opening (17) involves first patterning an initial blocking opening (17') in the auxiliary blocking mask layer (16) using photolithography and etching, and then forming a final blocking opening (17) by forming a liner (16') that is consistent with the sidewall of the initial blocking opening (17').

5. The method as described in claim 1, characterized in that, Also includes: After the first lower trench (26) is formed, an auxiliary barrier mask stack (66) is formed, the auxiliary barrier mask stack (66) including a mask material (68) filling the upper trench (22) and the first lower trench (26) and also including a resist layer (70). The patterning of the patterned upper memory layer (20) includes first patterning the auxiliary barrier mask stack (66) using photolithography and etching to form an auxiliary barrier (72), and then patterning the patterned upper memory layer (20) to form a second upper barrier (74), the patterning including etching while the auxiliary barrier (72) masks the patterned upper memory layer (20).

6. The method as described in claim 1, characterized in that, The auxiliary trench mask stack (80) includes a mask material (82) forming a planarization layer covering the second upper barrier (74), the sidewall spacer (24) and the patterned lower memory layer (14), and also includes a resist layer (84).

7. The method according to any one of claims 5-6, characterized in that, At least one auxiliary groove (86) extends above the first lower groove (26) and above the first upper barrier (19) located on the first lower barrier (28) in the first lower groove (26).

8. The method as described in claim 6, characterized in that, The mask material (68, 82) includes an organic spin coating.

9. The method as described in claim 1 or 2, characterized in that, At least one subset of the second lower trench (88) is arranged alternately with at least one subset of the first lower trench (26).

10. The method as described in claim 9, characterized in that, Each groove in at least one subset of the second lower groove (88) is separated from the adjacent groove in at least one subset of the first lower groove (26) by a corresponding lower line (97) formed by the wall-like portion (14d) of the patterned lower memory layer (14) retained below the spacer layer portion (24b).

11. A method for forming an interconnect structure, comprising: A target memory layer (12) is formed on top of the insulating layer (10); A first set of trenches and a second set of trenches are formed in the target memory layer according to the method described in any one of the preceding claims, wherein the bottom layer (12) is the target memory layer; After forming the first set of trenches and the second set of trenches in the target memory layer, the trenches are etched in the insulating layer (10) while the patterned layer masks the insulating layer (10); as well as Conductive material (104) is deposited in the trenches in the insulating layer (10).

12. The method as described in claim 11, characterized in that, Also includes: Prior to the patterning of the patterned upper memory layer (20): A second through-hole etch stack (56) is formed, the second through-hole etch stack (56) includes a mask material (58) filling the upper trench (22) and the first lower trench (26) and further includes a resist layer (60). An opening (62) is formed in the second through-hole etch stack (56), the opening (62) exposing the upper surface (20a) of the remaining portion of the upper memory layer (20). The exposed upper surface (20a) of the upper memory layer (20) is etched back to form an opening (64) in the upper memory layer, and The lower memory layer and the target memory layer (14, 12) are sequentially etched back through the opening (64) in the upper memory layer (20) to form an extended opening therethrough; The method also includes etching the insulating layer (10) through the extended opening.

13. The method as described in claim 12, characterized in that, The exposed upper surface (20a) of the upper memory layer is etched back at a rate greater than that of the mask material (58) and / or greater than that of the sidewall spacer line (24) to etch the upper memory layer.

14. The method according to any one of claims 12-13, characterized in that, The exposed upper surface (20a) of the upper memory layer (20) is located between a pair of upper trenches (22), and the width of the opening in the second via etch stack (56) exceeds the spacing between the pair of upper trenches (22).

15. The method as described in claim 11, characterized in that, Also includes: Prior to the patterning of the patterned upper memory layer (20): A first through-hole etch stack (44) is formed, the first through-hole etch stack (44) includes a mask material (46) filling the first lower trench (26) and upper trench (22) and further includes a resist layer (48). An opening (50) is formed in the first through-hole etch stack (44), the opening exposing the bottom surface (12a) of the selected first lower trench (26), and the opening (50) exposing the spacer layer portions (24a) on the opposite sides of the selected first lower trench (26). The exposed bottom surface (12a) is etched back to form an opening (52) in the target memory layer (12); The method also includes etching the insulating layer (10) through an opening (52) in the target memory layer (12).

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