Semiconductor device structure and method for manufacturing the same

Abstract

This disclosure describes a semiconductor device structure. The structure includes a first fin, a second fin adjacent to the first fin, and a third fin adjacent to the second fin. The structure further includes a combined second source / drain epitaxial feature and a first source / drain epitaxial feature. The structure also includes a third source / drain epitaxial feature and a liner layer, the liner layer being at a first distance from a first plane defined by a first sidewall of the first fin and at a second distance from a second plane defined by a second sidewall of the second fin. The first distance and the second distance are substantially the same, and the combined first source / drain epitaxial feature and the second source / drain epitaxial feature are disposed on the first liner layer. The structure further includes a dielectric feature disposed between the second source / drain epitaxial feature and the third source / drain epitaxial feature.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor device structure and a method for manufacturing the same, and more particularly to a semiconductor device structure and a method for manufacturing the same that include a dielectric structure to control the merging of epitaxial structures. Background Art

[0002] The growth of semiconductor integrated circuits (ICs) has been very rapid. The progress of integrated circuit materials and design has made each generation of circuit sizes smaller and more complex. During the progress of integrated circuits, when the geometric size (e.g., the smallest element or line that can be produced by the process) becomes smaller, the functional density (e.g., the number of devices contacted per wafer area) usually increases. This miniaturization process generally brings advantages such as increased production efficiency and reduced related costs, and also increases the difficulty of manufacturing integrated circuits.

[0003] Therefore, there is no need to further optimize the integrated circuit manufacturing process. Summary of the Invention

[0004] Some embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first fin, a second fin, a third fin, a first source / drain epitaxial feature, a second source / drain epitaxial feature, a third source / drain epitaxial feature, a first liner, and a dielectric feature. The first fin extends from a substrate. The first fin includes a first substrate portion having a first sidewall. The second fin extends from the substrate adjacent to the first fin. The second fin includes a second substrate portion having a second sidewall that faces the first sidewall. The third fin extends from the substrate adjacent to the second fin. The third fin includes a third substrate portion. The first source / drain epitaxial feature extends from the first substrate portion. The second source / drain epitaxial feature extends from the second substrate portion. The first source / drain epitaxial feature and the second source / drain epitaxial feature merge together. The third source / drain epitaxial feature extends from the third substrate portion. The first liner is at a first distance from a first plane defined by the first sidewall and at a second distance from a second plane defined by the second sidewall. The first distance and the second distance are substantially the same, and the merged first source / drain epitaxial feature and second source / drain epitaxial feature are disposed on the first liner. The dielectric feature is disposed between the second source / drain epitaxial feature and the third source / drain epitaxial feature.

[0005] Some embodiments of the present disclosure are a semiconductor device structure. The semiconductor device structure includes a first fin, a second fin, a third fin, a first source / drain epitaxial feature, a second source / drain epitaxial feature, a third source / drain epitaxial feature, a first liner layer, and a dielectric feature. The first fin extends from a substrate, wherein the first fin includes a first substrate portion and a plurality of first semiconductor layers disposed on the first substrate portion. The second fin extends from the substrate adjacent to the first fin, wherein the second fin includes a second substrate portion and a plurality of second semiconductor layers disposed on the second substrate portion. The third fin extends from the substrate adjacent to the second fin, wherein the third fin includes a third substrate portion and a plurality of third semiconductor layers disposed on the third substrate portion. The first source / drain epitaxial feature extends from the first substrate portion. The second source / drain epitaxial feature extends from the second substrate portion, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged together. The third source / drain epitaxial feature extends from the third substrate portion. The first liner layer includes a first portion disposed between the first semiconductor layer and the second semiconductor layer, wherein the first portion of the first liner layer has a first width. The dielectric feature is disposed between the second semiconductor layer and the third semiconductor layer, wherein the dielectric feature has a second width greater than the first width.

[0006] Some embodiments of the present disclosure are a method of manufacturing a semiconductor device structure, including forming a first fin, a second fin, and a third fin from a substrate, forming a liner layer, wherein a first portion of the liner layer is formed between the first fin and the second fin, and a second portion of the liner layer is formed between the second fin and the third fin, forming a low-k material on the second portion of the liner layer between the second fin and the third fin, forming a high-k material on the second portion of the liner layer and the low-k material, and the high-k material contacts the second portion of the liner layer and the low-k material, forming a sacrificial gate stack on the first portions of the first fin, the second fin, and the third fin and a third portion of the liner layer, wherein the second portions of the first fin, the second fin, and the third fin and a fourth portion of the first liner layer are exposed, removing a portion of the exposed second portions of the first fin, the second fin, and the third fin, recessing the exposed fourth portion of the liner layer, and forming a first source / drain epitaxial feature from the first fin and a second source / drain epitaxial feature from the second fin, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged and disposed on the fourth portion of the first liner layer.

[0007] Some embodiments of the present disclosure are a method of fabricating a semiconductor device structure, comprising forming a first fin, a second fin, and a third fin from a substrate, filling a first trench between the first fin and the second fin with a first liner layer, depositing a second liner layer between the second fin and the third fin, wherein the first liner layer and the second liner layer are deposited simultaneously, depositing a low-k dielectric material on the second liner layer between the second fin and the third fin, depositing a high-k dielectric material on the second liner layer and the low-k dielectric material, and the high-k dielectric material contacts the second liner layer and the low-k dielectric material, wherein the second liner layer, the low-k dielectric material, and the high-k dielectric material fill a second trench between the second fin and the third fin, removing a portion of the first fin, the second fin, and the third fin, recessing a first portion of the first liner layer, recessing a first portion of the high-k dielectric material, and forming a first source / drain epitaxial feature, a second source / drain epitaxial feature, and a third source / drain epitaxial feature, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged and disposed on the first portion of the first liner layer, and the second source / drain epitaxial feature and the third source / drain epitaxial feature are separated by the second liner layer, the low-k dielectric material, and the high-k dielectric material.

[0008] Some embodiments of the present disclosure are a method of fabricating a semiconductor device structure, comprising forming a first fin, a second fin, and a third fin from a substrate, depositing a first liner layer between the first fin and the second fin, forming a dielectric feature between the second fin and the third fin, forming a sacrificial gate stack on a first portion of the first fin, the second fin, the third fin, a first portion of the first liner layer, and a first portion of the dielectric feature, wherein a second portion of the first fin, the second fin, the third fin, a second portion of the first liner layer, and a second portion of the dielectric feature are exposed, removing the second portion of the first fin, the second fin, and the third fin, recessing the second portion of the first liner layer to a first height, recessing the second portion of the dielectric feature to a second height, removing the sacrificial gate stack, and recessing a portion of the first portion of the dielectric feature to a third height, wherein a remaining portion of the first portion has a fourth height greater than the second height, and the second height is greater than the third height.

[0009] Some embodiments of the present disclosure are methods of fabricating a semiconductor device structure, including forming a first fin, a second fin, and a third fin from a substrate, forming a liner layer, wherein a first portion of the liner layer is formed between the first fin and the second fin, and a second portion of the liner layer is formed between the second fin and the third fin, forming a low-k dielectric material on the second portion of the liner layer between the second fin and the third fin, forming a high-k dielectric material on the second portion of the liner layer and the low-k dielectric material, and the high-k dielectric material contacts the second portion of the liner layer and the low-k dielectric material, forming a sacrificial gate stack on the first portion of the first fin, the second fin, the third fin, and the third portion of the liner layer, wherein the second portions of the first fin, the second fin, and the third fin and the fourth portion of the first liner layer are exposed, removing a portion of the exposed second portions of the first fin, the second fin, and the third fin, removing the exposed fourth portion of the liner layer, and forming a first source / drain epitaxial feature from the first fin and a second source / drain epitaxial feature from the second fin, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0011] Figures 1 to 5 is a perspective view of one manufacturing stage of a semiconductor device structure in accordance with some embodiments of the present disclosure;

[0012] Figures 6 to 15 is a cross-sectional view along line A-A in various manufacturing stages of a semiconductor device structure in accordance with some embodiments of the present disclosure Figure 5 in. Figures 16A to 20A is a cross-sectional view along line A-A in various manufacturing stages of a semiconductor device structure in accordance with some embodiments of the present disclosure; Figure 5 in.

[0013] Figures 16B to 20B is a cross-sectional view along line B-B in various manufacturing stages of a semiconductor device structure in accordance with some embodiments of the present disclosure; Figure 15 in.

[0014] Figures 16C to 20C is a cross-sectional view along line C-C in various manufacturing stages of a semiconductor device structure in accordance with some embodiments of the present disclosure; Figure 15 in.

[0015] Figures 16D to 20D is a cross-sectional view along line D-D in various manufacturing stages of a semiconductor device structure in accordance with some embodiments of the present disclosure; Figure 15 in.

[0016] Figures 21A to 26A are perspective views of various manufacturing stages of a semiconductor device structure according to some embodiments of the present disclosure;

[0017] Figures 21B to 26B are cross-sectional views along line B-B in various manufacturing stages of a semiconductor device structure according to some embodiments of the present disclosure; Figure 21A in;

[0018] Figures 21C to 26C are cross-sectional views along line C-C in various manufacturing stages of a semiconductor device structure according to some embodiments of the present disclosure; Figure 21A in;

[0019] Figures 27A to 27B are perspective views of a semiconductor device structure in the manufacturing stage according to some embodiments of the present disclosure; Figure 26A of; Figures 28A to 28B is a cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure; Figures 29A to 29B is a cross-sectional view of a semiconductor device structure according to some embodiments of the present disclosure; Figure 30 is a top view of a semiconductor device structure according to some embodiments of the present disclosure.

[0020]

Symbol Description

[0021] 100: Semiconductor device structure

[0022] 101: Substrate

[0023] 102a: Substrate portion

[0024] 102b: Substrate portion

[0025] 102c: Substrate portion

[0026] 102d: Substrate portion

[0027] 102e: Substrate portion

[0028] 102f: Substrate portion

[0029] 104: Semiconductor layer stack

[0030] 106: First semiconductor layer

[0031] 108: Second semiconductor layer

[0032] 110: Mask layer

[0033] 112: Oxygen-containing layer

[0034] 114: Nitrogen-containing layer

[0035] 202a: Fin

[0036] 202b: Fin

[0037] 202c: Fin

[0038] 202d: Fin

[0039] 202e: Fin

[0040] 202f: Fin

[0041] 204: Groove

[0042] 302: Optional liner layer

[0043] 304: Liner layer

[0044] 402: Insulating material

[0045] 502: Groove

[0046] 504: Top surface

[0047] 602: Cladding layer

[0048] 604: Groove

[0049] 606: Groove

[0050] 702: Liner layer

[0051] 802: Low dielectric constant material

[0052] 1002: Groove

[0053] 1004: Groove

[0054] 1006: Top surface

[0055] 1102: High dielectric constant material

[0056] 1102a: High dielectric constant material

[0057] 1102b: High dielectric constant material

[0058] 1302: Dielectric feature

[0059] 1502: Sacrificial gate dielectric layer

[0060] 1504: Sacrificial gate electrode layer

[0061] 1506: Mask structure

[0062] 1508: Oxygen-containing layer

[0063] 1510: Nitrogen-containing layer

[0064] 1512: Sacrificial gate stack

[0065] 1703: First part

[0066] 1704: Second part

[0067] 1706: First part

[0068] 1706a: First part

[0069] 1706b: First part

[0070] 1708: Second part

[0071] 1708a: Second part

[0072] 1708b: Second part

[0073] 1802: Gap

[0074] 1902: Dielectric spacer

[0075] 2002: Source / drain epitaxial feature

[0076] 2008a: Sidewall

[0077] 2008b: Sidewall

[0078] 2010: Gap

[0079] 2102: Contact etch stop layer

[0080] 2104: Interlayer dielectric layer

[0081] 2106: Nitrogen-containing layer

[0082] 2302: Mask layer

[0083] 2602: Opening

[0084] 2802: Gate electrode layer

[0085] 2802a: First gate electrode layer

[0086] 2802b: Second gate electrode layer

[0087] 2802c: Third gate electrode layer

[0088] 2805: High-k dielectric layer

[0089] 2806: Dielectric material

[0090] 2808: Conductor feature

[0091] 2810: Top surface

[0092] 2902: Conductor Feature

[0093] A - A: Line

[0094] B - B: Line

[0095] C - C: Line

[0096] D - D: Line

[0097] D1: Distance

[0098] D2: Distance

[0099] D3: Distance

[0100] D4: Distance

[0101] H1: Height

[0102] H2: Height

[0103] H3: Height

[0104] H4: Height

[0105] W1: Width

[0106] W2: Width

[0107] W3: Width

[0108] W4: Width

[0109] X: Axis

[0110] Y: Axis

[0111] Z: Axis Detailed Implementation Manner

[0112] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0113] Additionally, for ease of description, in this document, spatial relative terms (such as "below", "beneath", "lower", "above", "upper", and the like) may be used to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0114] Figures 1 to 30 Illustrates an exemplary continuous process for fabricating the semiconductor device structure 100 in some embodiments. It can be understood that in other embodiments of this method, other operations may be provided before, during, and after the Figures 1 to 30 process, and some of the operations mentioned below may also be replaced or deleted. The order of operations and processes is interchangeable.

[0115] As Figure 1 shown, a semiconductor layer stack 104 is formed on the substrate 101. The substrate 101 may be a semiconductor substrate. In some embodiments, the substrate 101 comprises single-crystalline semiconductor material at least on the surface. The substrate 101 may comprise single-crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In this embodiment, the substrate 101 is made of silicon. In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) structure comprising an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide layer.

[0116] The substrate 101 may comprise one or more buffer layers (not shown) on the surface of the substrate 101. The function of the buffer layer is to gradually change the lattice constant of the substrate 101 to the source / drain regions grown on the substrate 101. The buffer layer may be an epitaxially grown single-crystalline semiconductor material, such as silicon, germanium, germanium tin (GeSn), silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimonide phosphide, gallium arsenide antimonide, gallium nitride (GaN), and indium phosphide. In one embodiment, the substrate 101 comprises a silicon germanium buffer layer epitaxially grown on the silicon substrate 101. The germanium concentration of the silicon germanium buffer layer may increase from 30% germanium atomic percentage of the bottommost buffer layer to 70% germanium atomic percentage of the topmost buffer layer.

[0117] The substrate 101 may include regions doped with appropriate impurities (e.g., p-type or n-type impurities). For example, the dopant of an n-type fin field effect transistor (FinFET) may be boron (B), and the dopant of a p-type fin field effect transistor may be phosphorus (P).

[0118] The semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 is made of silicon, and the second semiconductor layer 108 is made of silicon germanium. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 or a portion thereof may form one or more nanosheets channels of the semiconductor device structure 100. The semiconductor device structure 100 may include nanosheet transistors. The term "nanosheet" is used herein to designate any material portion having a nanoscale or microscale and an elongated shape, without limiting the cross-sectional shape of this material portion. The term nanosheet designates an elongated material portion with a circular or substantially circular cross-section and a beam or rod. For example, the rod may include a cylindrical shape or a substantially rectangular cross-section. The nanosheet channels in the semiconductor device structure 100 may be surrounded by a gate electrode layer. The nanosheet transistor may be referred to as a nanowires transistor, a gate-all-around (GAA) transistor, a multi-bridgechannel (MBC) transistor, or other transistors with a gate electrode layer surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels in the semiconductor device structure 100 will be further discussed below. In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 may be replaced by a single semiconductor material connected to the substrate 101, and this device is a fin field effect transistor.

[0119] It should be noted that Figure 1 three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged therein, which is only for illustration and is not intended to limit the description in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of semiconductor layers depends on the predetermined number of channels of the semiconductor device structure 100. In some embodiments, the number of first semiconductor layers 106, that is, the number of channels, is between 3 and 8.

[0120] Specifically, the first semiconductor layer 106 can serve as the channel of the semiconductor device structure 100, and the thickness of the channel is determined according to the performance calculation of the device. In some embodiments, each first semiconductor layer 106 has a thickness of about 6 nanometers to about 12 nanometers. The second semiconductor layer 108 can ultimately be removed and can be used to define the vertical distance between adjacent channels in the semiconductor device structure 100, and the thickness is determined according to the performance calculation of the device. In some embodiments, each second semiconductor layer 108 has a thickness of about 2 nanometers to about 6 nanometers.

[0121] The first semiconductor layer 106 and the second semiconductor layer 108 can be formed by any suitable deposition method (such as epitaxy). For example, the epitaxial growth of the semiconductor layer stack 104 can be operated by molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0122] A mask structure 110 is formed on the semiconductor layer stack 104. The mask structure 110 can include an oxygen-containing layer 112 and a nitrogen-containing layer 114. The oxygen-containing layer 112 can be a liner oxide layer, such as a silicon dioxide (SiO2) layer. The nitrogen-containing layer 114 can be a liner nitride layer, such as a silicon nitride (Si3N4) layer. The mask structure 110 can be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0123] Figure 2 According to some embodiments of the present disclosure, a perspective view of one manufacturing stage of the semiconductor device structure 100 is as Figure 2As shown, fins 202a and 202b are formed. In some embodiments, each of fins 202a and 202b includes a substrate portion 102a and 102b formed from substrate 101, a portion of semiconductor layer stack 104, and a portion of mask structure 110. Fins 202a and 202b can be fabricated through suitable processes, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine a lithography process and a self-alignment process, thereby enabling the fabrication of pattern pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and the sacrificial layer is patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern fins 202a and 202b by etching semiconductor layer stack 104 and substrate 101. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As Figure 2 shown, two fins are formed, but the number of fins is not limited to 2. In some embodiments, 3 to 6 fins are arranged on the X-axis, as Figure 6 shown.

[0124] In some embodiments, fins 202a and 202b can be fabricated through suitable processes, including lithography techniques or etching techniques. Lithography techniques can include forming a photoresist layer (not shown) on mask structure 110, exposing the photoresist to a pattern, performing a post-exposure bake, and finally developing the photoresist to form a patterned photoresist. In some embodiments, an electron beam (e-beam) lithography process can be utilized to pattern the photoresist to form a patterned photoresist. The patterned photoresist can be used to protect regions of substrate 101 and layers formed thereon. In regions not protected by mask structure 110, trenches 204 can be formed in semiconductor layer stack 104 and substrate 101 through an etching process, thus leaving extended fins 202a and 202b. Trenches 204 can be fabricated through dry etching (such as reactive ion etching), wet etching, reactive ion etching (RIE), and / or a combination thereof.

[0125] Figure 3 is a perspective view of one manufacturing stage of semiconductor device structure 100 in some embodiments. As Figure 3As shown, a liner layer 304 is formed on the substrate 101, the fins 202a and 202b. In some embodiments, the liner layer 304 can be made of a semiconductor material (such as silicon). In some embodiments, an optional liner layer 302 can be formed on the substrate 101, and the liner layer 304 is formed on the optional liner layer 302. The liner layer 304 can be made of a semiconductor material such as silicon. In some embodiments, the liner layer 304 can be made of the same material as the substrate 101. The optional liner layer 302 can be made of an oxygen-containing material such as an oxide. The liner layer 304 can be a conformal layer and can be fabricated by a conformal process, such as an atomic layer deposition (ALD) process. The term "conformal" is used herein to simplify the following description: a layer having substantially the same thickness over different regions. The optional liner layer 302 can be a conformal layer and can be fabricated by a conformal process, such as an atomic layer deposition process.

[0126] Figure 4 is a perspective view of one manufacturing stage of the semiconductor device structure 100 in some embodiments. As Figure 4 shown, an insulating material 402 is formed on the substrate 101. The insulating material 402 fills the trenches 204 ( Figure 2 ). First, the insulating material 402 is formed on the substrate 101, so that the fins 202a and 202b are buried in the insulating material 402. Then, a planarization process, such as chemical mechanical polishing (CMP) and / or etch back, is performed to expose the tops of the fins 202a and 202b (such as the liner layer 304) from the insulating material 402, as Figure 4 shown. The insulating material 402 can be made of an oxygen-containing material such as silicon oxide, fluorine-doped silicate glass (FSG), a nitrogen-containing material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), a low dielectric constant material, or any other suitable dielectric material. The insulating material 402 can be formed by any suitable process, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0127] Next, as Figure 5As shown, a portion of the insulating material 402 between the adjacent fins 202a and 202b is removed to recess the insulating material 402 to form a trench 502. The trench 502 can be formed by any suitable process, such as dry etching or wet etching of the semiconductor material that selectively removes the insulating material 402 but not the liner layer 304. The recessed insulating material 402 can be a shallow trench isolation (STI) structure. The insulating material 402 includes a top surface 504 that is flush with or below the surface of the second semiconductor layer 108 in contact with the substrate 101.

[0128] Figures 6 to 15 is a cross-sectional view taken along line A-A in Figure 5 during various manufacturing stages of a semiconductor device structure according to some embodiments of the present disclosure. As Figure 6 shown, four fins 202a, 202b, 202c, and 202d are formed in the X direction. The fins 202a, 202b, 202c, and 202d can respectively include substrate portions 102a, 102b, 102c, and 102d. The fins 202a and 202b can respectively have a first width W1, and the fins 202c and 202d can respectively have a second width W2. In some embodiments, the second width W2 is greater than the first width W1. As described above, the first semiconductor layer 106 can serve as a channel in a nanosheet transistor device. The first width W1 and the second width W2 can be the widths of the transistor channels. Devices with wider channels, such as those made from fins 202c and 202d, may be more suitable for high-speed applications, such as NAND devices. Devices with narrower channels, such as those made from fins 202a and 202b, may be more suitable for low-power, low-leakage applications, such as inverter devices. In some embodiments, in a system-on-a-chip (SOC) device, for example, devices with wider channels and devices with narrower channels can be formed on the same column (along the X direction), as Figure 6 shown.

[0129] As Figure 6As shown, the distances between adjacent fins 202a, 202b, 202c, and 202d can be different. In some embodiments, adjacent fins used to fabricate similar devices are separated by a first distance D1, and adjacent fins used to fabricate different devices are separated by a second distance D2. The first distance D1 or the second distance D2 can be defined by the distance between a first sidewall of one fin and a second sidewall of an adjacent second fin that faces the first sidewall. For example, fins 202a and 202b can be used to fabricate a converter device, fins 202c and 202d can be used to fabricate a device other than a converter device, such as an inverter device, and the first distance D1 between fins 202a and 202b is less than the second distance D2 between fins 202b and 202c. With the smaller first distance D1, the source / drain epitaxial features 2002 ( Figure 20A ) formed from the substrate portion 102a of fin 202a and the source / drain epitaxial features 2002 ( Figure 20A ) formed from the substrate portion 102b of fin 202b can be merged, as Figure 20A shown. Similarly, the source / drain epitaxial features 2002 ( Figure 20A ) formed from the substrate portion 102c of fin 202c and the source / drain epitaxial features 2002 ( Figure 20A ) formed from the substrate portion 102d of fin 202d can be merged, as Figure 20A shown. The merged source / drain epitaxial features 2002 ( Figure 20A ) may result in increased device density and reduced electrical resistance and contact resistance. Additionally, the channel regions formed from fins 202a and 202b (e.g., the channel formed from the first semiconductor layer 106) may share the same gate electrode layer 2802 ( Figure 28A and Figure 28B ). Thus, the first distance D1 between the channel region formed from fin 202a and the channel region formed from fin 202b may accommodate a narrow dielectric feature having a width less than about 10 nanometers (e.g., in Figure 28A , the second portion 1704 of the liner layer 702 between the channel regions). In some embodiments, the narrow dielectric feature (e.g., in Figure 28A , the second portion 1704 of the liner layer 702 between the channel regions) may be absent, as Figure 28B shown. The narrow or absent dielectric feature may result in reduced resistance of the gate electrode layer. In some embodiments, the second distance D2 may accommodate a wide dielectric feature (e.g., in Figure 20A , the dielectric feature 1302 between the source / drain epitaxial features) to separate the source / drain epitaxial features 2002 ( Figure 20A)。The wide dielectric feature portion can extend in the channel region between adjacent fins, and the gate electrode layer may or may not be separated or interrupted by the wide dielectric feature portion. The narrow dielectric feature portion and the wide dielectric feature portion will be described in detail below.

[0130] As Figure 6 shown, a cladding layer 602 is formed on the exposed surface ( Figure 5 ) of the liner layer 304, and for clarity, the optional liner layer 302 is omitted. During the formation of the cladding layer 602, the liner layer 304 may diffuse into the cladding layer 602. Thus, in some embodiments, the optional liner layer 302 is absent, and the cladding layer 602 contacts the semiconductor layer stack 104, as Figure 6 shown. In some embodiments, the cladding layer 602 comprises a semiconductor material. The cladding layer 602 is formed on the semiconductor material but not on the dielectric material. For example, the cladding layer 602 comprises silicon germanium and is formed on the silicon of the liner layer 304 but not on the dielectric material of the insulating material 402. In some embodiments, the cladding layer 602 can be formed by first forming a semiconductor layer on the liner layer 304 and the insulating material 402, and then removing the insulating material 402 on a portion of the semiconductor layer by an etching process. The etching process may remove some of the semiconductor layer formed on the tops of the fins 202a, 202b, 202c, and 202d, and the cladding layer 602 formed on the tops of the fins 202a, 202b, 202c, and 202d may have a curved surface instead of a planar surface. In some embodiments, the cladding layer 602 and the second semiconductor layer 108 may comprise the same material with the same etching selectivity. For example, the cladding layer 602 and the second semiconductor layer 108 comprise silicon germanium. The cladding layer 602 and the second semiconductor layer 108 can be removed sequentially to create a space between the electrode gate layers.

[0131] The cladding layer 602 can define the dimensions of the trenches 604 and 606 in the X direction. In some embodiments, the dimensions of the trenches 604 and 606 in the X direction are the widths of the trenches 604 and 606. The width of the trench 604 can be less than the width of the trench 606. The narrow dielectric material can be formed in the trench 604, and the wide dielectric material can be formed in the trench 606. The portion of the cladding layer 602 formed on the sidewalls of the fins 202a, 202b, 202c, and 202d can have a substantially the same thickness of about 0.5 nanometer to about 10 nanometers. The thickness of the cladding layer 602 formed on the sidewalls of the fins 202a, 202b, 202c, and 202d can define the space provided for the formation of the electrode gate layer 2802 after removing the cladding layer 602 ( Figure 28A and Figure 28B)。Therefore, if the thickness of the cladding layer 602 is less than about 0.5 nanometers, the space after removing the cladding layer 602 may be too small to form the electrode gate layer. On the other hand, if the thickness of the cladding layer 602 is greater than about 10 nanometers, the manufacturing cost will increase without bringing significant advantages.

[0132] Next, as Figure 7 shown, a liner layer 702 is formed on the tops of the fins 202a, 202b, 202c, and 202d and in the trenches 604 ( Figure 6 ). The liner layer 702 may comprise a low dielectric constant material (e.g., a material having a dielectric constant of about less than 7), such as silicon oxycarbide (SiOC), silicon oxynitride carbide, or silicon carbonitride. The liner layer 702 may be formed by a conformal process, such as an atomic layer deposition process. Due to the small width of the trench 604, the liner layer 702 can fill the trench 604. The liner layer 702 can be formed on the top surface 504 of the insulating material 402 at the bottom of the trench 606 and on the partial cladding layer 602 that serves as the sidewall of the trench 606. The liner layer 702 has a thickness of about 0.5 nanometers to about 8 nanometers. The liner layer 702 can fill the trench 604 but cannot fill the trench 606. Therefore, if the thickness of the liner layer 702 is less than about 0.5 nanometers, the trench 604 cannot be filled. On the other hand, if the thickness of the liner layer 702 is greater than about 5 nanometers, the trench 606 may be filled.

[0133] Next, as Figure 8 shown, a low dielectric constant material 802 is formed in the trench 606 and on the fins 202a, 202b, 202c, and 202d. The low dielectric constant material 802 may comprise a material having a dielectric constant of about less than 7, such as silicon dioxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or silicon oxynitride carbide. In one example, the low dielectric constant material 802 comprises silicon dioxide. The low dielectric constant 802 may comprise the same or different material as the liner layer 702. The low dielectric constant material 802 may be formed by a flowable process, such as flowable chemical vapor deposition. The low dielectric constant material 802 may have a thickness of about 2 nanometers to about 15 nanometers. The low dielectric constant material 802 can fill the trench 606. Therefore, if the thickness of the low dielectric constant material 802 is less than about 2 nanometers, the trench 606 cannot be filled. On the other hand, if the thickness of the low dielectric constant material 802 is greater than about 10 nanometers, the manufacturing cost will increase without bringing significant advantages.

[0134] Next, as Figure 9As shown, a planarization process is performed to expose the capping layer 602 disposed on top of the fins 202a, 202b, 202c, 202d, the liner layer 702, and the low-k dielectric material 802. The planarization process can be any suitable process, such as chemical mechanical polishing. The planarization process removes a portion of the low-k dielectric material 802 and a portion of the liner layer 702 on a portion of the capping layer 602 disposed on the fins 202a, 202b, 202c, 202d.

[0135] Next, as Figure 10 shown, the low-k dielectric material 802 and the liner layer 702 are recessed. The low-k dielectric material 802 and the liner layer 702 can be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process can be controlled such that the low-k dielectric material 802 and the liner layer 702 in the trench 606 ( Figure 6 ) are substantially flush with the top surface 1006 of the uppermost layer of the first semiconductor layer 106 of the semiconductor stack 104. The top surface 1006 of the uppermost layer of the first semiconductor layer 106 can contact the oxygen-containing layer 112 of the mask structure 110. Since the combined low-k dielectric material 802 and the liner layer 702 in the trench 606 ( Figure 6 ) have a larger dimension in the X direction compared to the liner layer 702 in the trench 604 ( Figure 6 ), the etchant removes less of the liner layer 702 in the trench 604 ( Figure 6 ) than the combined low-k dielectric material 802 and the liner layer 702 in the trench 606 ( Figure 6 ). Therefore, the etching rate of the combined low-k dielectric material 802 and the liner layer 702 in the trench 606 is faster than that of the liner layer 702 in the trench 604. Thus, the height of the liner layer 702 in the trench 604 ( Figure 6 ) in the Z direction may be greater than the combined low-k dielectric material 802 and the liner layer 702 in the trench 606 ( Figure 6 ). In some embodiments, the low-k dielectric material 802 and the liner layer 702 comprise the same material, and thus a single etching process can be performed to recess the low-k dielectric material 802 and the liner layer 702. The etching process can be a selective etching process that does not remove the semiconductor material of the capping layer 602. In some embodiments, the low-k dielectric material 802 and the liner layer 702 comprise different materials, and thus a first etching process can be performed to first recess the low-k dielectric material 802, and then a second etching process can be performed to recess the liner layer 702 in the trenches 604 and 606. The etching process can be a selective etching process that does not remove the semiconductor material of the capping layer 602. After the recessing process, trenches 1002 are formed between the fins 202a and 202b and between the fins 202c and 202d, and trenches 1004 are formed between the fins 202b and 202c and between the fin 202d and an adjacent fin (not shown).

[0136] Next, as Figure 11 shown, a high-k dielectric material 1102 is formed in the trenches 1002, 1004 and on the fins 202a, 202b, 202c, 202d. The high-k dielectric material 1102 may include a material having a dielectric constant of about greater than 7, such as hafnium dioxide (HfO2), zirconium oxide (ZrO2), hafnium aluminum oxide (HfAlO x ), hafnium silicon oxide (HfSiO x ), or aluminum oxide (Al2O3). The high-k dielectric material 1102 can be formed by any suitable process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, flowable chemical vapor deposition, or atomic layer deposition. The high-k dielectric material 1102 has a thickness of about 5 nanometers to about 30 nanometers. The high-k dielectric material 1102 can fill the trenches 1002 and 1004. Thus, if the thickness of the high-k dielectric material 1102 is less than about 5 nanometers, the trench 1004 cannot be filled. On the other hand, if the thickness of the low-k dielectric material 802 is greater than about 30 nanometers, the manufacturing cost will increase without bringing significant advantages.

[0137] A planarization process is performed to expose the nitrogen-containing layer 114, the capping layer 602, the liner layer 702, and the high-k dielectric material 1102, as Figure 12 shown. The planarization process can be any suitable process, such as chemical mechanical polishing. The planarization process removes a portion of the high-k dielectric material 1102 on a portion of the capping layer 602 disposed on the fins 202a, 202b, 202c, 202d.

[0138] Next, as Figure 13 shown, the capping layer 602 and the liner layer 702 are recessed to be substantially flush with the low-k dielectric material 802 (e.g., the top surfaces of the capping layer 602 and the liner layer 702 are substantially coplanar with the top surface of the low-k dielectric material 802). The recessing process can be one or more etching processes, such as dry etching, wet etching, or a combination thereof. In some embodiments, a first etching process is performed to first recess the liner layer 702, and then a second etching process is performed to recess the capping layer 602. The first and second etching processes can be selective etching processes that do not remove the nitrogen-containing layer 114 and the high-k dielectric material 1102. After the recessing process, a liner layer 702 is formed between the semiconductor stacks 104 of the fins 202a, 202b and between the semiconductor stacks 104 of the fins 202c, 202d. As Figure 13 shown, the high-k dielectric material 1102, the low-k dielectric material 802, and the liner layer 702 can be collectively referred to as a dielectric feature 1302. The dielectric feature 1302 can be the source / drain epitaxial feature 2002 that can separate different devices as described above ( Figure 20A) has a wide dielectric feature portion, and the liner layer 702 can be a narrow dielectric feature portion of the channel region that may or may not exist between adjacent fins 202a, 202b. In some embodiments, the dielectric feature 1302 can be a hybrid fin. The high-k material 1102 of the dielectric feature 1302 has a height H1 of about 10 nanometers to about 30 nanometers. The high-k material 1102 of the dielectric feature 1302 can be used to separate or truncate the gate electrode layer. Thus, if the height H1 is less than about 10 nanometers, the gate electrode layer cannot be substantially truncated. On the other hand, if the height H1 is greater than about 30 nanometers, the manufacturing cost will increase without bringing significant advantages.

[0139] As Figure 14 shown, the mask structure 110 ( Figure 13 ) is removed. The removal process can be one or more etching processes, such as dry etching, wet etching, or a combination thereof. In some embodiments, a first etching process is performed to first remove the nitrogen-containing layer 114 ( Figure 3 ), and then a second etching process is performed to remove the oxygen-containing layer 112 ( Figure 3 ). The first and second etching processes can be selective etching processes that do not remove the liner layer 702, the cladding layer 602, the first semiconductor layer 106, and the high-k material 1102. After the removal process, the semiconductor device structure 100 can have a substantially planar surface and the high-k material 1102 extends from the surface.

[0140] Next, as Figure 15As shown, a sacrificial gate dielectric layer 1502 is formed on the surface of the substantial plane of the semiconductor device structure 100 and on the high-k dielectric material 1102. The sacrificial gate dielectric layer 1502 may include one or more layers of dielectric materials, such as silicon dioxide, silicon nitride (SiN), high-k dielectric materials, and / or other suitable dielectric materials. In some embodiments, the sacrificial gate dielectric layer 1502 includes a material different from the high-k dielectric material 1102. In some embodiments, the sacrificial gate dielectric layer 1502 may be deposited by chemical vapor deposition, sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable processes. For example, the sacrificial gate dielectric layer 1502 can be used to avoid damage to the fins 202a, 202b, 202c, 202d caused by subsequent processes (such as the formation of a subsequent sacrificial gate stack). A sacrificial gate electrode layer 1504 and a mask structure 1506 are formed on the sacrificial gate dielectric layer 1502. The sacrificial gate electrode layer 1504 may include polysilicon. The mask structure 1506 may include an oxygen-containing layer 1508 and a nitrogen-containing layer 1510. In some embodiments, the sacrificial gate electrode layer 1504 and the mask structure 1506 can be formed by different processes such as layer deposition, such as chemical vapor deposition (including plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition), physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, other suitable deposition processes, or combinations thereof.

[0141] Figures 16A to 20A is a cross-sectional view along line A-A in each manufacturing stage of the semiconductor device structure according to some embodiments of the present disclosure. Figure 5 in. Figures 16B to 20B is a cross-sectional view along line B-B in each manufacturing stage of the semiconductor device structure according to some embodiments of the present disclosure. Figure 15 in. Figures 16C to 20C is a cross-sectional view along line C-C in each manufacturing stage of the semiconductor device structure according to some embodiments of the present disclosure. Figure 15 in. Figures 16D to 20D is a cross-sectional view along line D-D in each manufacturing stage of the semiconductor device structure according to some embodiments of the present disclosure. As Figure 15 shown, a portion of the sacrificial gate dielectric layer 1502, the sacrificial gate electrode layer 1504, and the mask structure 1506 are removed to form a sacrificial gate stack 1512. As Figures 16A to 16D shown, the sacrificial gate stack 1512 includes the sacrificial gate dielectric layer 1502, the sacrificial gate electrode layer 1504, and the mask structure 1506. Figures 16B to 16D shown.

[0142] The sacrificial gate stack 1512 can be formed through a patterning process or an etching process. For example, the patterning process may include a lithography process (such as photolithography or electron beam lithography), and also include photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying, hard baking), other lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (such as reactive ion etching), wet etching, other etching methods, and / or combinations thereof. As Figure 16C shown, by patterning the sacrificial gate stack 1512, the semiconductor layer stacks 104 in the fins 202a, 202b, 202c, 202d partially located on opposite sides of the sacrificial gate stack 1512 are exposed. As Figure 16B , Figure 16C , Figure 16D shown, one sacrificial gate stack 1512 is formed, but the number of sacrificial gate stacks 1512 is not limited to one. In some embodiments, two or more sacrificial gate stacks 1512 are arranged in the Y direction.

[0143] As Figures 17A to 17D shown, spacers 1702 are formed on the sidewalls of the sacrificial gate stack 1512. The spacers 1702 can be formed by first depositing a conformal layer and then etching back the conformal layer. For example, a spacer material layer can be conformally disposed on the exposed surface of the semiconductor device structure 100. The conformal spacer material layer can be formed by atomic layer deposition. Then, the spacer material layer is anisotropically etched, such as by reactive ion etching. During the anisotropic etching, most of the spacer material layer located on the horizontal surfaces, such as the tops of the fins 202a, 202b, 202c, 202d, the liner layer 702, the capping layer 602, and the high-k dielectric material 1102, is removed, leaving the spacer material layer located on the vertical surfaces, such as the sidewalls of the sacrificial gate stack 1512. The spacers 1702 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxynitride, and / or combinations thereof. In some embodiments, the spacers 1702 include multiple layers, such as a main spacer wall, a liner layer, or the like.

[0144] Next, through one or more suitable processes, such as dry etching, wet etching, or combinations thereof, the exposed portions of the fins 202a, 202b, 202c, 202d, the exposed portion of the capping layer 602, and the exposed portion of the liner layer 702 that are not covered by the sacrificial gate stack 1512 and the spacers 1702 are removed. In some embodiments, the exposed portions of the semiconductor layer stacks 104 of the fins 202a, 202b, 202c, 202d ( Figure 16C ) are removed to expose the substrate portions 102a, 102b, 102c, 102d, respectively. AsFigure 17A As shown, the height of the exposed portions of the recessed fins 202a, 202b, 202c, 202d to the top surface 504 of the insulating material 402 is at or below the top surface 504 of the insulating material 402, and the recessed exposed liner layer 702 is at a height H2 of from about 0.5 nanometer to about 15 nanometers. The exposed portion of the recessed liner layer 702 to the height H2 is to facilitate the coalescence of the source / drain epitaxial features 2002( Figure 20A ). Thus, if the height H2 of the liner layer 702 is greater than about 15 nanometers, the coalescence of adjacent source / drain epitaxial features can be avoided. In some embodiments, the exposed portion of the liner layer 702 is not recessed but removed( Figure 29B ). One or more etching processes may include a first etching process that removes the exposed portions of the fins 202a, 202b, 202c, 202d and the exposed portion of the cladding layer 602. Due to different etching selectivities, the first etching process may not be sufficient to remove the exposed portion of the liner layer 702 to the height H2. A second etching process may be performed to further reduce the height of the liner layer 702 to the height H2. The liner layer 702 includes a first portion 1703 having a height H2 and a second portion 1704 under the sacrificial gate stack 1512( Figure 17A and Figure 17D shown in dashed lines), and the second portion 1704 has a height H3 that may be greater than the height H2. The first portion 1703 of the liner layer 702 may be located between the source / drain regions, which may subsequently be defined by the source / drain epitaxial features 2002( Figure 20A ), and the second portion 1704 of the liner layer 702 under the sacrificial gate stack 1512 may be located between two channel regions. As Figure 29B shown, the first portion 1703 of the liner layer 702 may be absent. Additionally, one or more processes may reduce the width of the first portion 1703 of the liner layer 702. In some embodiments, as Figure 17A shown, the first portion 1703 of the liner layer 702 has a width W3, the second portion 1704 of the liner layer 702 has a width W4, and the width W3 of the first portion 1703 of the liner layer 702 is less than the width W4 of the second portion 1704 of the liner layer 702. The width W4 may be less than about 10 nanometers. As described above, the second portion 1704 of the liner layer 702 between the two channel regions may result in reducing the resistance of the gate electrode layer 2802( Figure 28A ). Thus, if the width W4 is greater than 10 nanometers, the second portion 1704 of the liner layer 702 may not be sufficient to reduce the resistance of the gate electrode layer 2802( Figure 28A ).

[0145] In some embodiments, as Figure 17A , Figure 17BAs shown, one or more etching processes may reduce the height of the exposed portion of the high-k material 1102 from H1 to H4. Thus, as Figure 17A , Figure 17B shown, the high-k material 1102 includes a first portion 1706 having a height H4 and a second portion 1708 having a height H1 greater than the height H4. The first portion 1706 of the high-k material 1102 may be located between the source / drain regions, and the second portion 1708 of the high-k material 1102 under the sacrificial gate stack 1512 may be located between the channel regions. The second portion 1708 may extend upward from the plane defined by the top surface 1006 of the topmost first semiconductor layer 106 ( Figure 13 ) by an amount equal to the height H1.

[0146] At this stage, Figure 17C as shown, the ends of the semiconductor layer stack 104 under the sacrificial gate stack 1512 have a substantially flat surface that may be flush with the spacers 1702. In some embodiments, the ends of the semiconductor layer stack 104 under the sacrificial gate stack 1512 are slightly etched horizontally.

[0147] Next, as Figures 18A to 18D shown, the edge portions of each second conductor layer 108 and the edge portions of the cladding layer 602 are removed to form gaps 1802. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process without removing the first semiconductor layer 106. For example, in the case where the second semiconductor layer 108 is made of silicon germanium and the first semiconductor layer 106 is made of silicon, a selective wet etching process including a mixture of ammonia and hydrogen peroxide (APM) may be used.

[0148] Next, as Figures 19A to 19D shown, dielectric spacers 1902 are formed in the gaps 1802. In some embodiments, the dielectric spacers 1902 may be made of a low-k material such as silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. In some embodiments, a conformal dielectric layer may be formed by a conformal deposition process such as atomic layer deposition. Next, an anisotropic etching is performed to remove the conformal dielectric layer other than the dielectric spacers 1902 to form the dielectric spacers 1902. The first semiconductor layer 106 may protect the dielectric spacers 1902 during the anisotropic etching.

[0149] Next, as Figures 20A to 20DAs shown, source / drain epitaxial features 2002 are formed on the substrate portions 102a, 102b, 102c, 102d of the fins 202a, 202b, 202c, 202d. In an n-type channel field effect transistor, the source / drain epitaxial features 2002 may include one or more layers of silicon, silicon phosphide, silicon carbide, and silicon carbon phosphide (SiCP), and in a p-type channel field effect transistor, the source / drain epitaxial features 2002 may include one or more layers of silicon, silicon germanium, and germanium. The source / drain epitaxial features 2002 may grow vertically and horizontally to form facets that can correspond to the crystal planes of the materials used for the substrate portions 102a, 102b, 102c, 102d. The source / drain epitaxial features 2002 are formed by an epitaxial growth method such as chemical vapor deposition, atomic layer deposition, or electron beam epitaxy. As Figure 20C shown, the source / drain epitaxial features 2002 contact the first semiconductor layer 106 and the dielectric spacer 1906. The source / drain epitaxial features 2002 may be source / drain regions. For example, as Figure 20C shown, one of a pair of source / drain epitaxial features 2002 located on one side of the semiconductor layer stack 104 is the source region 2004, and the other of the pair of source / drain epitaxial features 2002 located on the other side of the semiconductor layer stack 104 is the drain region 2006. A source epitaxial feature 2002 and a drain epitaxial feature 2002 connected by a channel (such as the first semiconductor layer 106) are collectively referred to as a pair of source / drain epitaxial features 2002. In this disclosure, the source and the drain may be used interchangeably, and the devices are substantially the same.

[0150] As Figure 20A shown, since the distance D1 ( Figure 6 ) between the fins 202a, 202b is very small, the source / drain epitaxial features 2002 formed from the fins 202a, 202b may merge. Between the source / drain regions, the first portion 1703 of the liner layer 702 having a height H2 does not prevent adjacent source / drain epitaxial features 2002 from merging together. The first portion 1703 may be located in the air gap 2010 under the merged source / drain epitaxial features. In some embodiments, as Figure 20A shown, the first portion 1703 of the liner layer 702 may be located at the substantial midpoint between the substrate portion 102a and the substrate portion 102b. For example, as Figure 20A shown, the first portion 1703 of the liner layer 702 may be located at a first surface distance D3 from the surface defined by the sidewall 2008a of the substrate portion 102a and at a second surface distance D4 from the surface defined by the sidewall 2008b of the substrate portion 102b. The distance D3 and the distance D4 may be substantially the same. In some embodiments, as Figure 20AAs shown, the first portion 1703 of the liner layer 702 contacts the merged source / drain epitaxial feature 2002. In some embodiments, the first portion 1703 of the liner layer 702 does not contact the merged source / drain epitaxial feature 2002. As described above, the source / drain epitaxial feature 2002 formed from the substrate portion 102b of the fin 202b and the source / drain epitaxial feature 2002 formed from the substrate portion 102c of the fin 202c can be used for different devices. Thus, as Figure 20A shown, the dielectric feature 1302 separates the source / drain epitaxial feature 2002 formed from the substrate portion 102b of the fin 202b from the source / drain epitaxial feature 2002 formed from the substrate portion 102c of the fin 202c.

[0151] Figures 21A to 25A are perspective views of various manufacturing stages of the semiconductor device structure 100 according to some embodiments of the present disclosure. Figures 21B to 25B are cross-sectional views along line B-B of various manufacturing stages of the semiconductor device structure 100 according to some embodiments of the present disclosure, Figure 21A as shown in. Figures 21C to 25C are cross-sectional views along line C-C of various manufacturing stages of the semiconductor device structure 100 according to some embodiments of the present disclosure, Figure 21A as shown in. Figure 21A illustrates a portion of the semiconductor device structure 100 adjacent to the semiconductor device structure 100 shown in Figure 20A in the X direction. For example, as Figure 21A shown, the substrate portion 102e of the fin 202e can be adjacent to the substrate portion 102d of the fin 202d ( Figure 20A ), and the dielectric feature 1302 ( Figure 20A ) can be located between the source / drain epitaxial feature 2002 ( Figure 20A ) formed from the substrate portion 102d of the fin 202d and the source / drain epitaxial feature 2002 ( Figure 20A ) formed from the substrate portion 102e of the fin 202e. The substrate portion 102f of the fin 202f is adjacent to the substrate portion 102e of the fin 202e, and the dielectric feature 1302 separates the source / drain epitaxial feature 2002 formed from the substrate portion 102f of the fin 202f from the source / drain epitaxial feature 2002 formed from the substrate portion 102e of the fin 202e. As Figure 21A shown, the dielectric feature 1302 includes a high-k material 1102, a low-k material 802, and a liner layer 702. The high-k material 1102 includes a first portion 1706 located between the source / drain regions and a second portion 1708 under the sacrificial gate stack 1512.

[0152] AsFigures 21A to 21C As shown, after forming the source / drain epitaxial feature 2002, a contact etch stop layer (CESL) 2102 is formed on the source / drain epitaxial feature 2002, the dielectric feature 1302, and the sacrificial gate stack 1512. The contact etch stop layer 2102 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof. The contact etch stop layer 2102 may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the contact etch stop layer 2102 is a conformal layer formed by an atomic layer deposition process. An interlayer dielectric (ILD) 2104 may be formed on the contact etch stop layer 2102. The material of the interlayer dielectric 2104 may include tetraethylorthosilicate (TEOS) oxide, undoped silicon glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric 2104 may be deposited by plasma-enhanced chemical vapor deposition or other suitable techniques. In some embodiments, after forming the interlayer dielectric 2104, a heat treatment may be performed on the semiconductor device structure 100 to anneal the interlayer dielectric 2104.

[0153] As Figures 21A to 21C shown, a planarization process is performed to expose the sacrificial gate electrode layer 1504. The planarization process may be any suitable process, such as chemical mechanical polishing. The planarization process removes a portion of the interlayer dielectric 2104 and a portion of the contact etch stop layer 2102 disposed on the sacrificial gate stack 1512. The planarization process may also remove the mask layer 1506 ( Figure 20B ). As Figures 21A to 21C shown, the interlayer dielectric 2104 may be recessed to a level below the top of the sacrificial gate electrode layer 1504, and a nitrogen-containing layer 2106, such as silicon carbonitride, may be formed on the recessed interlayer dielectric 2104. The nitrogen-containing layer 2106 may protect the interlayer dielectric 2104 in subsequent etching processes.

[0154] Figure 22A is at various manufacturing stages of the semiconductor device structure 100 according to some embodiments of the present disclosure, alongFigure 21A A perspective view of line A-A in Figure 22B is a cross-sectional view along line B-B in each manufacturing stage of the semiconductor device structure 100 according to some embodiments of the present disclosure. Figure 21A A cross-sectional view of line B-B in Figure 22C is a cross-sectional view along line C-C in each manufacturing stage of the semiconductor device structure 100 according to some embodiments of the present disclosure. As Figure 21A shown, a portion of the sacrificial gate electrode layer 1504 is removed, and the height of the remaining sacrificial gate electrode layer 1504 is lower than the top of the second portion 1708 of the high-k dielectric material 1102. In other words, the sacrificial gate electrode layer 1504 is recessed to a height lower than the top of the second portion 1708 of the high-k dielectric material 1102. A portion of the sacrificial gate dielectric layer 1502 formed on the high-k dielectric material 1102 is exposed. The portion of the sacrificial gate electrode layer 1504 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as tetramethylammonium hydroxide (TMAH) can selectively remove the sacrificial gate electrode layer 1504 without removing the nitrogen-containing layer 2106 and the contact etch stop layer 2102. In some embodiments, as Figures 22A to 22C shown, the etching process for removing the sacrificial gate electrode layer 1504 may remove a portion of the spacer 1702. Figures 22A to 22C

[0155] Then, as Figures 23A to 23C shown, a mask layer 2302 is formed on the exposed portion of the sacrificial gate dielectric layer 1502, and the mask layer 2302 can extend in the Y direction and also cover a portion of the spacer 1702, the contact etch stop layer 2102, and the nitrogen-containing layer 2106. A blanket layer can be first formed on the semiconductor device structure 100, and then a portion of the blanket layer is removed by a patterning process and an etching process to form the mask layer 2302. The mask layer 2302 can include an oxygen-containing material and / or a nitrogen-containing material. In some embodiments, the mask layer 2302 is a photoresist formed by first forming a conformal photoresist layer on the semiconductor device structure 100 and then patterning the conformal photoresist layer.

[0156] The mask layer 2302 can be above one or more second portions 1708 of the high-k dielectric material 1102. The mask layer 2302 protects the one or more second portions 1708 to ensure that the protected second portions 1708 can separate the subsequently formed gate electrode layer 2802 ( Figure 28A ). The unprotected second portions 1708 can be removed so that the subsequently formed gate electrode layer 2802 ( Figure 28A ) connects adjacent channel regions ( Figure 28A ))。In other words, if it is intended to separate and truncate the gate electrode layer 2802 in adjacent channel regions ( Figure 28A ), a mask layer 2302 is formed on the second portion 1708 of the high-k material 1102 of the dielectric feature 1302 between the adjacent channel regions. On the other hand, if it is intended to connect the gate electrode layer 2802 in adjacent channel regions ( Figure 28A ), the mask layer 2302 is not formed on the second portion 1708 of the high-k material 1102 of the dielectric feature 1302 between the adjacent channel regions. If the gate electrode layers 2802 ( Figure 28A ) are connected, a single signal (such as current) transmitted to the gate electrode layer 2802 can control two adjacent channel regions. If the gate electrode layer 2802 is truncated, independent signals (such as independent currents) can be transmitted to each gate electrode layer 2802 to control each adjacent channel region separately.

[0157] Next, as Figures 24A to 24C shown, the second portion 1708 of the high-k material 1102 not protected by the mask layer 2302 and the sacrificial gate dielectric layer 1502 formed thereon can be removed. The first portion 1706 of the high-k material 1102 under the interlayer dielectric layer 2104 is not removed. Removing the second portion 1708 can expose the underlying portion of the liner layer 702 and the low-k material 802. The removal process can be any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, an etching process can be performed to simultaneously remove a portion of the sacrificial gate dielectric layer 1502 and a portion of the second portion 1708 of the high-k material 1102. In some embodiments, a first etching process can be performed to remove a portion of the sacrificial gate dielectric layer 1502, and then a second etching process can be performed to remove a portion of the second portion 1708 of the high-k material 1102. As Figures 24A to 24C shown, one or more etching processes can also remove a portion of the sacrificial gate electrode layer 1504. These one or more etching processes do not remove the nitrogen-containing layer 2106, the contact etch stop layer 2102, and the spacers 1702. The spacers 1702 can protect the second portion 1708 of the high-k material 1102. Thus, at least one dielectric feature 1302 can include two or more separate high-k materials 1102, and the cross-section of each separate high-k material 1102 in the YZ plane is U-shaped, as Figure 24A shown. The U-shape may be caused by the shape of the first portion 1706 between the two second portions 1708. As described above, the first portion 1706 has a height H4 that is less than the height H1 of the second portion 1708.

[0158] After removing a portion of the sacrificial gate dielectric layer 1502 and a second portion 1708 of the high-k material 1102, the mask layer 2302 ( Figure 23A and Figure 23B ) can be removed. The mask layer 2302 can be removed by any suitable removal process, such as ashing, dry etching, wet etching, or a combination thereof.

[0159] Figure 24B FIG. shows a cross-sectional view of the semiconductor device structure 100 along the dielectric feature 1302 protected by the mask layer 2302. Thus, the protected dielectric feature 1302 includes a continuous high-k material 1102 having alternating first portions 1706 and second portions 1708. In some embodiments, multiple dielectric features 1302 are protected by the mask layer 2302 ( Figure 23A and Figure 23B ).

[0160] Next, as Figures 25A to 25C shown, the remaining portion of the sacrificial gate electrode layer 1504 is removed. The sacrificial gate electrode layer 1504 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as tetramethylammonium hydroxide can selectively remove the sacrificial gate electrode layer 1504 without removing the nitrogen-containing layer 2106, the sacrificial gate dielectric layer 1502, and the contact etch stop layer 2102.

[0161] Next, as Figures 26A to 26C shown, the remaining portions of the sacrificial gate dielectric layer 1502, the capping layer 602, and the second semiconductor layer 108 are removed. As Figures 26A to 26C shown, the removal process exposes the dielectric spacer 1902 and the first semiconductor layer 106. The removal process can be any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a first etch process can be performed to remove the remaining portion of the sacrificial gate dielectric layer 1502, and then a second etch process can be performed to remove the capping layer 602 and the second semiconductor layer 108. The first etch process can be a selective etch process that removes the sacrificial gate dielectric layer 1502 without removing the high-k material 1102. Similarly, the second etch process can be a selective etch process that removes the sacrificial capping layer 602 and the second semiconductor layer 108 without removing the high-k material 1102 and the first semiconductor layer 106. Thus, as Figure 26A and Figure 26C shown, an opening 2602 is formed in the channel region of the semiconductor device 100. The opening 2602 may expose the first semiconductor layer 106, the dielectric feature 1302, and the liner layer 702 ( Figure 27A ). Each first semiconductor layer 106 can be a nanosheet channel of a nanosheet transistor.

[0162] Figure 27A is a perspective view of the channel region of the semiconductor device structure 100 at the manufacturing stage according to some embodiments of the present disclosure. As Figure 26A shown, the semiconductor device structure 100 may include a plurality of fins 202 and a plurality of first semiconductor layers 106 disposed on each fin 202. The fin 202 can be Figure 27A any one of the fins 202a, 202b, 202c, 202d as shown. In some embodiments, the second portion 1704 of the liner layer 702 and / or the dielectric feature 1302 may be disposed between adjacent channel regions. As described above, the adjacent channel regions with the second portion 1704 of the liner layer 702 therebetween may share the gate electrode layer 2802 ( Figure 6 ), and the adjacent channel regions with the dielectric feature 1302 therebetween may or may not share the gate electrode layer 2802 ( Figure 28A ). Figure 28A )

[0163] Figure 27B is a perspective view of the channel region of the semiconductor device structure 100 in another embodiment according to the present disclosure at Figure 27A . As Figure 27B shown, in some embodiments, the second portion 1704 of the liner layer 702 located between adjacent channel regions is removed. As described above, the second portion 1704 of the liner layer 702 has a width less than about 10 nanometers or the second portion 1704 of the liner layer 702 does not exist to reduce the resistance of the gate electrode layer.

[0164] Figure 28A and Figure 28B are cross-sectional views of the channel region of the semiconductor device structure 100 according to some embodiments of the present disclosure. The semiconductor device structure 100 may include fins 202a, 202b, 202c, 202d, 202e having substrate portions 102a, 102b, 102c, 102d, 102e, respectively. In some embodiments, the second portion 1704 of the liner layer 702 and / or the dielectric feature 1302 may be disposed between adjacent channel regions, as Figure 28A shown. In some embodiments, the second portion 1704 of the liner layer 702 does not exist in the channel region, as Figure 28B shown.

[0165] As Figure 28A and Figure 28BAs shown, an oxygen-containing layer 2803 can be formed around the surface of the first semiconductor layer 106 that can be exposed in the opening 2602 and the surfaces of the exposed substrate portions 102a, 102b, 102c, 102d, 102e. Then, a high-k dielectric layer 2805 is formed on the oxygen-containing layer 2803 in the opening 2602. The oxygen-containing layer 2803 can be an oxide layer, and the high-k dielectric layer 2805 can include the same material as the high-k material 1102. The oxygen-containing layer 2803 and the high-k dielectric layer 2805 can be formed by any suitable process, such as atomic layer deposition. In some embodiments, the oxygen-containing layer 2803 and the high-k dielectric layer 2805 are formed by a conformal process.

[0166] Next, a gate electrode layer 2802 is formed in the opening 2602 and on the high-k dielectric layer 2805. The gate electrode layer 2802 is formed on the high-k dielectric layer 2805 to surround a portion of each first semiconductor layer 106. The gate electrode layer 2802 includes one or more layers of conductive materials, such as polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), tantalum nitride (TaN), nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 2802 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, or other suitable processes, and the gate electrode layer 2802 can also be deposited on the nitrogen-containing layer 2106 ( Figure 26A ). The gate electrode layer 2802 deposited on the nitrogen-containing layer 2106 can be removed by means such as chemical mechanical polishing until the nitrogen-containing layer 2106 is exposed.

[0167] Next, the gate electrode layer 2802 is recessed to a height below the top surface 2810 of the second portion 1708 of the high-k material 1102 of the dielectric feature 1302, as Figure 28A and Figure 28BAs shown. Accordingly, the second portion 1708 of the high-k material 1102 can be located between the two gate electrode layers 2802. The recess process can be any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, the recess process can be a selective dry etching process that substantially does not affect the nitrogen-containing layer 2106, the spacers 1702, and the high-k dielectric layer 2805. After the recess process, some adjacent channel regions can share the gate electrode layer 2802, and other adjacent channel regions can include different gate electrode layers 2802. For example, the channel regions formed from fins 202a and 202b share the gate electrode layer 2802, and the channel regions formed from fins 202b and 202c include different gate electrode layers 2802. As mentioned above, if adjacent channel regions share the gate electrode layer 2802, a single signal (such as current) transmitted to the gate electrode layer 2802 can control two adjacent channel regions. If the gate electrode layer is truncated, independent signals (such as independent currents) can be transmitted to each gate electrode layer 2802 to control each adjacent channel region separately. As Figure 28A and Figure 28B shown, the dielectric feature portion 1302 without the high-k material 1102 is located between the channel regions formed from fins 202d and 202e. To share the gate electrode layer 2802, part of the high-k material 1102 can be removed by the method in Figures 25A to 25C .

[0168] A metal layer 2804 can be formed on the gate electrode layer 2802, and a dielectric material 2806 can be formed on the metal layer 2804 and on the high-k dielectric layer 2805 on the second portion 1708 of the high-k material 1102, as Figure 28A and Figure 28BAs shown. The metal layer 2804 grows on the gate electrode layer 2802 but not on the high-k dielectric layer 2805, and may include any suitable metal, such as fluorine-free tungsten. The dielectric material 2806 may include silicon oxide, hafnium silicide (HfSi), silicon carbonitride, aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride, silicon carbon oxynitride, zirconium nitride (ZrN), or silicon carbonitride. The dielectric material 2806 may be formed by any suitable process such as plasma enhanced chemical vapor deposition. A conductor feature 2808 may be formed through the dielectric material 2806 and in contact with the metal layer 2804. The conductor feature 2808 may include a material having one or more of ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), titanium nitride (TiN), and tantalum nitride (TaN). The conductor feature 2808 may provide a signal such as current to the gate electrode layer 2802 shared by the channel regions formed from fins 202c, 202d, 202e, as Figure 28A and Figure 28B shown. The gate electrode layer 2802 shared by the channel regions formed from fins 202a, 202b may receive signals (not shown) from different conductor features 2808.

[0169] Figure 29A and Figure 29B are cross-sectional views of the source / drain regions of the semiconductor device structure 100 according to some embodiments of the present disclosure. Figure 29A and Figure 29B The semiconductor device structure 100 in Figure 28A and Figure 28B may include the channel regions represented in Figure 29A and Figure 29B As shown, the source / drain epitaxial features 2002 formed from the substrate portions 102a, 102b of fins 202a, 202b merge together, and the source / drain epitaxial features 2002 formed from the substrate portions 102c, 102d of fins 202c, 202d merge together. The source / drain epitaxial features 2002 formed from the substrate portions 102b, 102c of fins 202b, 202c are separated by the dielectric feature 1302, and the source / drain epitaxial features 2002 formed from the substrate portions 102d, 102e of fins 202d, 202e are separated by the dielectric feature 1302. The semiconductor device structure 100 may include a first portion 1703 of the liner layer 702, as Figure 29A shown, or the first portion 1703 of the liner layer 702 may be absent, asFigure 29B The dielectric feature 1302 located between the source / drain epitaxial feature 2002 formed from the substrate portion 102d of the fin 202d and the source / drain epitaxial feature 2002 formed from the substrate portion 102e of the fin 202e includes a first portion 1706 of the high-k dielectric material 1102, while a second portion 1708 of the high-k dielectric material 1102 between the fins 202d and 202e is removed ( Figure 28A 28B). As described above, the dielectric features 1302 can include a separate high-k material 1102 between source / drain regions.

[0170] like Figure 29A , Figure 29B As shown, in some embodiments, a conductor feature 2902 may be formed to penetrate the interlayer dielectric layer 2104 and the contact stop etch stop layer 2102 to contact the source / drain epitaxial feature 2002. The conductor feature 2902 may include the same material as the conductor feature 2808 and may be formed in the same manner as the conductor feature 2808. In some embodiments, a silicide layer (not shown) is formed on the source / drain epitaxial feature 2002, and the conductor feature 2902 is in contact with the silicide.

[0171] Figure 30 According to some embodiments of the present disclosure Figure 28A FIG. 1 is a top view of a semiconductor device structure 100. Figure 30 As shown, three gate electrode layers 2802a, 2802b, and 2802c extend across the fins 202a to 202e. The high dielectric constant material 1102a located between the fins 202b and 202c extends from the first gate electrode layer 2802a through the second gate electrode layer 2802b to the third gate electrode layer 2802c. The high dielectric constant material 1102a may be covered by the mask layer 2302 ( Figure 23A ) protection. The high dielectric constant material 1102b between the fins 202d and 202e does not pass through the second gate electrode layer 2802b. Figure 28A The method described above removes the second portion 1708b of the high-k dielectric material 1102b between the fins 202d and 202e. Therefore, the second gate electrode layer 2802b can be used to control the channel regions of the fins 202d and 202e.

[0172] The present disclosure provides a semiconductor device structure 100, including a first fin 202a having a first substrate portion 102a, a second fin 202b having a second substrate portion 102b adjacent to the first substrate portion 102a, and a third fin 202c having a third substrate portion 102c adjacent to the second substrate portion 102b. A first source / drain epitaxial feature 2002 extending from the first substrate portion 102a may be merged with a second source / drain epitaxial feature 2002 extending from the second substrate portion 102b, and a portion 1703 of the liner layer 702 may be below the merged source / drain epitaxial feature 2002. The dielectric feature 1302 may separate the second source / drain epitaxial feature 2002 from a third source / drain epitaxial feature 2002 extending from the third substrate portion 102c. Some embodiments may achieve advantages. For example, the recessed first portion 1703 of the liner layer 702 allows adjacent source / drain epitaxial features 2002 to merge, to increase device density and reduce resistance.

[0173] An embodiment is a semiconductor device structure. The structure includes a first fin extending from a substrate, and the first fin includes a first substrate portion having a first sidewall. The structure further includes a second fin extending from a substrate adjacent to the first fin, and the second fin includes a second substrate portion having a second sidewall facing the first sidewall. The structure further includes a third fin extending from a substrate adjacent to the second fin, and the third fin includes a third substrate portion. The structure further includes a first source / drain epitaxial feature extending from the first substrate portion, a second source / drain epitaxial feature extending from the second substrate portion, and the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged. The structure further includes a third source / drain epitaxial feature extending from the third substrate portion. The structure further includes a first liner layer having a first distance from a first plane defined by the first sidewall and a second distance from a second plane defined by the second sidewall. The first distance and the second distance are substantially the same, and the merged first source / drain epitaxial feature and the second source / drain epitaxial feature are disposed on the first liner layer. The structure further includes a dielectric feature disposed between the second source / drain epitaxial feature and the third source / drain epitaxial feature.

[0174] In some embodiments, the dielectric feature includes a second liner layer, a low dielectric constant material, and a high dielectric constant material. The low dielectric constant material is disposed on the second liner layer, and the high dielectric constant material is disposed on the second liner layer and the low dielectric constant material.

[0175] In some embodiments, the semiconductor device structure further includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is disposed on the first substrate portion, the second semiconductor layer is disposed on the second substrate portion, and the third semiconductor layer is disposed on the third substrate portion.

[0176] In some embodiments, the dielectric feature is disposed between the second semiconductor layer and the third semiconductor layer.

[0177] In some embodiments, the semiconductor device structure further includes a first gate structure electrode layer and a second gate electrode layer structure. The first gate structure electrode layer surrounds the first semiconductor layer and the second semiconductor layer, and the second gate electrode layer structure surrounds the third semiconductor layer.

[0178] In some embodiments, the high-k material includes a first portion and a second portion. The first portion is disposed between the second source / drain epitaxial feature and the third source / drain epitaxial feature, and the second portion is disposed between the first gate electrode layer source / drain epitaxial feature and the second gate electrode layer source / drain epitaxial feature.

[0179] In some embodiments, the first portion of the first high-k material has a first height, and the second portion of the first high-k material has a second height greater than the first height.

[0180] In some embodiments, the first liner layer includes a first portion and a second portion. The combined first source / drain epitaxial feature and the second source / drain epitaxial feature are disposed on the first portion of the first liner layer, and the second portion of the first liner layer is disposed between the first semiconductor layer and the second semiconductor layer.

[0181] In some embodiments, the first portion of the first liner layer has a first width, and the second portion of the first liner layer has a second width greater than the first width.

[0182] In some embodiments, the first liner layer is not between the first semiconductor layer and the second semiconductor layer.

[0183] Another embodiment is a semiconductor device structure. The structure includes a first fin extending from a substrate, and the first fin includes a first substrate portion and a plurality of first semiconductor layers disposed on the first substrate portion. The structure further includes a second fin extending from the substrate adjacent to the first fin, and the second fin includes a second substrate portion and a plurality of second semiconductor layers disposed on the second substrate portion. The structure further includes a third fin extending from the substrate adjacent to the first fin, and the third fin includes a third substrate portion and a plurality of third semiconductor layers disposed adjacent to the third substrate portion of the first fin. The structure further includes a first source / drain epitaxial feature extending from the first substrate portion, a second source / drain epitaxial feature extending from the second substrate portion, and the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged. The structure further includes a third source / drain epitaxial feature extending from the third substrate portion. The structure further includes a liner layer including a first portion disposed between the first semiconductor layer and the second semiconductor layer. The first portion of the first liner layer has a first width. The structure further includes a dielectric feature disposed between the second semiconductor layer and the third semiconductor layer, and the dielectric feature has a second width greater than the first width.

[0184] In some embodiments, the dielectric feature includes a second liner layer, a low-k material, and discrete high-k materials. The low-k material is disposed on the second liner layer, and the discrete high-k materials are disposed on the second liner layer and the low-k material.

[0185] In some embodiments, in a cross-sectional view of the semiconductor device structure, each discrete high-k material is U-shaped.

[0186] In some embodiments, the semiconductor device structure further includes a first gate structure electrode layer surrounding the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

[0187] In some embodiments, the first liner layer further includes a second portion disposed under the merged first source / drain epitaxial feature and the second source / drain epitaxial feature, and wherein the second portion of the first liner layer has a third width that is less than the first width of the first portion of the first liner layer.

[0188] Another embodiment is a method. The method includes forming a first fin, a second fin, and a third fin from a substrate, forming a first liner layer between the first fin and the second fin, forming a dielectric feature between the second fin and the third fin, and forming a sacrificial gate stack on a portion of the first fin, the second fin, the third fin, and a first portion of the first liner layer. A portion of the first fin, the second fin, the third fin, and a portion of the first liner layer are exposed. The method further includes removing at least a portion of the exposed portions of the first fin, the second fin, and the third fin, and removing at least a portion of the exposed portion of the first liner layer to form a second portion of the first liner layer. The first portion of the first liner layer has a first height, and the second portion of the first liner layer has a second height greater than the first height.

[0189] According to some embodiments, the above method further includes removing the second portion of the first liner layer.

[0190] According to some embodiments, the above method further includes removing the sacrificial gate stack and removing the first portion of the first liner layer, the first portion being disposed under the sacrificial gate stack.

[0191] According to some embodiments, forming the dielectric feature further includes forming a second liner layer between the second fin and the third fin, forming a low-k material on the second liner layer, and forming a high-k material on the second liner layer and the low-k material.

[0192] According to some embodiments, when removing a portion of the exposed portions of the first fin, the second fin, and the third fin, a portion of the high-k material is removed.

[0193] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that, Comprising: a first fin extending from a substrate, wherein the first fin includes a first substrate portion having a first sidewall; a second fin extending from the substrate adjacent to the first fin, wherein the second fin includes a second substrate portion having a second sidewall facing the first sidewall; a third fin extending from the substrate adjacent to the second fin, wherein the third fin includes a third substrate portion; a first source / drain epitaxial feature extending from the first substrate portion; a second source / drain epitaxial feature extending from the second substrate portion, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged together; a third source / drain epitaxial feature extending from the third substrate portion; a first liner layer having a first distance from a first plane defined by the first sidewall and a second distance from a second plane defined by the second sidewall, wherein the first distance and the second distance are substantially the same, and wherein the merged first source / drain epitaxial feature and the second source / drain epitaxial feature are disposed on the first liner layer; and a dielectric feature disposed between the second source / drain epitaxial feature and the third source / drain epitaxial feature.

2. The semiconductor device structure according to claim 1, wherein The dielectric feature comprises: a second liner layer; a low-k material disposed on the second liner layer; and a high-k material disposed on the second liner layer and the low-k material.

3. The semiconductor device structure according to claim 2, wherein, Further comprising: a plurality of first semiconductor layers disposed on the first substrate portion; a plurality of second semiconductor layers disposed on the second substrate portion; and a plurality of third semiconductor layers disposed on the third substrate portion.

4. The semiconductor device structure as described in claim 3, wherein, The dielectric feature is disposed between the second semiconductor layers and the third semiconductor layers.

5. The semiconductor device structure according to claim 4, characterized in that, Further comprising: a first gate electrode layer surrounding the first semiconductor layers and the second semiconductor layers; and a second gate electrode layer surrounding the third semiconductor layers.

6. The semiconductor device structure according to claim 5, wherein, The high-k material comprises: a first portion disposed between the second source / drain epitaxial feature and the third source / drain epitaxial feature; and a second portion disposed between the first gate electrode layer and the second gate electrode layer.

7. The semiconductor device structure according to claim 6, wherein, The first portion of the high-k material has a first height, and the second portion of the high-k material has a second height higher than the first height.

8. The semiconductor device structure according to claim 3, wherein, The first liner layer includes a first portion and a second portion, wherein the merged first source / drain epitaxial feature and the first source / drain epitaxial feature are disposed on the first portion of the first liner layer, and the second portion of the first liner layer is disposed between the first semiconductor layers and the second semiconductor layers.

9. The semiconductor device structure as claimed in claim 8, wherein The first portion of the first liner layer has a first width, and the second portion of the first liner layer has a second width greater than the first width.

10. The semiconductor device structure according to claim 3, wherein, The first liner layer is not between the first semiconductor layers and the second semiconductor layers.

11. A semiconductor device structure, characterized in that, Comprising: a first fin extending from a substrate, wherein the first fin includes a first substrate portion and a plurality of first semiconductor layers disposed on the first substrate portion; A second fin extending from the substrate adjacent to the first fin, wherein the second fin includes a second substrate portion and a plurality of second semiconductor layers disposed on the second substrate portion; A third fin extending from the substrate adjacent to the second fin, wherein the third fin includes a third substrate portion and a plurality of third semiconductor layers disposed on the third substrate portion; A first source / drain epitaxial feature extending from the first substrate portion; A second source / drain epitaxial feature extending from the second substrate portion, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged together; A third source / drain epitaxial feature extending from the third substrate portion; A first liner layer including a first portion disposed between the first semiconductor layers and the second semiconductor layers, wherein the first portion of the first liner layer has a first width; and A dielectric feature disposed between the second semiconductor layers and the third semiconductor layers, wherein the dielectric feature has a second width greater than the first width.

12. The semiconductor device structure according to claim 11, wherein The dielectric feature includes: A second liner layer; A low dielectric constant material disposed on the second liner layer; and A plurality of separate high dielectric constant materials disposed on the second liner layer and the low dielectric constant material.

13. The semiconductor device structure according to claim 12, wherein, In a cross-sectional view of the semiconductor device structure, each of the separate high dielectric constant materials is U-shaped.

14. The semiconductor device structure according to claim 13, wherein Further comprising: A first gate electrode layer surrounding the first semiconductor layers, the second semiconductor layers, and the third semiconductor layers.

15. The semiconductor device structure according to claim 11, wherein The first liner layer further includes a second portion disposed under the merged first source / drain epitaxial feature and the second source / drain epitaxial feature, and wherein the second portion of the first liner layer has a third width that is less than the first width of the first portion of the first liner layer.

16. A method of manufacturing a semiconductor device structure, characterized in that, Comprising: Forming a first fin, a second fin, and a third fin from a substrate; Forming a liner layer, wherein a first portion of the liner layer is formed between the first fin and the second fin, and a second portion of the liner layer is formed between the second fin and the third fin; Forming a low dielectric constant material on the second portion of the liner layer between the second fin and the third fin; Forming a high dielectric constant material on the second portion of the liner layer and the low dielectric constant material, and the high dielectric constant material contacts the second portion of the liner layer and the low dielectric constant material; Forming a sacrificial gate stack on a first portion of the first fin, the second fin, the third fin, and a third portion of the liner layer, wherein a second portion of the first fin, the second fin, the third fin, and a fourth portion of the liner layer are exposed; Removing a portion of the exposed second portion of the first fin, the second fin, and the third fin; Recessing the exposed fourth portion of the liner layer; And A first source / drain epitaxial feature is formed from the first fin, and a second source / drain epitaxial feature is formed from the second fin, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged and disposed on the fourth portion of the liner layer.

17. The method according to claim 16, wherein It further includes removing the fourth portion of the liner layer.

18. The method according to claim 16, characterized in that, It further includes: removing the sacrificial gate stack; and removing the third portion of the liner layer, which is disposed under the sacrificial gate stack.

19. The method according to claim 16, wherein The second portion of the liner layer, the low-k dielectric material, and the high-k dielectric material between the second fin and the third fin form a dielectric feature.

20. The method according to claim 19, wherein When removing the exposed second portions of the first fin, the second fin, and the third fin, a portion of the high-k dielectric material is removed.

21. A method of manufacturing a semiconductor device structure, characterized in that, It includes: forming a first fin, a second fin, and a third fin from a substrate; filling a first trench between the first fin and the second fin with a first liner layer; depositing a second liner layer between the second fin and the third fin, wherein the first liner layer and the second liner layer are deposited simultaneously; depositing a low-k dielectric material on the second liner layer between the second fin and the third fin; depositing a high-k dielectric material on the second liner layer and the low-k dielectric material, and the high-k dielectric material contacts the second liner layer and the low-k dielectric material, wherein the second liner layer, the low-k dielectric material, and the high-k dielectric material fill a second trench between the second fin and the third fin; removing a portion of the first fin, the second fin, and the third fin; recessing a first portion of the first liner layer; recessing a first portion of the high-k dielectric material; and forming a first source / drain epitaxial feature, a second source / drain epitaxial feature, and a third source / drain epitaxial feature, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged and disposed on the first portion of the first liner layer, and the second source / drain epitaxial feature and the third source / drain epitaxial feature are separated by the second liner layer, the low-k dielectric material, and the high-k dielectric material.

22. The method according to claim 21, wherein The first portion of the first liner layer is recessed by performing a first etching process and a second etching process.

23. The method according to claim 21, wherein It further includes forming a sacrificial gate stack on a second portion of the first liner layer and a second portion of the high-k dielectric material before removing the portion of the first fin, the second fin, and the third fin.

24. The method according to claim 23, wherein The first portion of the first liner layer is recessed to reduce a width of the first portion of the first liner layer, and the width of the first portion of the first liner layer is less than a width of the second portion of the first liner layer.

25. The method according to claim 24, wherein The first portion of the first liner layer is recessed to reduce a height of the first portion of the first liner layer, and the height of the first portion of the first liner layer is less than a height of the second portion of the first liner layer.

26. The method according to claim 25, wherein The height of the first portion of the first liner layer ranges from 0.5 nanometer to 15 nanometers.

27. The method according to claim 23, wherein Indent the first portion of the high-k dielectric material to reduce a height of the first portion of the high-k dielectric material, and the height of the first portion of the high-k dielectric material is less than a height of a second portion of the high-k dielectric material.

28. The method according to claim 27, wherein Further include forming a contact etch stop layer on the first source / drain epitaxial feature, the second source / drain epitaxial feature, the third source / drain epitaxial feature, and the first portion of the high-k dielectric material.

29. A method of manufacturing a semiconductor device structure, characterized in that, Include: Form a first fin, a second fin, and a third fin from a substrate; Deposit a first liner layer between the first fin and the second fin; Form a dielectric feature between the second fin and the third fin; Form a sacrificial gate stack on a first portion of the first fin, the second fin, the third fin, a first portion of the first liner layer, and a first portion of the dielectric feature, wherein a second portion of the first fin, the second fin, the third fin, a second portion of the first liner layer, and a second portion of the dielectric feature are exposed; Remove the second portion of the first fin, the second fin, and the third fin; Indent the second portion of the first liner layer to a first height; Indent the second portion of the dielectric feature to a second height; Remove the sacrificial gate stack; and Indent a portion of the first portion of the dielectric feature to a third height, wherein a remaining portion of the first portion has a fourth height greater than the second height, and the second height is greater than the third height.

30. The method according to claim 29, characterized in that, Forming the dielectric feature includes: Form a second liner layer between the second fin and the third fin; Form a low-k dielectric material on the second liner layer; Form a high-k dielectric material on the second liner layer and the low-k dielectric material.

31. The method according to claim 30, wherein, Indenting the second portion of the dielectric feature includes indenting a first portion of the high-k dielectric material.

32. The method according to claim 31, wherein, Indenting the portion of the first portion of the dielectric feature includes removing a second portion of the high-k dielectric material.

33. The method according to claim 32, characterized in that, After removing the second portion of the high-k dielectric material, a remaining portion of the high-k dielectric material has a U-shaped cross-section.

34. The method according to claim 29, wherein Further include forming a gate electrode layer on the first portion of the dielectric feature.

35. The method according to claim 34, wherein Further include indenting the gate electrode layer to a height lower than a top surface of the first portion of the dielectric feature.

36. A method of manufacturing a semiconductor device structure, characterized in that, Include: Form a first fin, a second fin, and a third fin from a substrate; Form a liner layer, wherein a first portion of the liner layer is formed between the first fin and the second fin, and a second portion of the liner layer is formed between the second fin and the third fin; Form a low-k dielectric material on the second portion of the liner layer between the second fin and the third fin; Form a high-k dielectric material on the second portion of the liner layer and the low-k dielectric material, and the high-k dielectric material contacts the second portion of the liner layer and the low-k dielectric material; Form a sacrificial gate stack on a first portion of the first fin, the second fin, the third fin, and a third portion of the liner layer, wherein a second portion of the first fin, the second fin, the third fin, and a fourth portion of the liner layer are exposed; Remove a portion of the exposed second part of the first fin, the second fin, and the third fin; Remove the fourth part of the exposed liner layer; and Form a first source / drain epitaxial feature from the first fin and a second source / drain epitaxial feature from the second fin, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature are merged.

37. The method according to claim 36, wherein Further comprising: Remove the sacrificial gate stack; and Remove the first part of the liner layer located under the sacrificial gate stack.

38. The method according to claim 37, wherein Further comprising forming a cladding layer surrounding the first fin, the second fin, and the third fin before forming the liner layer.

39. The method according to claim 38, wherein The first part of the liner layer and the cladding layer fill a space between the first fin and the second fin.

40. The method according to claim 39, characterized in that Further comprising recessing the low dielectric constant material, the second part of the liner layer, and the first part of the liner layer, wherein the first part of the liner layer and the second part of the liner layer are recessed to different heights.

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