Radiation detection device and preparation method thereof

Abstract

Disclosed herein is a device for detecting radiation and a method for preparing the same. The method may include forming a recess (104) in a semiconductor substrate (102), wherein a portion (107) of the semiconductor substrate (102) extends into and is surrounded by the recess (104); forming a semiconductor single crystal (106) in the recess (104), wherein the semiconductor single crystal (106) has a composition different from that of the semiconductor substrate (102); forming a first doped semiconductor region (108) in the semiconductor substrate (102); forming a second doped semiconductor region (109) in the semiconductor substrate (102); wherein the first doped semiconductor region (108) and the second doped semiconductor region (109) form a p-n junction separating the portion (107) from the rest of the semiconductor substrate (102).

Description

Technical field

[0001] The disclosure herein relates to radiation detection devices and methods of making the same. [Background Technology]

[0002] A radiation detector is a device that measures properties of radiation. Examples of these properties may include the spatial distribution of the radiation's intensity, phase, and polarization. The radiation may be radiation that has interacted with an object. For example, the radiation measured by a radiation detector may be radiation that has penetrated or reflected from an object. The radiation may be electromagnetic radiation, such as infrared light, visible light, ultraviolet light, X-rays, or gamma rays. Radiation may also be of other types, such as alpha and beta rays.

[0003] One type of radiation detector is based on the interaction between radiation and semiconductors. For example, this type of radiation detector may have a semiconductor layer that absorbs radiation and generates charge carriers (e.g., electrons and holes) and a circuit for detecting the charge carriers.

[0004] Cadmium zinc telluride (CdZnTe or Cd 1-x Zn x Te) is a direct-gap semiconductor and an excellent candidate for room-temperature radiation detection. CdZnTe is an alloy of zinc telluride and CdTe, where the x value is the molar concentration of zinc in CdZnTe. CdZnTe, whose x value ranges from 0.04 to 0.2, is considered a promising prospect for detector development because it can process and improve certain properties of CdTe. For example, both CdTe and CdZnTe have a large atomic number, which gives the material excellent braking power, resulting in high absorption efficiency for incident X-rays and gamma rays; and has a large band gap (e.g., 1.5eV-1.6eV), which can be used for room-temperature detectors; it also has a high resistivity to achieve a good signal-to-noise ratio for radiation detectors. At the same time, due to the incorporation of zinc, CdZnTe has a larger band gap than CdTe, thereby increasing the maximum achievable resistivity.

[0005] Practical uses of CdTe and CdZnTe detectors cover a wide range of applications, such as medical and industrial imaging, industrial metrology and non-destructive testing, security and surveillance, nuclear safeguards and non-proliferation, and astrophysics. [Summary of the invention]

[0006] A method is disclosed herein, comprising: forming a recess in a semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess; forming a semiconductor single crystal in the recess, the semiconductor single crystal having a composition different from that of the semiconductor substrate; forming a first doped semiconductor region in the semiconductor substrate; forming a second doped semiconductor region in the semiconductor substrate; wherein the first doped semiconductor region and the second doped semiconductor region form a pn junction separating the portion of the semiconductor substrate from a remainder of the semiconductor substrate.

[0007] According to an embodiment, the first doped semiconductor region surrounds the second doped semiconductor region.

[0008] According to an embodiment, the second doped semiconductor region is in electrical contact with the portion of the semiconductor substrate.

[0009] According to an embodiment, forming the second doped semiconductor region includes doping a portion of the first doped semiconductor region.

[0010] According to an embodiment, the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the semiconductor single crystal and the semiconductor substrate.

[0011] According to an embodiment, the second doped semiconductor region is coextensive with the first doped semiconductor region.

[0012] According to an embodiment, forming the recess includes forming a mask on the semiconductor substrate and etching a region of the semiconductor substrate not covered by the mask.

[0013] According to an embodiment, the mask comprises metal, silicon nitride, silicon dioxide or carbon.

[0014] According to an embodiment, etching the region is performed by wet etching, dry etching or a combination thereof.

[0015] According to an embodiment, the method disclosed herein further includes polishing the semiconductor substrate or the semiconductor single crystal so that the semiconductor single crystal and the semiconductor substrate are coextensive.

[0016] According to an embodiment, the semiconductor substrate includes silicon, germanium, GaAs or a combination thereof.

[0017] According to an embodiment, the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal.

[0018] According to an embodiment, the recess does not contain any semiconductor material other than the semiconductor single crystal after the semiconductor single crystal is formed.

[0019] According to an embodiment, the recess does not contain a semiconductor polycrystal after forming the semiconductor single crystal.

[0020] According to an embodiment, the recess is in the shape of a frustum, a prism, a pyramid, a cuboid or a cylinder.

[0021] According to an embodiment, forming the semiconductor single crystal in the recess includes depositing semiconductor particles into the recess, forming a melt by melting the semiconductor particles, and recrystallizing the melt in the recess.

[0022] According to an embodiment, recrystallizing the melt in the recess involves cooling the melt at a rate such that the melt recrystallizes into a single crystal.

[0023] According to an embodiment, cooling the melt is performed by moving the melt from a region having a temperature higher than or equal to a melting point of the semiconductor particles to another region having a temperature lower than the melting point.

[0024] According to an embodiment, forming the semiconductor single crystal includes using a vapor-phase precursor.

[0025] According to an embodiment, the method disclosed herein further includes bonding the semiconductor substrate to another substrate including an electronic system therein or thereon, wherein the electronic system is electrically connected to the second doped semiconductor region and is configured to process electrical signals generated in the semiconductor substrate.

[0026] Disclosed herein is a method comprising: forming a through hole in a semiconductor layer directly supported on an electrically insulating layer, wherein a portion of the semiconductor layer remains in and is surrounded by the through hole; forming a semiconductor single crystal in the through hole, the semiconductor single crystal having a composition different from that of the semiconductor layer; forming an opening through the electrically insulating layer such that the portion of the semiconductor layer is exposed in the opening; and forming an electrode in the opening, the electrode being in electrical contact with the portion of the semiconductor layer.

[0027] According to an embodiment, forming the through hole includes forming a mask on the semiconductor layer and etching a region of the semiconductor layer not covered by the mask.

[0028] According to an embodiment, the mask comprises metal, silicon nitride, silicon dioxide or carbon.

[0029] According to an embodiment, etching the region is performed by wet etching, dry etching or a combination thereof.

[0030] According to an embodiment, the method disclosed herein further includes polishing the semiconductor layer or the semiconductor single crystal so that the semiconductor single crystal and the semiconductor layer are coextensive.

[0031] According to an embodiment, the semiconductor layer includes silicon, germanium, GaAs or a combination thereof.

[0032] According to an embodiment, the electrically insulating layer includes oxide, nitride or oxynitride.

[0033] According to an embodiment, the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal.

[0034] According to an embodiment, the through-hole does not include other semiconductor materials except the semiconductor single crystal after the semiconductor single crystal is formed.

[0035] According to an embodiment, the through hole does not contain semiconductor polycrystal after forming the semiconductor single crystal.

[0036] According to an embodiment, the through hole has a shape of a frustum, a prism, a pyramid, a cuboid or a cylinder.

[0037] According to an embodiment, forming the semiconductor single crystal in the through-hole includes depositing semiconductor particles into the through-hole, forming a melt by melting the semiconductor particles, and recrystallizing the melt in the through-hole.

[0038] According to an embodiment, recrystallizing the melt in the through-hole involves cooling the melt at a rate such that the melt recrystallizes into a single crystal.

[0039] According to an embodiment, cooling the melt is performed by moving the melt from a region having a temperature higher than or equal to a melting point of the semiconductor particles to another region having a temperature lower than the melting point.

[0040] According to an embodiment, forming the semiconductor single crystal includes using a vapor-phase precursor.

[0041] According to an embodiment, the method disclosed herein further includes bonding the electrically insulating layer to an electronic layer, the electronic layer including a layer electrically connected to the electrode and configured to process an electrical signal generated in the semiconductor layer.

[0042] Disclosed herein is a radiation detector comprising: a semiconductor substrate; a recess in the semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess; a semiconductor single crystal in the recess, the semiconductor single crystal having a composition different from that of the semiconductor substrate; a first doped semiconductor region in the semiconductor substrate; and a second doped semiconductor region in the semiconductor substrate; wherein the first doped semiconductor region and the second doped semiconductor region form a pn junction separating the portion of the semiconductor substrate from the remainder of the semiconductor substrate.

[0043] According to an embodiment, the radiation detector is configured to absorb radiation particles incident on the semiconductor single crystal and generate carriers.

[0044] According to an embodiment, the first doped semiconductor region surrounds the second doped semiconductor region.

[0045] According to an embodiment, the second doped semiconductor region is in electrical contact with the portion of the semiconductor substrate.

[0046] According to an embodiment, the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the semiconductor single crystal and the semiconductor substrate.

[0047] According to an embodiment, the second doped semiconductor region is coextensive with the first doped semiconductor region.

[0048] According to an embodiment, the semiconductor single crystal and the semiconductor substrate are coextensive.

[0049] According to an embodiment, the semiconductor substrate includes silicon, germanium, GaAs or a combination thereof.

[0050] According to an embodiment, the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal.

[0051] According to an embodiment, the recess does not contain any semiconductor material other than the semiconductor single crystal after the semiconductor single crystal is formed.

[0052] According to an embodiment, the recess does not contain a semiconductor polycrystal after forming the semiconductor single crystal.

[0053] According to an embodiment, the recess is in the shape of a frustum, a prism, a pyramid, a cuboid or a cylinder.

[0054] According to an embodiment, the radiation detector disclosed herein further includes an electronics layer bonded to the semiconductor substrate, the electronics layer including an electronics system electrically connected to the second doped semiconductor region and configured to process an electrical signal generated in the semiconductor substrate.

[0055] Disclosed herein is a radiation detector comprising: an electrically insulating layer; a semiconductor layer directly supported on the electrically insulating layer; a through-hole in the semiconductor layer, wherein a portion of the semiconductor layer extends into and is surrounded by the through-hole; a semiconductor single crystal in the through-hole, the semiconductor single crystal having a different composition from that of the semiconductor layer; and an electrode passing through the electrically insulating layer, the electrode being in electrical contact with the portion of the semiconductor layer.

[0056] According to an embodiment, the semiconductor layer includes silicon, germanium, GaAs or a combination thereof.

[0057] According to an embodiment, the electrically insulating layer includes oxide, nitride or oxynitride.

[0058] According to an embodiment, the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal.

[0059] According to an embodiment, the through-hole does not include other semiconductor materials except the semiconductor single crystal after the semiconductor single crystal is formed.

[0060] According to an embodiment, the through hole does not contain semiconductor polycrystal after forming the semiconductor single crystal.

[0061] According to an embodiment, the through hole has a shape of a frustum, a prism, a pyramid, a cuboid or a cylinder.

[0062] According to an embodiment, the radiation detector disclosed herein further includes an electronic layer bonded to the electrically insulating layer, the electronic layer including an electronic system electrically connected to the electrodes and configured to process the electrical signals generated in the semiconductor layer.

Brief Description of the Drawings

[0063] Figure 1 A cross-sectional view schematically illustrates a radiation detector according to an embodiment.

[0064] Figure 2A A detailed cross-sectional view of the radiation detector according to an embodiment is schematically shown.

[0065] Figure 2B A detailed cross-sectional view of the radiation detector according to an embodiment is schematically shown.

[0066] Figure 2C-2E A top view of the radiation absorbing layer according to an embodiment is schematically shown.

[0067] Figure 3 Schematic diagram of the formation according to the embodiment Figure 2A process in the radiation absorbing layer.

[0068] Figure 4 Schematic diagram of the formation according to the embodiment Figure 2A The process of forming a concave portion of the radiation absorbing layer.

[0069] Figure 5 Schematically illustrating the Figure 2A A process of forming a semiconductor single crystal in the recessed portion of the radiation absorbing layer.

[0070] Figure 6 Schematic diagram of the formation according to the embodiment Figure 2B process in the radiation absorbing layer.

[0071] Figure 7 Schematic diagram of the formation according to the embodiment Figure 2B The process of forming a through-hole in the radiation absorbing layer.

[0072] Figure 8 Schematically illustrating the Figure 2A A process of forming a semiconductor single crystal in the through hole of the radiation absorbing layer.

[0073] Figure 9A and Figure 9B Schematically illustrating bonding between the radiation absorbing layer and the electronic layer to form Figure 2A and Figure 2B Radiation detector shown.

[0074] Figure 10A and Figure 10B Component diagrams of the electronic system according to embodiments are respectively shown.

[0075] Figure 11 The temporal profile of the voltage of the electrodes or the electrical contacts according to an embodiment is schematically shown. [Specific implementation method]

[0076] Figure 1 A cross-sectional view of a radiation detector 100 according to an embodiment is schematically shown. The radiation detector 100 may include a radiation absorbing layer 110 configured to absorb incident radiation and generate an electrical signal from the incident radiation, and an electronic layer 120 (e.g., an ASIC) for processing or analyzing the electrical signal generated in the radiation absorbing layer 110. The radiation detector 100 may or may not include a scintillator. The radiation absorbing layer 110 may include a semiconductor material such as silicon, germanium, GaAs, CdTe, CdZnTe, or a combination thereof. The semiconductor may have a high mass attenuation coefficient for the radiation of interest.

[0077] Figure 2AA schematic diagram shows a detailed cross-sectional view of a radiation detector 100 according to an embodiment. The radiation detector 100 includes a semiconductor substrate 102 and a recess 104 in the semiconductor substrate 102. A portion 107 of the semiconductor substrate 102 extends into and is surrounded by the recess 104. The radiation detector 100 includes a semiconductor single crystal 106 in the recess 104. The radiation detector 100 also includes a first doped semiconductor region 108 and a second doped semiconductor region 109 in the semiconductor substrate 102. The first doped semiconductor region 108 and the second doped semiconductor region 109 form a pn junction that separates the portion 107 of the semiconductor substrate 102 from the remainder of the semiconductor substrate 102. In other words, every electrical path between the portion 107 of the semiconductor substrate 102 and the remainder of the semiconductor substrate 102, as well as throughout the semiconductor substrate 102, traverses the pn junction. The portion 107 of the semiconductor substrate 102 can be in electrical contact with the second doped semiconductor region 109. The semiconductor substrate 102 (including the portion 107 of the semiconductor substrate 102 ), the semiconductor single crystal 106 , the first doped semiconductor region 108 , and the second doped semiconductor region 109 may be in the radiation absorbing layer 110 .

[0078] The semiconductor substrate 102 may include a semiconductor material such as silicon, germanium, GaAs, a combination thereof, or other suitable semiconductors. The semiconductor substrate 102 may be an extrinsic semiconductor (ie, doped with an electron donor or an electron acceptor).

[0079] The second doped semiconductor region 109 may be surrounded by the first doped semiconductor region 108. The second doped semiconductor region 109 does not need to be centered in the first doped semiconductor region 108. The first doped semiconductor region 108 may extend from the surface 102b of the semiconductor substrate 102 to the interface 106b between the semiconductor single crystal 106 and the semiconductor substrate 102. The second doped semiconductor region 109 may be coextensive with the first doped semiconductor region 108, for example, in a direction perpendicular to the semiconductor substrate 102.

[0080] The portion 107 of the semiconductor substrate 102 may be cylindrical or prismatic (e.g., rectangular or triangular). The portion 107 of the semiconductor substrate 102 may have a height equal to, greater than, or less than the height of the recess 104 (i.e., a dimension perpendicular to the semiconductor substrate 102). The portion 107 of the semiconductor substrate 102 may have a height of several micrometers. The portion 107 of the semiconductor substrate 102 may have the same doping type as the second doped semiconductor region 109 (e.g., both are n-type or both are p-type), but may have a doping type opposite to that of the remainder of the semiconductor substrate 102 (e.g., the portion 107 of the semiconductor substrate 102 is n-type, while the remainder of the semiconductor substrate 102 is p-type, or vice versa).

[0081] In an embodiment, the recess 104 includes one and only one semiconductor single crystal 106. For example, the recess 104 does not contain any other semiconductor material besides the semiconductor single crystal 106. For example, the recess 104 does not contain any semiconductor polycrystal. The semiconductor single crystal 106 can be coextensive with the semiconductor substrate 102 (i.e., the surface 106a of the semiconductor single crystal 106 can be coextensive with the surface 102a of the semiconductor substrate 102). The semiconductor single crystal 106 has a different composition than the semiconductor substrate 102. That is, the semiconductor single crystal 106 differs from the semiconductor substrate 102 not only in doping. The semiconductor single crystal 106 is not formed by doping the semiconductor substrate 102. For example, if the semiconductor substrate 102 is doped silicon, the semiconductor single crystal 106 is not doped silicon or intrinsic silicon. The semiconductor single crystal 106 can be a CdZnTe single crystal, a CdTe single crystal, or another suitable single crystal that can absorb incident radiation particles and generate carriers. The semiconductor single crystal 106 may be thick enough to have a sufficient absorption (e.g., >80% or >90%) of incident particles of radiation of interest (e.g., X-ray photons). The semiconductor single crystal 106 is in electrical contact with the portion 107 of the semiconductor substrate 102 and the remainder of the semiconductor substrate 102.

[0082] When radiation strikes the radiation-absorbing layer 110, the semiconductor single crystal 106 may absorb the incident radiation particle and generate one or more charge carriers through several mechanisms. One radiation particle may generate between 1 and 100,000 charge carriers. These charge carriers may include electrons and holes. Under the electric field between the portion 107 of the semiconductor substrate 102 and the remainder of the semiconductor substrate 102, these charge carriers may drift to the sidewalls 104 b of the recess 104 and the portion 107 of the semiconductor substrate 102. For example, the holes may drift to the sidewalls 104 b, and the electrons may drift to the portion 107 of the semiconductor substrate 102.

[0083] In an embodiment, the pn junction formed by the first doped semiconductor region 108 and the second doped semiconductor region 109 can be under a reverse bias during operation of the radiation detector 100. This reverse bias can be used to establish an electric field between the portion 107 and the remainder of the semiconductor substrate 102. The pn junction under the reverse bias substantially blocks current flow through the pn junction, but allows current to flow between the portion 107 and the electronic layer 120 through the second doped semiconductor region 109.

[0084] Figure 2B A detailed cross-sectional view of a radiation detector 190 according to an embodiment is schematically shown. The radiation detector 190 includes an electrical insulator layer 198, a semiconductor layer 192 directly supported on the electrical insulator layer 198, and a through-hole 194 in the semiconductor layer 192. A portion 197 of the semiconductor layer 192 extends into and is surrounded by the through-hole 194. The radiation detector 190 includes a semiconductor single crystal 196 in the through-hole 194. The radiation detector 190 also includes an electrode 199 in (e.g., extending through) the electrical insulator layer 198 and in electrical contact with the portion 197. The semiconductor layer 192 (including the portion 197), the semiconductor single crystal 196, the electrical insulator layer 198, and the electrode 199 may be included in a radiation absorbing layer 191.

[0085] The semiconductor layer 192 may include a semiconductor material such as silicon, germanium, GaAs, or a combination thereof. The semiconductor layer 192 may be an extrinsic semiconductor (ie, doped with an electron donor or an electron acceptor).

[0086] The electrical insulator layer 198 may be an oxide, a nitride, an oxynitride, or other suitable materials.

[0087] The portion 197 may be cylindrical or prism-shaped (e.g., rectangular or triangular). The portion 197 may have a height equal to, greater than, or shorter than the height of the through-hole 194 (i.e., a dimension perpendicular to the semiconductor layer 192). The portion 197 may have a height of several micrometers.

[0088] In an embodiment, the through hole 194 has one and only one semiconductor single crystal 196. For example, the through hole 194 does not contain any other semiconductor material besides the semiconductor single crystal 196. For example, the through hole 194 does not contain any semiconductor polycrystalline. The semiconductor single crystal 196 can be coextensive with the semiconductor layer 192 (i.e., the surface 196a of the semiconductor single crystal 196 can be coextensive with the surface 192a of the semiconductor layer 192). The semiconductor single crystal 196 has a different composition than the semiconductor layer 192. That is, the semiconductor single crystal 196 is different from the semiconductor layer 192 not only in terms of doping. The semiconductor single crystal 196 is not formed by doping the semiconductor layer 192. For example, if the semiconductor layer 192 is doped silicon, the semiconductor single crystal 196 is not doped silicon or intrinsic silicon. The semiconductor single crystal 196 can be a CdZnTe single crystal, a CdTe single crystal, or another suitable single crystal that can absorb radiation particles incident thereon and generate carriers. The semiconductor single crystal 196 can be of sufficient thickness to have sufficient absorption (e.g., >80% or >90%) of incident particles of radiation of interest (e.g., X-ray photons), and is in electrical contact with the portion 197 and the remainder of the semiconductor layer 192.

[0089] The electrode 199 may comprise a conductive material such as a metal (e.g., gold, copper, aluminum, platinum, etc.) or any other suitable conductive material (e.g., a doped semiconductor). The electrode 199 may be embedded in the electrical insulator layer 198 or may extend through the entire thickness of the electrical insulator layer 198.

[0090] When the radiation strikes the radiation absorbing layer 191, the semiconductor single crystal 196 may absorb the incident radiation particle and generate one or more carriers through several mechanisms. One radiation particle may generate 1 to 100,000 carriers. These carriers may include electrons and holes. Under the electric field between the portion 197 and the rest of the semiconductor layer 192, the carriers may drift to the sidewall 194b of the through-hole 194 and the portion 197. For example, the hole may drift to the sidewall 194b, and the electron may drift to the portion 197.

[0091] The recess 104 and the through-hole 194 may have a frustum, a prism, a pyramid, a cuboid, a cube, a cylinder, or other suitable shapes. The detector 100 or the radiation detector 190 may have multiple copies of the recess 104 or the through-hole 194, respectively, which may be arranged in a rectangular array, a honeycomb array, a hexagonal array, or any other suitable array. Figure 2C-2E Schematic top view of several examples of the radiation detector 100 having duplicates of the recess 104 or the through hole 194 or the radiation detector 190 having duplicates of the recess 104 or the through hole 194, which have various shapes and arrangements. The spacing between the duplicates (e.g., the shortest distance between adjacent duplicates) can be less than 10 μm, less than 20 μm, or less than 30 μm. The surface area of ​​each of the duplicates can be between 1 and 10,000 μm. 2 or any other suitable size.

[0092] The electronic layer 120 may include an electronic system 121 configured to process the electrical signals generated by the carriers collected on the portion 107 or the portion 197. The electronic system 121 may include analog circuits such as filter networks, amplifiers, integrators, and comparators, or digital circuits such as microprocessors and memory. The electronic system 121 may include one or more ADCs. The electronic system 121 may be electrically connected to the portion 107 via vias 131 and the second doped semiconductor region 109, or may be electrically connected to the portion 197 via vias 131 and the electrode 199. The spaces between the vias may be filled with a filler material 130, which may increase the mechanical stability of the connection between the electronic layer 120 and the radiation absorbing layer 110. Other bonding techniques may also be used to connect the electronic system 121 to the portion 107 or the portion 197 without the use of vias.

[0093] Figure 3 A process of forming the radiation absorbing layer 200 according to an embodiment is schematically illustrated.

[0094] In step 1010, according to an embodiment, a recess 204 is formed in a semiconductor substrate 210. A portion 207 of the semiconductor substrate 210 extends into the recess 204 and is surrounded by the recess 204. The recess 204 may be used as Figure 2A The recess 104 in the portion 207 can be used as Figure 2A in the portion 107.

[0095] In step 1020, a semiconductor single crystal 206 is formed in the recess 204. The semiconductor single crystal 206 may have a composition different from that of the semiconductor substrate 210. That is, the semiconductor single crystal 206 is different from the semiconductor substrate 210 in terms of doping. The semiconductor single crystal 206 may be used as Figure 2A The semiconductor single crystal 106 of the radiation absorbing layer 110.

[0096] In step 1030 , a first doped semiconductor region 218 is formed in the semiconductor substrate 210 .

[0097] In step 1040, a second doped semiconductor region 219 is formed in the semiconductor substrate 210. The first doped semiconductor region 218 and the second doped semiconductor region 219 form a pn junction that separates the portion 207 from the rest of the semiconductor substrate 210. The first doped semiconductor region 218 may surround the second doped semiconductor region 219. The second doped semiconductor region 219 may be in electrical contact with the portion 207.

[0098] The second doped semiconductor region 219 can be formed by doping a portion of the first doped semiconductor region 218. The first doped semiconductor region 218 can be formed by doping the semiconductor substrate 210 with a p-type or n-type dopant. The first doped semiconductor region 218 can extend from the surface 210a of the semiconductor substrate 210 to the interface 206a between the semiconductor single crystal 206 and the semiconductor substrate 210. The second doped semiconductor region 219 can be coextensive with the first doped semiconductor region 218. The doped semiconductor region 219 can be formed by doping the semiconductor substrate 210 with a p-type or n-type dopant, and the dopant used is opposite to the dopant used to form the first doped semiconductor region 218. For example, if the first doped semiconductor region 218 is formed by doping the semiconductor substrate 210 with a p-type dopant, the second doped semiconductor region 219 can be formed by doping the semiconductor substrate 210 with an n-type dopant, and vice versa.

[0099] In an embodiment, forming the recess 204 may include forming a mask 203 on the semiconductor substrate 210, and etching an area of ​​the semiconductor substrate 210 not covered by the mask 203, such as Figure 4As shown in steps 1011-1014. The mask 203 can be formed on the surface 210a of the semiconductor substrate 210, and the semiconductor substrate 210 can include a semiconductor material such as silicon, germanium, GaAs or a combination thereof. As shown in step 1013a or step 1013b, the mask 203 can be used as an etching mask for forming the recess 204. The mask 203 can include materials such as silicon dioxide, silicon nitride or metal (e.g., aluminum, chromium). The thickness of the mask 203 can be determined based on the depth of the recess 204 and the etching selectivity (i.e., the ratio of the etching rate of the mask 203 and the semiconductor substrate 210). In an embodiment, the mask 203 can have a thickness of several microns. The mask 203 can be formed on the surface 210a by various techniques, such as physical vapor deposition, chemical vapor deposition, spin coating, sputtering or any other suitable process.

[0100] In step 1012, as shown in the cross-sectional view, the mask 203 is patterned to have openings therein that expose the semiconductor substrate 210. The shape and position of the openings correspond to the shape and position of the footprints of the recesses 204 and other recesses formed in step 1013a or step 1013b. If the openings have a square shape (as shown in the top view in step 1012) and are arranged in a rectangular array, the footprints of the recesses 204 and other recesses also have a square shape and are arranged in a rectangular array. The formation of the pattern on the mask 203 can involve a photolithography process or any other suitable process. For example, a resist layer can first be deposited (e.g., by spin coating) on ​​the surface of the mask 203, and then photolithography can be performed to form the openings. The resolution of the photolithography is limited by the wavelength of the radiation used. Lithography tools using deep ultraviolet (DUV) light with wavelengths of approximately 248nm and 193nm can reduce the minimum feature size to approximately 50nm. Electron beam lithography tools use electron energies between 1 keV and 50 keV, capable of reducing minimum feature sizes to a few nanometers. In step 1013a or step 1013b, the recess 204 and other recesses can be formed in the surface 210a of the semiconductor substrate 210 by etching the portion of the semiconductor substrate 210 not covered by the mask 203 to a desired depth. The height of the portion 207 can be less than or equal to the depth of the recess 204. The recess 204 can have a frustum, prism, pyramid, cuboid, cube, or cylindrical shape. In the example of step 1013a, the recess 204 has a pyramidal shape; in the example of step 1013b, the recess 204 has a cuboid shape. The recess 204 can have a smooth surface.

[0101] In an embodiment, etching of a portion of the semiconductor substrate 210 can be performed by wet etching, dry etching, or a combination thereof. Wet etching is an etching process using a liquid etchant. The semiconductor substrate 210 can be immersed in an etchant liquid, and the area not protected by the mask can be removed. The size and shape of the recess 204 can be defined not only by the size and shape of the opening of the mask 203, but also by the material of the semiconductor substrate 210, the liquid chemicals or etchants used, the etching rate and duration, etc. The semiconductor substrate 210 can be a silicon substrate, and the recess 204 can be formed by anisotropic wet etching using an etchant such as potassium hydroxide (KOH), ethylenediaminecatechol (EDP), tetramethylammonium hydroxide (TMAH), etc. During the anisotropic wet etching of the silicon substrate, the liquid etchant can etch the silicon substrate at different rates depending on the silicon crystal plane exposed to the etchant, thereby forming recesses 204 with different shapes and sizes. In the example of step 1013a, when the surface 210a is a silicon crystal plane (100), a wet etchant such as KOH can be used to form a pyramid-shaped recess 204 having flat and angled etched walls. In the example of step 1013b, when the surface 210a is a silicon crystal plane (110), a wet etchant such as KOH can be used to form a rectangular parallelepiped recess 204.

[0102] In step 1014 , the mask 203 may be removed after the recess 204 is formed by wet etching, chemical mechanical polishing, or some other suitable technique.

[0103] exist Figure 5 In the steps 1021 to 1023 shown, the semiconductor single crystal 206 is formed in the recess 204. The semiconductor single crystal 206 can be used as Figure 2A The semiconductor single crystal 106 of the radiation absorbing layer 110 is formed in the semiconductor single crystal 106.

[0104] The formation of the semiconductor single crystal 206 can be accomplished by various techniques, for example, melt growth techniques, traveling heater techniques, vapor deposition techniques, epitaxial crystallization techniques, or any other suitable techniques. Melt growth techniques include melting semiconductor particles ("precursors") and recrystallizing the melt into a single crystal of the semiconductor. For example, melt growth techniques such as vertical Bridgman method and high pressure Bridgman method can be used to form a CdZnTe single crystal. Vapor deposition techniques may involve vaporizing a suitable semiconductor precursor and forming a semiconductor single crystal on a substrate from the vaporized semiconductor precursor. For example, a CdZnTe single crystal can be formed on a GaAs substrate from vaporized CdTe and zinc telluride precursors. Vapor deposition techniques can also be applied together with epitaxial crystallization techniques. For example, an epitaxial layer of a CdTe single crystal or a CdZnTe single crystal can be formed on a GaAs or Si substrate using metal organic vapor phase epitaxy technology with precursors such as dimethyl cadmium (DMCd), dimethyl zinc (DMZn), and diethyl tellurium (DETe), and hydrogen as a carrier gas. The selection of a suitable technique for forming the semiconductor single crystal 206 in the recess 204 depends on the characteristics of the semiconductor material, the substrate material, etc.

[0105] In the example of steps 1021-1023, a semiconductor single crystal 206 (in this example, a CdZnTe single crystal) is formed in the recess 204 using a vertical Bridgman technique. In step 1021, CdZnTe particles 205 (e.g., CnZnTe polycrystalline particles) can be deposited into the recess 204. In steps 1022 and 1023, the semiconductor single crystal 206 can be formed by melting the CdZnTe particles 205 (as shown in step 1023), and then the melt in the recess 204 is cooled to recrystallize. In the example of step 1022, the formation process can be performed in a vertical Bridgman furnace 250 including a growth chamber 213 and a heating element 214. The semiconductor substrate 210 (with the CdZnTe particles 205) is enclosed in the growth chamber 213, which is movable relative to the heating element 214. The temperature profile of the vertical Bridgman furnace 250 can be controlled by the heating element 214, such that the vertical Bridgman furnace 250 has a hot zone 215a and a gradient zone 215b. The temperature of the hot zone 215a can be equal to or higher than the melting temperature of the CdZnTe particles 205. In the gradient zone 215b, the temperature gradually decreases from the temperature in the hot zone 215a to below the melting temperature. When the growth chamber 213 is in the hot zone 215a, the CdZnTe particles 205 in the recess 204 melt. The melt is composed of volatile components, and vapor forms above the melt. This vapor is primarily composed of Cd atoms, as Cd has the highest vapor pressure among the components in the CdZnTe melt. To suppress potential vapor leakage and reduce the possibility of chamber rupture, the growth chamber 213 can be pressurized with an inert gas 216, such as argon. As the growth chamber 213 enters the gradient zone 215b from the hot zone 215a (e.g., in the direction indicated by the dashed arrow) at a very low speed (e.g., 1-2 mm / h), the melt is cooled and recrystallized from its lower end, so that the semiconductor single crystal 206 is gradually formed in the recess 204. In an embodiment, supplemental Cd vapor can be sent to the growth chamber 213 to compensate for any Cd loss and provide fine control over the molar concentrations of Cd and Zn in the semiconductor single crystal 206. In an embodiment, the formation process can also be performed in a horizontal geometry.

[0106] The yield of the semiconductor single crystal 206 (i.e., the probability that the recess 204 contains only the semiconductor single crystal 206) may depend on the applied formation technology, the properties of the semiconductor material, the formation conditions, etc. In the example of step 1022, the yield of the semiconductor single crystal 206 may be adjusted by the cooling rate, which may be adjusted by the movement speed of the growth chamber 213, the length of the gradient region 215b, etc.

[0107] In step 1023, after forming the semiconductor single crystal 206, the surface 210a of the semiconductor substrate 210 may be polished by wet etching, chemical mechanical polishing, or some other suitable technique. Alternatively, the surface 208 of each of the semiconductor single crystals 206 may be polished so that the surface 210a is coextensive with the surface 208. After polishing, the surface 210a and the surface 208 may be flat and smooth.

[0108] Figure 6 A process of forming the radiation absorbing layer 400 according to an embodiment is schematically illustrated.

[0109] In step 2010, a through hole 404 is formed in a semiconductor layer 410, which is supported directly on an electrical insulator layer 402. A portion 407 of the semiconductor layer 410 remains in and is surrounded by the through hole 404. Since the through hole 404 extends through the entire thickness of the semiconductor layer 410, at the end of step 2010, the portion 407 is electrically isolated from the rest of the semiconductor layer 410. The electrical insulator layer 402 can be used as a Figure 2B The electrical insulator layer 198 in the through hole 404 can be used as Figure 2B The through hole 194 in the portion 407 can be used as Figure 2B in the said section 197.

[0110] In step 2020, a semiconductor single crystal 406 is formed in the through hole 404. The semiconductor single crystal 406 may have a different composition than the semiconductor layer 410. The semiconductor single crystal 406 may be used as Figure 2B The semiconductor single crystal 196 in.

[0111] In step 2030 , an opening 409 is formed through the electrical insulator layer 402 such that the portion 407 is exposed in the opening 409 .

[0112] In step 2040, an electrode 419 is formed in the opening 409. The electrode 419 is in electrical contact with the portion 407. The electrode 419 can be used as Figure 2B The electrode 199 in.

[0113] In an embodiment, Figure 7As shown in steps 2011 to 2014, forming a through hole 404 in the semiconductor layer 410 may include forming a mask 403 on the semiconductor substrate 210 and etching the area of ​​the semiconductor layer 410 not covered by the mask 403. The mask 403 may be formed on the surface 410b of the semiconductor layer 410, and the semiconductor layer 410 may include a semiconductor material such as silicon, germanium, GaAs, or a combination thereof. As shown in step 2013a or step 2013b, the mask 403 may be used as an etching mask to form the through hole 404 and other through holes. The mask 403 may include a material such as silicon dioxide, silicon nitride, carbon, or a metal (e.g., aluminum, chromium). The thickness of the mask 403 may be determined based on the depth of the through hole 404 and other through holes and the etch selectivity (i.e., the ratio of the etch rate of the mask 403 to the etch rate of the semiconductor layer 410). In an embodiment, the mask 403 may have a thickness of several microns. The mask 403 may be formed on the surface 410 b by various techniques, such as physical vapor deposition, chemical vapor deposition, spin coating, sputtering, or any other suitable process.

[0114] In step 2012, as shown in the cross-sectional view, the mask 403 is patterned to have openings therein exposing the semiconductor layer 410. The shape and position of the openings correspond to the shape and position of the footprints of the through-holes 404 and other recesses formed in step 2013a or step 2013b. If the openings have a square shape (as shown in the top view in step 2012) and are arranged in a rectangular array, the footprints of the through-holes 404 and other through-holes also have a square shape and are arranged in a rectangular array. The formation of the pattern on the mask 403 can involve a photolithography process or any other suitable process. For example, a resist layer can first be deposited (e.g., by spin coating) on ​​the surface of the mask 403, and then photolithography can be performed to form the openings. The resolution of the photolithography is limited by the wavelength of the radiation used. Photolithography tools using deep ultraviolet (DUV) light with wavelengths of approximately 248nm and 193nm can reduce the minimum feature size to approximately 50nm. E-beam lithography tools use electron energies between 1keV and 50keV to reduce minimum feature sizes to a few nanometers.

[0115] In step 2013a or step 2013b, the through-hole 404 and other through-holes can be formed in the surface 410b of the semiconductor layer 410 by etching the portion of the semiconductor layer 410 not covered by the mask 403 to a desired depth. The height of the portion 407 can be less than or equal to the depth of the through-hole 404. The through-hole 404 can have a frustum, prism, pyramid, cuboid, cube, or cylinder shape. In the example of step 2013a, the through-hole 404 has a pyramid shape; in the example of step 2013b, the through-hole 404 has a cuboid shape. The through-hole 404 can have a smooth surface.

[0116] In an embodiment, etching of a portion of the semiconductor layer 410 can be performed by wet etching, dry etching, or a combination thereof. Wet etching is an etching process using a liquid etchant. The semiconductor layer 410 can be immersed in an etchant liquid, and the area not protected by the mask can be removed. The size and shape of the through hole 404 can be defined not only by the size and shape of the opening of the mask 403, but also by the material of the semiconductor layer 410, the liquid chemicals or etchants used, the etching rate and duration, etc. The semiconductor layer 410 can be a silicon substrate, and the through hole 404 can be formed by anisotropic wet etching using an etchant such as potassium hydroxide (KOH), ethylenediaminecatechol (EDP), tetramethylammonium hydroxide (TMAH), etc. During the anisotropic wet etching of the silicon substrate, the liquid etchant can etch the silicon substrate at different rates depending on the silicon crystal plane exposed to the etchant, thereby forming the through hole 404 with different shapes and sizes. In the example of step 2013a, when the surface 410b is a silicon crystal plane (100), a wet etchant such as KOH can be used to form a pyramid-shaped through-hole 404 having flat and angled etched walls. In the example of step 1013b, when the surface 410b is a silicon crystal plane (110), a wet etchant such as KOH can be used to form a rectangular parallelepiped through-hole 404.

[0117] In step 2014 , the mask 403 may be removed after forming the through hole 404 by wet etching, chemical mechanical polishing, or some other suitable technique.

[0118] exist Figure 8 In the steps 2021 to 2023 shown, the semiconductor single crystal (for example, the semiconductor single crystal 406 in step 1023) is formed in the through hole 404 and other through holes. The semiconductor single crystal (for example, the semiconductor single crystal 406 in step 1023) can be used as Figure 2B The semiconductor single crystal 196 of the radiation absorbing layer 110 in the embodiment of the present invention.

[0119] The formation of the semiconductor single crystal 406 can be accomplished by various techniques, for example, melt growth techniques, traveling heater techniques, vapor deposition techniques, epitaxial crystallization techniques, or any other suitable techniques. Melt growth techniques include melting semiconductor particles ("precursors") and recrystallizing the melt into a single crystal of the semiconductor. For example, melt growth techniques such as vertical Bridgman method and high pressure Bridgman method can be used to form a CdZnTe single crystal. Vapor deposition techniques may involve vaporizing a suitable semiconductor precursor and forming a semiconductor single crystal on a substrate from the vaporized semiconductor precursor. For example, a CdZnTe single crystal can be formed on a GaAs substrate from vaporized CdTe and zinc telluride precursors. Vapor deposition techniques can also be applied together with epitaxial crystallization techniques. For example, an epitaxial layer of a CdTe single crystal or a CdZnTe single crystal can be formed on a GaAs or Si substrate using metal organic vapor phase epitaxy technology with precursors such as dimethyl cadmium (DMCd), dimethyl zinc (DMZn), and diethyl tellurium (DETe), and hydrogen as a carrier gas. The selection of a suitable technique for forming the semiconductor single crystal 406 in the through hole 404 depends on the characteristics of the semiconductor material, the substrate material, etc.

[0120] In the example of steps 2021-2023, a semiconductor single crystal 406 (in this example, a CdZnTe single crystal) is formed in the through-hole 404 using a vertical Bridgman technique. In step 2021, CdZnTe particles 405 (e.g., CnZnTe polycrystalline particles) can be deposited into the through-hole 404. In steps 2022 and 2023, the semiconductor single crystal 406 can be formed by melting the CdZnTe particles 405 (as shown in step 2023), and then the melt in the through-hole 404 is cooled to recrystallize. In the example of step 2022, the formation process can be performed in a vertical Bridgman furnace 450 including a growth chamber 413 and a heating element 414. The semiconductor layer 410 (including the CdZnTe particles 405) is enclosed in the growth chamber 413, which is movable relative to the heating element 414. The temperature profile of the vertical Bridgman furnace 450 can be controlled by the heating element 414, such that the vertical Bridgman furnace 450 has a hot zone 415a and a gradient zone 415b. The temperature of the hot zone 415a can be equal to or higher than the melting temperature of the CdZnTe particles 405. In the gradient zone 415b, the temperature gradually decreases from the temperature in the hot zone 415a to below the melting temperature. When the growth chamber 413 is in the hot zone 415a, the CdZnTe particles 405 in the through-holes 404 melt. The melt is composed of volatile components, and vapor forms above the melt. The vapor is primarily composed of Cd atoms, as Cd has the highest vapor pressure among the components in the CdZnTe melt. To suppress potential leakage of the vapor and reduce the possibility of chamber rupture, the growth chamber 413 can be pressurized with an inert gas 416, such as argon. As the growth chamber 413 enters the gradient zone 415b from the hot zone 415a (e.g., in the direction indicated by the dashed arrow) at a very low speed (e.g., 1-2 mm / h), the melt is cooled and recrystallized from its lower end, so that the semiconductor single crystal 406 is gradually formed in the through-hole 404. In an embodiment, supplemental Cd vapor can be sent to the growth chamber 413 to compensate for any Cd loss and provide fine control over the molar concentrations of Cd and Zn in the semiconductor single crystal 406. In an embodiment, the formation process can also be performed in a horizontal geometry. The semiconductor single crystal 406 can be other single crystals, such as CdTe single crystals.

[0121] The yield of the semiconductor single crystal 406 (i.e., the probability that the through hole 404 contains only the semiconductor single crystal 406) may depend on the applied formation technology, the properties of the semiconductor material, the formation conditions, etc. In the example of step 2022, the yield of the semiconductor single crystal 406 may be adjusted by the cooling rate, which may be adjusted by the movement speed of the growth chamber 413, the length of the gradient region 415b, etc.

[0122] The semiconductor single crystal 406 is shown in step 2023. In an embodiment, after forming the semiconductor single crystal 406, the through hole 404 does not contain other semiconductor materials except the semiconductor single crystal 406. The through hole 404 does not contain semiconductor polycrystals.

[0123] The surface 410 b of the semiconductor layer 410 may be polished by wet etching, chemical mechanical polishing, or some other suitable technique after forming the semiconductor single crystal 406. Alternatively, the surface 408 of each of the semiconductor single crystals 406 may be polished so that the surface 410 b is coextensive with the surface 408. After polishing, the surface 410 b and the surface 408 may be flat and smooth.

[0124] Figure 9A Schematically shows Figure 2A The process of bonding the semiconductor substrate 102 to the electronic layer 120 is shown. The electronic layer 120 may include an electronic system electrically connected to the second doped semiconductor region 109 and configured to process the electrical signal generated in the radiation absorbing layer 110.

[0125] Figure 9B Schematically shows Figure 2B The process of bonding the electrical insulator layer 198 to the electronic layer 120 is shown. The electronic layer 120 may include an electronic system 121 electrically connected to the electrodes 199 and configured to process electrical signals generated in the radiation absorbing layer 191.

[0126] The second doped semiconductor region 109 or the electrode 199 as shown may be bonded to each of the through-holes 131 by a suitable technique such as direct bonding or flip-chip bonding.

[0127] Direct bonding is a die bonding process without any additional intermediate layers (e.g., solder bumps). The bonding process is based on a chemical bond between the two surfaces. Direct bonding can be performed at high temperatures, but this is not a requirement.

[0128] Flip-chip bonding uses solder bumps 132 deposited on contact pads (e.g., the contact surface of the second doped semiconductor region 109, the electrode 199, or the through-hole 131). The radiation absorbing layer 110 or 191 or the electronic layer 120 is flipped, and the second doped semiconductor region 109 or the electrode 199 is aligned with the through-hole 131. The solder bumps 132 can be melted to solder the second doped semiconductor region 109 or the electrode 199 to the through-hole 131. Any void space between the solder bumps 132 can be filled with an insulating material.

[0129] Figure 10A and Figure 10B Each diagram shows a component of the electronic system 121 according to an embodiment. The electronic system 121 may include a first voltage comparator 301 , a second voltage comparator 302 , a counter 320 , a switch 305 , a voltmeter 306 , and a controller 310 .

[0130] The first voltage comparator 301 is configured to compare the voltage of an electrode (e.g., the second doped semiconductor region 109 on the semiconductor single crystal 106 or the electrode 199 on the semiconductor single crystal 106 or 196) with a first threshold value. The first voltage comparator 301 can be configured to directly monitor the voltage or calculate the voltage by integrating the current flowing through the electrode over a period of time. The first voltage comparator 301 can be controllably activated or deactivated by the controller 310. The first voltage comparator 301 can be a continuous comparator. That is, the first voltage comparator 301 can be configured to be continuously activated and continuously monitor the voltage. Configuring the first voltage comparator 301 as a continuous comparator reduces the chance that the system 121 will miss a signal generated by an incident radiation particle. Configuring the first voltage comparator 301 as a continuous comparator is particularly suitable when the incident radiation intensity is relatively high. The first voltage comparator 301 can be a clocked comparator, which has the advantage of lower power consumption. Configuring the first voltage comparator 301 as a clocked comparator can cause the system 121 to miss signals generated by some incident radiation particles. When the incident radiation intensity is low, the chance of missing an incident radiation particle is low because the time interval between two consecutive radiation particles is relatively long. Therefore, configuring the first voltage comparator 301 as a clocked comparator is particularly suitable when the incident radiation intensity is relatively low. The first threshold value can be 5-10%, 10-20%, 20-30%, 30-40%, or 40-50% of the maximum voltage generated by an incident radiation particle on the semiconductor single crystal 106 or 196. The maximum voltage can depend on the energy of the incident radiation particle (i.e., the wavelength of the incident radiation), the material of the radiation absorbing layer 110 or 191, and other factors. For example, the first threshold value can be 50 mV, 100 mV, 150 mV, or 200 mV.

[0131] The second voltage comparator 302 is configured to compare the voltage with a second threshold value. The second voltage comparator 302 can be configured to directly monitor the voltage or to calculate the voltage by integrating the current flowing through the electrode over a period of time. The second voltage comparator 302 can be a continuous comparator. The second voltage comparator 302 can be controllably activated or deactivated by the controller 310. When the second voltage comparator 302 is deactivated, the power consumption of the second voltage comparator 302 can be less than 1%, less than 5%, less than 10% or less than 20% of the power consumption when the second voltage comparator 302 is activated. The absolute value of the second threshold value is greater than the absolute value of the first threshold value. As used herein, the term "absolute value" or "modulus" |x| of a real number x is a non-negative value of x regardless of its sign. That is, The second threshold value may be 200%-300% of the first threshold value. The second threshold value is at least 50% of the maximum voltage of an incident radiation particle generated on the semiconductor single crystal 106 or 196. For example, the second threshold value may be 100 mV, 150 mV, 200 mV, 250 mV, or 300 mV. The second voltage comparator 302 and the first voltage comparator 301 may be the same component. That is, the system 121 may have a single voltage comparator that can compare the voltage to two different threshold values ​​at different times.

[0132] The first voltage comparator 301 or the second voltage comparator 302 may include one or more operational amplifiers or any other suitable circuits. The first voltage comparator 301 or the second voltage comparator 302 may have a high speed to allow the system 121 to operate at a high flux of high incident radiation. However, having high speed generally comes at the expense of power consumption.

[0133] The counter 320 is configured to record a number of radiation particles that reach the semiconductor single crystal 106 or 196. The counter 320 may be a software component (eg, a number stored in a computer memory) or a hardware component (eg, 4017 IC and 7490 IC).

[0134] The controller 310 can be a hardware component such as a microcontroller or microprocessor. The controller 310 is configured to initiate a time delay from the time the first voltage comparator 301 determines that the absolute value of the voltage equals or exceeds the absolute value of the first threshold (e.g., the absolute value of the voltage increases from below the absolute value of the first threshold to equal or exceed the absolute value of the first threshold). The absolute value is used here because the voltage can be negative or positive, depending on whether the voltage at the cathode or anode of the diode is used or which electrical contact is used. The controller 310 can be configured to disable the second voltage comparator 302, the counter 320, and any other circuitry not required for the operation of the first voltage comparator 301 until the first voltage comparator 301 determines that the absolute value of the voltage equals or exceeds the absolute value of the first threshold. The time delay can expire before or after the voltage becomes stable (i.e., the rate of change of the voltage is substantially zero). The phrase "rate of change is substantially zero" means that the temporal rate of change of the voltage is less than 0.1% / ns. The phrase "substantially non-zero rate of change" means that the temporal rate of change of the voltage is at least 0.1% / ns.

[0135] The controller 310 may be configured to activate the second voltage comparator during the time delay (including the start and expiration). In an embodiment, the controller 310 is configured to activate the second voltage comparator at the start of the time delay. The term "activate" means to put a component into an operational state (e.g., by sending a signal such as a voltage pulse or logic level, by providing power, etc.). The term "deactivate" means to put a component into a non-operating state (e.g., by sending a signal such as a voltage pulse or logic level, by cutting off power, etc.). The operational state may have a higher power consumption than the non-operating state (e.g., 10 times higher, 100 times higher, 1000 times higher). The controller 310 itself may be deactivated until the output of the first voltage comparator 301 is equal to or exceeds the absolute value of the first threshold value, thereby activating the controller 310.

[0136] If the second voltage comparator 302 determines that the absolute value of the voltage is equal to or exceeds the absolute value of the second threshold during the time delay, the controller 310 may be configured to increase the number recorded by the counter 320 by one.

[0137] The controller 310 can be configured to cause the voltmeter 306 to measure the voltage upon expiration of the time delay. The controller 310 can be configured to connect the electrode to an electrical ground to reset the voltage and discharge any carriers accumulated on the electrode. In an embodiment, the electrode is connected to an electrical ground after the time delay has expired. In an embodiment, the electrode is connected to an electrical ground for a limited reset period. The controller 310 can connect the electrode to the electrical ground by controlling the switch 305. The switch can be a transistor such as a field effect transistor (FET).

[0138] In an embodiment, the system 121 is free of analog filter networks (eg, RC networks). In an embodiment, the system 121 is free of analog circuits.

[0139] The voltmeter 306 may feed the measured voltage to the controller 310 in the form of an analog or digital signal.

[0140] The system 121 may include a capacitor module 309 electrically connected to the electrodes, wherein the capacitor module is configured to collect carriers from the electrodes. The capacitor module may include a capacitor in the feedback path of the amplifier. An amplifier configured in this manner is referred to as a capacitive transimpedance amplifier (CTIA). The CTIA has a high dynamic range by preventing the amplifier from saturating and improves the signal-to-noise ratio by limiting the bandwidth in the signal path. The carriers from the electrodes are collected over a period of time ("integration period") (e.g., Figure 7As shown, the voltage is accumulated on the capacitor between time t0 and time t1, or between time t1 and time t2. After the integration period expires, the capacitor voltage is sampled and then reset by a reset switch. The capacitor module may include a capacitor directly connected to the electrode.

[0141] Figure 11 The diagram schematically illustrates the temporal variation of the current flowing through the electrode (upper curve) caused by carriers generated by radiation particles incident on the semiconductor single crystal 106 or 196, and the corresponding temporal variation of the voltage at the electrode (lower curve). The voltage may be the integral of the current with respect to time. At time t0, the radiation particles impact the semiconductor single crystal 106 or 196, carriers begin to be generated on the semiconductor single crystal 106 or 196, current begins to flow through the electrode of the semiconductor single crystal 106 or 196, and the absolute value of the voltage at the electrode or electrical contact begins to increase. At time t1, the first voltage comparator 301 determines that the absolute value of the voltage equals or exceeds the absolute value of the first threshold V1. The controller 310 initiates time delay TD1 and may deactivate the first voltage comparator 301 at the start of TD1. If the controller 310 was deactivated before time t1, it is activated at time t1. During TD1, the controller 310 activates the second voltage comparator 302. As used herein, the term "during" a time delay means the start and the expiration (i.e., the end) and any time in between. For example, the controller 310 may activate the second voltage comparator 302 when the TD1 expires. If, during the TD1, the second voltage comparator 302 determines that the absolute value of the voltage at time t2 is equal to or exceeds the absolute value of the second threshold, the controller 310 increases the number recorded by the counter 320 by one. At time t e , all carriers generated by the radiation particles drift out of the radiation absorbing layer 110. At time t s , the time delay TD1 expires. Figure 11 In the example, time t s At time t e After that, TD1 expires after all carriers generated by the radiation particles drift out of the radiation absorbing layer 110. At time t s The rate of change of the voltage is thus substantially zero. The controller 310 may be configured to disable the second voltage comparator 302 upon expiration of TD1 or at time t2, or any time in between.

[0142] The controller 310 may be configured to cause the voltmeter 306 to measure the voltage when the time delay TD1 expires. In an embodiment, the controller 310 causes the voltmeter 306 to measure the voltage after the time delay TD1 expires and the rate of change of the voltage becomes substantially zero. The voltage at this time is proportional to the number of carriers generated by the radiation particle, and the number of carriers is related to the energy of the radiation particle. The controller 310 may be configured to determine the energy of the radiation particle based on the voltage measured by the voltmeter 306. One method of determining the energy is by binning the voltage. The counter 320 may have a sub-counter for each bin. When the controller 310 determines that the energy of the radiation particle falls into a bin, the controller 310 may increase the number recorded in the sub-counter for that bin by one. Thus, the system 121 is capable of detecting radiation patterns and resolving the radiation energy of each radiation particle.

[0143] After TD1 expires, the controller 310 connects the electrode to electrical ground for a reset period RST to allow the carriers accumulated on the electrode to flow to ground and reset the voltage. After RST, the system 121 is ready to detect another incident radiation particle. Implicitly, Figure 11 In the example of FIG1 , the rate of incident radiation particles that the system 121 can process is limited to 1 / (TD1 + RST). If the first voltage comparator 301 is disabled, the controller 310 can activate it at any time before the expiration of RST. If the controller 310 is disabled, it can be activated before the expiration of RST.

[0144] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for illustrative purposes only and are not intended to be limiting, and their true scope and spirit should be determined by the claims herein.

Claims

1. A method comprising: forming a recess in a semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess; forming a semiconductor single crystal in the recess, the semiconductor single crystal having a composition different from that of the semiconductor substrate; forming a first doped semiconductor region in the semiconductor substrate; forming a second doped semiconductor region in the semiconductor substrate; The first doped semiconductor region and the second doped semiconductor region form a pn junction separating the portion of the semiconductor substrate from the rest of the semiconductor substrate. 2 . The method of claim 1 , wherein the first doped semiconductor region surrounds the second doped semiconductor region. The method of claim 1 , wherein the second doped semiconductor region is in electrical contact with the portion of the semiconductor substrate. The method of claim 1 , wherein forming the second doped semiconductor region comprises doping a portion of the first doped semiconductor region. 5 . The method of claim 1 , wherein the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the semiconductor single crystal and the semiconductor substrate. The method of claim 1 , wherein the second doped semiconductor region is coextensive with the first doped semiconductor region. 7 . The method according to claim 1 , wherein forming the recess comprises forming a mask on the semiconductor substrate and etching a region of the semiconductor substrate not covered by the mask.

8. The method of claim 7, wherein the mask comprises metal, silicon nitride, silicon dioxide, or carbon.

9. The method of claim 7, wherein etching the region is performed by wet etching, dry etching, or a combination thereof.

10. The method of claim 1, further comprising polishing the semiconductor substrate or the semiconductor single crystal to make the semiconductor single crystal and the semiconductor substrate coextensive.

11. The method of claim 1, wherein the semiconductor substrate comprises silicon, germanium, GaAs, or a combination thereof. 12 . The method of claim 1 , wherein the semiconductor single crystal is a cadmium zinc telluride (CdZnTe) single crystal or a cadmium telluride (CdTe) single crystal. 13 . The method according to claim 1 , wherein the recess does not contain any semiconductor material other than the semiconductor single crystal after the semiconductor single crystal is formed. The method according to claim 1 , wherein the recess does not contain a semiconductor polycrystal after forming the semiconductor single crystal.

15. The method of claim 1, wherein the recess has a shape of a frustum, a prism, a pyramid, a cuboid, or a cylinder. 16 . The method of claim 1 , wherein forming the semiconductor single crystal in the recess comprises depositing semiconductor particles into the recess, forming a melt by melting the semiconductor particles, and recrystallizing the melt in the recess.

17. The method of claim 16, wherein said recrystallizing the melt in the recess involves cooling the melt at a rate such that the melt recrystallizes into a single crystal.

18. The method of claim 17, wherein cooling the melt is accomplished by moving the melt from a region having a temperature higher than or equal to a melting point of the semiconductor particles to another region having a temperature lower than the melting point.

19. The method of claim 1, wherein forming the semiconductor single crystal comprises using a vapor-phase precursor.

20. The method of claim 1, further comprising bonding the semiconductor substrate to another substrate including an electronic system therein or thereon, wherein the electronic system is electrically connected to the second doped semiconductor region and is configured to process electrical signals generated in the semiconductor substrate.

21. A method comprising: forming a through-hole in a semiconductor layer supported directly on an electrically insulating layer, wherein a portion of the semiconductor layer remains in and is surrounded by the through-hole; forming a semiconductor single crystal in the through hole, the semiconductor single crystal having a composition different from that of the semiconductor layer; forming an opening through the electrically insulating layer such that the portion of the semiconductor layer is exposed in the opening; An electrode is formed in the opening, the electrode being in electrical contact with the portion of the semiconductor layer. 22 . The method of claim 21 , wherein forming the through hole comprises forming a mask on the semiconductor layer and etching a region of the semiconductor layer not covered by the mask.

23. The method of claim 22, wherein the mask comprises metal, silicon nitride, silicon dioxide, or carbon.

24. The method of claim 22, wherein etching the region is performed by wet etching, dry etching, or a combination thereof.

25. The method of claim 22, further comprising polishing the semiconductor layer or the semiconductor single crystal to make the semiconductor single crystal and the semiconductor layer coextensive.

26. The method of claim 21, wherein the semiconductor layer comprises silicon, germanium, GaAs, or a combination thereof.

27. The method of claim 21, wherein the electrically insulating layer comprises an oxide, a nitride, or an oxynitride.

28. The method of claim 21, wherein the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal. 29 . The method of claim 21 , wherein the through-hole does not contain other semiconductor materials other than the semiconductor single crystal after forming the semiconductor single crystal.

30. The method of claim 21, wherein the through hole does not contain semiconductor polycrystal after forming the semiconductor single crystal.

31. The method of claim 21, wherein the through-hole has a shape of a frustum, a prism, a pyramid, a cuboid, or a cylinder.

32. The method of claim 21, wherein forming the semiconductor single crystal in the through-hole comprises depositing semiconductor particles into the through-hole, forming a melt by melting the semiconductor particles, and recrystallizing the melt in the through-hole.

33. The method of claim 32, wherein said recrystallizing the melt in the through-hole involves cooling the melt at a rate such that the melt recrystallizes into a single crystal.

34. The method of claim 33, wherein cooling the melt is accomplished by moving the melt from a region having a temperature greater than or equal to a melting point of the semiconductor particles to another region having a temperature less than the melting point.

35. The method of claim 21, wherein forming the semiconductor single crystal comprises using a vapor phase precursor.

36. The method of claim 21, further comprising bonding the electrically insulating layer to an electronic layer, the electronic layer comprising a layer electrically connected to the electrode and configured to process electrical signals generated in the semiconductor layer.

37. A radiation detector comprising: semiconductor substrates; a recess in the semiconductor substrate, wherein a portion of the semiconductor substrate extends into and is surrounded by the recess; a semiconductor single crystal in the recess, the semiconductor single crystal having a composition different from that of the semiconductor substrate; a first doped semiconductor region in the semiconductor substrate; as well as a second doped semiconductor region in the semiconductor substrate; The first doped semiconductor region and the second doped semiconductor region form a pn junction separating the portion of the semiconductor substrate from the rest of the semiconductor substrate.

38. The radiation detector of claim 37, wherein the radiation detector is configured to absorb radiation particles incident on the semiconductor single crystal and generate carriers.

39. The radiation detector of claim 37, wherein the first doped semiconductor region surrounds the second doped semiconductor region.

40. The radiation detector of claim 37, wherein the second doped semiconductor region is in electrical contact with the portion of the semiconductor substrate.

41. The radiation detector of claim 37, wherein the first doped semiconductor region extends from a surface of the semiconductor substrate to an interface between the semiconductor single crystal and the semiconductor substrate.

42. The radiation detector of claim 37, wherein the second doped semiconductor region is coextensive with the first doped semiconductor region.

43. The radiation detector of claim 37, wherein the semiconductor single crystal and the semiconductor substrate are coextensive.

44. The radiation detector of claim 37, wherein the semiconductor substrate comprises silicon, germanium, GaAs, or a combination thereof.

45. The radiation detector of claim 37, wherein the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal. 46 . The radiation detector of claim 37 , wherein the recess does not contain other semiconductor materials other than the semiconductor single crystal after the semiconductor single crystal is formed.

47. The radiation detector of claim 37, wherein the recess does not contain a semiconductor polycrystal after forming the semiconductor single crystal.

48. The radiation detector of claim 37, wherein the recess is in the shape of a frustum, a prism, a pyramid, a cuboid, or a cylinder.

49. The radiation detector of claim 37, further comprising An electronic layer is bonded to the semiconductor substrate, the electronic layer including an electronic system electrically connected to the second doped semiconductor region and configured to process an electrical signal generated in the semiconductor substrate.

50. A radiation detector comprising: Electrical insulation layer; a semiconductor layer supported directly on the electrically insulating layer; a through hole in the semiconductor layer, wherein a portion of the semiconductor layer extends into and is surrounded by the through hole; a semiconductor single crystal in the through hole, the semiconductor single crystal having a composition different from that of the semiconductor layer; as well as An electrode passes through the electrically insulating layer, the electrode being in electrical contact with the portion of the semiconductor layer.

51. The radiation detector of claim 50, wherein the semiconductor layer comprises silicon, germanium, GaAs, or a combination thereof.

52. The radiation detector of claim 50, wherein the electrically insulating layer comprises an oxide, a nitride, or an oxynitride.

53. The radiation detector of claim 50, wherein the semiconductor single crystal is a CdZnTe single crystal or a CdTe single crystal.

54. The radiation detector of claim 50, wherein the through-hole does not contain other semiconductor materials other than the semiconductor single crystal after the semiconductor single crystal is formed.

55. The radiation detector of claim 50, wherein the through hole does not contain semiconductor polycrystal after forming the semiconductor single crystal.

56. The radiation detector of claim 50, wherein the through-hole is in the shape of a frustum, a prism, a pyramid, a cuboid, or a cylinder.

57. The radiation detector of claim 50, further comprising an electronics layer bonded to the electrically insulating layer, the electronics layer comprising an electronics system electrically connected to the electrodes and configured to process electrical signals generated in the semiconductor layer.

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