High-efficiency SFQ logic bias technology

Abstract

This document discloses an embodiment including an electrical structure comprising a first cell, a first inductor, a first resistor, and a first shunt Josephson junction. The first inductor is connected in series with the first shunt Josephson junction at a first terminal end, and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first terminal of the first resistor is connected to ground, and a second terminal of the first shunt Josephson junction is connected to the first shunt Josephson junction at a terminal not connected to the first inductor. A current source outside the first cell is connected at a common point to the first shunt junction and the first resistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 817,227, filed March 12, 2019, which is incorporated herein by reference in its entirety for all purposes.

[0003] According to MPEP §310, regarding research or development funded by the U.S. federal government.

[0004] This invention was made with government support from the Intelligence Advanced Research Projects Activity (IARPA) of the United States. Through paid licensing, the U.S. government has certain rights to the invention(s) claimed herein. More specifically, in limited circumstances, the U.S. government may require the patent holder to license the technology covered by this patent to others under reasonable terms as set forth in IARPA Contract No. W911NF-17-9-0001. Technical Field

[0005] This disclosure is of great significance in the general electronics field, including the following topics: electronic design automation, superconducting circuit devices, and biasing techniques for high-efficiency fast single-throughput quantum (ERSFQ) circuits. Background Technology

[0006] It is well known that digital logic systems can be implemented using superconducting circuit devices based on Josephson junctions. While this technology presents its challenges, one of its main potential advantages is the significantly reduced power consumption compared to semiconductor technology, although Josephson systems need to operate at temperatures close to absolute zero. It is for this reason that there has been considerable recent interest in Josephson technology, such as in the IARPA SuperTools project, which aims to develop a comprehensive suite of electronic design automation (EDA) and technical computer-aided design (TCAD) tools for very large-scale integration (VLSI) design of superconducting electronic circuits. Synopsys is the lead developer in this project.

[0007] Several Josephson logic families are being developed and supported by different organizations, each with its own advantages and disadvantages relative to the others. Reciprocal quantum logic (RQL) and adiabatic quantum flux parameter (AQFP) are two such examples. A third major technique is single-flux quantum (SFQ) logic, which comes in different styles, including fast or resistive SFQ (RSFQ) and high-efficiency SFQ (ERSFQ or EERSFQ). SFQ circuits can utilize DC bias, while other circuits require polyphase microwave power signals that must be routed to a large number of gates while maintaining timing accuracy and amplitude. Circuits based on polyphase microwave power signals are technically more challenging than SFQ circuits utilizing DC bias.

[0008] RSFQ is the original SFQ method, where 'R' stands for "resistive" or "fast". This logic was invented in the 1980s, and work continues to use the same basic approach because it requires the simplest bias circuitry. It has the disadvantage of relatively high power consumption.

[0009] The ERSFQ method was proposed as a low-power SFQ derivative, offering approximately an order of magnitude lower power consumption compared to the standard RSFQ. The ERSFQ family, used for over a decade, employs an on-chip voltage regulator implemented as a Josephson transmission line (JTL), referred to herein as a "feed JTL." One objective of fed JTLs is to achieve a very low on-chip power supply (tens of microvolts), ensuring low power consumption by maintaining a very low chip bias voltage. However, fed JTLs themselves can require significant operating current and contribute substantially to circuit area requirements and component count. Therefore, this regulation method can have significant drawbacks in these aspects. Attached Figure Description

[0010] The following detailed description, accompanying drawings, and claims illustrate the uses and advantages of the claimed invention and its embodiments. All drawings are for illustrative purposes only and do not limit the scope of the claimed invention and its embodiments. These drawings are not necessarily to scale.

[0011] Similar parts or features used in the accompanying drawings may have the same or similar reference numerals (such as alphanumeric symbols, e.g., reference numerals) in label form and may indicate similar or equivalent uses. Furthermore, various parts of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar parts. If only the first reference label is used in the specification, its use applies to any similar parts having the same first reference label, regardless of the second reference label. A brief description of the accompanying drawings is provided below.

[0012] Figure 1 An example of a powered fast single-throughput quantum (RSFQ) circuit device is illustrated.

[0013] Figure 2 The illustration shows the current-voltage (IV) characteristics of a shunt Josephson junction as a current source according to an exemplary embodiment of the present disclosure.

[0014] Figure 3 The illustration shows a simulation of a Josephson current source element according to an exemplary embodiment of the present disclosure.

[0015] Figure 4 The illustration depicts an exemplary embodiment of the present disclosure, for... Figure 3 The current and voltage characteristics of the Josephson current source element.

[0016] Figure 5 The diagram illustrates the electrical structure using a fed Josephson transmission line (JTL).

[0017] Figure 6 An electrical structure according to an exemplary embodiment of the present disclosure is illustrated.

[0018] Figure 7 The illustration depicts an exemplary embodiment of the present disclosure, for... Figure 6 The current and voltage characteristics of the electrical structure.

[0019] Figure 8 The illustration shows another electrical structure according to an exemplary embodiment of the present disclosure.

[0020] Figure 9 The illustration depicts an exemplary embodiment of the present disclosure, for... Figure 8 The voltage characteristics of the electrical structure over time.

[0021] Figure 10 The illustration shows flowcharts of various processes used during the design and manufacture of integrated circuits according to an exemplary embodiment of the present disclosure.

[0022] Figure 11A and Figure 11B An abstract diagram of a computer system for an embodiment of the claimed invention is illustrated, along with an embodiment of a circuit design and an embodiment of a manufactured circuit used in this disclosure.

[0023] In the accompanying drawings, reference numerals may be omitted, as is consistent with accepted engineering practice; however, those skilled in the art will understand that the illustrated components are readily understood when viewed in the context of the illustrations as a whole and the accompanying disclosure describing these various drawings. Detailed Implementation

[0024] The accompanying drawings and detailed descriptions are provided only to give knowledge and understanding of the claimed invention. To minimize the length of the detailed descriptions, various features, structures, or characteristics may be described together in a single embodiment, but they may also be used in other embodiments without being written down. The drawings and detailed descriptions may also imply or explicitly represent advantages and improvements of the claimed invention and its embodiments.

[0025] In the accompanying drawings and detailed descriptions, numerous specific details may be described to implement at least one embodiment of the claimed invention. Any embodiment disclosed herein represents a tangible form of the claimed invention. For the purpose of presentation and illustration, some elements known to those skilled in the art may be combined and not described in detail, so as not to obscure the importance of these embodiments and / or examples. For the purpose of presentation and illustration, some well-known processes, machines, systems, manufactures, or compositions are not described in detail. Therefore, the detailed descriptions focus on unique elements that implement the claimed invention and exemplary embodiments. When certain elements are referred to in the singular tense in this detailed description, more than one element may be depicted in the drawings, and similar elements are labeled using similar reference numerals.

[0026] In this disclosure, various embodiments based on the ERSFQ (High Energy Efficiency RSFQ) method are detailed as low-power SFQ derivatives. This has approximately an order of magnitude less power consumption compared to utilizing standard RSFQ.

[0027] Detailed Implementation – RSFQ Bias Circuit Device

[0028] Figure 1 The illustration shows a method for powering a fast single-throughput quantum (RSFQ) circuit device. Figure 1 The diagram illustrates an RSFQ circuit 100 with a step-down resistor 102 and a bias voltage source 106. Due to the step-down resistor 102, the RSFQ circuit 100 exhibits high power consumption. (As...) Figure 1 As shown, bias voltage source 106 is connected to step-down resistor 102, and step-down resistor 102 is connected to Josephson junction 104. Although Figure 1 The diagram shows only one example of a step-down resistor 102 and a Josephson junction 104, but the RSFQ circuit can have multiple similar Josephson junctions 104, each connected to a step-down resistor similar to the step-down resistor 102. As a non-limiting example, for the RSFQ circuit 100, an off-chip bias voltage source 106 can be provided.

[0029] The time-averaged voltage across the Josephson junction 104 can range from 0 volts (when the Josephson junction does not switch at all) to a voltage proportional to the system clock frequency (when the Josephson junction generates a pulse on each clock cycle). The average voltage across the Josephson junction depends on the frequency of the pulse, and its proportionality constant is twice the electron charge divided by Planck's constant, or approximately 500 MHz per microvolt.

[0030] Therefore, a bias current is obtained from the voltage source 106 by using a step-down resistor 102. The values ​​of the voltage source 106 and the step-down resistor 102 specify the bias current. For the RSFQ circuit 100, the average voltage across the step-down resistor 102 can vary according to the switching probability of the Josephson junction 104, and the bias current supplied to the Josephson junction 104 can be changed accordingly. A change in the bias current through the Josephson junction 104 can cause spurious triggering or the absence of expected triggering. Therefore, to prevent spurious triggering or the absence of expected triggering, the bias source voltage 106 may need to be at least ten times higher than the voltage corresponding to the system clock frequency. Thus, in very low temperature environments, the step-down resistor 104 can dissipate at least 90 percent of the chip power as heat.

[0031] Detailed Implementation – Josephson Junction as a Current Source

[0032] In some embodiments, as a non-limiting example, the Josephson junction, acting as a current source, can be used as a constant current bias for the circuit junction. In this case, the total power consumption can be lower compared to using the step-down resistor 102 when the on-chip voltage remains low. As a non-limiting example, the total power consumption can be approximately 10 times lower than the total power consumption using the step-down resistor.

[0033] Figure 2 The illustration shows the current-voltage (IV) characteristics of a shunt Josephson junction as a current source according to some embodiments. The current source is evident from the IV characteristics of the shunt Josephson junction, which show that the average current change is very small compared to the voltage change, such as... Figure 2 As shown in Figure 202. In other words, when the voltage across the Josephson junction, which acts as a current source, is kept low, the ratio of the current difference to the voltage difference (di / dv) is almost zero. Therefore, power dissipation is kept low, and the current flowing through the Josephson junction can be controlled to the threshold current I required by the Josephson junction. c The same applies. In addition to the constant DC current, there will also be a significant AC current, which can be filtered to prevent interference with the biased circuitry. This AC current can be filtered out using an inductor placed in series with the Josephson junction.

[0034] Figure 3 The illustration shows a simulation of a Josephson current source element according to some embodiments. The simulation of a Josephson current source element can be performed using a circuit simulator. An example of such a circuit simulator could be the WRspice circuit simulator from Whiteley Research Inc. Using the SPICE (Simulation Programming Interface) specification language, the circuit simulator can accept a circuit description as input. Figure 3As shown, the biased Josephson junction 302 is connected to a constant voltage source 304. Another voltage source (308), which can vary over time, is used to model the Josephson junction as a load. The voltage across voltage source 308 can be varied so that the effect of the voltage change across the junction can be simulated. As a non-limiting example, the voltage of the other voltage source 308 can be varied from 0 V to 18 μV and from 18 μV to 0 V, and the voltage of voltage source 304 can be 20 μV. Therefore, in this case, the average voltage across the Josephson current source can be varied by a factor of 10.

[0035] Figure 4 Current graph 402 and voltage graph 404 are shown. Current graph 402 indicates the current passing through the current source at point 306, and voltage graph 404 indicates the voltage measured at point 308. Figure 4 As shown, the long ramp 406 is due to the filter inductor 310 (e.g., with a value of 1 nanohenry) charging from the voltage source 304. Figure 4 As shown, the bias current may contain approximately 1% ripple 408, which is shown as an amplified ripple 410. However, the bias current ripple 408, 410 can be reduced by using a large inductor filter.

[0036] Figure 5 The illustration shows an example of a fed JTL with adjustable bias line voltage. Figure 5 A power supply JTL 502, a bias line 504, a ground plane 506, a JTL clock 508, and a logic circuit arrangement 510 are shown. The power supply JTL 502 is driven by the JTL clock 508. The JTL clock 508 can supplement the system clock, and the frequency of the JTL clock 508 can set the voltage across the power supply JTL and the bias voltage for the bias line 504. However, any benefit of precise voltage regulation using conventional techniques with the power supply JTL 502 is likely to be overshadowed by the complexity and additional power consumption of the power supply JTL 502. The power supply JTL is used to establish a known reference voltage from which the SFQ circuit arrangement is powered, but this can be replaced by a more efficient method, as shown below.

[0037] Specific implementation method—Josephson junction as a current source with a resistor connected to ground

[0038] exist Figure 6In some embodiments, the feed JTL 502 can be removed and replaced by resistor 602. This replacement of feed JTL 502 with resistor 602 frees up significant circuit area because the JTL clock 508 and associated inductors 502a to 502h are no longer needed. As a non-limiting example, each bias feed point can have an added resistor to ground, and approximately 10% of the total chip bias current can flow to ground through multiple resistors. When the chip is biased by a relatively high impedance source, the multiple resistors to ground can provide a well-defined bias voltage. Furthermore, the on-chip voltage can be unclamped (as is typically seen in fed JTLs), and instead can vary with the bias current. The voltage across resistor 602 is the "excess" current not consumed by the Josephson junction current source 608 multiplied by the value of the resistor. Since resistor 602 is in parallel with the Josephson junction and the bias line, the on-chip voltage can be provided as desired by adjusting the bias current.

[0039] While both the feed JTL and the embodiments described herein can use resistors as part of the bias network, the embodiments described herein differ from the feed JTL. For example, the feed JTL can use a buck resistor 102 that appears in series with the Josephson junction 104. The value of the buck resistor can be high, and the buck resistor can act as a current source to the load. On the other hand, in the bias circuit arrangements described herein with reference to various embodiments, a practical current source can be provided, and a resistor with a small resistance to ground can be used to control the voltage at the feed point. Because only a small amount of current may need to flow through these resistors to ground, power consumption is low. As a non-limiting example, the power consumption through the resistor to ground can be approximately 10% of the total power consumption. Furthermore, the value of the ground-to-resistor 602 used in the embodiments is very small compared to the buck resistor 104. Therefore, the ground-to-resistor used in the embodiments may require significantly less circuit area. Thus, the ground-to-resistor used to drain excess current can allow the Josephson junction current source to replace the function of the buck resistor.

[0040] In some embodiments, when the feed JTL 502 is replaced by a resistor 602 to ground, approximately 25% of the Josephson junctions required in the ERSFQ logic chip can be eliminated. With the elimination of the Josephson junctions, the associated inductors can also be eliminated, which can free up significant chip area for additional circuitry and functionality, or allow for the use of smaller die sizes to minimize the overall circuitry.

[0041] Figure 7 The illustration depicts an exemplary embodiment of the present disclosure, for... Figure 6The current and voltage characteristics of the electrical structure. As mentioned above, the feed JTL 502 can provide a precise regulated voltage, but requires more circuit area. The voltages measured at points 504 and 506 compared to the feed JTL 502 indicate that the voltages at points 604 and 606 may not be as precise as those available using the feed JTL 502. However, it is known that the lack of precise voltage control is not associated with any adverse effects during testing. This is because the system power regulator can provide and control the power required to adapt to the system clock frequency. Furthermore, in Figure 7 In the figures, the current measured at points 612 and 614 and the voltage measured at points 604 and 606 for each bias feed branch are shown in Figures 702, 704, 706, and 708, respectively. Enlarged versions of Figures 702, 704, 706, and 708 are also shown in Figures 710, 712, 714, and 716, respectively. As mentioned above, the current ripple shown in Figures 710 and 712 remains less than 1%. In other words, the current across Josephson junctions 616 and 618 remains constant. Even in the presence of excess inductance, for example, when inductors 620 and 622 are placed to simulate a bias line, which in a chip layout can be a narrow and tortuous band. Furthermore, as can be seen from voltage figures 706 and 708 or 714 and 716, the time required to charge the inductors to their quiescent current is significantly reduced.

[0042] Based on the above disclosure, in some embodiments, parameterized power distribution point units can be designed for use in electronic design automation (EDA) systems.

[0043] Figure 8 The illustration shows four power distribution point units according to some embodiments. For example... Figure 8 As shown, four power distribution point units 802, 804, 806, and 808 simulate a circuit load. Each power distribution point unit 802, 804, 806, and 808 may include: a current source Josephson junction (e.g., 802a, 804a, 806a, and 808a), a filter inductor (e.g., 802b, 804b, 806b, and 808b), and a resistor to ground (e.g., 802c, 804c, 806c, and 808c). The value of the resistor to ground and the junction critical current are set by the unit parameters, which are the current delivered by the power distribution unit. The power distribution system requires no additional circuitry, and the actual inductances 810, 812, and 814 of the on-chip power lines can be incorporated into the schematic.

[0044] Figure 9 The illustration depicts an exemplary embodiment of the present disclosure, for... Figure 8The voltage characteristics of the electrical structure over time. Simulations and measurements of current at points 816, 818, 820, and 822, and simulations and measurements of voltage at points 824, 826, 828, and 830. Figure 9 The numbers are shown as 902, 904, 906, 908, 910, 912, 914, and 916 respectively, which can be compared with, for example... Figure 7 The current and voltage characteristics shown are consistent.

[0045] Finally, compared to logic circuits with fed JTLs, the logic circuits based on the embodiments disclosed herein require significantly less circuit area because they require far fewer components and circuit arrangements. Furthermore, since at least 25% of the Josephson junctions in the Josephson junctions can be eliminated, the overall cost of the logic circuits can be reduced while increasing yield.

[0046] Data and Information While 'data' and 'information' are often used interchangeably (e.g., 'data processing' and 'information processing'), the term 'data' (plural 'data') typically identifies a representation of the measured value of a physical quantity (e.g., current in a wire) or an answer to a question (e.g., 'yes' or 'no'), while the term 'information' typically identifies a structured dataset (often identified by 'data structure'). A specified data structure is used to construct electronic devices intended to be used as artifacts of a particular machine. Data and information are physical, such as being implemented in a circuit as binary data ('bits', typically represented by '0' and '1') with two different voltage levels. For example, data can be implemented as electrical, magnetic, optical, or acoustic signals; quantum states such as the spin of a 'qubit'; or physical states of atoms or molecules. When enabled, all such data and information will be stored, accessed, transmitted, combined, compared, or otherwise performed, actions that require energy.

[0047] As used herein, the term 'process' refers to a non-natural sequence of physical actions and / or transformations (both also referred to as 'operations' or 'steps') that produce at least one result. Actions and transformations are technical applications of one or more laws of natural science or laws of non-natural technology. Actions and transformations typically alter the physical state of a machine, the structure of data and information, or the composition of matter. If two or more actions produce the same result, they can occur simultaneously, or one action can occur before or after another. Descriptions of physical actions and / or transformations that include a process are typically represented by a set of gerund phrases (or their semantic equivalents), which are usually followed by the pronoun "...steps" (e.g., "a process that includes measurement steps, transformation steps, partitioning steps, and then allocation steps...").

[0048] As used herein, the term 'component' (also referred to as 'part' when described in patent text or figures, and generally as 'element') refers to a physical object used in conjunction with other components to realize a process. For example, electronic components are used in processes that affect the physical state of one or more electromagnetic particles / waves or quantum particles / waves (e.g., electrons, photons) or quasi-particles (e.g., electron holes, phonons, magnetic domains) and their associated fields or signals. Electronic components have at least two connection points as attached 'leads,' typically wires or optical fibers, with one end attached to the component and the other end attached to another component, usually as part of a circuit with current flowing. There are at least three types of electrical components: passive, active, and electromechanical. Passive electronic components typically do not introduce energy into the circuit—such components include resistors, memristors, capacitors, magnetic sensors, crystals, Josephson junctions, transducers, sensors, antennas, waveguides, etc. Active electronic components require an energy source and can inject energy into a circuit—these components include semiconductors (e.g., diodes, transistors, optoelectronic devices), vacuum tubes, batteries, power supplies, and displays (e.g., LEDs, LCDs, lamps, CRTs, plasma displays). Electromechanical components use mechanical forces and structures to influence electric current—these components include switches, relays, protection devices (e.g., fuses, circuit breakers), heat sinks, fans, cables, wires, terminals, connectors, and printed circuit boards. As used herein, the term 'netlist' is a specification of the components that make up a circuit and the electrical connections between those components. The programming language of the SPICE circuit simulation program is commonly used to specify netlists. In the context of circuit design, the term 'instance' refers to each time a component is specified in the netlist.

[0049] As used herein, the term 'integrated circuit' refers to a collection of interconnected electronic components on a small substrate of semiconductor material such as silicon or gallium arsenide (hence the pronoun 'chip'), where components are fabricated on one or more layers. Other pronouns for 'integrated circuit' include 'monolithic integrated circuit', 'IC', 'chip', 'microchip', and 'system-on-a-chip' ('SoC'). Examples of types of integrated circuits include gate / logic arrays, processors, memory, interface chips, power controllers, and operational amplifiers. The term 'cell' used in electronic circuit design refers to a specification of one or more components, such as a collection of transistors interconnected to serve as logic gates. Cells are often stored in databases for access by circuit designers and the design process.

[0050] As used herein, the term 'module' refers to a tangible structure used for processing data and information. For example, the term 'module' can refer to a process that transforms data and information, such as a process involving a computer program. The term 'module' can also refer to one or more interconnected electronic components, such as digital logic devices. If specified in a programming language such as SystemC or Verilog, a process including modules can also be translated into a specification of an electronic component structure that transforms data and information to produce the same results as the process.

[0051] Modules can be permanently structured (e.g., circuits with unchangeable connections), temporarily structured (e.g., circuits or processes that change as the dataset changes), or a combination of both. Permanently structured modules can be fabricated using application-specific integrated circuits ('ASICs'), such as arithmetic logic units ('ALUs'), arrays of programmable logic ('PLAs'), or read-only memory ('ROMs'), all of which are typically structured during manufacturing. For example, a permanently structured module can include an integrated circuit. Temporarily structured modules, for example, can be fabricated using field-programmable gate arrays (FPGAs, such as those sold by Xilinx or Intel's Altera), random access memory (RAM), or microprocessors. For example, data and information can be translated using addresses in RAM or ROM memory that store output data and information. Temporarily structured modules can be embedded within permanently structured modules (e.g., FPGAs embedded within an ASIC).

[0052] Temporarily structured modules can be structured over multiple time periods. For example, a processor comprising one or more modules has modules that are first structured by the manufacturer in a factory and then further structured by the user. During the first time period, the processor may include a set of one or more modules, and then during a second time period, it may be restructured into a different set of one or more modules. The decision to manufacture or implement a module in a permanent structured form, a temporary structured form, or a combination of both depends on factors such as cost, time considerations, resource constraints, tariffs, maintenance requirements, national intellectual property laws, and / or specific design goals. The way a module is used is essentially independent of the physical form in which it is manufactured or implemented. (The last sentence is also from a modified Church-Turing paper.)

[0053] As used herein, the term 'processor' refers to a tangible data and information processing machine that uses at least one process to physically transform, transfer, and / or deliver data and information. A processor comprises one or more modules (e.g., a central processing unit 'CPU'; input / output ('I / O') controllers, memory controllers, network controllers, and other modules). The term 'processor' can refer to one or more processors, or one or more processors having multiple computing cores / CPUs, dedicated processors (e.g., graphics processors or signal processors), and combinations thereof. In cases where two or more processors interact, one or more processors can be remotely located. When the term 'processor' is used in other contexts (such as 'chemical processor'), it will be identified and defined in that context.

[0054] Processors may include, for example, digital logic circuit devices (e.g., binary logic gates) and / or analog circuit devices (e.g., operational amplifiers). Processors may also use optical signal processing, DNA conversion or quantum computing, microfluidic logic processing, or a combination of these technologies, such as optoelectronic processors. Any processor that can use AND, OR, and NOT logic operations (and their derivatives, such as NAND, NOR, and XOR operations) to transform data and information structured in binary data can also use any Boolean logic function to transform data and information. Processors such as analog processors (e.g., artificial neural networks) can also transform data and information. There is no scientific evidence that any of these technological processors is using any process or structure equivalent to the bioelectrical structure and processes of the human brain to process, store, and retrieve data and information.

[0055] One or more processors may also use processes in a 'cloud computing' environment, where multiple users or processors communicating with a computer share the time and resources of multiple remote computers. For example, a group of processors may use at least one process available at a distributed or remote system that uses a communication network (e.g., the Internet or Ethernet) and one or more designated interfaces (e.g., application programming interfaces ('APIs') that represent the functionality and data structures for communicating with remote processes).

[0056] As used herein, the terms 'computer' and 'computer system' (further defined below) include at least one processor that, with the addition of memory (e.g., memory constructed using flip-flops to perform NOT-AND or NOT-OR operations), performs operations on data and information, such as (but not limited to) AND, OR, and NOT logical operations using electronic gates that may include transistors. Such a processor is Turing-complete and computationally general. A computer may include a simple architecture, for example, comprising I / O modules, a CPU, and memory, which performs processes such as inputting, converting, and outputting signals without human intervention.

[0057] As used herein, the term 'programming language' refers to a structured syntax used to specify various sets of operations and data used by modules, processors, and computers. Programming languages ​​include assembler instructions, instruction set architecture instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more high-level languages, such as the C programming language and similar general-purpose programming languages ​​(e.g., Fortran, Basic, Javascript, PHP, Python, C++), knowledge-based programming languages ​​(e.g., Lisp, Smalltalk, Prolog, or CycL), electronic structure programming languages ​​(e.g., VHDL, Verilog, SPICE, or SystemC), text-based programming languages ​​(e.g., SGML, HTML, or XML), or audiovisual programming languages ​​(e.g., SVG, MathML, X3D / VRML, or MIDI), and any future equivalent programming languages. As used herein, the term 'source code' refers to a set of instructions and data specified in textual form using a programming language. A large amount of source code used to implement any claimed invention is available on the Internet, such as from source code repositories like GitHub.

[0058] As used herein, the term 'program' (also referred to as 'application') means one or more processes and data structures that construct a module, processor, or computer to be used as a "specific machine". One use of a program is to structure one or more computers (e.g., standalone computers, client or server computers), or one or more modules, or one or more systems of such computers or modules. As used herein, the term 'computer application' means a program that implements a specific purpose, such as text processing operations or encryption of datasets. As used herein, the term 'firmware' means a type of program that typically structures a processor or computer, where firmware is smaller in size than a typical application and is generally not accessible or modifiable by the user of the computer. Computer programs and firmware are typically specified using source code written in a programming language such as C. For example, modules, circuits, processors, programs, and computers can be specified at multiple levels of abstraction using the SystemC programming language.

[0059] A program is transferred from a data and information device or storage system to one or more memories of a computer or computer system. A computer system typically has devices for reading the storage medium used to transfer the program, and / or interface devices for receiving the program over a network.

[0060] Figure 11A and Figure 11B This is a diagram of an example computer system suitable for implementing embodiments of the claimed invention.

[0061] exist Figure 11A In this system, the architecture of computer system 1110 typically includes at least one computer 1114 that communicates with peripheral devices via bus subsystem 1112. Typically, the computer includes a processor (e.g., a microprocessor, graphics processing unit, or digital signal processor) or its electronic processing equivalent, such as an application-specific integrated circuit ('ASIC') or a field-programmable gate array ('FPGA'). Peripheral devices typically include a storage subsystem 1124, a user interface input device 1122, a user interface output device 1120, and / or a network interface subsystem 1116. The storage subsystem 1124 includes a memory subsystem 1126 and a file storage subsystem 1128. The input and output devices enable direct user interaction and remote user interaction with computer system 1110. The computer system uses at least one output device and / or network interface subsystem to perform important post-processing activities.

[0062] Computer systems can be configured as servers, clients, workstations, mainframes, personal computers (PCs), tablets, set-top boxes (STBs), personal digital assistants (PDAs), cellular phones, smartphones, network equipment, rack-mounted 'blades', kiosks, televisions, game consoles, network routers, switches, or bridges, or any data processing machine having instructions specifying actions to be taken by the data processing machine. The term 'server' as used herein refers to a computer or processor that typically performs processing for another computer or processor and sends data and information to another computer or processor.

[0063] Computer systems are typically structured in part using at least one operating system program, such as Microsoft Windows, Sun Microsystems Solaris, Apple Computer's macOS and iOS, Google's Android, Linux, and / or Unix. A computer system typically includes a Basic Input / Output System (BIOS) and processor firmware. The processor uses the operating system, BIOS, and firmware to structure and control any subsystems and interfaces connected to the processor. Common processors that implement these operating systems include Intel's Pentium, Itanium, and Xeon processors; Advanced Micro Devices' Opteron and Athlon processors; Amazon's Graviton processors; IBM's POWER processors; Oracle's SPARC processors; and ARM processors from ARM Holdings.

[0064] The claimed invention and its embodiments are neither limited to electronic digital logic computers utilizing programmable structures nor to electronically programmable devices. For example, the claimed invention may use optical computers, quantum computers, analog computers, etc. Furthermore, the singular form of this term, used to refer only to a single computer system or a single machine, may also refer to any structure of a computer system or machine used by an individual or collaborative process. Due to the constantly evolving nature of computers and networks, the description of the computer system 1110 depicted in Figure 11 is intended only as an example. Many other structures of the computer system 1110 have more or fewer components than the computer system depicted in Figure 11.

[0065] Network interface subsystem 1116 provides an interface to external networks, including an interface to communication network 1118, and network interface subsystem 1116 is coupled to corresponding interface devices in other computer systems or machines via communication network 1118. Communication network 1118 may include a number of interconnected computer systems, machines, and physical communication connections (represented by 'links'). These communication links may be wired links, optical links, wireless links (e.g., using Wi-Fi or Bluetooth protocols), or any other physical device used for information communication. Communication network 1118 may be any suitable computer network, such as a wide area network (WAN) like the Internet and / or a local area network to a wide area network (LAN-WAN) like Ethernet. The communication network is wired and / or wireless, and many communication networks use encryption and decryption processes, such as those available for virtual private networks (VPNs). The communication network uses one or more communication interfaces that receive data from other systems and transmit data to other systems. Examples of communication interfaces typically include Ethernet cards, modems (e.g., telephone, satellite, cable, or ISDN), (asynchronous) digital subscriber line (DSL) units, FireWire interfaces, USB interfaces, etc. One or more communication languages ​​can be used to specify communication algorithms ('protocols'), such as HTTP, TCP / IP, RTP / RTSP, IPX, and / or UDP.

[0066] User interface input device 1122 may include alphanumeric keypads, keypads, pointing devices (such as mice, trackballs, toggle switches, touchpads, pens), graphics tablets, optical scanners (such as barcode readers), touchscreen electronics for display devices, audio input devices (such as speech recognition systems or microphones), eye gaze recognition, brainwave pattern recognition, optical character recognition systems, and other types of input devices. Such devices are connected to the computer system via wired or wireless means. Generally, the term 'input device' refers to all possible types of devices and processes that transmit data and information to computer system 1110 or to communication network 1118. User interface input devices typically enable users to select objects, icons, text, etc., that appear on some type of user interface output device (e.g., a display subsystem).

[0067] User interface output device 1120 may include a display subsystem, printer, fax machine, or non-visual communication device such as audio and haptic devices. The display subsystem may include a cathode ray tube (CRT), a flat panel device (such as a liquid crystal display (LCD)), an image projection device, or other devices for creating visible stimuli (such as virtual reality systems). The display subsystem may also provide non-visual stimuli, such as via audio output, scent generation, or touch / haptic output (e.g., vibration and force) devices. Generally, the term 'output device' refers to all possible types of devices and processes that transmit data and information from computer system 1110 to a user or another machine or computer system. Such devices are connected to the computer system via wired or wireless means. Note: Some devices transmit data and information to and from the computer; for example, haptic devices that generate vibrations and forces on the user's hand while also including sensors to measure the position and movement of the hand. Ergonomic and semiotic techniques are applied to improve the efficiency of user interaction with any processes and computers disclosed herein, such as any interaction related to the design and manufacture of circuitry using any of the aforementioned input or output devices.

[0068] The memory subsystem 1126 typically includes multiple memories, including: a main random access memory ('RAM') 1130 (or other volatile storage device) for storing instructions and data during program execution, and a read-only memory ('ROM') 1132 in which fixed instructions are stored. The file storage subsystem 1128 provides persistent storage for program and data files and may include hard disk drives, floppy disk drives and associated removable media, CD-ROM drives, optical drives, flash memory (such as USB drives), or removable media cartridges. If the computer system 1110 includes an input device that performs optical character recognition, printed text and symbols on paper can be used as a device for storing program and data files. Databases and modules used in some embodiments may be stored by the file storage subsystem 1128.

[0069] Bus subsystem 1112 provides a means for transferring data and information between various components and subsystems of computer system 1110. Although bus subsystem 1112 is described as a single bus, alternative embodiments of the bus subsystem may use multiple buses. For example, main memory using RAM may communicate directly with a file storage system using a direct memory access ('DMA') system.

[0070] Figure 11BThe image depicts a memory 1140 (such as a non-transitory, processor-readable data and information storage medium associated with a file storage subsystem 1128 and / or a network interface subsystem 1116), and may include data structures specified in the circuit design. The memory 1140 may be a hard disk, floppy disk, CD-ROM, optical medium, removable media cartridge, or any other medium that stores computer-readable data in volatile or non-volatile form, such as text and symbols on paper that can be processed by an optical character recognition system. In some examples, the memory 1140 may include multiple units 1180 for storing data. Programs entering and leaving the processor from such memory can be converted into physical signals that propagate through a medium (such as a network, connector, wire, or circuit trace, as electrical pulses); or propagate through a medium such as space or the atmosphere as acoustic signals; or propagate as electromagnetic radiation with wavelengths longer than infrared light in the electromagnetic spectrum.

[0071] Figure 10 A set of processes 1000 used during the design, verification, and manufacturing of an in-process, such as an integrated circuit, are described to convert and verify design data and instructions representing that integrated circuit. Each of these processes can be built and implemented as multiple modules. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with the creation of a product concept 1010 using information provided by a designer, which is converted to create an article of art using a set of EDA processes 1012. When the design is complete, it is tape-out 1034, which typically involves sending the workpiece of the integrated circuit (e.g., a geometric pattern) to a manufacturing facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are manufactured 1036, and packaging and assembly processes 1038 are performed to produce the finished integrated circuit.

[0072] Specifications for circuits or electronic structures use multiple levels of useful abstraction, ranging from low-level transistor material placement to high-level description languages. Most designers begin by describing one or more modules at a high level of abstraction with less detail, in order to design their circuits and systems using hardware description languages ​​('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. High-level descriptions are easier for designers to understand, especially for large systems, and very complex systems that are difficult to understand can be described using lower levels of abstraction that are more detailed. HDL descriptions can be translated into other levels of abstraction used by developers. For example, a high-level description can be translated into a logic-level register-transfer-level ('RTL') description, a gate-level description, a placement-level description, or a mask-level description. Each lower level of abstraction, as a less abstract description, adds more useful details to the design description, such as more details about the modules that make up the description. Lower levels of abstraction for less abstract descriptions can be computer-generated, derived from design libraries, or created by another design automation process. An example of a specification language used to specify lower levels of abstraction for more detailed descriptions is SPICE, which is often used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is implemented for use by the corresponding tool at that level (e.g., a formal verification tool), and some modules in the abstract module need not be novel or obscure.

[0073] The design process using EDA procedure 1012 includes procedures 1014 to 1032, which are described below. This design flow description is for illustrative purposes only and is not intended to be limiting. For example, an integrated circuit designer can use... Figure 10 The different sequences of orders described herein utilize design processes. For the embodiments disclosed herein, products from Synopsys, Inc. (hereinafter referred to as 'Synopsys'), a company based in Mountain View, California, and / or similar products from other companies are used to implement these processes.

[0074] During System Design 1014, the designer specifies the functionality to be manufactured. The designer can also optimize power, performance, and area (physical and / or lines of code) and minimize cost, among other things. At this stage, the design can be divided into different types of modules. Exemplary EDA products from Synopsys that implement System Design 1014 include Model Architect, Sabre, System Studio, and DesignWare.

[0075] During logic design and functional verification 1016, modules in the circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked; that is, the module produces output that matches the requirements of the specifications of the circuit or system being designed. Exemplary HDL languages ​​are Verilog, VHDL, and SystemC. Functional verification typically uses simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some cases, special module systems, referred to as 'simulators' or 'prototype systems,' are used to accelerate functional verification. Exemplary EDA products from Synopsys that can be used at this stage include VCS, Vera, DesignWare, Magellan, Formality, ESP, and Leda products. Exemplary simulators and prototyping products available from Synopsys for implementing logic design and functional verification 1016 include ZeBu.RTM and Protocol.RTM (RTM stands for 'registered trademark').

[0076] During synthesis and design for testing (1018), HDL code is converted into a netlist (typically a graph structure where edges represent components of a circuit and nodes represent how components are interconnected). Both HDL code and netlist are layered artifacts that EDA products can use to verify that an integrated circuit performs as designed when manufactured. The netlist can be optimized for a target semiconductor manufacturing technology. Furthermore, the completed integrated circuit is tested to verify that it meets specification requirements. Exemplary EDA products from Synopsys for synthesis and design for testing include the Design Compiler, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, TetraMAX, and DesignWare products.

[0077] During Netlist Validation 1020, the netlist is checked to ensure it conforms to timing constraints and corresponds to the HDL code. Exemplary EDA products from Synopsys that implement Netlist Validation 1020 include Formality, Primetime, and VCS.

[0078] During Design Planning 1022, the overall layout plan for the integrated circuit is built and analyzed for timing and top-level routing. Exemplary EDA products from Synopsys for implementing Design Planning 1022 include Astro and IC Compiler products.

[0079] During layout implementation 1024, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connection of components via multiple conductors) are performed, and cells are selected from a library to implement specific logic functions. As used herein, the term 'cell' refers to a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit 'block' comprises two or more cells. Both cells and circuit blocks can be referred to as modules and can be implemented as physical structures and in simulations. Parameters such as size are specified for the selected cells (based on 'standard cells') and are accessible in a database for use by EDA products. Examples of databases that can be used to access cells include MySQL and PostgreSQL. Exemplary EDA products from Synopsys that implement layout implementations include Astro and IC Compiler products.

[0080] During the analysis and extraction of 1026, circuit functionality is verified at the layout level, which allows for refinement of the layout design. Exemplary EDA products from Synopsys that implement analysis and extraction include Astrorail, Primerail, Primetime, and Star RC / XT products.

[0081] During Physical Verification 1028, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, and lithographic constraints, are correct, and that the circuit device functionality matches the HDL design specifications. Exemplary EDA products from Synopsys that implement Physical Verification 1028 include Hercules products.

[0082] During Resolution Enhancement 1030, the geometry of the layout is transformed to improve the way the design is manufactured. Exemplary EDA products from Synopsys that implement Resolution Enhancement 1030 include the Proteus product.

[0083] During tape-out, data is created for the production of the photomask (if applicable, after the application of lithographic enhancements). Example EDA products from Synopsys that implement tape-out include the IC Compiler and Custom Designer products.

[0084] During mask data preparation 1032, "wafer fabrication" data is used to produce a photolithography mask, which is then used to produce the finished integrated circuit. Exemplary EDA products from Synopsys that implement mask data preparation 1032 include the CATS family of products.

[0085] For all of the above EDA products, as an alternative, similar products from other EDA vendors (such as Cadence, Siemens, and other corporate entities) or various non-commercial products from universities or open-source repositories can be used.

[0086] Computer systems (such as) Figure 11A The storage subsystem of the computer system 1110 is preferably used to store programs and data structures used by some or all of the EDA products described herein, and to store products that are units used to develop libraries and for physical and logical designs that use libraries.

[0087] Based on the teachings contained in this disclosure, those skilled in the art can use Figure 11A It may be apparent that embodiments of this disclosure can be made and used using data processing devices, computer systems, and / or computer architectures other than those shown herein. In particular, embodiments may operate using software, hardware, and / or operating system implementations different from those described herein.

[0088] It should be understood that the Detailed Description section, and not any other section, is intended to interpret the claims. The other sections may set forth one or more, but not all, exemplary embodiments contemplated by the inventors(s), and are therefore not intended to limit this disclosure or the appended claims in any way. The Detailed Description and any corresponding figures may be represented for knowledge and understanding purposes only. To minimize the length of the Detailed Description, various features, structures, or characteristics may be described together in a single embodiment, but they may also be used in other embodiments without being described.

[0089] While this disclosure describes exemplary embodiments of the fields and applications, it should be understood that this disclosure is not limited thereto. Other embodiments and modifications thereof are possible and are within the scope and spirit of this disclosure. For example, and without limiting the generality of this paragraph, embodiments are not limited to the software, hardware, firmware, and / or entities shown in the figures and / or described herein. Furthermore, embodiments (whether or not explicitly described herein) have significant utility for fields and applications beyond the examples described herein.

[0090] This document has described embodiments using functional building blocks, which illustrate the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and relationships (or their equivalents) are appropriately executed. Furthermore, alternative embodiments may use a different order of execution for functional blocks, steps, operations, methods, etc., than that described herein.

[0091] References to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," or similar phrases herein indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment.

[0092] Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, incorporating such feature, structure, or characteristic into other embodiments will be within the knowledge of those skilled in the art, whether or not it is expressly mentioned or described herein. Additionally, some embodiments may be described using the expressions “coupled” and “connected” together with their derivatives. These terms are not necessarily intended to be synonyms with each other. For example, the terms “connected” and / or “coupled” may be used to describe some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0093] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. An electronic structure comprising: Unit 1 includes: First shunt Josephson node; A first inductor is connected in series with a first shunt Josephson junction at a first terminal end, and a second terminal end of the first inductor is connected to the feed point of the first unit being powered; and A first resistor has a first end and a second end, the first end being connected to ground, and the second end being connected to the first shunt Josephson junction at a terminal of the first shunt junction that is not connected to the first inductor; and A current source outside the first unit, wherein the current source is directly connected to the first shunt Josephson junction and the first resistor at the common point of the first shunt Josephson junction and the first resistor, and The first resistor is connected in parallel with the first shunt Josephson junction.

2. The electronic structure according to claim 1, wherein when powered, the current to the feed point of the first unit varies by less than 10%.

3. The electronic structure according to claim 1, wherein the first inductor is adapted to filter the alternating current (AC) component of the current flowing through the first inductor to the feed point of the first cell.

4. The electronic structure according to claim 1 further includes: Unit Two includes: Second shunt Josephson node; A second inductor is connected in series with the second shunt Josephson junction at its first terminal end, and the second terminal end of the second inductor is connected to the feed point of the powered second unit; and The second resistor has a first end and a second end, the first end being connected to the ground, and the second end being connected to the second shunt Josephson junction at a terminal not connected to the second inductor where the current source is applied.

5. The electronic structure according to any one of the preceding claims, wherein the first inductor or the second inductor is a narrow band or a twisted band.

6. The electronic structure according to claim 4, wherein the first unit or the second unit is a parameterized unit.

7. The electronic structure according to claim 1, wherein the electronic structure is implemented as one or more geometric mask features on a mask set or an integrated circuit.

8. A method for designing electronic structures, the method comprising: At the first terminal end of the first inductor, the first inductor is connected in series with the first shunt Josephson junction; The second terminal of the first inductor is connected to the feed point of the first unit that is powered, the first unit including the first inductor, the first shunt Josephson junction and the first resistor; Connect the first end of the first resistor to ground, and connect the second end of the first resistor to the first shunt Josephson junction at the terminal of the first shunt Josephson junction that is not connected to the first inductor; as well as The first unit is powered by a current source located outside the first unit, and the current source is directly connected to the first shunt Josephson junction and the first resistor at the common point of the first shunt Josephson junction and the first resistor. The first resistor is connected in parallel with the first shunt Josephson junction.

9. The method of claim 8, wherein the current to the feed point of the first unit being powered varies by less than 10%.

10. The method of claim 8, wherein the first inductor is adapted to filter the alternating current (AC) component of the current flowing through the first inductor to the feed point of the first unit.

11. The method of claim 8, further comprising: At the first terminal end of the second inductor, the second inductor is connected in series with the second shunt Josephson junction; The second terminal of the second inductor is connected to the feed point of the second unit that is powered, the second unit including the second inductor, the second shunt Josephson junction and the second resistor; as well as The first end of the second resistor is connected to the ground, and the second end of the second resistor is connected to the second shunt Josephson junction at the following terminal, which is not connected to the second inductor and the current source is applied at that terminal.

12. The method according to claim 11 further comprises forming the first inductor or the second inductor with a twisted strip.

13. The method according to claim 11 further includes designing the first unit or the second unit as a parameterized unit.

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