Task allocation method, device, electronic device and computer readable storage medium

Abstract

The disclosed embodiment discloses a task allocation method, device, electronic device and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, the main processing core executes a task update instruction to obtain a task segment to be executed; the processing core of the task to be executed receives the task segment to be executed, wherein the processing core of the task to be executed includes the main processing core and / or the slave processing core; the processing core of the task to be executed executes the task segment to be executed; in response to completing the execution of the task segment to be executed, the processing core of the task to be executed sends a synchronization request signal, wherein the synchronization request signal is used to trigger the generation of the synchronization signal. By allocating the task segment executed by the processing core according to the synchronization signal by the main processing core in the chip in the above method, the technical problems of inflexible task allocation and complex control of the processing core in the prior art are solved.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and in particular to a task allocation method, device, electronic device, and computer-readable storage medium. Background Art

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. An important feature of the intelligent era is that people obtain more and more types of data, the amount of data obtained is increasing, and the speed of processing data is getting higher and higher. Chips are the cornerstone of task allocation, which fundamentally determines people's ability to process data. From the perspective of application fields, there are two main routes for chips: one is the general chip route, such as CPU, etc., which can provide great flexibility, but the effective computing power is relatively low when processing algorithms in specific fields; the other is the dedicated chip route, such as TPU, etc., which can play a higher effective computing power in certain specific fields, but in the face of flexible and changeable more general fields, their processing capabilities are relatively poor or even unable to process. Due to the wide variety and huge amount of data in the intelligent era, chips are required to have both extremely high flexibility, able to process algorithms in different fields and changing with each passing day, and extremely strong processing capabilities, able to quickly process huge and rapidly growing amounts of data.

[0003] In neural network calculations, multi-core or multi-core chips are often used. How to make many processing cores efficiently exert their computing power is the key to determining the performance of the entire chip. The computing power of each processing core depends on many factors, such as task scheduling and allocation, chip architecture, processing core structure, processing core circuits, etc. Among them, task scheduling and allocation is a very critical factor. If the scheduling and allocation of tasks are reasonable, the effective computing power of each processing core can be fully utilized.

[0004] In the prior art, the following two solutions are generally used to schedule core tasks:

[0005] like Figure 1aThe figure shows a scheme for task allocation using a scheduler. In this scheme, the scheduler receives instructions from an instruction source, and then transmits the instructions to each processing core according to a certain strategy, such as in sequence. Each processing core executes the same instruction but processes different data. Each processing core can be a relatively simple structure, such as SIMD (Single Instruction Multiple Data) with shared control circuits and registers, or a relatively complex structure with a certain degree of autonomy, such as SIMT (Single Instruction Multiple Threads) with independent control circuits and registers. However, in this scheme, the scheduler can only passively receive instructions from an external instruction source and then distribute them to each processing core. It has a single function and lacks flexibility. Regardless of whether it is a SIMD structure or a SIMT structure, each processing core can only execute the same instruction, and each processing core has a small degree of freedom and simple control.

[0006] like Figure 1b The figure shows a solution where the processing cores independently execute tasks. In this solution, each processing core can independently read instructions from the memory and perform operations; each processing core has a complete control circuit, register group and other circuits. However, for this solution, it is difficult for each processing core to cooperate with each other to efficiently complete a complete task; the circuit control is complex, and each core is almost a complete CPU, which is difficult to design, and has large power consumption and area; multiple processing cores may frequently access the instruction storage area, causing a decrease in storage access efficiency, which in turn affects the performance of the chip computing power. Summary of the invention

[0007] This summary is provided to introduce concepts in a brief form that will be described in detail in the detailed description below. This summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] In order to solve the technical problems of inflexible task allocation and complex control of processing cores in the prior art, the embodiments of the present disclosure propose the following technical solutions:

[0009] In a first aspect, an embodiment of the present disclosure provides a task allocation method for use in a chip, wherein the chip includes a master processing core and at least one slave processing core, wherein the method includes:

[0010] In response to receiving the synchronization signal, the main processing core executes a task update instruction to obtain a task segment to be executed, wherein the task segment to be executed is a part of the task;

[0011] The processing core of the task to be executed receives the task segment to be executed, wherein the processing core of the task to be executed includes the master processing core and / or the slave processing core;

[0012] The processing core of the task to be executed executes the task segment to be executed;

[0013] In response to completing the execution of the task segment to be executed, the processing core of the task to be executed sends a synchronization request signal, wherein the synchronization request signal is used to trigger the generation of the synchronization signal.

[0014] Further, the main processing core executes the task update instruction to obtain the task segment to be executed, including:

[0015] The main processing core executes the task update instruction to send the task segment acquisition instruction to the storage manager;

[0016] The storage manager executes the task segment acquisition instruction to read the to-be-executed task segment from the external memory and sends the task segment to the master processing core and the slave processing core.

[0017] Furthermore, the method further comprises:

[0018] The processing core of the task to be executed sends a data acquisition instruction according to the received task segment to be executed;

[0019] According to the data acquisition instruction, the processing cores of the tasks to be executed receive respective input data.

[0020] Further, the processing core of the task to be executed receives respective input data according to the data acquisition instruction, including:

[0021] The identifier of the processing core of the task to be executed is used as a parameter of the data acquisition instruction to acquire the input data of the processing core of the task to be executed.

[0022] Further, the synchronization request signal is used to trigger the generation of the synchronization signal, including:

[0023] In response to the processing cores of the tasks to be executed all sending the synchronization request signal, the generation of the synchronization signal is triggered.

[0024] Further, in response to receiving the synchronization signal, the main processing core executes the task update instruction to obtain the task segment to be executed, including:

[0025] In response to receiving the synchronization signal, the main processing core uses the number of times the synchronization signal is received as a parameter for executing the task update instruction to generate a task segment acquisition instruction;

[0026] The main processing core sends the task segment acquisition instruction to acquire the corresponding task segment to be executed.

[0027] Further, after receiving the synchronization signal, the method further includes:

[0028] The main processing core starts a synchronization counter to record the number of times the synchronization signal is received by the main processing core.

[0029] In a second aspect, an embodiment of the present disclosure provides a chip, including:

[0030] a master processing core, at least one slave processing core, and a storage manager;

[0031] The main processing core is used to execute a task update instruction in response to a received synchronization signal to obtain a task segment to be executed, wherein the task segment to be executed is a part of the task;

[0032] The storage manager is used to fetch the to-be-executed task segment corresponding to the task update instruction from the external memory based on the task update instruction, and send the to-be-executed task segment to the processing core of the to-be-executed task;

[0033] Wherein, the processing core of the task to be executed includes the master processing core and / or the slave processing core;

[0034] The processing core of the task to be executed is used to receive the task segment to be executed;

[0035] The processing core of the task to be executed is also used to execute the task segment to be executed;

[0036] The processing core of the task to be executed is also used to send a synchronization request signal in response to completing the execution of the task segment to be executed, wherein the synchronization request signal is used to trigger the generation of the synchronization signal.

[0037] Furthermore, the chip further comprises:

[0038] The on-chip network is connected to the master processing core, the slave processing core and the storage manager, and is used for transmitting data between the processing core, the slave processing core and the storage manager.

[0039] Furthermore, the main processing core is also used to: execute a task update instruction to send a task segment acquisition instruction to the storage manager; the storage manager is used to execute the task segment acquisition instruction to read the task segment to be executed from the external memory and send it to the processing core of the task to be executed.

[0040] Furthermore, the processing core of the task to be executed is also used to send a data acquisition instruction according to the received task segment to be executed; and receive respective input data according to the data acquisition instruction.

[0041] Furthermore, the processing core of the task to be executed is also used to use the identification of the processing core of the task to be executed as a parameter of the data acquisition instruction to obtain the input data of each processing core of the task to be executed.

[0042] Further, the synchronization request signal is used to trigger the generation of the synchronization signal, including:

[0043] In response to the processing cores of the tasks to be executed all sending the synchronization request signal, the generation of the synchronization signal is triggered.

[0044] Furthermore, the main processing core is also used to respond to receiving a synchronization signal, use the number of times the synchronization signal is received as a parameter to execute the task update instruction to generate a task segment acquisition instruction; and send the task segment acquisition instruction to acquire the corresponding task segment to be executed.

[0045] Furthermore, after receiving the synchronization signal, the main processing core is further configured to start a synchronization counter to record the number of times the synchronization signal is received by the main processing core.

[0046] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that when the processors are executed, any task allocation method described in the first aspect is implemented.

[0047] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute any task allocation method described in the first aspect.

[0048] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, characterized in that it includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any task allocation method described in the first aspect.

[0049] In a sixth aspect, an embodiment of the present disclosure provides a computing device, characterized in that it comprises one or more chips described in the second aspect.

[0050] The embodiment of the present disclosure discloses a task allocation method, device, electronic device and computer-readable storage medium. The task allocation method is used in a chip, wherein the chip includes a main processing core and at least one slave processing core, and is characterized in that the method includes: in response to receiving a synchronization signal, the main processing core executes a task update instruction to obtain a task segment to be executed, and the task segment to be executed is a part of the task; the processing core of the task to be executed receives the task segment to be executed, wherein the processing core of the task to be executed includes the main processing core and / or the slave processing core; the processing core of the task to be executed executes the task segment to be executed; in response to completing the execution of the task segment to be executed, the processing core of the task to be executed sends a synchronization request signal, wherein the synchronization request signal is used to trigger the generation of the synchronization signal. By allocating the task segment executed by the processing core according to the synchronization signal by the main processing core in the chip in the above method, the technical problems of inflexible task allocation and complex control of the processing core in the prior art are solved.

[0051] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0053] Figure 1a-1b It is a schematic diagram of the prior art of the present disclosure;

[0054] Figure 2a and Figure 2b A flowchart of an embodiment of the task allocation method provided by the present disclosure;

[0055] Figure 3 A schematic diagram of the structure of the chip provided by the present disclosure;

[0056] Figure 4 A schematic diagram of the structure of an example of a chip provided by the present disclosure;

[0057] Figure 5 A schematic diagram of a neural network computing task performed by a chip example provided in the present disclosure;

[0058] Figure 6 A schematic diagram of a core pipeline calculation process when a chip example provided by the present disclosure executes a task allocation method;

[0059] Figure 7 A timing diagram of a microprocessor and a processing core when the chip example provided in the present invention executes a task allocation method. DETAILED DESCRIPTION

[0060] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0061] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0062] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0063] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0064] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0065] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0066] Figure 2a This is a flowchart of an embodiment of a task allocation method provided by an embodiment of the present disclosure. The task allocation method provided by this embodiment is used in a chip, wherein the chip includes a master processing core and at least one slave processing core. Figure 2a As shown, the method comprises the following steps:

[0067] Step S201, in response to receiving a synchronization signal, the main processing core executes a task update instruction to obtain a task segment to be executed, wherein the task segment to be executed is a part of the task;

[0068] In the disclosed embodiment, during the operation of the chip, a certain processing core will be pre-designated as the master core MC (Master Core), and the other processing cores are slave processing cores SC (Slave Core). In addition to executing the task segments that need to be executed by itself, the master processing core is also used to execute the task update program to allocate task segments to the processing cores of the chip. The task update program can use dynamic allocation rules, in which case the allocation of task segments is dynamically allocated by the master processing core to one or more processing cores of the tasks to be executed according to actual conditions; the task update program can also use pre-set fixed allocation rules, in which case how the task segments are allocated and which processing cores they are allocated to are predetermined.

[0069] The task segment is a part of a complete task. Accordingly, according to the difference of the task update program run by the above-mentioned main processing core, the complete task can be dynamically or pre-divided into multiple task segments for storage and execution by the processing core of the task to be executed. When the synchronization signal is received, the main processing core executes the task update instruction pre-stored in the main processing core according to the received synchronization signal to determine the various processing cores of the task to be executed in the chip and the task segments to be executed by each processing core. Among them, the various processing cores of the task to be executed include one or more of the main processing core and the at least one slave processing core.

[0070] Optionally, step S201 includes: in response to receiving a synchronization signal, the main processing core uses the number of received synchronization signals as a parameter for executing the task update instruction to generate a task segment acquisition instruction; the main processing core sends the task segment acquisition instruction to acquire the corresponding task segment to be executed. In this embodiment, the main processing core stores a pre-loaded allocation strategy, which sets which processing core or processing cores need to update the task segment they execute in a certain synchronization cycle, and the main processing core counts the synchronization signal each time it receives the synchronization signal, and determines whether it is necessary to allocate a task segment to the processing core based on the counting result. Exemplarily, in the above optional embodiment, the number of synchronization signals is used as a parameter of the task update instruction, the task update instruction is executed to acquire the parameters of the task segment acquisition instruction, and the parameters of the task segment acquisition instruction are used to configure the task segment acquisition instruction. In the embodiment of the present disclosure, the task segments to be executed acquired by the task segment acquisition instruction can be the same or different.

[0071] In one embodiment, the main processing core further includes a synchronization counter or the task update program in the main processing core includes a synchronization counter, and after receiving the synchronization signal, the main processing core further includes: the main processing core starts the synchronization counter to record the number of synchronization signals received by the main processing core. The main processing core can determine the processing core of the task to be executed and the task segment to be executed according to the number of synchronization signals.

[0072] Optionally, the main processing core executes a task update instruction to instruct the storage controller to read the task segment to be executed from the external memory and send it to the corresponding processing core.

[0073] Most of the time, the main processing core executes its own task segment. A task update program is stored in the main processing core, and the task update program includes a task update instruction. When the synchronization signal is received, the main processing core executes the task update instruction in the task update program to generate a task segment acquisition instruction. The task update instruction can be, for example, a general update instruction. When executed, the main processing core obtains parameters of the instruction, such as: the processing core of the task to be executed indicated by the task update instruction, the task segment to be executed, and the storage location of the task segment to be executed in the external memory, etc.

[0074] Exemplarily, the storage controller is a memory management engine (MME), and the storage management engine may be, for example, a DMAC (Direct Memory Access Controller), or other hardware or software that can implement storage management functions.

[0075] The main processing core executes the task update instruction, generates a task segment acquisition instruction that can be executed by the MME, and the MME receives the task segment acquisition instruction, decodes and executes it to acquire the corresponding task segment to be executed from the external memory and send it to the corresponding processing core. The process of acquiring the corresponding task segment to be executed from the external memory and sending it to the corresponding processing core does not require the participation of the main processing core.

[0076] Exemplarily, each time the synchronization signal is received, the main processing core executes the task update instruction, determines the processing core of the task to be executed according to the number of synchronization signals, that is, the processing core that needs to update the task segment, determines the task segment to be executed and the storage location of the task segment to be executed and other parameters, and uses these parameters to configure the task segment to obtain instructions.

[0077] Optionally, the complete task can be pre-divided into multiple task segments, that is, the size of each task segment and the first address for storing each task segment are pre-set. When executing the task segment acquisition instruction, the MME can obtain the task segment to be executed from the external memory according to the size and the first address of the task segment.

[0078] Optionally, the complete task segment can be dynamically divided into multiple task segments, that is, the number and size of the task segments are uncertain before allocation. At this time, the main processing core instructs the MME to read the task segment to be executed from the external memory and send it to the processing core of the task to be executed, including: the main processing core obtains the size of the storage space of the processing core of the task to be executed; the main processing core instructs the MME to read the task segment that matches the size of the storage space of the processing core of the task to be executed from the memory and send it to the processing core. Each processing core has its own storage space, and the available size of the storage space may be different. Therefore, when the main processing core instructs the processing core to allocate a task segment, the main processing core first obtains the size of the storage space of the processing core of the task to be executed, determines the size of the task segment by the size of the storage space, and then determines the range of the task segment sent to the processing core in the entire task by the first address of the task segment and the size of the task segment.

[0079] Exemplarily, a storage location is set in the storage space of the slave processing core to store the remaining storage space of the current slave processing core, and the master processing core obtains the remaining storage space of the slave processing core from the location before executing the task update instruction; or the master processing can set a storage location in its own storage space to store the remaining storage space of each processing core, and the initial storage space of each processing core is known. The allocation of task segments is performed by the master processing core, so the master processing core can calculate the remaining storage space of each processing core based on the allocation of task segments. After the current task segment is determined, the first address of the next task segment is also determined, which is used for the allocation of the next task segment.

[0080] Optionally, the dynamic allocation can be performed dynamically each time, that is, the size of the storage space of the processing core to be executed is obtained each time the task segment allocation instruction is executed; or the dynamic allocation can be performed only for the first time, that is, it is considered that the storage space size of the processing core is fixed when executing the task, and when the task segments are allocated for the first time, the complete task is divided into multiple task segments according to the storage space size of the processing core and the size of the complete task, and then each time the task segments are allocated to the processing core according to the size of the task segments divided this time.

[0081] Step S202, the processing core of the task to be executed receives the task segment to be executed;

[0082] In this step, the processing core of the task to be executed is one or more of the master processing core and the at least one slave processing core. In this step, the processing core of the task to be executed receives the task segment to be executed sent by the storage controller.

[0083] Exemplarily, the storage controller is connected to all processing cores in the chip via an on-chip network (Noc). In this step, the processing cores of the tasks to be executed respectively receive the task segments to be executed via the on-chip network.

[0084] Optionally, in one embodiment, the main processing core is one of the processing cores of the task to be executed. In this step, the processing core of the task to be executed receives the task segment to be executed, including: the main processing core starts to receive the task segment to be executed after executing the task update instruction, and the other processing cores of the task to be executed directly enter the state of receiving the task segment to be executed after receiving the synchronization signal, and wait for the MME to send the task segment to be executed to the processing core of the task to be executed.

[0085] Optionally, in another embodiment, the main processing core is not one of the processing cores of the task to be executed. In this step, the processing core of the task to be executed receives the task segment to be executed, including: the processing core of the task to be executed enters a state of receiving the task segment to be executed after receiving the synchronization signal, and waits for the MME to send the task segment to be executed to the processing core of the task to be executed.

[0086] Step S203, the processing core of the task to be executed executes the task segment to be executed;

[0087] After receiving the task segment to be executed, the processing core of the task to be executed executes the task segment to be executed to generate output data. Exemplarily, the output data is a part of the output result of the complete task, and each output data generated by the task segment to be executed in multiple synchronous cycles is processed to form the output result of the complete task.

[0088] Step S204: in response to completing the execution of the task segment to be executed, the processing core of the task to be executed sends a synchronization request signal, wherein the synchronization request signal is used to trigger the generation of the synchronization signal.

[0089] When executing the task segment to be executed, each processing core of the task to be executed sends a synchronization request signal respectively when the execution of the task segment to be executed is completed, wherein the synchronization request signal is used to trigger the generation of a synchronization signal.

[0090] It can be understood that the synchronization signal can be generated by a synchronization signal generating unit in the chip. In this case, the synchronization signal generating unit is a special component, which triggers the generation of the first synchronization signal at startup, and then triggers the generation of the synchronization signal after receiving the synchronization signal request sent by all processing cores.

[0091] Optionally, the synchronization signal generating unit can be a program unit. In this case, the synchronization signal is generated by the program unit. In this case, a program is required to generate the first synchronization signal after startup, and then trigger the generation of the synchronization signal after receiving the message packet of the synchronization signal request sent by all processing cores.

[0092] After step S204, when the main processing core receives the synchronization signal, it calls the task update instruction and adds the parameters of the next task segment including the processing core of the task to be executed, the task segment address or size, etc. to the task segment acquisition instruction. The task segment acquisition instruction is used to instruct sending the next task segment to be executed to the processing core of the task to be executed indicated by the parameters.

[0093] like Figure 2b As shown, in one embodiment, the task allocation method further includes:

[0094] Step S205, the processing core of the task to be executed sends a data acquisition instruction according to the received task segment to be executed;

[0095] Step S206: According to the data acquisition instruction, the processing cores of the tasks to be executed receive their respective input data.

[0096] It can be understood that the above steps S205 and S206 are performed after step S202 and between step S203, that is, before the processing core of the task to be executed executes the task segment to be executed, the input data corresponding to the task segment to be executed is first obtained.

[0097] Similarly, the input data is also obtained by sending a data acquisition instruction to the storage manager. After receiving the data acquisition instruction, the storage manager decodes the data acquisition instruction, executes the instruction to obtain the corresponding input data, and sends it to the corresponding processing core.

[0098] Optionally, the step S206 includes: using the identifier of the processing core of the task to be executed as a parameter of the data acquisition instruction to obtain the input data of each of the master processing core and the slave processing core. Exemplarily, in the steps S205 and S206, the processing cores of the task to be executed use their respective identifiers as parameters of the data acquisition instruction to configure the data acquisition instruction, and then send the data acquisition instruction with the configuration parameters to the storage manager to obtain the data corresponding to the identifier of each processing core of the task to be executed from the external memory and send it to the processing core corresponding to the identifier as input data when the processing core executes the task segment.

[0099] It is understandable that, depending on different application scenarios, the input data of different processing cores can be the same or different. For example, in order to speed up the calculation, multiple processing cores execute the same task segment in parallel to quickly obtain the output data of the task segment. At this time, the input data of each processing core is different to obtain a better parallel computing effect. For example, in another scenario, multiple processing cores execute different task segments respectively. At this time, the same input data may need to be processed by multiple task segments respectively. At this time, the input data obtained by multiple processing cores is the same.

[0100] In this embodiment, when the main processing core receives the first synchronization signal, the synchronization signal does not need to be triggered by the synchronization request signal. At this time, the main processing core calls and executes the task update instruction. The task update instruction can divide different tasks into different numbers of segments and assign them to different processing cores for parallel processing. Exemplarily, there are two processing cores in the chip that execute the task, one main processing core and one slave processing core. The task update instruction can divide the complete task into two task segments, and each task segment is simultaneously handed over to the main processing core and the slave processing core, and is executed by the main processing core and the slave processing core respectively.

[0101] In this optional embodiment, the synchronization request signal includes the synchronization request signal generated by the at least two processing cores that execute the task. That is, when there are multiple processing cores, each processing core will send its own synchronization request signal.

[0102] Further, the synchronization request signal is used to trigger the generation of the synchronization signal, including: in response to the processing cores of the tasks to be executed all sending the synchronization request signal, triggering the generation of the synchronization signal. In this embodiment, the synchronization signal is generated only after each processing core of the tasks to be executed sends the synchronization request signal.

[0103] The above embodiment discloses a task allocation method, which is used in a chip, wherein the chip includes a main processing core and at least one slave processing core, wherein the task allocation method includes: in response to receiving a synchronization signal, the main processing core executes a task update instruction to obtain a task segment to be executed, wherein the task segment to be executed is a part of the task; the processing core of the task to be executed receives the task segment to be executed, wherein the processing core of the task to be executed includes the main processing core and / or the slave processing core; the processing core of the task to be executed executes the task segment to be executed; in response to completing the execution of the task segment to be executed, the processing core of the task to be executed sends a synchronization request signal, wherein the synchronization request signal is used to trigger the generation of the synchronization signal. By allocating the task segment executed by the processing core according to the synchronization signal by the main processing core in the chip in the above method, the technical problems of inflexible task allocation and complex control of the processing core in the prior art are solved.

[0104] In the above, although the various steps in the above method embodiment are described in the above order, those skilled in the art should be aware that the steps in the embodiments of the present disclosure are not necessarily executed in the above order, and they may also be executed in other orders such as reverse order, parallel order, and cross order. Moreover, on the basis of the above steps, those skilled in the art may also add other steps. These obvious variations or equivalent replacement methods should also be included in the protection scope of the present disclosure and will not be repeated here.

[0105] Figure 3 This is a schematic diagram of the structure of the chip provided in the embodiment of the present disclosure. Figure 3 The chip 300 shown includes: a main processing core 301, at least one slave processing core 302 and a storage manager 303. The main processing core is used to execute a task update instruction in response to receiving a synchronization signal to obtain a task segment to be executed, and the task segment to be executed is a part of the task; the storage manager is used to retrieve the task segment to be executed indicated by the task update instruction from an external memory based on the task update instruction, and send the task segment to be executed to the processing core of the task to be executed; the processing core of the task to be executed includes the main processing core and / or the slave processing core; the processing core of the task to be executed is used to receive the task segment to be executed; the processing core of the task to be executed is also used to execute the task segment to be executed; the processing core of the task to be executed is also used to send a synchronization request signal in response to the completion of the task segment to be executed, wherein the synchronization request signal is used to trigger the generation of the synchronization signal. The main processing core also includes an internal storage space PRAM for storing the task update program and the task segment; the slave processing core also includes an internal storage space PRAM for storing the task segment.

[0106] The chip 300 may further include a synchronization signal generating unit 304 , which is connected to the multiple processing cores and is used to generate a synchronization signal Sync, and the synchronization signal is sent to each of the multiple processing cores.

[0107] Optionally, the synchronization signal generating unit is a dedicated hardware component, which generates the first synchronization signal when it is started, and then triggers the generation of the synchronization signal after receiving the synchronization signal request sent by the processing cores of all tasks to be executed.

[0108] Optionally, the synchronization signal generating unit is a program unit. In this case, the synchronization signal is generated by the program unit. In this case, a program is required to generate the first synchronization signal after startup, and then trigger the generation of the synchronization signal after receiving the synchronization signal request message packet sent by the processing cores of all tasks to be executed.

[0109] In an optional implementation, the synchronization signal generating unit may also be connected only to the master processing core, and the synchronization of the slave processing core is achieved by the master processing core instructing the MME, which is not elaborated here.

[0110] The following is attached Figure 3 The process of generating the synchronization signal in this embodiment is the same as that in the method embodiment, and will not be repeated here. In this embodiment, all processing cores are processing cores of the tasks to be executed.

[0111] like Figure 3 As shown, when the first preset condition is met, each processing core of the task to be executed sends a synchronization request signal SQ_1, SQ_2, ... SQ_N respectively. After the synchronization signal generating unit receives the synchronization request signals sent by all the processing cores of the tasks to be executed, the synchronization signal Sync is generated, and the synchronization signal is sent by the synchronization signal generating unit to the processing cores of each task to be executed at the same time.

[0112] Furthermore, the main processing core is also used to: execute a task update instruction to send a task segment acquisition instruction to the storage manager; the storage manager is used to execute the task segment acquisition instruction to read the task segment to be executed from the external memory and send it to the processing core of the task to be executed.

[0113] Furthermore, the processing core of the task to be executed is also used to send a data acquisition instruction according to the received task segment to be executed; and receive respective input data according to the data acquisition instruction.

[0114] Furthermore, the processing core of the task to be executed is also used to use the identification of the processing core of the task to be executed as a parameter of the data acquisition instruction to obtain the input data of each processing core of the task to be executed.

[0115] Further, the synchronization request signal is used to trigger the generation of the synchronization signal, including:

[0116] In response to the processing cores of the tasks to be executed all sending the synchronization request signal, the generation of the synchronization signal is triggered.

[0117] Furthermore, the main processing core is also used to respond to receiving a synchronization signal, use the number of times the synchronization signal is received as a parameter for executing the task update instruction to generate a task segment acquisition instruction; and send the task segment acquisition instruction to acquire the corresponding task segment to be executed.

[0118] Furthermore, after receiving the synchronization signal, the main processing core is further configured to start a synchronization counter to record the number of times the synchronization signal is received by the main processing core.

[0119] like Figure 3 As shown, optionally, the processing cores of the tasks to be executed in each synchronization cycle and the task segments to be executed are pre-allocated by the system, and the allocation parameters of the task update program are generated. The allocation parameters corresponding to all synchronization cycles form the fixed allocation rules. The main processing core 301 executes the task update program to allocate the corresponding task segments to the processing cores of the tasks to be executed; exemplarily, the allocation parameters of the task update program are allocation parameters pre-compiled and generated outside the chip, which determine the processing cores of the tasks to be executed in each clock cycle and the task segments to be executed corresponding to the processing cores of each task to be executed. The main processing core acts as an execution unit of the task update program, and executes the task update instructions in the task update program to allocate the task segments to be executed to the processing cores of each task to be executed. In this case, the main processing core is an execution unit, which only needs to allocate the task segments to be executed to the processing cores of the tasks to be executed in each synchronization cycle according to the pre-set settings.

[0120] Optionally, the processing core of the task to be executed in each synchronization cycle and the task segment to be executed can also be dynamically determined by the task update program, and the main processing core 301 dynamically obtains the allocation parameters. Exemplarily, the dynamic allocation rule is to determine the processing core of the task to be executed in each cycle and the size and / or storage address of the corresponding task segment to be executed according to the specific status of each processing core in each cycle, such as the size of the remaining storage space. In this case, the main processing core is a computing unit, which needs to calculate the processing core of the task to be executed in the current synchronization cycle and the size and / or storage address of the corresponding task segment according to the status of each processing core in the current synchronization cycle according to the preset dynamic allocation rule.

[0121] Taking system pre-allocation as an example, the allocation parameters are set in an external memory or other host. When the chip is initialized, the main processing core reads the allocation parameters from the external memory or other host. The allocation parameters of a complete task include the processing core of the task to be executed used in each synchronization cycle of the complete task and the task segment to be executed by the processing core of the task to be executed. In the first synchronization cycle, the main processing core receives the synchronization signal, executes the task update instruction, and writes the allocation parameters of the first synchronization cycle into the task segment acquisition instruction. The allocation parameters include the processing core of the task to be executed in the first synchronization cycle, the task segment to be allocated, and the storage address of the task segment to be allocated. The main processing core sends the task segment acquisition instruction to the MME, so that when the MME executes the task segment acquisition instruction, it reads the corresponding task segment from the external memory 305 and sends it to the corresponding processing core of the task to be executed.

[0122] The processing core includes an internal storage space PRAM for storing the task segment; the task segment consists of a series of instructions, and the processing core reads the instructions from the PRAM, decodes the instructions, and then executes the instructions, and no longer needs to read the instructions from the external memory. The storage space of the PRAM of each processing core is limited, so a complete task needs to be divided into multiple task segments for execution. When the processing core completes the task segment, it will execute a synchronization signal request instruction to send a synchronization signal request to the synchronization signal generating unit.

[0123] After receiving the synchronization signal request from each processing core of the task to be executed, the synchronization signal generating unit generates a new synchronization signal and sends it to each processing core that sends the synchronization request signal; after the main processing core receives the synchronization signal, it determines the number of synchronization signals received and executes the task update instruction. The allocation parameters are determined according to the number of synchronization signals, and the allocation parameters determine the processing core of the task to be executed and the task segment to be executed. The allocation parameters are written into the task segment acquisition instruction so that the storage controller executes the task acquisition instruction to take the corresponding task segment from the external memory and send it to the corresponding processing core. At other times when the task update instruction is not executed, the main processing core can execute its own task segment without being idle like a dedicated scheduler, thereby improving the execution efficiency of the main processing core.

[0124] The following is an actual application scenario to illustrate the task allocation process in the present disclosure. Figure 4An example of a chip described in an embodiment of the present disclosure is shown. In this example, the chip includes two processing cores C1 and C2, wherein the main processing core is C1 and the slave processing core is C2, and a storage controller, wherein the memory is connected to the external memory. The chip may also include a synchronization signal generating unit. It can be understood that the synchronization signal generating unit can be implemented as hardware inside a chip or as a synchronization signal generating program, which will not be repeated here. Exemplarily, the PRAM size of the processing cores C1 and C2 is 36KB, wherein C1 is the main processing core, and there is a 4KB task update program in its PRAM. The task update program is a resident program and does not change during the execution of the task. When a new task is executed, it can be updated by initializing the main processing core. The other 32KB is used to store other programs, i.e., the task segment to be executed. In this example, C1 and C2 execute the same task segment.

[0125] In one embodiment, the task is a computational task of a two-layer neural network, such as Figure 5 As shown, the neural network in this example includes two layers, layer1 and layer2, where layer1 receives input data and calculates, and inputs the calculation result into layer2, and layer2 calculates the data input from layer1 to obtain the final output. The size of the calculation program P1 of the first layer is 64KB, and the size of the calculation program P2 of the second layer is also 64KB. Then the entire network can be assigned to two processing cores for parallel pipeline calculation according to the task allocation strategy, that is, each layer is divided into two task segments for execution, and C1 and C2 are responsible for the execution of the two task segments of each layer of the network at the same time, each obtains input data and executes the corresponding task segment. In the first time period, C1 receives the first segment of input data of the first layer, and C1 processes the first segment of input data of the first layer according to the first task segment of the first layer; C2 receives the second segment of input data of the first layer, and C2 processes the second segment of input data of the first layer according to the first task segment of the first layer. In the second clock cycle, C1 uses the output data of C1 in the first cycle as the input data in the second clock cycle, and processes it according to the second task segment of the first layer; similarly, C2 uses the output data of C2 in the first cycle as the input data in the second clock cycle, and processes it according to the second task segment of the first layer; similarly, in the third and fourth clock cycles, C1 and C2 use the output data of one clock cycle as the input data of this clock cycle respectively, and process it according to the first task segment and the second task segment of the second layer. Finally, the outputs of the two processing cores in the fourth time cycle are merged into the final output result.

[0126] The process of pipeline calculation is as follows: Figure 6As shown, at time t1, C1 receives the first segment of input data of the first layer, processes the input data according to the first task segment of the first layer, and caches the processing results; at time t1, C2 receives the second segment of input data of the first layer, processes the input data according to the first task segment of the first layer, and caches the processing results. At time t2, C1 and C2 update the second segment calculation program of the first layer, and process the input data according to the second segment of the first layer to obtain the processing results, and merge the processing results obtained at t1 and t2 into the output results of the first layer; continue the above process, update the calculation program to the task segment of the second layer in the next two time periods, use the output results of the first layer as the input data of the second layer to obtain the output results of the second layer; finally, integrate the output results of the second layer to obtain the complete output results.

[0127] Figure 7 The following is a timing diagram of task allocation and execution of a processing core. In this example, a task is divided into two task segments P_1 and P_2 for execution. Figure 7 As shown, initially, the synchronization signal generating unit generates the first synchronization signal. At this time, the main processing core C1 executes the task update instruction in the resident task update program, starts the counter to count the synchronization signal Sync, and generates a task segment acquisition instruction according to the number of Sync and the allocation parameters corresponding to the number. The task segment acquisition instruction includes parameters such as the processing cores C1 and C2 of the task to be executed, the task segments P_1 to be executed by C1 and C2, and the storage address of the task segment P_1 to be executed. The main processing core sends the task segment acquisition instruction to the MME; the MME decodes and executes the task segment acquisition instruction, reads the first task segment P_1 of C1 and C2 from the external memory, and writes it into the PRAM of C1 and C2, that is, Figure 7 In the t1 period, after receiving the Sync signal, C1 executes the task segment update program, and then the MME obtains the task segment P_1 to be executed from the external memory according to the task acquisition instruction and sends the task segment P_1 to be executed to C1 and C2. In the remaining time of the synchronization period, C1 and C2 obtain their corresponding input data and execute the first task segment until the execution is completed. After C1 executes the first task segment, it sends a synchronization signal request SQ_1 to the synchronization signal generating unit, and after C2 executes the first task segment, it sends a synchronization signal request SQ_2 to the synchronization signal generating unit; after receiving SQ_1 and SQ_2, the synchronization signal generating unit generates a new synchronization signal Sync; then C1 continues the above process according to the new synchronization signal Sync, so that C1 and C2 execute the second task segment P_2, and repeats until a complete task is executed in parallel by C1 and C2. Afterwards, C1 and C2 can continue to execute the next task (2 according to the task update instruction). nd task).

[0128] The solution shown in the above example is that all processing cores execute a task segment in parallel to speed up the execution of the task segment. It is understandable that in actual applications, in the first synchronization cycle, the task segment may be allocated to only one processing core. For example, C2 needs to wait for the execution result of the first task segment of C1 as the input data of the first task segment of C2. At this time, C2 can execute other tasks or wait idle in the first synchronization cycle. More generally, when a processing core needs to wait for the output result of another processing core as its input, it can execute other tasks or wait idle before obtaining the output result of the other processing core. This is related to the pre-set allocation strategy.

[0129] An embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that when the processors are executed, any of the task allocation methods in the embodiments is implemented.

[0130] The embodiment of the present disclosure also provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute any of the task allocation methods described in the aforementioned embodiments.

[0131] The embodiment of the present disclosure also provides a computer program product, wherein the characteristic is: it includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any of the task allocation methods in the aforementioned embodiments.

[0132] The disclosed embodiments further provide a computing device, characterized in that it comprises any chip described in the embodiments.

[0133] The flowcharts and block diagrams in the accompanying drawings of the present disclosure illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, task segment, or a part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0134] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0135] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0136] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Claims

1. A task allocation method, used in a chip, wherein the chip includes a master processing core and at least one slave processing core, characterized in that: The method comprises: In response to receiving the synchronization signal, the main processing core executes a task update instruction to obtain a task segment to be executed, the task segment to be executed is a part of the task to be executed, and the synchronization signal is generated by a synchronization signal generating unit in the chip; The main processing core instructs the storage manager to read the task segment to be executed from the external memory and send it to the task core of the task to be executed; The processing core of the task to be executed receives the task segment to be executed, wherein the processing core of the task to be executed includes the master processing core and the slave processing core, or the processing core of the task to be executed includes the slave processing core; The processing core of the task to be executed executes the task segment to be executed; In response to completing the execution of the task segment to be executed, the processing core of the task to be executed sends a synchronization request signal, wherein the synchronization request signal is used to trigger the synchronization signal generating unit to generate the synchronization signal.

2. The task allocation method according to claim 1, wherein the main processing core executes the task update instruction to obtain the task segment to be executed, comprising: The main processing core executes the task update instruction to send the task segment acquisition instruction to the storage manager; The storage manager executes the task segment acquisition instruction to read the to-be-executed task segment from the external memory and sends the task segment to the master processing core and the slave processing core.

3. The task allocation method according to claim 1 or 2, characterized in that: The method further comprises: The processing core of the task to be executed sends a data acquisition instruction according to the received task segment to be executed; According to the data acquisition instruction, the processing cores of the tasks to be executed receive respective input data.

4. The task allocation method according to claim 3, wherein the processing cores of the tasks to be executed receive their respective input data according to the data acquisition instruction, comprising: The identifier of the processing core of the task to be executed is used as a parameter of the data acquisition instruction to acquire the input data of the processing core of the task to be executed.

5. The task allocation method according to claim 1 or 2, characterized in that: The synchronization request signal is used to trigger the generation of the synchronization signal, including: In response to the processing cores of the tasks to be executed all sending the synchronization request signal, the generation of the synchronization signal is triggered.

6. The task allocation method according to claim 1 or 2, characterized in that: In response to receiving the synchronization signal, the main processing core executes the task update instruction to obtain the task segment to be executed, including: In response to receiving the synchronization signal, the main processing core uses the number of times the synchronization signal is received as a parameter for executing the task update instruction to generate a task segment acquisition instruction; The main processing core sends the task segment acquisition instruction to acquire the corresponding task segment to be executed.

7. The task allocation method according to claim 1 or 2, characterized in that: After receiving the synchronization signal, the method further includes: The main processing core starts a synchronization counter to record the number of times the synchronization signal is received by the main processing core.

8. A chip, characterized in that: include: a master processing core, at least one slave processing core, and a storage manager; The main processing core is used to execute a task update instruction to obtain a task segment to be executed in response to a received synchronization signal, and to instruct a storage manager to read the task segment to be executed from an external memory and send it to a task core of the task to be executed; the task segment to be executed is a part of the task to be executed, and the synchronization signal is generated by a synchronization signal generating unit in the chip; The storage manager is used to fetch the to-be-executed task segment corresponding to the task update instruction from the external memory based on the task update instruction, and send the to-be-executed task segment to the processing core of the to-be-executed task; The processing cores of the tasks to be executed include the master processing core and the slave processing core, or the processing cores of the tasks to be executed include the slave processing core; The processing core of the task to be executed is used to receive the task segment to be executed; The processing core of the task to be executed is also used to execute the task segment to be executed; The processing core of the task to be executed is also used to send a synchronization request signal in response to completing the execution of the task segment to be executed, wherein the synchronization request signal is used to trigger the synchronization signal generating unit to generate the synchronization signal.

9. The chip according to claim 8, characterized in that The chip further comprises: The on-chip network is connected to the master processing core, the slave processing core and the storage manager, and is used for transmitting data between the processing core, the slave processing core and the storage manager.

10. A computing device, characterized in that: Comprising one or more chips according to any one of claims 8 or 9.

Images