Data transmission method, device, electronic device and storage medium

Abstract

The embodiment of the present application provides a data transmission method, device, electronic device and storage medium, the method comprising: obtaining the digital code of the data to be sent; determining the GPIO level frames of each general input / output port corresponding to the digital code of the data to be sent according to the preset frame time and the preset coding level conversion rule, and obtaining each target GPIO level frame, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rule is the correspondence rule between the digital code and the GPIO level frame; and sending each target GPIO level frame to the receiving end in sequence. In the data transmission method of the embodiment of the present application, data transmission is performed in the form of a GPIO level frame, and the duration of each single-frame GPIO level frame is the preset frame time. Each GPIO level frame can be effectively distinguished by the duration, thereby effectively distinguishing each data, reducing the sampling difficulty, and effectively realizing point-to-point single-line GPIO data transmission.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device, electronic device and storage medium. Background Art

[0002] Among point-to-point single-wire communication protocols, the most commonly used are UART (Universal Asynchronous Receiver / Transmitter) and 1-WIRE protocols. In these protocols, the receiving end needs to continuously detect the received signal at a sampling frequency far exceeding the baud rate of the sending end, which puts a heavy load on the CPU. In addition, it is difficult to implement the existing UART or 1-WIRE protocol on GPIO (General Purpose Input / Output) through software. There are two main reasons: 1. The BIT (binary digit) edge sampling is inaccurate, and 2. It is difficult to sample multiple consecutive 0 or consecutive 1 data. Therefore, there is an urgent need for a single-wire GPIO data transmission method that can be effectively applied to point-to-point. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a data transmission method, device, electronic device and storage medium to provide an effective single-line GPIO data transmission method for point-to-point transmission. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a sending end, and the method includes:

[0005] Get the digital code of the data to be sent;

[0006] According to the preset frame time and the preset coding level conversion rule, each general purpose input / output port GPIO level frame corresponding to the digital code of the data to be sent is determined to obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset coding level conversion rule is the correspondence rule between the digital code and the GPIO level frame;

[0007] The target GPIO level frames are sent to the receiving end in sequence.

[0008] Optionally, the GPIO level frame represents different digital codes through different levels of interruption times and / or levels.

[0009] Optionally, the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0010] Optionally, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0011] Optionally, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0012] Optionally, the sending end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0013] In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a receiving end, and the method includes:

[0014] Receive each GPIO level frame to be decoded sent by the transmitter;

[0015] According to the preset frame time and the preset coding level conversion rule, each of the GPIO level frames to be decoded is decoded into digital codes in turn, wherein the preset frame time is the duration of a single GPIO level frame, and the preset coding level conversion rule is the correspondence rule between digital codes and GPIO level frames.

[0016] Optionally, the GPIO level frame represents different digital codes through different levels of interruption times and / or levels.

[0017] Optionally, the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0018] Optionally, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0019] Optionally, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0020] Optionally, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0021] In a third aspect, an embodiment of the present application provides a data transmission device, applied to a transmitting end, the device comprising:

[0022] A digital code acquisition module, used to acquire the digital code of the data to be sent;

[0023] A GPIO level frame determination module is used to determine the GPIO level frames of each general input / output port corresponding to the digital code of the data to be sent according to a preset frame time and a preset coding level conversion rule, and obtain each target GPIO level frame, wherein the preset frame time is the duration of a single GPIO level frame, and the preset coding level conversion rule is the correspondence rule between the digital code and the GPIO level frame;

[0024] The GPIO level frame sending module is used to send each of the target GPIO level frames to the receiving end in sequence.

[0025] Optionally, the GPIO level frame represents different digital codes through different levels of interruption times and / or levels.

[0026] Optionally, the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0027] Optionally, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0028] Optionally, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0029] Optionally, the sending end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0030] In a fourth aspect, an embodiment of the present application provides a data transmission device, applied to a receiving end, the device comprising:

[0031] The GPIO level frame receiving module is used to receive each GPIO level frame to be decoded sent by the sending end;

[0032] The digital code conversion module is used to decode each of the GPIO level frames to be decoded into digital codes in sequence according to a preset frame time and a preset code level conversion rule, wherein the preset frame time is the duration of a single GPIO level frame, and the preset code level conversion rule is the correspondence rule between the digital code and the GPIO level frame.

[0033] Optionally, the GPIO level frame represents different digital codes through different levels of interruption times and / or levels.

[0034] Optionally, the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0035] Optionally, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0036] Optionally, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0037] Optionally, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0038] In a fifth aspect, an embodiment of the present application provides an electronic device, including a memory and at least two processors, wherein the at least two processors are connected via a GPIO;

[0039] The memory is used to store computer programs;

[0040] The processor is used to implement any of the above-mentioned data transmission methods when executing the program stored in the memory.

[0041] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any of the above-mentioned data transmission methods is implemented.

[0042] The data transmission method, device, electronic device and storage medium provided in the embodiment of the present application obtain the digital code of the data to be sent; determine the GPIO level frames of each general input / output port corresponding to the digital code of the data to be sent according to the preset frame time and the preset coding level conversion rule, and obtain each target GPIO level frame, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rule is the corresponding rule between the digital code and the GPIO level frame; and send each target GPIO level frame to the receiving end in sequence. A data transmission method based on GPIO level frames is provided, which uses the form of GPIO level frames for data transmission. The duration of each single-frame GPIO level frame is the preset frame time, and each GPIO level frame can be effectively distinguished according to the duration. Even if multiple consecutive 0s or 1s are sent, they can be effectively distinguished according to the duration, reducing the sampling difficulty and effectively realizing point-to-point single-line GPIO data transmission. Of course, the implementation of any product or method of the present application does not necessarily require all the advantages described above to be achieved at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic diagram of a data transmission method applied to a sending end according to an embodiment of the present application;

[0045] Figure 2 A schematic diagram of an application scenario of an embodiment of the present application;

[0046] Figure 3 A schematic diagram of the levels in the data transmission method according to an embodiment of the present application;

[0047] Figure 4 A schematic diagram of a data transmission method applied to a receiving end according to an embodiment of the present application;

[0048] Figure 5 A schematic diagram of a data transmission device applied to a sending end according to an embodiment of the present application;

[0049] Figure 6 A schematic diagram of a data transmission device applied to a receiving end according to an embodiment of the present application;

[0050] Figure 7 A schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] First, the professional terms in the embodiments of the present application are explained:

[0053] GPIO: (General Purpose Input / Output) is a controllable pin of an embedded device that is connected to external devices to achieve external communication, control, and data acquisition functions.

[0054] Interrupt: refers to the process in which a computer automatically stops the running program and switches to a program that handles the new situation when some unexpected situation occurs during the operation of the computer and requires host intervention. After the processing is completed, the computer returns to the originally paused program and continues to run. The interrupt of the GPIO level frame in the embodiment of the present application is triggered by the rising edge and falling edge of the level.

[0055] Embedded: A device used to control, monitor or assist in the operation of machines and equipment. It is a special-purpose computer system with strict requirements on functions, reliability, cost, volume, power consumption, etc. It is a combination of software and hardware.

[0056] Baud rate: It indicates the number of code symbols transmitted per second. It is an indicator to measure the data transmission rate and is expressed by the number of times the carrier modulation state changes per unit time.

[0057] CPU: (Central Processing Unit) is a large-scale integrated circuit, which is the computing core and control unit of a computer. Its main function is to interpret computer instructions and process data in computer software.

[0058] GPIO is widely used in existing CPU chips. In many communication methods, a device is divided into multiple sub-boards. In many cases, the signal interfaces between sub-boards are relatively few, but each module needs to communicate with each other. In the prior art, network communication is often used between modules, but when IP addresses and MAC addresses are not configured between sub-boards, network communication cannot be used.

[0059] In view of this, the present application embodiment provides a data transmission method, which is applied to the sending end, see Figure 1 , the method comprising:

[0060] S101, obtaining the digital code of the data to be sent.

[0061] The data transmission method applied to the sending end in the embodiment of the present application can be implemented by an electronic device, specifically, can be implemented by a CPU of the electronic device, and the receiving end and the sending end can be different CPUs, for example, see Figure 2 , only one GPIO signal connection line is needed for data transmission between two devices. When there are few interface signals between two devices and network communication has not been established, the embodiment of the present application can meet the needs of simple communication between the two devices. Since the GPIO interface is the most common in chips, and GPIO has the advantages of low power consumption, simple wiring, and strong applicability, GPIO is used for communication in the embodiment of the present application.

[0062] The data to be sent may be transmitted in the form of digital codes. The data to be sent is converted into digital codes, such as binary codes or decimal codes, to obtain the digital codes of the data to be sent.

[0063] S102, according to the preset frame time and the preset coding level conversion rule, determine each GPIO level frame corresponding to the digital code of the above-mentioned data to be sent, and obtain each target GPIO level frame, wherein the above-mentioned preset frame time is the duration of a single-frame GPIO level frame, and the above-mentioned preset coding level conversion rule is the correspondence rule between the digital code and the GPIO level frame.

[0064] In the embodiment of the present application, data transmission is carried out in the form of GPIO level frames. GPIO level frame refers to the GPIO level within a unit duration, and the unit duration is the preset frame time, which can be customized according to actual conditions. The preset coding level conversion rule is the correspondence rule between digital coding and GPIO level frame. Different digital codes correspond to different GPIO level frames. The data transmission in the embodiment of the present application can be divided into three stages, including: Start, Trans and Stop. Start indicates the start of data transmission, Trans indicates the specific data to be transmitted, that is, the data to be sent, and Stop indicates the stop of data transmission. According to the preset coding level conversion rule, with the preset frame time as the duration of each frame of GPIO level frame, each GPIO level frame corresponding to the digital coding of the data to be sent, that is, each target GPIO level frame, is generated in sequence.

[0065] In a possible implementation manner, the GPIO level frame represents different digital codes through different levels of level interruption times and / or levels.

[0066] In the embodiment of the present application, the level interrupt is triggered by the rising edge and falling edge of the level. When the level is converted from a low level to a high level, a level interrupt is triggered. Similarly, when the level is converted from a high level to a low level, a level interrupt is also triggered. The number of level interrupts within a unit time length (i.e., in a GPIO level frame) and / or the level (i.e., high level, low level) can be used to distinguish different digital codes, Start, Stop, etc.

[0067] Because the number of interruptions in the present application embodiment represents different digital codes, the selection of the counting time point is particularly important. In order to avoid confusion between the counting of each BIT in different stages and between BYTEs (bytes), a frame time (preset frame time) is introduced after each stage and each BIT transmission to distinguish each GPIO level frame. The interval time of continuous baud rate interruptions can be ignored compared to the frame time.

[0068] S103, sending the above target GPIO level frames to the receiving end in sequence.

[0069] The sending end sends each target GPIO level frame to the receiving end in sequence.

[0070] In an embodiment of the present application, a data transmission method based on GPIO level frames is provided, and data transmission is performed in the form of GPIO level frames. The duration of each single-frame GPIO level frame is a preset frame time, and each GPIO level frame can be effectively distinguished according to the duration. Even if multiple consecutive 0s or 1s are sent, they can be effectively distinguished according to the duration, thereby reducing the sampling difficulty and effectively realizing point-to-point single-line GPIO data transmission.

[0071] Taking binary coding as an example, the number of interrupts of 0 (BIT0) and 1 (BIT1) in the Trans phase is adjustable and can be customized according to the actual situation. In a possible implementation, the above digital coding is binary coding, see Figure 3 The above binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0072] GPIO level frames are distinguished by frame time intervals. Combined with the counting characteristics of different stages, the number of interruptions is calculated, and finally the target GPIO level frames corresponding to the data to be sent are calculated. The Trans stage is between the Start and Stop stages. In the Trans stage, a BYTE consists of eight BITs, and each BIT can be 0 or 1. In order to distinguish BIT0 from BIT1, BIT0 can be designed as 1 interrupt and BIT1 as 3 consecutive interrupts.

[0073] In one possible implementation, see Figure 3 The GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the above-mentioned start signal and the above-mentioned end signal are different.

[0074] The start signal indicates Start, which means the start of transmission; the end signal indicates Stop, which means the end of transmission. There are 5 consecutive interrupts in the Start stage, and 5 consecutive interrupts in the Stop stage. Although there are 5 consecutive interrupts in both the Start and Stop stages, Start and Stop can be distinguished by different starting levels. For example, the starting level in the Start stage is high, and the level remains low after 5 flips, while the starting level in the Stop stage is low, and the level remains high after 5 flips. Of course, the starting levels of the Start stage and the Stop stage can also be swapped, and can be customized according to actual conditions.

[0075] In the embodiment of the present application, the starting levels of the start signal and the end signal are different, which can effectively distinguish the Start stage and the Stop stage.

[0076] In a possible implementation, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0077] In the Trans stage, for the counting of the first digital bit, only one GPIO level frame is used, which cannot effectively distinguish whether it is BIT0 or BIT1. Therefore, the Trans stage is divided into two parts: the first digital bit and the other bits.

[0078] For the first digital bit, two GPIO level frames are selected, that is, one frame time after the end of Start plus the frame time after the end of a digital bit. For example, for a single frame BIT0 is 1 interrupt and a single frame BIT1 is 3 consecutive interrupts, if the first digital bit is BIT0, the GPIO interrupt count is 2 after two frames; if the first digital bit is BIT1, the GPIO interrupt count is 4 after two frames.

[0079] In the Trans phase, only one GPIO level frame is needed to count the bits other than the first digit, and the end time of the count is the frame time after the end of the bit. If a bit other than the first digit is BIT0, the GPIO interrupt count is 1 after the GPIO level frame of the bit ends; if a bit other than the first digit is BIT1, the GPIO interrupt count is 3 after the GPIO level frame of the bit ends.

[0080] In a possible implementation manner, the transmitting end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0081] In single GPIO mode, in order to prevent the two parties of the GPIO connection from preempting GPIO transmission, one party is specified as the HOST (master device) and the other party is specified as the SLAVE (slave device). All communication processes must be initiated by the HOST, that is, the data sent by the SLAVE party is also initiated after being notified by the HOST, thereby avoiding the abnormal situation caused by the two ends sending data at the same time.

[0082] The present application also provides a data transmission method, which is applied to a receiving end. Figure 4 , the method comprising:

[0083] S201, receiving each GPIO level frame to be decoded sent by a transmitting end.

[0084] S202, according to the preset frame time and the preset coding level conversion rule, decode each of the above-mentioned GPIO level frames to be decoded into digital codes in turn, wherein the above-mentioned preset frame time is the duration of a single frame of GPIO level frame, and the above-mentioned preset coding level conversion rule is the correspondence rule between digital code and GPIO level frame.

[0085] In a possible implementation manner, the GPIO level frame represents different digital codes through different levels of level interruption times and / or levels.

[0086] In a possible implementation manner, the digital code is a binary code, and the binary code includes 0 and 1. The GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0087] In a possible implementation manner, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0088] In a possible implementation, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0089] In a possible implementation manner, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0090] Set the GPIO interrupt mode to rising edge and falling edge trigger. The counting is distinguished by frame time intervals, combined with the counting characteristics of different stages, the interrupt number is compared, and the transmission data is finally calculated.

[0091] In the Start and Stop stages, the number of interrupts is different from that in the Trans stage, and the level states after the transmission are also different. The level is low after the Start transmission is completed, and the level is high after the Stop transmission is completed. Therefore, the Start and Stop stages are very easy to distinguish in the timing.

[0092] In the Trans stage, for the first bit count, only one frame time is used, and it is impossible to determine whether it is BIT0 or BIT1, so the count must be divided into two parts: the count of the first bit and the count of other bits. For the first bit, two frames are used, that is, one frame time after the end of Start plus the frame time after the end of the first bit. If the first bit is BIT0, the GPIO interrupt count is 2 after two frames; if the first bit is BIT1, the GPIO interrupt count is 4 after two frames.

[0093] For the counting of other bits except the first bit in the Trans phase, only one frame time is needed, and the frame time is the frame time after the end of the bit. If the first bit is BIT0, the GPIO interrupt count is 1 after the frame ends; if the first bit is BIT1, the GPIO interrupt count is 3 after the frame ends.

[0094] Although the Stop stage is defined as 5 interrupts, since the count of each bit in the Trans stage is the frame time after that bit, in actual judgment, only 4 interrupts are left for the Stop bit.

[0095] In an embodiment of the present application, a data transmission method based on a GPIO level frame is provided, which effectively realizes point-to-point single-line GPIO data transmission.

[0096] The present application also provides a data transmission device. Figure 5 , applied to the transmitting end, the device comprises:

[0097] A digital code acquisition module 11 is used to acquire the digital code of the data to be sent;

[0098] The GPIO level frame determination module 12 is used to determine the GPIO level frames of each general input / output port corresponding to the digital code of the data to be sent according to the preset frame time and the preset code level conversion rule, and obtain each target GPIO level frame, wherein the preset frame time is the duration of a single frame GPIO level frame, and the preset code level conversion rule is the correspondence rule between the digital code and the GPIO level frame;

[0099] The GPIO level frame sending module 13 is used to send the above target GPIO level frames to the receiving end in sequence.

[0100] Optionally, the GPIO level frame represents different digital codes through different levels of interruption times and / or levels.

[0101] Optionally, the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0102] Optionally, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0103] Optionally, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0104] Optionally, the sending end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0105] The present application also provides a data transmission device. Figure 6 , applied to a receiving end, the above device comprises:

[0106] The GPIO level frame receiving module 21 is used to receive each GPIO level frame to be decoded sent by the sending end;

[0107] The digital code conversion module 22 is used to decode each of the above-mentioned GPIO level frames to be decoded into digital codes in sequence according to the preset frame time and the preset code level conversion rule, wherein the above-mentioned preset frame time is the duration of a single frame of GPIO level frame, and the above-mentioned preset code level conversion rule is the correspondence rule between digital code and GPIO level frame.

[0108] Optionally, the GPIO level frame represents different digital codes through different levels of interruption times and / or levels.

[0109] Optionally, the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.

[0110] Optionally, the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different.

[0111] Optionally, during the transmission phase, the first digital bit is represented by two GPIO level frames.

[0112] Optionally, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.

[0113] The present application also provides an electronic device, see Figure 7 , including a memory 32 and at least two processors 31, wherein the at least two processors 31 are connected via GPIO;

[0114] The memory 32 is used to store computer programs;

[0115] The processor 31 is used to implement any of the above-mentioned data transmission methods when executing the program stored in the memory 32.

[0116] The memory may include RAM (Random Access Memory) or NVM (Non-Volatile Memory), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0117] The above-mentioned processor can be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc.; it can also be a DSP (Digital Signal Processing), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0118] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-mentioned data transmission methods is implemented.

[0119] It should be noted that, in this article, the technical features in each optional solution can be combined to form a solution as long as there is no contradiction, and these solutions are all within the scope disclosed in this application. Relational terms such as first and second, etc. are only used to distinguish an entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements that are not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0120] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, electronic device, and storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0121] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A data transmission method, characterized in that: Applied to the sending end, the method includes: Get the digital code of the data to be sent; According to a preset frame time and a preset coding level conversion rule, each general purpose input / output port GPIO level frame corresponding to the digital code of the data to be sent is determined to obtain each target GPIO level frame; Sending each of the target GPIO level frames to the receiving end in sequence; Among them, the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rule is the correspondence rule between digital coding and GPIO level frames; in the transmission stage, the first digital bit is represented by two frames of GPIO level frames; the digital code is binary coding, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts; the GPIO level frames corresponding to the start signal and the end signal each include 5 interrupts, and the starting levels of the start signal and the end signal are different; data transmission is divided into three stages, including: start, transmission, and stop; after each stage and each bit transmission is completed, wait for the preset frame time.

2. The method according to claim 1, characterized in that The GPIO level frame represents different digital codes through the level of the level.

3. The method according to claim 1, characterized in that: The sending end is a master device or a slave device, wherein the communication process is initiated by the master device.

4. A data transmission method, characterized in that: Applied to the receiving end, the method includes: Receive each GPIO level frame to be decoded sent by the transmitter; According to a preset frame time and a preset coding level conversion rule, each of the GPIO level frames to be decoded is sequentially decoded into a digital code, wherein the preset frame time is the duration of a single GPIO level frame, and the preset coding level conversion rule is a correspondence rule between a digital code and a GPIO level frame; In the transmission phase, the first digital bit is represented by two GPIO level frames; The digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts; The GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different; Data transmission is divided into three stages, including: start, transmission, and stop; after each stage and each bit transmission is completed, wait for the preset frame time.

5. The method according to claim 4, characterized in that The GPIO level frame represents different digital codes through the level of the level.

6. The method according to claim 4, characterized in that The receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.

7. A data transmission device, characterized in that: Applied to a transmitting end, the device comprises: A digital code acquisition module, used to acquire the digital code of the data to be sent; The GPIO level frame determination module is used to determine the GPIO level frames of each general input / output port corresponding to the digital code of the data to be sent according to the preset frame time and the preset coding level conversion rule, and obtain each target GPIO level frame, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rule is the correspondence rule between the digital code and the GPIO level frame; in the transmission stage, the first digital bit is represented by two frames of GPIO level frames; the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts; the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different; data transmission is divided into three stages, including: start, transmission, and stop; after each stage and each bit transmission is completed, wait for the preset frame time; The GPIO level frame sending module is used to send each of the target GPIO level frames to the receiving end in sequence.

8. A data transmission device, characterized in that: Applied to a receiving end, the device comprises: The GPIO level frame receiving module is used to receive each GPIO level frame to be decoded sent by the sending end; A digital code conversion module is used to decode each of the GPIO level frames to be decoded into digital codes in sequence according to a preset frame time and a preset code level conversion rule, wherein the preset frame time is the duration of a single GPIO level frame, and the preset code level conversion rule is the correspondence rule between the digital code and the GPIO level frame. In the transmission stage, the first digital bit is represented by two GPIO level frames; the digital code is a binary code, and the binary code includes 0 and 1, the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts; the GPIO level frames corresponding to the start signal and the end signal respectively include 5 interrupts, and the starting levels of the start signal and the end signal are different; data transmission is divided into three stages, including: start, transmission, and stop; after each stage and each bit transmission is completed, wait for the preset frame time.

9. An electronic device, characterized in that: It includes a memory and at least two processors, wherein the at least two processors are connected via GPIO; The memory is used to store computer programs; The processor is used to implement the data transmission method described in any one of claims 1-6 when executing the program stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the data transmission method according to any one of claims 1 to 6 is implemented.

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