Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked, a channel structure extending through the gate structure, and a source conductive pattern between the substrate and the gate structure. The source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern. The channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern. In a cross-sectional view of the semiconductor device, a lower surface of the channel pattern is at a level higher than an upper surface of the upper source conductive pattern but lower than a level of a lower surface of a lowermost gate electrode among the gate electrodes, and the substrate provides a reference level.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0051528, filed on April 28, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Disclosed example embodiments relate to a semiconductor device including a channel pattern and a method of manufacturing the same. BACKGROUND

[0003] Data erasing of a vertical NAND flash memory can be performed through a gate-induced drain leakage (GIDL) operation in which holes are generated using GIDL.

[0004] When the GIDL operation is performed in a vertical NAND flash memory, it can be required to diffuse impurities around a channel region of an erase control transistor to generate holes. For this, a method of diffusing impurities included in a source conductive pattern disposed between a substrate and a gate electrode through a heat treatment process can be applied to such a vertical NAND flash memory.

[0005] Such a channel pattern can include polysilicon. In relation to this, because the polysilicon has a crystal structure, a diffusion rate of impurities in the channel pattern can vary according to an arrangement state of crystals of the channel pattern. That is, diffusion can be successfully performed in a portion of the channel pattern, and can be less successfully performed in another portion of the channel pattern. As a result, diffusion in a portion of an area around the channel region of the erase control transistor can be excessively performed, and thus a concentration of the impurities in the portion can be excessively high, whereas diffusion in another portion of the area can be insufficiently performed, and thus a concentration of the impurities in the other portion can be lower than a required degree. As a result, reliability of the GIDL erasing operation can be deteriorated. SUMMARY

[0006] Example embodiments of the inventive concept can physically improve a diffusion distance of N-type impurities required for a gate-induced drain leakage (GIDL) operation in a vertical NAND flash memory device. In addition, example embodiments of the inventive concept can provide a method capable of properly controlling a degree of diffusion of N-type impurities even after a desired physical distance of the N-type impurities is secured.

[0007] A semiconductor device according to an embodiment of the inventive concept includes a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked, a channel structure extending through the gate structure, and a source conductive pattern disposed between the substrate and the gate structure, wherein the source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern, wherein the channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern disposed between the insulating pattern and the data storage pattern, wherein, in a cross-sectional view of the semiconductor device, a lower surface of the channel pattern is disposed at a level higher than a level of an upper surface of the upper source conductive pattern and lower than a level of a lower surface of a lowermost gate electrode among the gate electrodes, and the substrate provides a reference level.

[0008] A semiconductor device according to another embodiment of the inventive concept includes a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked, a channel structure extending through the gate structure, and a source conductive pattern disposed between the substrate and the gate structure, wherein the source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern, wherein the channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern disposed between the insulating pattern and the data storage pattern, wherein a portion of the lower source conductive pattern is disposed between the insulating pattern and the data storage pattern while physically contacting a lower surface of the channel pattern, wherein, in a cross-sectional view of the semiconductor device, the lower surface of the channel pattern is disposed at a level higher than a level of a lower surface of the data storage pattern, and the substrate provides a reference level.

[0009] A semiconductor device according to another embodiment of the inventive concept includes a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked, a channel structure extending through the gate structure, and a source conductive pattern disposed between the substrate and the gate structure, wherein the source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern, wherein the channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern disposed between the insulating pattern and the data storage pattern, wherein the data storage pattern includes a tunnel insulating layer, a charge storage layer, and a blocking layer sequentially stacked on the channel pattern, wherein the lower source conductive pattern includes a horizontal extension on an upper surface of the substrate, a vertical extension extending between the insulating pattern and the upper source conductive pattern, and a protrusion protruding from an upper surface of the vertical extension, wherein the protrusion includes a first protrusion disposed between the insulating pattern and the tunnel insulating layer while physically contacting a lower surface of the channel pattern. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is a schematic layout of a unit area in a semiconductor device according to example embodiments of the inventive concept.

[0011] FIG. 2 is a cross-sectional view taken along the line I-I' in FIG. 1

[0012] FIG. 3 is a planar layout of the source conductive pattern shown in FIG. 2

[0013] FIG. 4A is an enlarged view of the area P1 in FIG. 2

[0014] FIG. 4B is an enlarged view of the area A1 in FIG. 4A

[0015] FIG. 5A is an enlarged view of the area P1 in FIG. 2

[0016] FIG. 5B is an enlarged view of the area A2 in FIG. 5A

[0017] FIG. 6A is an enlarged view of the area P1 in FIG. 2

[0018] FIG. 6B is an enlarged view of the area A3 in FIG. 6A

[0019] FIG. 7A is an enlarged view of the area P1 in FIG. 2

[0020] FIG. 7B is an enlarged view of the area A4 in FIG. 7A

[0021] FIG. 8A is an enlarged view of the area P1 in FIG. 2

[0022] FIG. 8B is an enlarged view of the area A5 in FIG. 8A

[0023] FIG. 9A is an enlarged view of the area P1 in FIG. 2

[0024] ​​​​​​​​​​​​​FIG. 9B is an enlarged view of area A6 in FIG. 9A

[0025] FIG. 10A is an enlarged view of area P1 in FIG. 2

[0026] FIG. 10B is an enlarged view of area A7 in FIG. 10A

[0027] FIG. 11A is an enlarged view of area P1 in FIG. 2

[0028] FIG. 11B is an enlarged view of area A8 in FIG. 11A

[0029] FIG. 12A is an enlarged view of area P1 in FIG. 2

[0030] FIG. 12B is an enlarged view of area A9 in FIG. 12A

[0031] FIG. 13 to FIG. 24 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals are used to refer to like elements throughout the drawings and redundant descriptions thereof will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "on" another element, "attached" to another element, "connected" to another element, "combined with" another element, "contacting" another element, etc., it can be directly on, attached to, connected to, combined with, or contacting the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on," "directly attached" to, "directly connected" to, "directly combined with" or "directly contacting" another element, there are no intervening elements. It will be understood that aspects described with respect to one embodiment can be incorporated into different embodiments although not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0033] FIG. 1 ​​​​​​​is a schematic layout of a unit region in a semiconductor device according to an example embodiment of the inventive concept.

[0034] Referring to FIG. 1 , a semiconductor device according to an example embodiment of the inventive concept can include a channel structure CH, a common source structure CSS, a string select line SSL, a string select line separation pattern SSLC, and a bit line BL as shown in the configuration.

[0035] The channel structure CH can have a circular shape. The channel structure CH is arranged along a first direction D1, and as such, a row of pads (or referred to as "lands") can be formed. Accordingly, a plurality of rows of pads can be arranged in parallel along a second direction D2. The channel structure CH can be arranged in a form of a close hexagonal lattice or in a zigzag manner.

[0036] The common source structure CSS can extend along the second direction D2 while being arranged in parallel in a state where the channel structure CH is disposed between the common source structures CSS. Each common source structure CSS can include a common source line CSL and a spacer SS. The spacer SS can be disposed at opposite side surfaces of the common source line CSL.

[0037] The string select line SSL can be disposed between the common source structures CSS. The string select lines SSL can be separated from each other by the common source structures CSS. In addition, the string select lines SSL can be separated from each other by the string select line separation pattern SSLC.

[0038] The string select line separation pattern SSLC can extend in the second direction D2 and can separate each string select line SSL into a pair of string select lines spaced apart from each other in the first direction D1.

[0039] The bit line BL can extend in the first direction D1 while being arranged in parallel. The bit line BL can be disposed to be vertically overlaid with the channel structure CH. For example, one channel structure CH can be overlaid with two bit lines BL.

[0040] FIG. 2 is a cross-sectional view taken along a line I-I' in FIG. 1 . FIG. 3 is a planar layout of a source conductive pattern as shown in FIG. 2 .

[0041] Referring to FIG. 2 , a semiconductor device according to an example embodiment of the disclosed inventive concept can include a substrate 10, an insulating film 11, a source conductive pattern 70, a gate structure 80, a channel structure CH, a dummy channel structure DCH, a cap layer 50, a common source structure CSS, a buffer pattern BF, a lower contact 90, an interlayer insulating layer 93, and an upper contact 95 as shown in the configuration. A bit line BL (refer to FIG. 1 ) can be located on the upper contact 95.

[0042] The substrate 10 can be a semiconductor substrate. For example, the substrate 10 can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0043] The source conductive pattern 70 can be provided on the substrate 10. The source conductive pattern 70 can include a lower source conductive pattern 71 and an upper source conductive pattern 73.

[0044] Referring to FIG. 2 and FIG. 3 The lower source conductive pattern 71 can be on and at least partially cover an upper surface of the substrate 10. The lower source conductive pattern 71 can include a recessed side surface RS. The recessed side surface RS can have a concave shape extending inward toward the lower source conductive pattern 71. The insulating film 11 can be provided at the upper surface of the substrate 10 exposed between the recessed side surfaces RS.

[0045] The upper source conductive pattern 73 can be provided on the lower source conductive pattern 71. The upper source conductive pattern 73 can be on and at least partially cover an upper surface and side surfaces of the lower source conductive pattern 71. A portion of the lower source conductive pattern 71 can extend into a hole formed at the upper source conductive pattern 73. The upper source conductive pattern 73 can be on and at least partially cover the insulating film 11. In an embodiment, when the insulating film 11 is omitted, the upper source conductive pattern 73 can be directly on and at least partially cover the upper surface of the substrate 10 exposed between the recessed side surfaces RS.

[0046] Each of the upper source conductive pattern 73 and the lower source conductive pattern 71 can include a semiconductor material doped with an impurity. For example, each of the upper source conductive pattern 73 and the lower source conductive pattern 71 can include a semiconductor material doped with an N-type impurity. The upper source conductive pattern 73 and the lower source conductive pattern 71 can have different impurity concentrations. For example, the lower source conductive pattern 71 can have a greater N-type impurity concentration than an N-type impurity concentration of the upper source conductive pattern 73.

[0047] Referring again to FIG. 2 The gate structure 80 can be provided on the source conductive pattern 70. The gate structure 80 can include insulating layers 21d and 21u and gate electrodes 82d, 82d-1, 82d-2, and 82u alternately and repeatedly stacked.

[0048] The gate electrodes 82d, 82d-1, 82d-2, and 82u can include lower gate electrodes 82d, 82d-1, and 82d-2, and an upper gate electrode 82u. The insulating layers 21d and 21u can include a planarization layer 23 disposed between the lower gate electrodes 82d, 82d-1, and 82d-2 and the upper gate electrode 82u.

[0049] The lower gate electrodes 82d, 82d-1, and 82d-2 can include an erase control gate electrode ERL and a ground select gate electrode GSL. The erase control gate electrode ERL can be a lowermost one of the lower gate electrodes 82d, 82d-1, and 82d-2 (i.e., the gate electrode 82d-1). In an embodiment, the lower gate electrodes 82d, 82d-1, and 82d-2 can include a double-layered erase control gate electrode ERL including the gate electrodes 82d-1 and 82d-2. That is, the gate electrode 82d-2 closest to the gate electrode 82d-1 vertically disposed among the lower gate electrodes 82d, 82d-1, and 82d-2 can also be the erase control gate electrode ERL. The ground select gate electrode GSL can be disposed on the erase control gate electrode ERL. The ground select gate electrode GSL can be an uppermost one of the lower gate electrodes 82d, 82d-1, and 82d-2 (i.e., the gate electrode 82d). The erase control gate electrode ERL can function as a gate electrode of an erase control transistor to control an erase operation of a memory cell array in the semiconductor device. The ground select gate electrode GSL can function as a gate electrode of a ground select transistor in the semiconductor device.

[0050] The planarization layer 23 can be interposed between the uppermost gate electrode 82d among the lower gate electrodes 82d, 82d-1, and 82d-2 and a lowermost one of the upper gate electrodes 82u. The planarization layer 23 can have a thickness different from that of the lower insulating layer 21d and / or the upper insulating layer 21u, the lower insulating layer 21d being disposed between (in a cross-sectional view) vertically adjacent gate electrodes among the lower gate electrodes 82d, 82d-1, and 82d-2, and the upper insulating layer 21u being disposed between (in a cross-sectional view) vertically adjacent gate electrodes among the upper gate electrodes 82u. FIG. 2 The planarization layer 23 can be interposed between the uppermost gate electrode 82d among the lower gate electrodes 82d, 82d-1, and 82d-2 and a lowermost one of the upper gate electrodes 82u. The planarization layer 23 can have a thickness different from that of the lower insulating layer 21d and / or the upper insulating layer 21u, the lower insulating layer 21d being disposed between (in a cross-sectional view) vertically adjacent gate electrodes among the lower gate electrodes 82d, 82d-1, and 82d-2, and the upper insulating layer 21u being disposed between (in a cross-sectional view) vertically adjacent gate electrodes among the upper gate electrodes 82u. FIG. 2 The planarization layer 23 can be interposed between the uppermost gate electrode 82d among the lower gate electrodes 82d, 82d-1, and 82d-2 and a lowermost one of the upper gate electrodes 82u. The planarization layer 23 can have a thickness different from that of the lower insulating layer 21d and / or the upper insulating layer 21u, the lower insulating layer 21d being disposed between (in a cross-sectional view) vertically adjacent gate electrodes among the lower gate electrodes 82d, 82d-1, and 82d-2, and the upper insulating layer 21u being disposed between (in a cross-sectional view) vertically adjacent gate electrodes among the upper gate electrodes 82u.

[0051] The upper gate electrodes 82u can include a cell gate electrode CGL and a string select gate electrode SSL. The cell gate electrode CGL can be disposed between the planarization layer 23 and the string select gate electrode SSL. The string select gate electrode SSL is disposed on the cell gate electrode CGL and can be an uppermost one of the upper gate electrodes 82u.

[0052] For example, the lower gate electrodes 82d, 82d-1, and 82d-2 and the upper gate electrode 82u can include a metal, a doped semiconductor, a conductive metal nitride, and / or a transition metal. The lower insulating layer 21d, the upper insulating layer 21u, and the planarization layer 23 can include silicon oxide and / or a low dielectric film.

[0053] The channel structure CH can (in a cross-sectional view) extend vertically from the lower source conductive pattern 71 through the gate structure 80. The channel structure CH can include the insulating pattern 45, the channel pattern 43, the data storage pattern 41, and the conductive pad 47. FIG. 2

[0054] The data storage pattern 41 can be disposed outside the channel pattern 43. The data storage pattern 41 can be disposed between the channel pattern 43 and the gate structure 80. The channel pattern 43 can be disposed between the insulating pattern 45 and the data storage pattern 41. The insulating pattern 45 can be disposed inside the channel pattern 43. The insulating pattern 45 extends downward beyond a lower surface of the channel pattern 43 such that the insulating pattern 45 extends through the lower source conductive pattern 71 and the upper source conductive pattern 73. A lower surface of the insulating pattern 45 can physically contact the dummy channel structure DCH.

[0055] Each of the channel pattern 43 and the data storage pattern 41 can have a shape of a hollow cylinder or a hollow tube, but embodiments of the inventive concept are not limited to such shapes. For example, the channel pattern 43 can include a semiconductor material such as silicon, germanium, or silicon germanium. Optionally, the channel pattern 43 can be an intrinsic semiconductor that is not doped with impurities or a semiconductor that is doped with impurities. The channel pattern 43 can include a polycrystalline semiconductor material.

[0056] The dummy channel structure DCH can be disposed between the substrate 10 and the lower source conductive pattern 71. When the source conductive pattern 70 is disposed between the dummy channel structure DCH and the channel structure CH, the dummy channel structure DCH and the channel structure CH can be vertically spaced apart from each other in a cross-sectional view. FIG. 2 As shown in a cross-sectional view, the dummy channel structure DCH and the channel structure CH can be vertically spaced apart from each other in a cross-sectional view. FIG. 2 As shown in a cross-sectional view, the dummy channel structure DCH and the channel structure CH can be vertically spaced apart from each other in a cross-sectional view.

[0057] The conductive pad 47 can be disposed on the insulating pattern 45 and the channel pattern 43. The conductive pad 47 can be disposed inside the data storage pattern 41. The data storage pattern 41 can be on and at least partially cover an outer lateral surface of the conductive pad 47. An upper surface of the conductive pad 47 and an upper surface of the data storage pattern 41 can be substantially coplanar. For example, the conductive pad 47 can include a semiconductor material doped with impurities and / or a conductive material. ​

[0058] A cap layer 50 can be disposed on the gate structure 80 such that the cap layer 50 is on and at least partially covers upper surfaces of the gate structure 80, the data storage pattern 41, and the conductive pad 47. As shown in the cross-sectional view of FIG. 1A, the cap layer 50 can be disposed on the upper surface of the gate structure 80, the upper surface of the data storage pattern 41, and the upper surface of the conductive pad 47. The cap layer 50 can be disposed on the upper surface of the upper source conductive pattern 73. The cap layer 50 can be disposed on the upper surface of the upper source conductive pattern 73 and the upper surface of the data storage pattern 41. The cap layer 50 can be disposed on the upper surface of the upper source conductive pattern 73 and the upper surface of the conductive pad 47. The cap layer 50 can be disposed on the upper surface of the upper source conductive pattern 73 and the upper surface of the data storage pattern 41 and the upper surface of the conductive pad 47. The cap layer 50 can be disposed on the upper surface of the upper source conductive pattern 73, the upper surface of the data storage pattern 41, and the upper surface of the conductive pad 47. FIG. 2 As shown in the cross-sectional view of FIG. 1A, a common source structure CSS can vertically extend through the gate structure 80 and the cap layer 50. A spacer SS can be disposed between the common source line CSL and the gate structure 80. Portions of the common source line CSL can extend into the substrate 10. A buffer pattern BF can border and at least partially surround portions of an outer lateral surface of the spacer SS. The buffer pattern BF can be disposed within the upper source conductive pattern 73. An upper surface of the buffer pattern BF can physically contact a lowermost one of the lower insulating layers 21d.

[0059] An interlayer insulating layer 93 can be disposed on the cap layer 50. For example, each of the cap layer 50 and the interlayer insulating layer 93 can include an insulating material such as silicon oxide. A lower contact 90 can extend through the cap layer 50 such that the lower contact 90 is connected to the conductive pad 47. An upper contact 95 can extend through the interlayer insulating layer 93 such that the upper contact 95 is connected to the lower contact 90. Each of the lower contact 90 and the upper contact 95 can include a conductive material.

[0060] FIG. 2 is a close-up view of the region P1 in FIG. 4A is a close-up view of the region P1 in FIG. 2 is a close-up view of the region A1 in FIG. 4B is a close-up view of the region A1 in FIG. 4A is a close-up view of the region P1 in FIG. 5A is a close-up view of the region P1 in FIG. 2 is a close-up view of the region A2 in FIG. 5B is a close-up view of the region A2 in

[0061] Referring to FIG. 5AThe data storage pattern 41 can include a blocking layer 41a, a charge storage layer 41b, and a tunnel insulating layer 41c. The dummy data storage pattern 41d can include a dummy blocking layer 41d_a, a dummy charge storage layer 41d_b, and a dummy tunnel insulating layer 41d_c. The charge storage layer 41b can include a trap insulating film, a floating gate electrode, and / or an insulating film including electrically conductive nanodots. For example, the charge storage layer 41b can include a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride, nanocrystalline silicon, and / or a laminated trap layer. The blocking layer 41a can include a material having a larger bandgap than a material of the charge storage layer 41b. For example, the blocking layer 41a can include a high dielectric film such as an aluminum oxide film or a hafnium oxide film. The tunnel insulating layer 41c can include a material having a larger bandgap than a material of the charge storage layer 41b. For example, the tunnel insulating layer 41c can include a silicon oxide film. The dummy data storage pattern 41d can include the same materials as the data storage pattern 41.

[0062] In embodiments, as shown in a cross-sectional view of FIG. 1A, the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than a level of the lower surface 41_L of the data storage pattern 41. As shown in a cross-sectional view of FIG. 1B, the lower surface 43_L of the channel pattern 43 can be disposed adjacent to the lower surface 82d-1_L of the lowermost gate electrode 82d-1 at a level lower than a level of the lower surface 82d-1_L of the lowermost gate electrode 82d-1. FIG. 4A to FIG. 5B FIG. 4B In embodiments, as shown in a cross-sectional view of FIG. 1A, the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than a level of the lower surface 41_L of the data storage pattern 41. As shown in a cross-sectional view of FIG. 1B, the lower surface 43_L of the channel pattern 43 can be disposed adjacent to the lower surface 82d-1_L of the lowermost gate electrode 82d-1 at a level lower than a level of the lower surface 82d-1_L of the lowermost gate electrode 82d-1.

[0063] Referring to FIGS. 1A and 1B, FIG. 4A and FIG. 4A The lower source conductive pattern 71 can include a horizontal extension 71a, a vertical extension 71b, and a protrusion 71c. The horizontal extension 71a can be directly on and at least partially cover the upper surface of the substrate 10 while interposed between the substrate 10 and the upper source conductive pattern 73. In cross-sectional views of FIGS. 1A and 1B, FIG. 4B and FIG. 4A The vertical extension 71b extends upward and downward from the horizontal extension 71a and, as such, can take a shape having portions protruding from the upper surface and the lower surface of the horizontal extension 71a, respectively. The vertical extension 71b can extend between the substrate 10 and the insulating pattern 45 and can extend between the upper source conductive pattern 73 and the insulating pattern 45. The vertical extension 71b can physically contact the outer lateral surface of the insulating pattern 45 and can border and at least partially surround portions of the outer lateral surface of the insulating pattern 45.

[0064] ​In an embodiment, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45.

[0065] The protrusion 71c can extend upward from the upper surface of the vertical extension 71b and can be disposed between the data storage pattern 41 and the insulating pattern 45. The upper surface of the protrusion 71c can physically contact the lower surface 43_L of the channel pattern 43. The protrusion 71c can extend downward from the lower surface of the vertical extension 71b and can be disposed between the dummy data storage pattern 41d and the insulating pattern 45. The lower surface of the protrusion 71c can physically contact the upper surface of the dummy channel pattern 43d. The outer side surface of the protrusion 71c can physically contact the inner side surface of the tunnel insulating layer 41c or the inner side surface of the dummy tunnel insulating layer 41d_c.

[0066] In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45. FIG. 4B In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45. FIG. 4A In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45. FIG. 4B In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45. FIG. 4B In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45.

[0067] In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45. FIG. 5A FIG. 5B In an embodiment, as shown in the cross-sectional view of FIG. 11A, the protrusion 71c can have a shape protruding from the vertical extension 71b. The protrusion 71c can have a shape having portions protruding upward and downward from the upper and lower surfaces of the vertical extension 71b, respectively. The protrusion 71c can border and at least partially surround a portion of the outer side surface of the insulating pattern 45.

[0068] FIG. 6A ​is a close-up view of region P1 in FIG. 2 FIG. 6B is a close-up view of region A3 in FIG. 6A

[0069] Referring to FIG. 6A and FIG. 6B In embodiments, the lower surface 43_L of the channel pattern 43 and the lower surface 41_L of the data storage pattern 41 can be disposed at substantially the same level between the upper surface 73_U of the upper source conductive pattern 73 and the lower surface 82d-1_L of the lowermost gate electrode 82d-1. That is, the lower surface 43_L of the channel pattern 43 and the lower surface 41_L of the data storage pattern 41 can be substantially coplanar. In embodiments, the lower surface 43_L of the channel pattern 43 and the lower surface 41_L of the data storage pattern 41 can be disposed closer to the lower surface 82d-1_L of the lowermost gate electrode 82d-1 than to the upper surface 73_U of the upper source conductive pattern 73. For example, in cross-sectional views of FIG. 6A and FIG. 6B In cross-sectional views of

[0070] FIG. 7A is a close-up view of region P1 in FIG. 2 FIG. 7B is a close-up view of region A4 in FIG. 7A FIG. 8A is a close-up view of region P1 in FIG. 2 FIG. 8B is a close-up view of region A5 in FIG. 8A FIG. 9A is a close-up view of region P1 in FIG. 2 FIG. 9B is a close-up view of region A6 in FIG. 9A FIG. 10A is a close-up view of region P1 in FIG. 2 FIG. 10B is a close-up view of region A7 in FIG. 10A

[0071] Referring to FIG. 7A to FIG. 10B In embodiments, the lower source conductive pattern 71 can include a plurality of protrusions 71c and 71d. The plurality of protrusions 71c and 71d can include first protrusions 71c and second protrusions 71d. In cross-sectional views of FIG. 7A to FIG. 10B In cross-sectional views of FIG. 7A to FIG. 10B ​​​​​​​​​​In the cross-sectional view, the first protrusion 71c and the second protrusion 71d can have different heights. In an embodiment, the height of the first protrusion 71c and the height of the second protrusion 71d can be substantially equal in the cross-sectional view of the semiconductor device. In an embodiment, at least one of the first protrusion 71c and the second protrusion 71d can have an upper surface that has a portion disposed at a different level in the cross-sectional view of the semiconductor device. In an embodiment, at least one of the first protrusion 71c and the second protrusion 71d can have a flat upper surface.

[0072] In an embodiment, for example, as shown in the cross-sectional view of FIG. 6A, the upper surface of the first protrusion 71c can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73 but lower than the level of the lower surface 82d-1_L of the lowermost gate electrode 82d-1. Also, for example, as shown in the cross-sectional view of FIG. 6B, at least a portion of the upper surface of the second protrusion 71d can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73 but lower than the level of the lower surface 82d-1_L of the lowermost gate electrode 82d-1. FIG. 7B FIG. 7B In an embodiment, for example, as shown in the cross-sectional view of FIG. 6A, the upper surface of the first protrusion 71c can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73 but lower than the level of the lower surface 82d-1_L of the lowermost gate electrode 82d-1. Also, for example, as shown in the cross-sectional view of FIG. 6B, at least a portion of the upper surface of the second protrusion 71d can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73 but lower than the level of the lower surface 82d-1_L of the lowermost gate electrode 82d-1.

[0073] As described above, since the lower source conductive pattern 71 includes a plurality of protrusions 71c and 71d, the lower surface 43_L of the channel pattern 43 that physically contacts the upper surface of the lower source conductive pattern 71 and the lower surface 41_L of the data storage pattern 41 that physically contacts the upper surface of the lower source conductive pattern 71 can be disposed at different levels in the cross-sectional view of the semiconductor device. Also, in the cross-sectional view of the semiconductor device, different portions of the lower surface 41_L of the data storage pattern 41 can be disposed at different levels. For example, as shown in the cross-sectional view of FIG. 6A, a portion (e.g., 41a_L and 41c_L) of the lower surface of the data storage pattern 41 can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73, and another portion (e.g., 41b_L) of the lower surface of the data storage pattern 41 can be disposed at a level lower than the level of the upper surface 73_U of the upper source conductive pattern 73. FIG. 7B

[0074] Referring to FIG. 7A to FIG. 8B In an embodiment, the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than the level of the uppermost portion of the lower surface of the data storage pattern 41. That is, in the cross-sectional view of FIG. 6A, the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than the level of the uppermost one of the lower surfaces 41a_L, 41b_L, and 41c_L of the blocking layer 41a, the charge storage layer 41b, and the tunnel insulating layer 41c. FIG. 7A to FIG. 8B

[0075] In detail, referring to​​​FIG. 7A and FIG. 7B In this embodiment, the lower surface 41c_L of the tunnel insulating layer 41c is disposed at a level higher than the lower surface 41b_L of the charge storage layer 41b, and the lower surface 41a_L of the barrier layer 41a may be disposed at a level higher than the lower surface 41c_L of the tunnel insulating layer 41c. FIG. 7A to FIG. 7B In the cross-sectional view, the lower surface 43_L of the trench pattern 43 can be set at a level higher than the level of the lower surface 41c_L of the tunnel insulation layer 41c.

[0076] Reference FIG. 8A and FIG. 8B In an embodiment, the lower surface 41a_L of the barrier layer 41a can be disposed at a level higher than the lower surface 41c_L of the tunnel insulating layer 41c, and the lower surface 41b_L of the charge storage layer 41b can be disposed at a level higher than the lower surface 41a_L of the barrier layer 41a. FIG. 8A to FIG. 8B In the cross-sectional view, the lower surface 43_L of the channel pattern 43 can be positioned at a level higher than the lower surface 41b_L of the charge storage layer 41b. FIG. 8A to FIG. 8B In the cross-sectional view, the lower surface 43_L of the channel pattern 43 and the lower surface 41b_L of the charge storage layer 41b can be positioned at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73. FIG. 8A to FIG. 8B In the cross-sectional view, the lower surface 41a_L of the barrier layer 41a and the lower surface 41c_L of the tunnel insulating layer 41c may be disposed at a level lower than the level of the upper surface 73_U of the upper source conductive pattern 73. Optionally, in an embodiment, in the cross-sectional view of the semiconductor device, the lower surface 41a_L of the barrier layer 41a may be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73, and only the lower surface 41c_L of the tunnel insulating layer 41c may be disposed at a level lower than the level of the upper surface 73_U of the upper source conductive pattern 73.

[0077] Reference FIG. 9A to FIG. 10B In an embodiment, the lower surface 43_L of the channel pattern 43 can be positioned at a level lower than the uppermost portion of the lower surface 41_L of the data storage pattern 41. That is, in FIG. 9A to FIG. 10B In the cross-sectional view, the lower surface 43_L of the channel pattern 43 can be positioned at a level lower than the uppermost of the lower surfaces of the barrier layer 41a, the charge storage layer 41b, and the tunnel insulation layer 41c. FIG. 9A to FIG. 10B In the cross-sectional view, the uppermost lower surface of the data storage pattern 41 can be set at a level that is higher than the lower surface 43_L of the channel pattern 43 but lower than the lower surface 82d-1_L of the lowermost gate electrode.

[0078] In detail, referring to FIG. 9A and FIG. 9B , the lower surface 41c_L of the tunnel insulating layer 41c can be disposed at a level higher than that of the lower surface 41b_L of the charge storage layer 41b. In FIG. 9A to FIG. 9B , the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than that of the lower surface 41c_L of the tunnel insulating layer 41c, and the lower surface 41a_L of the barrier layer 41a can be disposed at a level higher than that of the lower surface 43_L of the channel pattern 43. In FIG. 9A to FIG. 9B , the lower surface 41a_L of the barrier layer 41a and the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than that of the upper surface 73_U of the upper source conductive pattern 73. In FIG. 9A to FIG. 9B , the lower surface 41c_L of the tunnel insulating layer 41c can be disposed at a level higher than that of the upper surface 73_U of the upper source conductive pattern 73, and the lower surface 41b_L of the charge storage layer 41b can be disposed at a level lower than that of the upper surface 73_U of the upper source conductive pattern 73. Alternatively, in an embodiment, in a cross-sectional view of the semiconductor device, the lower surface 41c_L of the tunnel insulating layer 41c and the lower surface 41b_L of the charge storage layer 41b can be disposed at a level lower than that of the upper surface 73_U of the upper source conductive pattern 73, respectively.

[0079] Referring to FIG. 10A and FIG. 10B , the lower surface 41a_L of the barrier layer 41a can be disposed at a level higher than that of the lower surface 41c_L of the tunnel insulating layer 41c, and the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than that of the lower surface 41a_L of the barrier layer 41a. In FIG. 10A to FIG. 10B , the lower surface 41b_L of the charge storage layer 41b can be disposed at a level higher than that of the lower surface 43_L of the channel pattern 43. For example, in FIG. 10A to FIG. 10B , the lower surface 43_L of the channel pattern 43 and the lower surface 41b_L of the charge storage layer 41b can be disposed at a level higher than that of the upper surface 73_U of the upper source conductive pattern 73, respectively. In FIG. 10A to FIG. 10B , the lower surface 41a_L of the barrier layer 41a and the lower surface 41c_L of the tunnel insulating layer 41c can be disposed at a level lower than that of the upper surface 73_U of the upper source conductive pattern 73, respectively. Alternatively, in an embodiment, in a cross-sectional view of the semiconductor device, the lower surface 41a_L of the barrier layer 41a can be disposed at a level higher than that of the upper surface 73_U of the upper source conductive pattern 73, and the lower surface 41c_L of the tunnel insulating layer 41c can be disposed at a level lower than that of the upper surface 73_U of the upper source conductive pattern 73.

[0080] FIG. 11A is a close-up view of the region P1 in FIG. 2 FIG. 11B is a close-up view of the region A8 in FIG. 11A FIG. 12A is a close-up view of the region P1 in FIG. 2 FIG. 12B is a close-up view of the region A9 in FIG. 12A Referring to

[0081] and FIG. 11A , the lower surface 41_L of the data storage pattern 41 can be disposed at substantially the same level as the lower surface 73_L of the upper source conductive pattern 73. That is, in cross-sectional views of FIG. 11B and FIG. 11A , the upper surface of the vertical extension 71b and the upper surface of the horizontal extension 71a can be disposed at substantially the same level. As shown in cross-sectional views of FIG. 11B and FIG. 11A , the vertical length of the protrusion 71c can be greater than the thickness of the upper source conductive pattern 73 in the vertical direction. FIG. 11B Referring to

[0082] and FIG. 12A , in embodiments, the lower surface 41_L of the data storage pattern 41 can be disposed at a level lower than the level of the lower surface 73_L of the upper source conductive pattern 73. Thus, portions of the data storage pattern 41 can be disposed between the protrusion 71c and the horizontal extension 71a. FIG. 12B As shown in

[0083] , the lower surface 43_L of the channel pattern 43 can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73. In some embodiments, in a cross-sectional view of the semiconductor device, the lower surface 43_L of the channel pattern 43 and the lower surface 82d-1_L of the erase control gate electrode 82d-1 (ERL) are disposed at substantially the same level. Further, in a cross-sectional view of the semiconductor device, at least portions of the lower surface 41_L of the data storage pattern 41 can be disposed at a level higher than the level of the upper surface 73_U of the upper source conductive pattern 73. As described above, since the level of the lower surface 43_L of the channel pattern 43 and the level of the lower surface 41_L of the data storage pattern 41 are appropriately configured, it can be possible to form the lower source conductive pattern 71 such that at least portions thereof are disposed in the vicinity of the lowermost gate electrode 82d-1 (i.e., the erase control gate electrode ERL). Thus, it can be possible to appropriately control the physical diffusion distance of impurities between the lower source conductive pattern 71 and the erase control gate electrode ERL. FIG. 4A to FIG. 12B

[0084] ​​​​Further, C and / or N can be included in a region of the lower surface 43_L of the channel pattern 43 or below thereof. Thus, even when a physical distance between the lower source conductive pattern 71 and the erase control gate electrode ERL is very small, diffusion of impurities can be appropriately controlled.

[0085] FIG. 13 to FIG. 24 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concepts.

[0086] Referring to FIG. 13 , the method can include forming an insulating film 11 on a substrate 10 and forming a lower sacrificial pattern 12 and a mask pattern 13 on the insulating film 11.

[0087] The substrate 10 can be a semiconductor substrate. For example, the substrate 10 can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The insulating film 11 can include, for example, silicon oxide.

[0088] The step of forming the lower sacrificial pattern 12 can include forming a lower sacrificial film on the insulating film 11, forming the mask pattern 13 on the lower sacrificial film, and etching the lower sacrificial film using the mask pattern 13 as an etching mask. Upon partially etching the lower sacrificial film, the lower sacrificial pattern 12 having an opening OP can be formed. An upper surface of the insulating film 11 can be partially exposed through the opening OP.

[0089] The lower sacrificial pattern 12 can include a material having etching selectivity with respect to the insulating film 11. For example, the lower sacrificial pattern 12 can include silicon nitride, silicon oxynitride, silicon carbide, and / or silicon-germanium. The mask pattern 13 can be removed after forming the lower sacrificial pattern 12.

[0090] Referring to FIG. 14 , the method can further include forming a liner 14 located on the lower sacrificial pattern 12 and at least partially covering the lower sacrificial pattern 12, forming a source conductive layer 15 on the liner 14, forming a buffer layer 16 on the source conductive layer 15, and forming a stack structure 20.

[0091] The liner 14 can be on and can at least partially conformally cover upper and side surfaces of the lower sacrificial pattern 12. For example, the liner 14 can include silicon oxide. The source conductive layer 15 can be on and at least partially cover upper and side surfaces of the liner 14 while at least partially filling the opening OP. In FIG. 14 , a cross-sectional view, the source conductive layer 15 can be formed to have a uniform thickness and, as such, can have an upper surface that is recessed at a position vertically stacked with the opening OP. For example, the source conductive layer 15 can include a polysilicon film doped with an N-type impurity (e.g., phosphorus (P) or arsenic (As)).

[0092] A buffer layer 16 can be formed on the upper surface of the recess of the source conductive layer 15. The step of forming the buffer layer 16 can include forming an insulating film on the source conductive layer 15, and planarizing the insulating film to expose the upper surface of the source conductive layer 15. For example, the insulating film can include silicon oxide.

[0093] The step of forming the stack structure 20 can include alternately stacking the insulating layers 21d, 21u, and 23 and the sacrificial layers 22d and 22u on the source conductive layer 15. The insulating layers 21d, 21u, and 23 can include a material having etch selectivity with respect to the sacrificial layers 22d and 22u. In an embodiment, the sacrificial layers 22d and 22u can include the same material as the material of the lower sacrificial pattern 12. For example, the sacrificial layers 22d and 22u can include silicon nitride, and the insulating layers 21d, 21u, and 23 can include silicon oxide.

[0094] The insulating layers 21d, 21u, and 23 are respectively disposed between vertically adjacent ones of the sacrificial layers 22d and 22u, and can include a planarization layer 23 having a thickness greater than the thickness of the insulating layers 21d, 21u, and the sacrificial layers 22d and 22u. In an embodiment, the planarization layer 23 can include silicon oxide. FIG. 14 In a cross-sectional view of the stack structure 20, the insulating layers 21d, 21u, and 23 can include a lower insulating layer 21d disposed below the planarization layer 23 and an upper insulating layer 21u disposed above the planarization layer 23. Similarly, in a cross-sectional view of the stack structure 20, the sacrificial layers 22d and 22u can include a lower sacrificial layer 22d disposed below the planarization layer 23 and an upper sacrificial layer 22u disposed above the planarization layer 23. FIG. 14 In a cross-sectional view of the stack structure 20, the insulating layers 21d, 21u, and 23 can include a lower insulating layer 21d disposed below the planarization layer 23 and an upper insulating layer 21u disposed above the planarization layer 23. Similarly, in a cross-sectional view of the stack structure 20, the sacrificial layers 22d and 22u can include a lower sacrificial layer 22d disposed below the planarization layer 23 and an upper sacrificial layer 22u disposed above the planarization layer 23.

[0095] Referring to FIG. 15 The method can further include forming a channel structure CH extending through the insulating film 11, the lower sacrificial pattern 12, the pad 14, the source conductive layer 15, and the stack structure 20, and forming a cap layer 50 on the stack structure 20 and the channel structure CH.

[0096] The step of forming the channel structure CH can include forming a channel hole H extending through the stack structure 20, the source conductive layer 15, the pad 14, and the lower sacrificial pattern 12. The channel hole H can expose the base 10 therethrough. The step of forming the channel structure CH can include sequentially forming the data storage pattern 41, the channel layer 42, the insulating pattern 45, and the conductive pad 47 in the channel hole H.

[0097] Each of the data storage pattern 41 and the channel layer 42 can be conformally formed in the channel hole H and can not completely fill the channel hole H. After the data storage pattern 41 and the channel layer 42 are formed, the insulating pattern 45 can at least partially fill the space remaining in the channel hole H. The data storage pattern 41 can include a blocking layer, a charge storage layer, and a tunnel insulating layer which are sequentially stacked.

[0098] The step of forming the channel layer 42 can include conformally depositing a semiconductor layer on the data storage pattern 41 by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process and performing a planarization process. The channel layer 42 can include a semiconductor doped with an impurity, or can be an intrinsic semiconductor which is not doped with an impurity.

[0099] The conductive pad 47 can be formed in the channel hole H on the data storage pattern 41, the channel layer 42, and the insulating pattern 45. After the conductive pad 47 is formed, the cap layer 50 can be formed to cover the upper surface of the stack structure 20 and the upper surface of the conductive pad 47.

[0100] Referring to FIG. 16 The method can further include forming a trench T extending through the cap layer 50 and the stack structure 20 and forming a sacrificial spacer layer 55 in the trench T. The trench T can expose the source conductive layer 15 therethrough. In an embodiment, the trench T can extend through the buffer layer 16, thereby forming a buffer pattern BF.

[0101] The sacrificial spacer layer 55 can be conformally formed on and at least partially cover the upper surface of the cap layer 50 while at least partially filling a portion of the trench T. For example, the sacrificial spacer layer 55 can include a polysilicon film.

[0102] Referring to FIG. 17 The method can further include forming a sacrificial spacer 57 and a vertical via region VT and removing the lower sacrificial pattern 12.

[0103] The step of forming the sacrificial spacer 57 can include anisotropically etching the sacrificial spacer layer 55. The source conductive layer 15 and the liner 14 can be partially etched according to the anisotropic etching process for the sacrificial spacer layer 55. Accordingly, the trench T further vertically extends downward in a cross-sectional view of FIG. 17 The vertical via region VT can be formed such that the lower sacrificial pattern 12 is exposed through the vertical via region VT. The vertical via region VT can expose the insulating film 11 therethrough, or can expose the upper surface of the base 10 therethrough.

[0104] The step of removing the lower sacrificial pattern 12 can include forming horizontal via regions HT by performing an isotropic etching process on the vertical via regions VT. The horizontal via regions HT can pass through portions of the outer side surfaces of the channel structures CH (i.e., the data storage patterns 41). In addition, the horizontal via regions HT can pass through the inner side surface of the pad 14 and the upper surface of the insulating film 11. The isotropic etching process can be performed using etching conditions having etching selectivity with respect to the sacrificial spacers 57, the source conductive layer 15, the pad 14, the insulating film 11, and the buffer patterns BF.

[0105] The source conductive layer 15 can function as a support to prevent or reduce the possibility of the stacked structure 20 collapsing during the step of forming the horizontal via regions HT.

[0106] Referring to FIG. 18 and FIG. 19 The method can further include removing portions of the data storage patterns 41 exposed by the horizontal via regions HT, thereby exposing portions of the side surfaces of the channel layer 42. As shown in the cross-sectional view of FIG. 19 When the portions of the data storage patterns 41 are removed, the data storage patterns 41 can be divided into the data storage patterns 41 and dummy data storage patterns 41d vertically spaced apart from each other. Portions of the channel layer 42 can be exposed between the data storage patterns 41 and the dummy data storage patterns 41d vertically spaced apart from each other.

[0107] The step of removing the portions of the data storage patterns 41 can include partially removing the insulating film 11 and removing the pad 14. Accordingly, the lower surface of the source conductive layer 15 and the upper surface of the substrate can be exposed through the horizontal via regions HT.

[0108] When the portions of the data storage patterns 41 are removed, an undercut region UC can be formed. The undercut region UC can be a region vertically extending from the horizontal via regions HT in the cross-sectional view of FIG. 19 When portions of the data storage patterns 41 disposed below the upper surface of the substrate 10 are removed and portions of the data storage patterns 41 disposed above the lower surface of the source conductive layer 15 are removed, the undercut region UC can be formed. The undercut region UC can extend between the source conductive layer 15 and the channel layer 42 and between the substrate 10 and the channel layer 42.

[0109] The step of removing the portions of the data storage patterns 41 can be performed by an etching process having etching selectivity with respect to the substrate 10, the source conductive layer 15, the channel layer 42, and the sacrificial spacers 57.

[0110] The profile of the lower surface of the data storage pattern 41 and the profile of the upper surface of the dummy data storage pattern 41d can vary depending on a variation in conditions of an etching process for partially removing the data storage pattern 41.

[0111] Referring to FIG. 20 and FIG. 21 , the method can further include removing a portion of the trench layer 42 exposed through the horizontal via region HT and the undercut region UC. Upon removing the portion of the trench layer 42, the trench layer 42 can be divided into the trench pattern 43 and the dummy trench pattern 43d vertically spaced apart from each other in a cross-sectional view of the semiconductor device. FIG. 21 A portion of the insulating pattern 45 can be exposed between the trench pattern 43 and the dummy trench pattern 43d spaced apart from each other.

[0112] In the process of partially removing the trench layer 42, the source conductive layer 15 can also be partially removed. Upon partially removing the source conductive layer 15, the horizontal via region HT can be extended. Thus, a height W2 of the horizontal via region HT can be greater than a height W1 of the horizontal via region HT (see FIG. 2) before the trench layer 42 is partially removed. FIG. 19 Furthermore, the undercut region UC can be extended depending on the partial removal of the source conductive layer 15.

[0113] Upon partially removing the trench layer 42, an extended undercut region UE can be formed. The extended undercut region UE can be a region vertically extended from the undercut region UC. The extended undercut region UE extends between the data storage pattern 41 and the insulating pattern 45 and between the dummy data storage pattern 41d and the insulating pattern 45. As shown in a cross-sectional view of the semiconductor device, FIG. 21 Upon forming the extended undercut region UE, a lower surface of the trench pattern 43 can be disposed above a lower surface of the data storage pattern 41 and an upper surface of the dummy trench pattern 43d can be disposed below an upper surface of the dummy data storage pattern 41d, as shown in a cross-sectional view of the semiconductor device.

[0114] In an embodiment, the extended undercut region UE can extend to a level corresponding to an upper surface of a lowermost insulating layer 21d (i.e., a lower surface of a lowermost sacrificial layer 22d) disposed at a lowest level in the stack structure 20 in a cross-sectional view of the semiconductor device. That is, in the cross-sectional view of the semiconductor device, the lower surface of the trench pattern 43 can be disposed at a level equal to or higher than an upper surface of the source conductive layer 15 and can be disposed at a level equal to or lower than the upper surface of the lowermost insulating layer 21d (i.e., the lower surface of the lowermost sacrificial layer 22d).

[0115] In an embodiment, the method can further include doping a lower surface of the channel pattern 43 with C or N. Since C or N is formed at the lower surface of the channel pattern 43 or at the lower portion of the channel pattern 43, diffusion of N-type impurities can be controlled in a subsequent heat treatment process for diffusing N-type impurities (N-type impurities of a subsequently formed source conductive pattern). C or N can be implanted into the channel pattern 43 through the undercut region UC and / or the extended undercut region UE. C or N can be formed not only at the lower portion of the channel pattern 43 but also in a region adjacent to the lower portion of the channel pattern 43. For example, C or N can also be formed at a surface of the data storage pattern 41.

[0116] Referring to FIG. 22 The method can further include forming a conductive layer 60 in the horizontal via region HT, the undercut region UC, the extended undercut region UE, and the vertical via region VT.

[0117] The conductive layer 60 can be formed using CVD or ALD, for example. The conductive layer 60 can be a semiconductor layer doped with impurities. For example, the conductive layer 60 can include polysilicon doped with impurities.

[0118] The conductive layer 60 can be located on and at least partially cover the inner surfaces of the horizontal via region HT, the undercut region UC, the extended undercut region UE, and the vertical via region VT with a uniform thickness. The conductive layer 60 can not completely fill the vertical via region VT. An air gap or a seam can be formed at a portion of the conductive layer 60 in the horizontal via region HT. The conductive layer 60 can be directly on and at least partially cover the side surfaces of the insulating pattern 45. In addition, the conductive layer 60 can directly physically contact the source conductive layer 15, the data storage pattern 41, the channel pattern 43, the dummy data storage pattern 41d, and the dummy channel pattern 43d.

[0119] Referring to FIG. 23 The method can further include forming a source conductive pattern 70 by partially removing the conductive layer 60, and forming a word line cut WLC extending through the stack structure 20. Upon removing a portion of the conductive layer 60 formed in the vertical via region VT, a lower source conductive pattern 71 can be formed. The lower source conductive pattern 71 can be formed in the horizontal via region HT, the undercut region UC, and the extended undercut region UE.

[0120] The source conductive layer 15 can also be partially etched during the isotropic etching process for the conductive layer 60. The upper source conductive pattern 73 can be formed when the source conductive layer 15 is etched. The word line cut WLC can be formed when the portions of the conductive layer 60 and the portions of the source conductive layer 15 are etched. The word line cut WLC can expose the inner side surfaces of the stack structure 20 therethrough.

[0121] The isotropic etching process for partially removing the conductive layer 60 can be performed using etching conditions having etching selectivity with respect to the stack structure 20. For example, the isotropic etching process for etching the conductive layer 60 can be a wet etching process using a mixed solution of deionized water (SC-1: standard clean-1) or ammonia water (NH4OH).

[0122] Referring to FIG. 24 The method can further include forming the gate electrode 82 including a lower gate electrode 82d and an upper gate electrode 82u. The step of forming the gate electrode 82 can include forming a gate region by removing the sacrificial layers 22d and 22u of the stack structure 20. The step of removing the sacrificial layers 22d and 22u can include performing an etching process having etching selectivity with respect to the insulating layers 21d, 21u and 23, the data storage pattern 41, the lower source conductive pattern 71, the upper source conductive pattern 73, and the substrate 10. The gate region can expose the upper and lower surfaces of the insulating layers 21d, 21u and 23 therethrough, and can expose portions of the side surfaces of the data storage pattern 41 therethrough.

[0123] Thereafter, the gate electrode 82 can be formed in the gate region and can at least partially fill the gate region. The step of forming the gate electrode 82 can include forming a gate electrode layer to at least partially fill the word line cut WLC and the gate region, and then removing portions of the gate electrode layer in the word line cut WLC, thereby forming the gate electrode 82 in the gate region.

[0124] Referring again to FIG. 2 The method can further include forming a common source structure CSS in the word line cut WLC. The method can further include forming a lower contact 90 extending through the cap layer 50 and forming an interlayer insulating layer 93, an upper contact 95, and a bit line BL on the cap layer 50. In addition, the method can further include performing a heat treatment process for diffusing N-type impurities from the lower source conductive pattern 71 around the lowermost gate electrode 82d-1 by heat treatment.

[0125] According to embodiments of the inventive concept, it can be possible to provide a proper physical distance between a gate-induced drain leakage (GIDL) erase gate and a source conductive pattern, and it can be possible to provide impurity diffusion control at an interface between a channel pattern and the source conductive pattern. Thus, it can be possible to properly secure holes for an erase operation, and as such, it can be possible to enhance reliability of a GIDL erase operation.

[0126] While embodiments of the inventive concept have been described with reference to the drawings, it is to be understood that various modifications can be made by those skilled in the art without departing from the scope of what is disclosed and described herein and without utilizing all of the features of the inventive concept. Therefore, the above description should not be construed as limiting, but merely as descriptive.

Claims

1. A semiconductor device comprising: a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked; a channel structure extending through the gate structure; and a source conductive pattern between the substrate and the gate structure, wherein the source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern, wherein the channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern, and wherein, in a cross-sectional view of the semiconductor device, a lower surface of the channel pattern is at a level higher than a level of an upper surface of the upper source conductive pattern and lower than a level of a lower surface of a lowermost gate electrode among the gate electrodes, and the substrate provides a reference level. In a cross-sectional view of the semiconductor device, a lower surface of the channel pattern is at a level higher than a level of a lower surface of the data storage pattern, and the substrate provides a reference level.

2. The semiconductor device according to claim 1, wherein In a cross-sectional view of the semiconductor device, a lower surface of the data storage pattern is at a level lower than a level of an upper surface of the upper source conductive pattern, and the substrate provides a reference level.

3. The semiconductor device according to claim 2, wherein In a cross-sectional view of the semiconductor device, a lower surface of the data storage pattern is at a level higher than a level of an upper surface of the upper source conductive pattern, and the substrate provides a reference level.

4. The semiconductor device according to claim 2, wherein In a cross-sectional view of the semiconductor device, a lower surface of the channel pattern is at the same level as a lower surface of the data storage pattern.

5. The semiconductor device according to claim 1, wherein 6. The semiconductor device according to claim 1, wherein: In a cross-sectional view of the semiconductor device, a portion of a lower surface of the data storage pattern is at a level higher than a level of an upper surface of the upper source conductive pattern, and the substrate provides a reference level; and In a cross-sectional view of the semiconductor device, another portion of a lower surface of the data storage pattern is at a level lower than a level of an upper surface of the upper source conductive pattern, and the substrate provides a reference level. In a cross-sectional view of the semiconductor device, an uppermost portion of a lower surface of the data storage pattern is at a level lower than a level of a lower surface of the channel pattern, and the substrate provides a reference level.

7. The semiconductor device according to claim 1, wherein In a cross-sectional view of the semiconductor device, an uppermost portion of a lower surface of the data storage pattern is at a level higher than a level of a lower surface of the channel pattern and lower than a level of a lower surface of a lowermost gate electrode among the gate electrodes, and the substrate provides a reference level.

8. The semiconductor device according to claim 1, wherein 9. The semiconductor device according to claim 1, wherein: the data storage pattern includes a tunnel insulating layer, a charge storage layer, and a barrier layer sequentially stacked on an outer side surface of the channel pattern; and In a cross-sectional view of the semiconductor device, a lower surface of the barrier layer, a lower surface of the charge storage layer, and a lower surface of the tunnel insulating layer are at different levels, respectively. A portion of the lower source conductive pattern is between the insulating pattern and the barrier layer while physically contacting the lower surface of the channel pattern.

10. The semiconductor device according to claim 9, wherein The lower portion of the channel pattern includes C or N.

11. The semiconductor device according to claim 1, wherein 12. A semiconductor device comprising: a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked; a channel structure extending through the gate structure; and a source conductive pattern between the substrate and the gate structure, wherein the source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern, wherein the channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern, and wherein, in a cross-sectional view of the semiconductor device, a lower surface of the channel pattern is at a level higher than a level of an upper surface of the upper source conductive pattern and lower than a level of a lowermost gate electrode among the gate electrodes, and the substrate provides a reference level. a source conductive pattern between the substrate and the gate structure, wherein the source conductive pattern includes a lower source conductive pattern and an upper source conductive pattern on the lower source conductive pattern, wherein the channel structure includes an insulating pattern extending through the source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern, wherein a portion of the lower source conductive pattern is between the insulating pattern and the data storage pattern while physically contacting a lower surface of the channel pattern, and wherein, in a cross-sectional view of the semiconductor device, the lower surface of the channel pattern is at a level higher than a level of a lower surface of the data storage pattern, and the substrate provides a reference level.

13. The semiconductor device according to claim 12, wherein The lower surface of the channel pattern is closer to a lower surface of a lowermost one of the gate electrodes than to an upper surface of the upper source conductive pattern.

14. The semiconductor device according to claim 12, wherein In a cross-sectional view of the semiconductor device, a lower surface of the data storage pattern is at a level lower than a level of an upper surface of the upper source conductive pattern, and the substrate provides a reference level.

15. The semiconductor device according to claim 12, wherein In a cross-sectional view of the semiconductor device, a lower surface of the data storage pattern is at a level equal to or higher than a level of an upper surface of the upper source conductive pattern, and the substrate provides a reference level.

16. A semiconductor device, the semiconductor device comprising: a gate structure on a substrate, the gate structure including insulating layers and gate electrodes alternately stacked; a lower source conductive pattern between the substrate and the gate structure; an upper source conductive pattern between the lower source conductive pattern and the gate structure; a channel structure extending through the gate structure; a common source structure extending through the channel structure; a contact on the channel structure; and a bit line on the contact, wherein the channel structure includes an insulating pattern extending through the upper source conductive pattern and the lower source conductive pattern, a data storage pattern, and a channel pattern between the insulating pattern and the data storage pattern, wherein the data storage pattern includes a tunnel insulating layer, a charge storage layer, and a barrier layer sequentially stacked on the channel pattern, wherein the lower source conductive pattern includes a horizontal extension on an upper surface of the substrate, a vertical extension extending between the insulating pattern and the upper source conductive pattern, and a protrusion protruding from an upper surface of the vertical extension, and wherein the protrusion includes a first protrusion between the insulating pattern and the tunnel insulating layer while physically contacting a lower surface of the channel pattern. In a cross-sectional view of the semiconductor device, an upper surface of the vertical extension is at a level higher than a level of an upper surface of the upper source conductive pattern but lower than a level of a lower surface of a lowermost one of the gate electrodes, and the substrate provides a reference level.

17. The semiconductor device according to claim 16, wherein 18. The semiconductor device according to claim 16, wherein: In a cross-sectional view of the semiconductor device, an upper surface of the first protrusion is at a level higher than a level of an upper surface of the upper source conductive pattern but lower than a level of a lower surface of a lowermost one of the gate electrodes, and the substrate provides a reference level; and In a cross-sectional view of the semiconductor device, an upper surface of the vertical extension is at a level lower than a level of the upper source conductive pattern, and the substrate provides a reference level. ​ 19. The semiconductor device according to claim 16, wherein The protrusion also includes a second protrusion extending between the tunnel insulating layer and the lowermost insulating layer of the insulating layers.

20. The semiconductor device according to claim 19, wherein, The second protrusion is located between the charge storage layer and the lowermost insulating layer of the insulating layers while physically contacting a lower surface of the barrier layer.

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