Data processing device and method

Abstract

The embodiment of the present application discloses a data processing device and a related method, wherein a data processing device may include a first chip and a second chip in a stacked package; the first chip includes a general-purpose processor, a bus and at least one first dedicated processing unit DPU, the general-purpose processor and the at least one first dedicated processing unit are connected to the bus, and the general-purpose processor is used to generate data processing tasks; the second chip includes a second dedicated processing unit, one or more first dedicated processing units in the at least one first dedicated processing unit and at least one of the second dedicated processing units can process at least a part of the data processing task based on the computing function; wherein the first chip and the second chip are connected to each other through an inter-chip interconnection line. The data processing device can meet the user's increasingly high power consumption and computing requirements without increasing the product volume.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a data processing device and method. Background Art

[0002] The system-on-chip (SOC) of smart terminals has been evolving and developing along with the progress of semiconductor technology, from 28nm to 7nm and even 5nm. The technology enables machine vision, such as camera algorithms, and neural network algorithms to be integrated into smart terminal SOC chips, and the power consumption of smart terminal SOC chips does not exceed the current battery power supply and heat dissipation capabilities.

[0003] However, as Moore's Law slows down, the pace of process evolution lengthens, and the cost of each generation of process investment increases step by step, which brings great challenges to product competitiveness. Therefore, the traditional SOC integrated chip architecture is gradually unable to meet current needs, and the technical bottlenecks faced by its traditional SOC integrated chip architecture are mainly due to the limited chip area, resulting in insufficient chip computing power, excessive power consumption, and insufficient chip storage bandwidth. The existing chip stacking technology uses silicon through-hole interconnection to realize the chip stacking architecture, which can be used to separate and decouple devices such as storage, analog or input / output IO from the main chip, that is, storage, analog or input / output IO and other devices become independent chips, so that the two chips use different process processes and the purpose of independent technology evolution. Moreover, the stacked chip architecture will not significantly increase the volume of the product. However, with the rapid development of current Internet media and neural network algorithms, and the increase in user demand for audio and video on smart terminals, the requirements for chip computing power, power consumption and chip storage bandwidth of SOC integrated chips on smart terminals have also been greatly improved. In the existing stacking scheme, the chip only splits the analog and input / output devices into independent chips by expanding the stacked memory. The stacked chip architecture cannot meet the users' increasingly high computing needs and complex and changing application scenarios. Moreover, the power consumption performance of the chip architecture after splitting and then stacking is not optimized enough.

[0004] Therefore, how to provide an efficient chip structure to meet users' increasingly high power consumption and computing requirements without increasing product volume, and to meet the flexibility of task processing while improving product performance, is an urgent problem to be solved. Summary of the invention

[0005] The embodiments of the present application provide a data processing device and related methods to improve product performance without increasing product volume and meet the flexibility of task processing.

[0006] In a first aspect, an embodiment of the present application provides a data processing device, which may include a first chip and a second chip in a stacked package; the first chip includes a general-purpose processor, a bus and at least one first dedicated processing unit DPU, the general-purpose processor and the at least one first dedicated processing unit are connected to the bus, and the general-purpose processor is used to generate data processing tasks; the second chip includes a second dedicated processing unit, the second dedicated processing unit has at least partially the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit, and at least one of the one or more first dedicated processing units and the second dedicated processing unit can process at least a part of the data processing task based on the computing function; wherein the first chip and the second chip are interconnected by inter-chip interconnect lines.

[0007] Through the device provided in the first aspect, when the general processor in the first chip generates a data processing task, because the second dedicated processing unit has at least partially the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit, the second dedicated processing unit can process at least a part of the data processing task based on the at least partially same computing function. Therefore, the data processing device can flexibly allocate the data processing task to the first dedicated processing unit and the second dedicated processing unit according to the needs of the data task to meet the user's computing needs, for example: when the amount of data processing tasks is small, it can be allocated to the first dedicated processing unit alone, or allocated to the second dedicated processing unit alone, etc.; for example: when the amount of data processing tasks is large, it can be allocated to the first dedicated processing unit and the second dedicated processing unit at the same time. Moreover, the stacked chip architecture in the data processing device can also assist the first dedicated processing unit in processing data processing tasks without significantly increasing the overall chip volume, and enhance the computing power of the first dedicated processing unit, which largely alleviates and solves the demand for chip computing power improvement due to the rapid development of the current algorithm, and also avoids the problem that the chip cannot complete the data processing task due to insufficient computing power of the first dedicated processing unit. Therefore, the data processing device can meet the users' increasingly higher power consumption and computing requirements without increasing the volume of the product, while also improving the performance of the product and satisfying the flexibility of task processing.

[0008] In one possible implementation, the second dedicated processing unit has the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit. In implementing the embodiment of the present application, the second dedicated processing unit has the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit, so the second dedicated processing unit can process the same data processing task as one or more first dedicated processing units. For example: when one or more first dedicated processing units are unable to perform data processing tasks in a timely manner, the second dedicated processing unit can assist the one or more first dedicated processing units in performing data processing tasks to meet the user's increasingly high computing needs.

[0009] In a possible implementation, the general processor includes a central processing unit (CPU). In implementing the embodiment of the present application, the general processor in the first chip may be a central processing unit, which may serve as the computing and control core of the chip system, generate data processing tasks, and is also the final execution unit for information processing and program running to meet the basic computing needs of users.

[0010] In a possible implementation, each of the one or more first dedicated processing units and the second dedicated processing unit includes at least one of a graphics processing unit GPU, an image signal processor ISP, a digital signal processor DSP, or a neural network processing unit NPU. In implementing the embodiment of the present application, the one or more first dedicated processing units and the second dedicated processing unit can be used to perform data processing tasks of different data types, so that the smart terminal can adapt to the user's increasing different types of data processing needs.

[0011] In one possible implementation, the chip-to-chip interconnection line includes at least one of a through silicon via TSV interconnection line or a wire bonding interconnection line. In implementing the embodiments of the present application, the chip-to-chip interconnection line can adopt a variety of efficient chip-to-chip interconnection lines, such as through silicon via TSV interconnection lines, wire bonding interconnection lines, and the like. For example, TSV, as a through-hole interconnection technology between chips, has a small aperture, low latency, and flexible configuration of data bandwidth between chips, which improves the overall computing efficiency of the chip system. Using TSV silicon through-hole technology, a bump-free bonding structure can also be achieved, and adjacent chips of different properties can be integrated together. The stacked chip wire bonding interconnection line reduces the length of the chip-to-chip interconnection line and effectively improves the working efficiency of the device itself.

[0012] In a possible implementation, the device further includes a third chip, the third chip is stacked and packaged with the first chip and the second chip, and the third chip is connected to at least one of the first chip or the second chip through the inter-chip interconnection line; the third chip includes at least one of a memory, a power transmission circuit module, an input-output circuit module, or an analog module. In implementing the embodiment of the present application, the first chip can be stacked and packaged with the third chip. For example, stacking the memory with the first chip can partially solve the problem of insufficient storage bandwidth while increasing the computing power of the chip; stacking one or more of the power transmission circuit module, the input-output circuit module, or the analog module with the first chip can achieve the purpose of separating and decoupling the simulation and logical calculation of the SOC chip while increasing the computing power of the chip, continuing the increasingly high demands on chips in chip evolution and business scenarios.

[0013] In one possible implementation, the inter-chip interconnection line is connected between the one or more first dedicated processing units and the second dedicated processing unit; the second dedicated processing unit is used to obtain at least a portion of the data processing task from the one or more first dedicated processing units. In implementing the embodiment of the present application, the second chip is connected to the one or more first dedicated processing units in the first chip, and can obtain at least a portion of the data processing task from the one or more first dedicated processing units. Therefore, the second dedicated processing unit can accept the deployment of one or more first dedicated processing units to perform at least a portion of the data processing task, thereby meeting the flexibility of task processing.

[0014] In a possible implementation, the inter-chip interconnection line is connected between the second dedicated processing unit and the bus, and the second dedicated processing unit is used to obtain at least a part of the data processing task from the general processor through the bus. In implementing the embodiment of the present application, the second chip is connected to the bus in the first chip to obtain at least a part of the data processing task from the general processor. Therefore, the second dedicated processing unit can accept the deployment of the general processor and execute at least a part of the data processing task alone or together with one or more first dedicated processing units, thereby meeting the flexibility of task processing.

[0015] In one possible implementation, the general processor is used to send startup information to the second dedicated processing unit through the inter-chip interconnection line; the second dedicated processing unit is used to switch from a waiting state to a startup state in response to the startup information, and process at least a part of the data processing task based on the computing function. In implementing the embodiment of the present application, the general processor can allocate the computing power of the second dedicated processing unit, for example: when the general processor in the first chip sends startup information to the second dedicated processing unit through the inter-chip interconnection line, the second chip can switch from a waiting state to a startup state to perform data processing tasks, wherein the power consumption of the waiting state is lower than the power consumption of the startup state. Therefore, when the general processor does not send startup information to the second dedicated processing unit, the second dedicated processing unit will remain in a waiting state, thereby effectively controlling the power consumption of the stacked chips.

[0016] In a possible implementation, the general processor is used to send startup information to the second dedicated processing unit through the inter-chip interconnection line when the computing power of the one or more first dedicated processing units does not meet the demand. In the implementation of the embodiment of the present application, when one or more first dedicated processing units in the first chip are performing data processing tasks and the computing power of one or more first dedicated processing units is insufficient, the second chip in the stacked chip can receive the startup information sent by the general processor, and according to the startup information, the second chip is converted from a waiting state to a startup state, and the one or more first dedicated processing units of the first chip are assisted to perform data processing tasks, so as to enhance or supplement the computing power of the one or more first dedicated processing units, and avoid the chip being unable to complete the data processing task of the target data due to insufficient computing power of one or more first dedicated processing units. Therefore, when the computing power of the one or more first dedicated processing units meets the computing requirements, the second chip can be in a waiting state all the time, and there is no need to start the startup state of the second chip, and only the dedicated processing unit in the first chip is made to perform data processing tasks, thereby reducing the power consumption of the chip as a whole.

[0017] In a possible implementation, the one or more first dedicated processing units are used to send startup information to the second dedicated processing unit through the inter-chip interconnection line; the second dedicated processing unit is used to respond to the startup information, switch from a waiting state to a startup state, and process at least a part of the data processing task based on the computing function. In implementing the embodiment of the present application, one or more first dedicated processing units can allocate the computing power of the second dedicated processing unit, for example: when one or more first dedicated processing units of the general-purpose processor in the first chip send startup information to the second dedicated processing unit through the inter-chip interconnection line, the second chip can be converted from a waiting state to a startup state to perform data processing tasks, wherein the power consumption of the waiting state is lower than the power consumption of the startup state. Therefore, when one or more first dedicated processing units do not send startup information to the second dedicated processing unit, the second dedicated processing unit will always be in a waiting state, thereby effectively controlling the power consumption of the stacked chips.

[0018] In a possible implementation, the one or more first dedicated processing units are used to send startup information to the second dedicated processing unit through the inter-chip interconnection line when the computing power of the one or more first dedicated processing units does not meet the demand. In the implementation of the present application, when one or more first dedicated processing units in the first chip are performing data processing tasks and the computing power of one or more first dedicated processing units is insufficient, the second chip in the stacked chip can receive the startup information sent by the one or more first dedicated processing units, and convert the second chip from the waiting state to the startup state according to the startup information, assisting the one or more first dedicated processing units of the first chip to perform data processing tasks, so as to enhance or supplement the computing power of the one or more first dedicated processing units, and avoid the chip being unable to complete the data processing task of the target data due to insufficient computing power of one or more first dedicated processing units, so as to meet the computing needs of the user. Therefore, when the computing power of the one or more first dedicated processing units meets the computing requirements, the second chip can be in a waiting state all the time, and there is no need to start the startup state of the second chip, and only the dedicated processing unit in the first chip is made to perform data processing tasks, thereby reducing the overall power consumption of the chip.

[0019] In a second aspect, an embodiment of the present application provides a data processing method, characterized in that it includes: generating a data processing task by a general-purpose processor in a first chip, the first chip includes the general-purpose processor, a bus and at least one first dedicated processing unit DPU, the general-purpose processor and the at least one first dedicated processing unit are connected to the bus; processing at least a part of the data processing task by one or more first dedicated processing units in the at least one first dedicated processing unit and at least one second dedicated processing unit in a second chip package, the second dedicated processing unit having at least partially the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit, the first chip and the second chip are stacked and packaged and connected to each other through chip-to-chip interconnect lines.

[0020] In one possible implementation, processing at least a portion of the data processing task by one or more of the at least one first dedicated processing units and at least one of the second dedicated processing units in the second chip package includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the general-purpose processor; switching from a waiting state to a startup state by the second dedicated processing unit in response to the startup information, and processing at least a portion of the data processing task based on the computing function.

[0021] In a possible implementation, sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the general-purpose processor includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the general-purpose processor when the computing power of the one or more first dedicated processing units does not meet the demand.

[0022] In one possible implementation, processing at least a portion of the data processing task by one or more of the at least one first dedicated processing units and at least one of the second dedicated processing units in the second chip package includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the one or more first dedicated processing units; the second dedicated processing unit is used to switch from a waiting state to a startup state in response to the startup information, and process at least a portion of the data processing task based on the computing function.

[0023] In one possible implementation, sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the one or more first dedicated processing units includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the one or more first dedicated processing units when the computing power of the one or more first dedicated processing units does not meet the demand.

[0024] In a third aspect, an embodiment of the present application provides a chip system, which includes any one device for supporting the data processing involved in the above-mentioned first aspect. The chip system can be composed of a chip, or can include a chip and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments of the present application will be described below.

[0026] Figure 1 This is a traditional von Neumann chip architecture diagram provided in an embodiment of the present application.

[0027] Figure 2A It is a schematic diagram of a data processing architecture provided in an embodiment of the present application.

[0028] Figure 2B It is a schematic diagram of a chip architecture of a stacked package provided in an embodiment of the present application.

[0029] Figure 2C It is a schematic diagram of a chip architecture of a stacked package in practical application provided in an embodiment of the present application.

[0030] Figure 2D This is an embodiment of the present application. Figure 2C A schematic diagram of the interaction between the second dedicated processing unit and the first dedicated processing unit in the stacked packaged chip is shown.

[0031] Figure 2E This is a schematic diagram of another chip architecture of stacked packaging in practical applications provided by an embodiment of the present application.

[0032] Figure 2F This is an embodiment of the present application. Figure 2E A schematic diagram of the interaction between the second dedicated processing unit and the first dedicated processing unit in the stacked packaged chip is shown.

[0033] Figure 2G It is a schematic diagram of another chip architecture of stacked packaging provided in an embodiment of the present application.

[0034] Figure 3 It is a flowchart of a data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0036] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0039] The "connection" involved in this embodiment refers to the communication, data exchange, energy transmission, etc. that can be carried out between the connected modules, units or devices. It can be a direct connection or an indirect connection through other devices or modules. For example, it can be connected through some wires, conductors, media, interfaces, devices or units because it can be regarded as an electrical connection or coupling in a broad sense.

[0040] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0041] (1) Through Silicon Via (TSV), also known as through silicon via, is a vertical interconnection that penetrates a silicon wafer or chip. TSV can be used to implement 3D integrated circuit (IC) packaging, following Moore's Law. For example, TSV can stack multiple chips. Its design concept comes from the printed circuit board (PCB). Specifically, a small hole is drilled in the chip (the process can be divided into two types: via first drilling and via last drilling), and metal is filled from the bottom of the small hole. For example, a hole (via) is drilled on the silicon wafer that forms the chip by etching or laser, and then filled with conductive materials such as copper, polysilicon, tungsten and other substances. This technology can effectively improve the integration and performance of the system at a lower cost.

[0042] (2) System on Chip (SOC), also known as system on chip, is a dedicated integrated circuit that contains a fully functional circuit system and all the contents of embedded software. SOC includes multiple different functional components, which will be introduced later.

[0043] (3) Stacking structure refers to a type of system packaging, in which system packaging can be divided into three types: adjacent structure, stacking structure and buried structure. The use of stacking structure can increase the packaging density in three dimensions and can be applied to packaging at different levels or levels, such as package stacking (PoP), package in package (PiP), chip or die stacking, and chip and wafer stacking. Chip stacking is common in various terminal products. Its advantage is that standard chips and wire bonding and subsequent packaging can be achieved using existing equipment and processes, but it has restrictions on the thickness of the entire package and cannot be too large. At present, it is possible to vertically install up to 8 dies in a package with a thickness of less than 1.2 mm. This requires that each die in the stacked package chip is a thin wafer, a thin substrate, a low lead curvature, a low mold cap height, etc.

[0044] (4) Round wafer refers to the silicon chip used to make silicon semiconductor integrated circuits. Due to its round shape, it is also called a wafer.

[0045] (5) Bare die is an integrated circuit product that contains various circuit component structures and has specific electrical functions after being processed and cut on a wafer. Bare die can be packaged to make a chip.

[0046] (6) Graphics Processing Unit (GPU), also known as display core, visual processor, display chip, is a microprocessor that specializes in image and graphics related computing on personal computers, workstations, game consoles and some mobile devices (such as tablets, smart phones, etc.). GPU reduces the dependence of devices on CPU and performs some of the work originally done by CPU, especially in 3D graphics processing. The core technologies used by GPU include hardware geometry transformation and lighting processing (T&L), cubic environment material mapping and vertex blending, texture compression and bump mapping, dual texture four-pixel 256-bit rendering engine, etc. Hardware geometry transformation and lighting processing technology can be said to be the hallmark of GPU.

[0047] (7) Digital Signal Processing (DSP). DSP usually refers to a chip or processor that performs digital signal processing technology. Digital signal processing technology is a technology that converts analog information (such as sound, video, and pictures) into digital information. They may also be used to process this analog information and then output it as analog information. It can also be based on digital signal processing theory, hardware technology, and software technology to study digital signal processing algorithms and their implementation methods.

[0048] (8) Neural-network Processing Unit (NPU) is a processor that processes neural models. It can be considered a component (or subsystem), and is sometimes called an NPU coprocessor. It generally adopts a "data-driven parallel computing" architecture and is particularly good at processing massive multimedia data such as videos and images.

[0049] (9) Printed circuit boards (PCBs) are providers of electrical connections for electronic components. According to the number of layers, they can be divided into single-layer boards, double-layer boards, four-layer boards, six-layer boards, and other multi-layer boards.

[0050] (10) Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that as long as the memory remains powered, the data stored in it can be kept constant. In contrast, the data stored in dynamic random access memory (DRAM) needs to be updated periodically. However, when the power supply stops, the data stored in SRAM will still disappear (called volatile memory), which is different from ROM or flash memory that can still store data after power failure.

[0051] (11) Input / Output (I / O) usually refers to the input and output of data between internal devices and external memory or other peripheral devices. It is the communication between the information processing system of the internal device (such as a computer) and the external world (which may be a human or another information processing system). Input is the signal or data received by the system, and output is the signal or data sent from it. The term can also be used as part of an action; to "perform I / O" is to perform an input or output operation.

[0052] (12) The von Neumann architecture, also known as the Princeton architecture, is a memory structure that combines program instruction memory and data memory. The program instruction storage address and the data storage address point to different physical locations in the same memory, so the width of the program instruction and the data are the same.

[0053] (13) Arithmetic unit refers to the smallest unit of operation in the arithmetic unit of the CPU, which is a hardware structure. Currently, operations are completed through logic circuits formed by tiny components such as electronic circuits, and all they process are high and low level signals, that is, binary signals.

[0054] Please refer to the attached Figure 1 , Figure 1 This is a traditional von Neumann chip architecture diagram provided in an embodiment of the present application, such as Figure 1 As shown, it includes an arithmetic unit, a controller, a memory, an input device and an output device.

[0055] The traditional von Neumann chip architecture is difficult to meet the current needs of chip computing power, power consumption and chip storage bandwidth. Therefore, chip stacking technology can be used to solve some of the problems caused by limited chip area, such as insufficient chip computing power, excessive power consumption and insufficient chip storage bandwidth. Regarding the chip stacking technology (taking the SOC chip of a mobile smart terminal as an example), the power transmission circuit, I / O or radio frequency circuit in the SOC chip can be separated into another chip separately, which can realize the decoupling of circuits with different functions. The embodiment of the present application can also decouple the input / output (I / O) module or the dedicated processing unit from the function of the main chip as an independent chip, so that the main chip will no longer have the function of the decoupled independent chip, and the main chip and the independent chip need to work at the same time, and the power consumption performance is not optimized enough.

[0056] In view of the above analysis, the data processing device provided by the present application can enhance the computing power of the chip in processing data, reduce the power consumption of the chip as a whole, and take into account the product volume problem. In order to facilitate the understanding of the present application embodiment, the following first describes one of the data processing device architectures based on the present application embodiment. Please refer to the attached Figure 2A , Figure 2A is a schematic diagram of a data processing architecture provided in an embodiment of the present application. Figure 2A The architecture shown is mainly based on stacked chips and is described from the perspective of data processing.

[0057] It should be noted that in a broad sense, a chip can be a packaged chip or an unpackaged chip, that is, a bare chip. The chips in the chip structure for stacking and packaging, such as the "first chip", "second chip" and "main chip" involved in this application, can all be understood as unpackaged chips, that is, bare chips (die), which refer to integrated circuit products that contain various circuit element structures on a cut silicon wafer and have specific electrical functions. Therefore, the chips that need to be stacked and packaged involved in the embodiments of the present application are bare chips that have not yet been packaged.

[0058] like Figure 2A As shown, when the user has finished using the recording function of the smart terminal, the smart terminal can process the recorded audio file through the stacked chips and save it in the memory. Among them, the stacked chip system in the smart terminal includes a first chip 001 and a second chip 002, the first chip 001 can be a system-level chip SOC, the first chip 001 includes a general processor 011, a bus 00 and at least one first dedicated processing unit (DomainProcessing Unit, DPU) 021, the general processor 011 and the at least one first dedicated processing unit 021 are connected to the bus, wherein at least one first dedicated processing unit 021 can be sequentially recorded as: DPU_1 to DPU-n; the second chip 002 includes a second dedicated processing unit 012 (can be recorded as: DPU-A); the first chip 001 and the second chip 002 are connected through an inter-chip interconnection line.

[0059] The first chip 001 is used to process data and generate data processing tasks, and can also send startup information to the second chip 002. The second chip 002 is used to switch from a waiting state to a startup state when receiving the startup information, and execute part or all of the data processing tasks through the second dedicated processing unit.

[0060] Among them, the general processor 011 (for example: central processing unit, CPU) in the first chip 001 serves as the computing and control core of the chip system and is the final execution unit for information processing and program running. In the field of mobile terminals, the general processor 011 may generally include a reduced instruction set processor (Advanced RISC Machines, ARM) series, which may include one or more core processing units. In an embodiment of the present application, the general processor 011 can be used to generate data processing tasks for target data. Optionally, the general processor 011 can also select at least a part of the data processing tasks of one or more first dedicated processing units 021 from at least one first dedicated processing unit 021 according to the data processing task. Optionally, the general processor 011 can also be used to process simple data processing tasks without the assistance of at least one first dedicated processing unit 021 and the second dedicated processing unit 012.

[0061] At least one first dedicated processing unit 021 in the first chip 001 can process at least a part of the data processing task based on the computing function, for example, a graphics processing unit GPU can perform a data processing task of image recognition. Optionally, at least one first dedicated processing unit 021 may include at least one of a graphics processing unit GPU, an image signal processor ISP, a digital signal processor DSP, or a neural network processing unit NPU. Optionally, all first dedicated processing units DPU in at least one first dedicated processing unit 021 can work simultaneously, or only one can work.

[0062] The bus 00 in the first chip 001 is also called the internal bus, board-level bus or microcomputer bus. It can be used to connect the functional components in the chip to form a complete chip system, and can also be used to transmit various data signals, control commands, etc., to assist the communication between various functional components. For example, the general processor 011 and at least one first dedicated processing unit 021 can be connected, so that the general processor 011 can control one or more of the at least one first dedicated processing unit 021 to perform data processing tasks.

[0063] The second dedicated processing unit 012 in the second chip 002 has at least partially the same computing function as one or more first dedicated processing units 021 in the at least one first dedicated processing unit 021, and at least one of the one or more first dedicated processing units 021 and the second dedicated processing unit 012 can process at least a part of the data processing task based on the computing function. The second dedicated processing unit 012 having at least partially the same computing function as the one or more first dedicated processing units 021 may mean that the computing function of the second dedicated processing unit 012 and the computing function of the one or more first dedicated processing units 021 may be at least partially the same, and the same part of the function is the function shared by the second dedicated processing unit 012 and the one or more first dedicated processing units 021, and this part of the shared function can be used to calculate the data processing task, and the data processing task can be assigned to the second dedicated processing unit 012 and the one or more first dedicated processing units 021 for processing, for example, the second dedicated processing unit 012 and the one or more first dedicated processing units 021 share the computing power, which will be introduced in detail in the subsequent lectures. Of course, the computing functions of the second dedicated processing unit 012 and the one or more first dedicated processing units 021 may also be completely the same. For example, the second dedicated processing unit 012 and the one or more first dedicated processing units 021 may perform the same data processing task through partially the same operation logic, operation mode and / or operation purpose. For example: the one or more first dedicated processing units 021 may include convolutional neural network operation capabilities, and the second dedicated processing unit 012 may also include at least part of the convolutional neural network operation capabilities, such as most of the capabilities. For another example: in performing neural operations, the one or more first dedicated processing units 021 may convert a segment of speech into several keywords through a speech recognition method, and the second dedicated processing unit 012 may convert a segment of speech into a string of text including keywords through a speech recognition method. For another example, the one or more first dedicated processing units 021 may include the image operation processing capabilities of the ISP to generate captured images, for example, the capabilities may include white balance, noise elimination, pixel calibration, image sharpening, and gamma calibration. The second dedicated processing unit 012 may also include most of the image operation processing capabilities that may include the previous ISP to generate captured images, for example, the capabilities may include white balance, noise elimination, pixel calibration or image sharpening.

[0064] Optionally, the second dedicated processing unit 012 in the second chip 002 has the same computing function as one or more first dedicated processing units 021 in the at least one first dedicated processing unit 021, and can be used to perform all processing tasks of the acquired data processing task. The second dedicated processing unit 012 and the one or more first dedicated processing units 021 can have the same computing function, which can include: the second dedicated processing unit 012 and the one or more first dedicated processing units 021 can have exactly the same operation logic and / or operation mode to perform data processing tasks. For example: when a first dedicated processing unit 021 in the at least one first dedicated processing unit 021 includes a unit for a parallel matrix operation array, the second dedicated processing unit 012 can also include a unit for implementing a parallel matrix operation array, and the algorithm type can also be consistent with the algorithm type used by the first dedicated processing unit 021.

[0065] The inter-chip interconnection line includes any one of silicon through-hole via (TSV) interconnection line and wire bonding interconnection line. For example, TSV, as an inter-chip through-hole interconnection technology, has a small aperture, low latency, and flexible configuration of inter-chip data bandwidth, which improves the overall computing efficiency of the chip system. With TSV silicon through-hole technology, a non-bump bonding structure can be achieved, and adjacent chips of different properties can be integrated together. The stacked chip wire bonding interconnection line reduces the length of the inter-chip interconnection line and effectively improves the working efficiency of the device itself.

[0066] It should be noted that the connection signals of the chip-to-chip interconnection lines may include data signals and control signals, wherein the digital signals may be used to transmit the target data, and the control signals may be used to allocate data processing tasks for the target data, and this application does not make any specific limitations.

[0067] It should also be noted that Figure 2A The data processing architecture in the embodiment of the present application is only an exemplary implementation, and the data processing architecture in the embodiment of the present application includes but is not limited to the above data processing architecture. For example: the first chip 001 can also be stacked and packaged with multiple second chips 002 to form a chip, and the second dedicated processing units included in the multiple second chips 002 respectively have at least partially the same computing function as at least one first dedicated processing unit 021 included in the first chip 001.

[0068] It should also be noted that the stacked chip system can be configured in different data processing devices, corresponding to different forms of master control in different data processing devices. The embodiments of the present application do not limit the form of the master control, such as server laptops, smart phones, car TVs, etc.

[0069] Secondly, based on the above Figure 2A The data processing architecture provided in this application embodiment describes two chip stacking architectures based on the data processing device architecture. Figure 2B , attached Figure 2B is a schematic diagram of a chip architecture of a stacked package provided in an embodiment of the present application, such as Figure 2B In the stacked package chip architecture shown, the first chip and the second chip are connected to each other through inter-chip interconnection lines, and the SOC chip is mainly used as the main chip, and is described from the perspective of data processing.

[0070] like Figure 2B The chip architecture shown includes: a first chip 001 and a second chip 002; the first chip 001 includes a general-purpose processor 011 (such as: CPU, or optionally a microcontroller), at least one first dedicated processing unit 021 (DPU_1, DPU_2...DPU_n) and a bus 00, and also includes: a memory 031, an analog module 041, an input / output module 051, etc.; the second chip 002 is a computing power stacking chip connected to the first dedicated processing unit DPU_1, and the second chip 002 includes a second dedicated processing unit 012 (ie: DPU_A).

[0071] The general processor 011 in the first chip 001 may be a CPU, which is used to generate data processing tasks.

[0072] Optionally, the general processor 011 in the first chip 001 is also used to allocate data processing tasks to one or more first dedicated processing units in at least one first dedicated processing unit 021, and / or the second dedicated processing unit 012 in the second chip. The general processor 011 in the first chip 001 can flexibly allocate data processing tasks to the first dedicated processing unit and the second dedicated processing unit according to the needs of data tasks, so as to meet the increasingly high computing needs of users. For example, when the amount of data processing tasks is small, it can be allocated to the first dedicated processing unit alone; for example, when the amount of data processing tasks is large, it can be allocated to the first dedicated processing unit and the second dedicated processing unit at the same time, or allocated to the second dedicated processing unit alone, etc. The flexibility of task processing can be met without increasing the volume of the product.

[0073] Optionally, the inter-chip interconnection line is connected between the second dedicated processing unit and the bus, and the general processor 011 in the first chip 001 can also be used to send startup information to the second dedicated processing unit through the inter-chip interconnection line, so that the second dedicated processing unit responds to the startup information, switches from a waiting state to a startup state, and processes at least a part of the data processing task based on its computing function. The power consumption of the waiting state is lower than that of the startup state. Therefore, when the general processor does not send startup information to the second dedicated processing unit, the second dedicated processing unit will always be in a waiting state, thereby effectively controlling the power consumption of the stacked chips.

[0074] Optionally, the inter-chip interconnection line is connected between the second dedicated processing unit and the bus, and the general processor 011 in the first chip 001 can also be used to send startup information to the second dedicated processing unit through the inter-chip interconnection line when the computing power of the one or more first dedicated processing units does not meet the demand. When one or more first dedicated processing units 021 in the first chip are performing data processing tasks and the computing power of one or more first dedicated processing units 021 is insufficient, the second chip 002 in the stacked chip can receive the startup information sent by the general processor 011, and according to the startup information, the second chip 002 is converted from a waiting state to a startup state, and assists the one or more first dedicated processing units 021 of the first chip 001 in performing data processing tasks, so as to enhance or supplement the computing power of the one or more first dedicated processing units 021, and avoid the chip being unable to complete the data processing task of the target data due to insufficient computing power of one or more first dedicated processing units 021.

[0075] It should be noted that, based on the computing power of the one or more first dedicated processing units 021, it is predicted whether the one or more first dedicated processing units 021 can complete the data processing task within the preset time; if the one or more first dedicated processing units 021 cannot complete the data processing task within the preset time, it is determined that the one or more first dedicated processing units 021 have insufficient computing power when performing the data processing task.

[0076] The at least one first dedicated processing unit 021 in the first chip 001 is respectively recorded as: DPU_1, DPU_2...DPU_n from left to right, wherein one or more first dedicated processing units 021 in the at least one first dedicated processing unit 021 are used to obtain and execute data processing tasks based on corresponding computing functions.

[0077] Optionally, the at least one first dedicated processing unit 021 may include one or more of a graphics processing unit GPU, an image signal processor ISP, a digital signal processor DSP, and a neural network processing unit NPU. For example, the GPU and ISP can be used to process graphic data in a smart terminal; the DSP can be used to process digital signal data in a smart terminal; and the NPU can be used to process massive multimedia data such as videos and images in a smart terminal. Therefore, the at least one first dedicated processing unit 021 can be used to perform different data processing tasks through different computing functions, so that the smart terminal can adapt to the increasing data processing needs of users. The DPU_1 in the first chip 001 of the embodiment of the present application is used to perform data processing tasks.

[0078] Optionally, the inter-chip interconnection line is connected between the one or more first dedicated processing units and the second dedicated processing unit; the one or more first dedicated processing units 021 in the first chip 001 are also used to send startup information to the second chip 002 when the one or more first dedicated processing units 021 execute the data processing task, and allocate part or all of the processing tasks of the data processing task to the second dedicated processing unit 012 of the second chip 002. So that the second dedicated processing unit 012 responds to the startup information, switches from the waiting state to the startup state, and processes at least part of the data processing task based on its computing function that is at least partially the same as that of the one or more first dedicated processing units 021. Among them, the power consumption of the waiting state is lower than the power consumption of the startup state. Therefore, when one or more first dedicated processing units 021 do not send startup information to the second dedicated processing unit 012, the second dedicated processing unit 012 will always be in the waiting state, thereby effectively controlling the power consumption of the stacked chips. It should be noted that the power consumption of the waiting mode is lower than the power consumption of the working mode.

[0079] Optionally, the inter-chip interconnection line is connected between the one or more first dedicated processing units and the second dedicated processing unit; the one or more first dedicated processing units 021 in the first chip 001 are used to send startup information to the second dedicated processing unit 012 through the inter-chip interconnection line when the computing power of the one or more first dedicated processing units 021 does not meet the demand. When the one or more first dedicated processing units 021 in the first chip 001 are performing data processing tasks and the computing power of the one or more first dedicated processing units 021 is insufficient, the second chip 002 in the stacked chip can receive the startup information sent by the one or more first dedicated processing units 021, and convert the second chip 002 from a waiting state to a startup state according to the startup information, to assist the one or more first dedicated processing units 021 of the first chip 001 in performing data processing tasks, so as to enhance or supplement the computing power of the one or more first dedicated processing units 021, and avoid the chip being unable to complete the data processing task of the target data due to insufficient computing power of the one or more first dedicated processing units 021, so as to meet the computing needs of the user.

[0080] The bus 00 in the first chip 001 is used to connect the general processor 011 and the at least one first dedicated processing unit 021 .

[0081] The memory 031 in the first chip 001 is used to store target data and data processing tasks corresponding to the target data. The target data type may include graphic data, video data, audio data, text data, etc.

[0082] The analog module 041 in the first chip 001 mainly implements analog processing functions, such as RF front-end simulation, port physical layer (Physical, PHY), etc.

[0083] The input / output module 051 in the first chip 001 is a general interface of the SOC chip to external devices, which is used for data input and output, and generally includes a controller and a port physical layer (Physical, PHY), such as a Universal Serial Bus (USB) interface, a Mobile Industry Processor Interface (MIPI), and the like.

[0084] The second dedicated processing unit 012 in the second chip 002 has at least partially the same computing function as one or more first dedicated processing units 021 in the at least one first dedicated processing unit 021, and can be used to perform part or all of the processing tasks of the data processing tasks assigned by the general processor 011 or one or more first dedicated processing units 021. For example: when one of the at least one first dedicated processing unit 021 is an NPU, the core of its NPU is a unit of a parallel matrix operation array. Then the second dedicated processing unit 012 is also used to implement the unit of the parallel matrix operation array, and the algorithm type is also consistent with the algorithm type used by the NPU, such as Int8, Int6, F16, etc. However, in terms of the number of computing units, the second dedicated processing unit 012 and the NPU may be different, that is. The second dedicated processing unit 012 and the first dedicated processing unit 021 implement the same computing function, but the computing power is different.

[0085] Optionally, the second dedicated processing unit 012 in the second chip 002 has the same computing function as one or more first dedicated processing units 021 in the at least one first dedicated processing unit 021. Therefore, the second dedicated processing unit 012 can process the same data processing task as one or more first dedicated processing units 021. For example, when one or more first dedicated processing units 021 perform a data processing task, the second dedicated processing unit 012 can assist the one or more first dedicated processing units 021 to jointly perform the data processing task, so as to more efficiently meet the user's increasingly high computing needs.

[0086] Optionally, the second second dedicated processing unit in the second chip 002 is used to respond to the startup information, switch from the waiting state to the startup state, and process at least a part of the data processing task based on the computing function. When one or more first dedicated processing units 021 in the first chip 001 are performing data processing tasks, the second chip 002 in the stacked chip system can receive the startup information sent by the one or more first dedicated processing units 021, and according to the startup information, the second chip 002 is switched from the waiting mode to the working mode, and assists the one or more first dedicated processing units 021 of the first chip 001 to perform data processing tasks, so as to enhance or supplement the computing power of the one or more first dedicated processing units 021, and avoid the chip being unable to complete the data processing task of the target data due to insufficient computing power of one or more first dedicated processing units 021. Therefore, when the general processor does not send the startup information to the second dedicated processing unit, the second dedicated processing unit will always be in the waiting state, thereby effectively controlling the power consumption of the stacked chip.

[0087] In a possible implementation, the second dedicated processing unit 012 includes one or more corresponding operation units in the first dedicated processing unit 021 having at least partially the same computing function, and the operation units corresponding to the one or more first dedicated processing units 021 are respectively used to process the target data through operation logic. For example, when the second dedicated processing unit 012 has at least partially the same computing function as the neural network processing unit NPU, because the operation units of the neural network processing unit NPU include: matrix unit Matrix Unit, vector unit Vector Unit and scalar unit ScalarUnit, the second dedicated processing unit 012 in the second chip 002 may also include one or more of Matrix Unit, Vector Unit and Scalar Unit, so as to be used to perform data processing tasks assigned to the second chip 002 to perform matrix multiplication, vector operation, scalar operation, etc. on the data.

[0088] Optionally, the chip-to-chip interconnection lines of the first chip 001 and the second chip 002 are TSVs. Since the TSV process technology can achieve a single silicon through-hole via with a diameter as small as ~10um, the number of TSV interconnection lines between the first chip 001 and the second chip 002 can be determined as needed without occupying too much area, and this application does not make specific limitations.

[0089] In one possible implementation, Figure 2B The first chip 001 may include multiple first dedicated processing units 021, wherein each first dedicated processing unit 021 can receive a data processing task sent by the general processor 011, and is used to process a corresponding type of data processing task. For example, the first chip 001 generally includes a graphics processing unit GPU, an image signal processor ISP, a digital signal processor DSP, and a neural network processing unit NPU. Among them, the graphics processing unit GPU and the image signal processor ISP can be used to process the graphic data in the smart terminal; the digital signal processor DSP can be used to process the execution digital signal data in the smart terminal; the neural network processing unit NPU can be used to process the massive multimedia data of videos and images in the smart terminal.

[0090] In a possible implementation, the second dedicated processing unit 012 in the second chip 002 may include one or more operation units, and the one or more operation units are used to process data through corresponding operation logics. For example, when the second dedicated processing unit 012 has at least partially the same computing function as the NPU, because the core computing units of the NPU are the matrix unit, the vector unit, and the scalar unit, the second dedicated processing unit 012 in the second chip 002 may also include one or more of the matrix unit, the vector unit, and the scalar unit, which are used to execute the data processing tasks assigned to the second chip 002 to perform matrix multiplication, vector operation, or scalar operation on the data, etc.

[0091] It should be noted that, when the general processor in the first chip generates a data processing task, because the second dedicated processing unit has at least partially the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit, the second dedicated processing unit can process at least partially the same data processing task as one or more first dedicated processing units. Therefore, the data processing device can flexibly allocate the data processing tasks to the first dedicated processing unit and the second dedicated processing unit according to the needs of the data task, so as to meet the increasingly high computing needs of users, for example: when the amount of data processing tasks is small, it can be allocated to the first dedicated processing unit alone; for example: when the amount of data processing tasks is large, it can be allocated to the first dedicated processing unit and the second dedicated processing unit at the same time, or allocated to the second dedicated processing unit alone, etc. At the same time, stacking the second chip on the first chip can meet the volume requirements of the product without significantly increasing the volume of the chip architecture. Moreover, when only one chip performs a data processing task, the other chip can be in a low power consumption state, which can effectively control the power consumption of the stacked chip when performing the data processing task. Therefore, the data processing device can meet the increasingly high power consumption and computing needs of users without increasing the volume of the product, while improving product performance and meeting the flexibility of task processing.

[0092] Based on the above Figure 2A The data processing architecture provided, and Figure 2B The stacked package chip architecture provided is based on the following application scenario where one or more first dedicated processing units 021 call the second dedicated processing unit 012 to perform enhanced computing power calculation when the computing power is insufficient. Please refer to the attached Figure 2C and attached Figure 2D , attached Figure 2C Schematic diagram of a chip architecture of a stacked package in practical application provided by an embodiment of the present application, Figure 2DThis is an embodiment of the present application. Figure 2C The schematic diagram of the interaction between the second dedicated processing unit and the first dedicated processing unit in the stacked packaged chip is shown. Figure 2C The provided stacked package chip architecture is used to support and execute the following method flow steps 1 to 7.

[0093] like Figure 2C As shown, the second dedicated processing unit DPU-A included in the second chip 002 in the stacked package chip architecture is connected to the first dedicated processing unit DPU_1 through TSV interconnect lines. Among them, the second dedicated processing unit DPU_A may include a memory (Buffer) 0121 and a task scheduler (Task Scheduler) 0122, and an AI algorithm operation module 0123 for directly scheduling task sequences and data by the first dedicated processing unit DPU_1 (the AI ​​algorithm operation module 0123 includes: a matrix unit 01 (Matrix Unit), a vector unit 02 (Vector Unit) and a scalar unit 03 (Scalar Unit)). Among them, the memory (Buffer) 0121 is used to store data and corresponding data processing tasks, the task scheduler (Task Scheduler) 0122 is used to receive assigned data processing tasks, and the AI ​​algorithm operation module 0123 is used to execute data processing tasks. The first dedicated processing unit DPU_1 may also include: a memory (Buffer) 0211 and a task scheduler (Task Scheduler) 0212, wherein the corresponding functions may refer to the related descriptions of the various functional modules of the first dedicated processing unit DPU_1 mentioned above.

[0094] Specifically, DPU_A is directly scheduled by DPU_1, so the signals that connect the two devices directly through TSV silicon vias include at least two types: data signals and control signals. The number of bits of the two signals depends on the specific design requirements. The number of bits of Data Signals is the number of bits required for parallel computing of data, which is generally at least a multiple of 64 bits, such as 64b, 128b, ... 1028b, etc., while Control signals generally include single bits such as Enable signals, start / stop control signals, and interrupt signals. Figure 2D As shown by the dotted line in , DPU_1 first moves the data processed in the previous link from the memory 031 to the buffer 0211 of the DPU_1 unit, and then decides whether to send it to DPU_A for auxiliary calculation processing according to the calculation requirements.

[0095] It should be noted that the relevant description of other functional units in the data processing device described in the embodiments of the present application can be found in the above Figure 2B The description of the chip architecture of the stacked package provided in the specification and the description of steps 1 to 7 of the following method flow will not be repeated here.

[0096] Among them, Figure 2D The schematic diagram of the interaction between the second dedicated processing unit and the first dedicated processing unit in the stacked packaged chip shown, the data processing method may include:

[0097] 1. After receiving the data processing task sent by CPU 011 through Task Scheduler 0212, DPU_1 moves the target data from the memory to the temporary cache Buffer 0211 inside DPU_1;

[0098] 2. DPU_1 predicts whether the computing power of the data processing task is sufficient through Task Scheduler0212. If the computing processing power of DPU_1 cannot meet the needs of the data processing task, Task Scheduler0212 sends a startup message to DPU_A through TSV's Controlsignals;

[0099] 3. After receiving the startup information, DPU_A wakes up from the low power state, enters the startup state, and feeds back the waiting signal to DPU_1 through the Control signals of TSV;

[0100] 4. Task Scheduler0212 of DPU_1 sends the assigned data processing task to TaskScheduler0122 of DPU_A, and DPU_A moves the data to be processed by DPU_A to Buffer0121 of DPU_A unit;

[0101] 5. Task Scheduler 0212 of DPU_A starts AI algorithm operation module 0123 (including Matrix Unit 01, Vector Unit 02 and Scalar Unit 03, etc.) according to the data processing task. AI algorithm operation module 0123 reads the data of Buffer 0121 and starts to execute the data processing task.

[0102] 6. The AI ​​algorithm operation module 0123 stores the operation-completed data into the Buffer 0121 of DPU_A;

[0103] 7. Task Scheduler 0122 of DPU_A sends a processing completion signal back to TaskScheduler 0212 of DPU_1, and writes the data from Buffer 0121 of DPU_A back to Buffer 0211 inside DPU_1.

[0104] It should be noted that DPU_1, as a dedicated processing unit for AI processing, generally has a core computing part that includes parallel Matrix Unit 01, Vector Unit 02, and Scalar Unit 03, as well as internal temporary data storage buffer 0211 and task scheduler 0212. DPU_A, as a computing power enhancement unit of DPU_1, has a computing core that includes Matrix Unit 01, and optionally Vector Unit 02 and Scalar Unit 03. DPU_A can also include Buffer 0121 and Task Scheduler 0122 as needed. Although the computing core of DPU_A can include Matrix Unit 01, Vector Unit 02, and Scalar Unit 03, the number of operators or MACs in each unit may be different from that of DPU_1.

[0105] In the embodiment of the present application, the DPU_A of the second chip 002 is positioned as a computing power enhancement module, which is directly scheduled and controlled by the DPU_1 in the first chip 001. Under normal scenarios, the computing power of DPU_1 itself is sufficient to meet the needs. At this time, the DPU_A of the second chip 002 can be put into a waiting state to save the overall power consumption of the chip system; when some scenarios, such as video processing, require AI processing with high computing power or assist in processing, DPU_1 can activate DPU_A through TSV's Control signals and participate in the calculation and processing together.

[0106] It can be understood that, in the embodiment of the present application, the AI ​​enhanced computing unit is taken as an example, but the present application is not limited to this scenario. Other first dedicated processing units (such as DPU_1...DPU_n) can also be connected to DPU_A to enhance the computing power of other dedicated processing units, such as GPU, ISP, etc. The embodiment of the present application does not make specific limitations on this.

[0107] Based on the above Figure 2A The data processing architecture provided, and Figure 2B The stacked package chip architecture provided is based on the application scenario of the general processor 011 calling the second dedicated processing unit 012 to perform calculations. Please refer to the attached Figure 2E and attached Figure 2F , attached Figure 2EFIG. 1 is another schematic diagram of a chip architecture of a stacked package in practical application provided by an embodiment of the present application, and FIG. Figure 2F This is an embodiment of the present application. Figure 2E The schematic diagram of the interaction between the second dedicated processing unit and the first dedicated processing unit in the stacked packaged chip is shown. Figure 2E The provided stacked package chip architecture is used to support and execute the following method flow steps 1 to 6.

[0108] like Figure 2E As shown, the stacked chip system includes a first chip 001 and a second chip 002, and the second chip 002 in the stacked package chip architecture is connected to the bus 00 in the first chip 001 through a TSV interconnection line. That is, the inter-chip interconnection line is connected between the second dedicated processing unit 012 and the bus 00, wherein the second dedicated processing unit DPU_A may include a memory (Buffer) 0121 and a task scheduler (Task Scheduler) 0122, and an AI algorithm operation module 0123 (AI algorithm operation module 0123 includes: Matrix Unit 01, Vector Unit 02 and Scalar Unit 03) for directly scheduling task sequences and data by the first dedicated processing unit DPU_1. Among them, Buffer 0121 is used to store data and corresponding data processing tasks, Task Scheduler 0122 is used to receive assigned data processing tasks, and AI algorithm operation module 0123 is used to execute data processing tasks. The first dedicated processing unit DPU_1 may also include: a memory (Buffer) 0211 and a task scheduler (Task Scheduler) 0212, wherein the corresponding functions may refer to the related descriptions of the various functional modules of the first dedicated processing unit DPU_1 mentioned above.

[0109] Specifically, DPU_A is directly controlled and scheduled by the CPU 011 of the first chip 001, and DPU_A is directly connected to the bus 00 of the first chip 001, so the TSV interconnection signals between DPU_A and the first chip 001 generally use the standard protocol bus (Advanced eXtensible Interface, AXI) and peripheral bus (Advanced Peripheral Bus, APB), among which the AXI bus is used for reading and writing data signals, and the APB bus is used for control signal configuration.

[0110] The functions of other functional units in the data processing device described in the embodiments of the present application can be found in the above Figure 2B-2C The description of the chip architecture of the stacked package provided in the specification and the description of steps 1 to 6 of the following method flow will not be repeated here.

[0111] Among them, Figure 2F The schematic diagram of the interaction between the second dedicated processing unit 012 and the first dedicated processing unit 021 in the stacked package chip system is shown, and the data processing method includes:

[0112] 1. CPU 011, as a general processor of the first chip 001, initiates the startup information of DPU_1 to DPU_A of the second chip 002 through bus 00, and configures at least part of the data processing task to TaskScheduler0122 of DPU_A unit;

[0113] 2. After receiving the startup information, DPU_A enters the startup state from the waiting state, that is, it is awakened from the low power consumption state; Task Scheduler 0122 of DPU_A receives the data processing task issued by CPU 011, and moves data from the memory 031 in the chip to Buffer 0121 inside DPU_A through bus 00;

[0114] 3. Task Scheduler 0122 of DPU_A starts AI algorithm operation module 0123 (including Matrix Unit 01, Vector Unit 02 and Scalar Unit 03) according to the data processing task. AI algorithm operation module 0123 reads the data in buffer 0121 and starts to execute the data processing task.

[0115] 4. The AI ​​algorithm operation module 0123 stores the operation-completed data into the Buffer 0121 of DPU_A;

[0116] 5. DPU_A writes the processed data from Buffer0121 back to the memory 031 in the chip through bus 00;

[0117] 6. The Task Scheduler 0122 of DPU_A sends a processing completion signal back to the CPU 011 of the first chip 001 to complete the calculation of this data processing task.

[0118] Optionally, in the embodiment of the present application, the second chip 002 is connected to the bus in the first chip 001 through TSV interconnect lines, that is, the data processing task of the target data can be controlled by the CPU 011 to be executed by DPU_1 alone, DPU_1 and DPU_A in parallel, or DPU_A alone.

[0119] In the embodiment of the present application, the second dedicated processing unit DPU_A of the second chip 002 is a computing power enhancement module, which is directly scheduled and controlled by the CPU 011 in the first chip 001. In conventional scenarios, the computing power of DPU_1 in the first chip 001 is sufficient to meet the demand. At this time, the DPU_A of the second chip 002 can be put in a waiting state; or, only the DPU_A of the second chip 002 can be put in a startup state. When some scenarios, such as video processing, require AI processing with high computing power, the CPU can activate the DPU_A computing unit through the TSV control line to participate in high computing power processing together.

[0120] Optional, based on the above Figure 2A The data processing architecture provided, and Figure 2B In the provided stacked package chip architecture, the first chip can also be stacked and packaged with multiple second chips to form a chip system, and the second dedicated processing unit contained in each of the multiple second chips can match the same or partially the same computing function as one or more first dedicated processing units in at least one first dedicated processing unit. For another example: the first chip can also be stacked and packaged with the second chip and the third chip, respectively, wherein the third chip includes one or more of a memory, a power transmission circuit module, an input-output circuit module, or an analog module. Please refer to the attached Figure 2G , Figure 2G FIG. 1 is a schematic diagram of another chip architecture of a stacked package provided in an embodiment of the present application. Figure 2G As shown, in addition to the stacked computing units, memory 003 (Stacked Memory) can also be stacked to further bring the storage closer to the computing units, improve the data processing bandwidth and efficiency of the overall system, and solve the problem of insufficient chip storage bandwidth after stacking. Optionally, one or more of the power transmission circuit module, input and output circuit module, or analog module can also be stacked to achieve the purpose of separating and decoupling the simulation and logical computing of the chip, continuing the increasingly high demands of chip evolution and business scenarios on chips.

[0121] It should be noted that Figure 2C and Figure 2E The stacked packaged chip in the embodiment is only an exemplary implementation in the embodiment of the present application. The stacked packaged chip architecture in the embodiment of the present application includes but is not limited to the above stacked packaged chip architecture.

[0122] It should also be noted that the stacked packaged chips can be configured in different data processing devices, corresponding to different forms of master control in different data processing devices. The embodiments of the present application do not limit the form of the master control, for example, server laptops, smart phones, car TVs, etc.

[0123] See also Figure 3 , Figure 3 is a flow chart of a data processing method provided in an embodiment of the present application, which can be applied to the above Figure 2A In the structure of the data processing device described in Figure 2B The provided stacked package chip architecture, wherein the data processing device may include the above Figure 2B The stacked package chip architecture provided is used to support and execute Figure 3 The method flow shown in FIG. 1 is steps S301 to S302.

[0124] Step S301: Generate a data processing task through a general-purpose processor in a first chip. Specifically, the data processing device generates a data processing task through the general-purpose processor. The first chip includes the general-purpose processor, a bus, and at least one first dedicated processing unit DPU, the general-purpose processor and the at least one first dedicated processing unit are connected to the bus, and the first chip and the second chip are stacked and packaged into a chip architecture.

[0125] Optionally, the general purpose processor includes a central processing unit CPU.

[0126] Optionally, each of the one or more first dedicated processing units and the second dedicated processing unit includes at least one of a graphics processing unit GPU, an image signal processor ISP, a digital signal processor DSP, or a neural network processing unit NPU. For example, the graphics processing GPU can be used to process graphics data in the smart terminal; the signal processing DSP can be used to process digital signal data in the smart terminal; the neural network processing unit NPU can be used to process massive multimedia data such as videos and images in the smart terminal. Therefore, the at least one first dedicated processing unit DPU can be used to perform data processing tasks of different data types, so that the smart terminal can adapt to the increasing data processing needs of users.

[0127] Step S302: Process at least a portion of the data processing task by one or more first dedicated processing units in at least one first dedicated processing unit and at least one second dedicated processing unit in the second chip package. Specifically, the data processing device processes at least a portion of the data processing task by one or more first dedicated processing units in at least one first dedicated processing unit and at least one second dedicated processing unit in the second chip package, the second dedicated processing unit has the same computing function as one or more first dedicated processing units in the at least one first dedicated processing unit, and the first chip and the second chip are stacked and packaged and connected to each other through chip-to-chip interconnection lines.

[0128] Optionally, processing at least a portion of the data processing task by one or more of the at least one first dedicated processing units and at least one of the second dedicated processing units in the second chip package includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the general-purpose processor; switching from a waiting state to a startup state by the second dedicated processing unit in response to the startup information, and processing at least a portion of the data processing task based on the computing function.

[0129] Optionally, sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the general-purpose processor includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the general-purpose processor when the computing power of the one or more first dedicated processing units does not meet the demand.

[0130] Optionally, processing at least a portion of the data processing task by one or more of the at least one first dedicated processing units and at least one of the second dedicated processing units in the second chip package includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the one or more first dedicated processing units; the second dedicated processing unit is used to switch from a waiting state to a startup state in response to the startup information, and process at least a portion of the data processing task based on the computing function.

[0131] Optionally, sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the one or more first dedicated processing units includes: sending startup information to the second dedicated processing unit through the inter-chip interconnection line by the one or more first dedicated processing units when the computing power of the one or more first dedicated processing units does not meet the demand.

[0132] It should be noted that the relevant description of steps S301 to S302 in the embodiment of the present application can also refer to the above Figure 2A-2G The relevant descriptions of each embodiment will not be repeated here.

[0133] By implementing the embodiment of the present application, the stacked chip architecture in the data processing device can flexibly allocate data processing tasks to the first dedicated processing unit and the second dedicated processing unit, respectively. When the first dedicated processing unit is processing data processing tasks alone, the second processing unit of the stacked second chip will be in a waiting state, and will only be converted from the waiting state to the starting state when the second dedicated processing unit receives the startup information. Since the power consumption of the waiting state is lower than that of the starting state, the overall power consumption control of the stacked chip architecture is more flexible and efficient, and the energy efficiency of the chip system is improved. Moreover, the stacked chip architecture can also assist the first dedicated processing unit in processing data processing tasks without increasing the overall volume, and enhance the computing power of the first dedicated processing unit, which greatly alleviates and solves the demand for chip computing power improvement caused by the rapid development of current algorithms, and avoids the chip from being unable to complete the data processing task of the target data due to insufficient computing power of the first dedicated processing unit. Further, the computing power stacking chip architecture can also continue the demand for higher computing power in chip evolution and business scenarios by vertically stacking computing power (i.e., stacking the first chip and the second chip) when Moore's Law slows down and the terminal chip area is limited.

[0134] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required for the present application.

[0135] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual connection or communication connection shown or discussed can be a communication connection of devices or units connected by some wires, conductors, interfaces, or can be electrical or other forms.

[0136] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0138] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing device, characterized in that: A first chip and a second chip comprising a stacked package; The first chip includes a general-purpose processor, a bus and at least one first dedicated processing unit DPU, the general-purpose processor and the at least one first dedicated processing unit DPU are connected to the bus, and the general-purpose processor is used to generate data processing tasks; The second chip includes a second dedicated processing unit, the second dedicated processing unit having at least partially the same computing function as one or more first dedicated processing units of the at least one first dedicated processing unit, and at least one of the one or more first dedicated processing units and the second dedicated processing unit can process at least a part of the data processing task based on the computing function; The first chip and the second chip are connected to each other via an inter-chip interconnection line.

2. The device according to claim 1, characterized in that: The second special-purpose processing unit has the same computing function as one or more first special-purpose processing units in the at least one first special-purpose processing unit.

3. The device according to claim 1, characterized in that: The general purpose processor includes a central processing unit CPU.

4. The device according to claim 1, characterized in that: Each of the one or more first dedicated processing units and the second dedicated processing unit includes at least one of a graphics processing unit GPU, an image signal processor ISP, a digital signal processor DSP, or a neural network processing unit NPU.

5. The device according to claim 1, characterized in that: The inter-chip interconnection line includes at least one of a through silicon via (TSV) interconnection line or a wire bonding interconnection line.

6. The device according to claim 1, characterized in that: The device further includes a third chip, the third chip is stacked and packaged with the first chip and the second chip, and the third chip is connected to at least one of the first chip or the second chip through the inter-chip interconnection line; The third chip includes at least one of a memory, a power transmission circuit module, an input-output circuit module or an analog module.

7. The device according to claim 1, characterized in that: The inter-chip interconnection line is connected between the one or more first dedicated processing units and the second dedicated processing unit; the second dedicated processing unit is used to obtain at least a part of the data processing task from the one or more first dedicated processing units.

8. The device according to claim 1, characterized in that: The inter-chip interconnection line is connected between the second dedicated processing unit and the bus, and the second dedicated processing unit is used to obtain at least a part of the data processing task from the general processor through the bus.

9. The device according to any one of claims 1 to 8, characterized in that: The general processor is used to send startup information to the second dedicated processing unit through the inter-chip interconnection line; The second dedicated processing unit is used to switch from a waiting state to a starting state in response to the starting information, and process at least a part of the data processing task based on the computing function.

10. The device according to claim 9, characterized in that The general-purpose processor is used to send startup information to the second dedicated processing unit through the inter-chip interconnection line when the computing power of the one or more first dedicated processing units does not meet the demand.

11. The device according to any one of claims 1 to 8, characterized in that: The one or more first dedicated processing units are used to send startup information to the second dedicated processing unit through the inter-chip interconnection line; The second dedicated processing unit is used to switch from a waiting state to a starting state in response to the starting information, and process at least a part of the data processing task based on the computing function.

12. The device according to claim 11, characterized in that The one or more first dedicated processing units are used to send startup information to the second dedicated processing unit through the inter-chip interconnection line when the computing power of the one or more first dedicated processing units does not meet the demand.

13. A data processing method, characterized in that: include: Generate a data processing task by a general-purpose processor in a first chip, wherein the first chip comprises the general-purpose processor, a bus and at least one first dedicated processing unit DPU, wherein the general-purpose processor and the at least one first dedicated processing unit are connected to the bus; At least a portion of the data processing task is processed by one or more of the at least one first dedicated processing units and at least one of the second dedicated processing units in the second chip package, the second dedicated processing unit having at least partially the same computing function as one or more of the at least one first dedicated processing unit, the first chip and the second chip are stacked and packaged and connected to each other through chip-to-chip interconnection lines.

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