Semiconductor Structure and Method for Forming the Same

Abstract

The method includes forming a first dielectric layer; forming a first redistribution line including a first via hole extending into the first dielectric layer and a first trace located above the first dielectric layer; forming a second dielectric layer covering the first redistribution line; and patterning the second dielectric layer to form a via opening. The first redistribution line is exposed through the via opening. The method further includes forming a second via hole in the second dielectric layer and forming a conductive pad in contact with the second via hole above the second via hole; and forming a conductive bump above the conductive pad. The conductive pad is larger than the conductive bump, and a first center of the conductive pad is offset from a second center of the conductive bump. The second via hole is offset further from the second center of the conductive bump. Embodiments of the present application also relate to a semiconductor structure and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] With the development of semiconductor technology, semiconductor chips / die have become smaller and smaller. At the same time, more functions need to be integrated into the semiconductor die. Therefore, semiconductor die need to package an increasingly large number of I / O pads into a smaller area, and the density of I / O pads has increased rapidly over time. As a result, the packaging of semiconductor die has become more difficult, which adversely affects the yield of the package.

[0003] A typical bonding structure may include an under-bump metal (UBM) as a metal pad and a metal pillar on the UBM. A solder region may be used to bond the metal pillar to another electrical connector of another packaging component. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor structure, including: forming a first dielectric layer; forming a first redistribution line, the first redistribution line including a first via hole extending into the first dielectric layer and a first trace located above the first dielectric layer; forming a second dielectric layer covering the first redistribution line; patterning the second dielectric layer to form a via hole opening, wherein the first redistribution line is exposed through the via hole opening; forming a second via hole in the second dielectric layer, and forming a conductive pad contacting the second via hole above the second via hole; and forming a conductive bump above the conductive pad, wherein the conductive pad is larger than the conductive bump, and a first center of the conductive pad is offset from a second center of the conductive bump, and wherein the second via hole is offset further from the second center of the conductive bump.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a first dielectric layer; a first via hole extending into the first dielectric layer; a conductive trace located above the first dielectric layer, wherein the conductive trace is located above the first via hole and coupled to the first via hole; a second dielectric layer covering the conductive trace; a second via hole located in the second dielectric layer; a conductive pad located above the second via hole and contacting the second via hole; wherein the conductive pad has a first center; and a conductive bump located above the conductive pad and contacting the conductive pad, wherein the conductive bump has a second center, and wherein the second center of the second via hole and the conductive bump are located on opposite sides of the first center of the conductive pad.

[0006] Some other embodiments of the present application provide a semiconductor structure, comprising: a plurality of dielectric layers; a plurality of redistribution lines located in the plurality of dielectric layers, wherein each of the plurality of redistribution lines includes a via hole and a trace located above and in contact with the via hole, and some of the via holes in the plurality of redistribution lines are stacked to form a via stack, wherein the via holes are vertically aligned; a top via hole located above and in contact with a top trace in a top redistribution line of the plurality of redistribution lines; a conductive pad located above and in contact with the top via hole; and a conductive bump located above and bonded to the conductive pad, wherein the conductive bump and the top via hole are eccentric, and wherein the conductive pad includes: a first portion extending beyond a first edge of the conductive bump by a first distance, and a second portion extending beyond a second edge of the conductive bump by a second distance less than the first distance, wherein the first portion is narrower than the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 12 A cross-sectional view showing an intermediate stage of forming an interconnect assembly including an eccentric bonding structure according to some embodiments is shown.

[0009] Figure 13 An encapsulation including an eccentric bonding structure according to some embodiments is shown.

[0010] Figure 14 A cross-sectional view of an eccentric bonding structure according to some embodiments is shown.

[0011] Figure 15 A top view of an eccentric bonding structure according to some embodiments is shown.

[0012] Figure 16 A top view of a redistribution line having a narrower middle portion according to some embodiments is shown.

[0013] Figure 17 A cross-sectional view of an eccentric bonding structure according to some embodiments is shown.

[0014] Figure 18 A top view of an eccentric bonding structure according to some embodiments is shown.

[0015] Figure 19 A top view of a redistribution line having a narrower middle portion according to some embodiments is shown.

[0016] Figure 20 and Figure 21 illustrates a structure simulated according to some embodiments.

[0017] Figure 22 illustrates a process flow for forming an interconnect assembly including an eccentric engagement structure according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0019] Further, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0020] An encapsulation and a method of forming the same including an eccentric bonding structure are provided. According to some embodiments of the present invention, conductive bumps (which may be metal pillars) are formed, and conductive pads are formed under the conductive bumps, wherein the conductive pads are larger than the conductive bumps. The conductive pads are elongated and may have a side that is narrower than the other side. A first via is located under the conductive pad and is bonded to the conductive pad. The first via is vertically offset from the center of the upper conductive bump. The redistribution line located under the first via and bonded to the first via may have a narrower central portion. A plurality of second vias located under the first via and electrically connected to the first via are also offset from the first via. The offset and specific shape of the conductive pad and the redistribution line can prevent the conductive bumps, the conductive pads, and the vias with a high coefficient of thermal expansion (CTE) value from being vertically aligned, and thus can reduce stress. The embodiments discussed herein will provide examples to enable the practice or use of the subject matter of the present invention, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of the different embodiments. Throughout the various views and exemplary embodiments, the same reference numerals are used to indicate the same elements. Although the method embodiments discussed may be performed in a specific order, other method embodiments may be performed in any logical order.

[0021] Figures 1 to 12 A cross-sectional view showing an intermediate stage in the formation of an interconnect assembly including an eccentric bonding structure according to some embodiments of the present invention is shown. The corresponding process is also schematically reflected in Figure 22 the process flow shown. It can be understood that although the interconnect assembly including the eccentric bonding structure is formed starting from a carrier, it can also be formed starting from other groups such as a fan-out interconnect structure of a device die, a part of a device die, or an interposer.

[0022] Figure 1 A carrier 20 and a release film 22 formed on the carrier 20 are shown. The carrier 20 can be a glass carrier, a silicon wafer, an organic carrier, etc. According to some embodiments, the carrier 20 can have a circular top view shape. The release film 22 can be formed of a polymer-based material (such as a light-to-heat conversion (LTHC) material) that can be decomposed under radiation such as a laser beam, so that the carrier 20 can be peeled off from the upper structure formed in subsequent processes. According to some embodiments of the present invention, the release film 22 includes an epoxy-based thermal release material coated onto the carrier 20.

[0023] As Figures 1 to 4 shown, a plurality of dielectric layers and a plurality of RDLs are formed above the release film 22. The corresponding process is shown as process 202 in the process flow 200 shown in Figure 22 Reference Figure 1, first, a dielectric layer 24 is formed on the release film 22. According to some embodiments of the present invention, the dielectric layer 24 is formed of a polymer, which may also be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., which can be easily patterned using a lithography process.

[0024] According to some embodiments, redistribution lines (RDLs) 26 are formed above the dielectric layer 24. The formation of the RDLs 26 may include forming a seed layer (not shown) above the dielectric layer 24, forming a patterned mask (not shown) such as a photoresist above the seed layer, and then performing a metal plating process on the exposed seed layer. Then, the patterned mask and the portions of the seed layer covered by the patterned mask are removed, leaving the RDLs 26 as shown in Figure 1 . According to some embodiments of the present invention, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or a similar process. Plating can be performed using, for example, electroless plating.

[0025] Further referring to Figure 1 , a dielectric layer 28 is formed on the RDLs 26. The bottom surface of the dielectric layer 28 contacts the top surface of the RDLs 26 and the dielectric layer 24. According to some embodiments of the present invention, the dielectric layer 28 is formed of a polymer that may be a photosensitive material such as PBO, polyimide, BCB, etc. Optionally, the dielectric layer 28 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. Then, the dielectric layer 28 is patterned to form openings 30 therein. Thus, some portions of the RDLs 26 are exposed through the openings 30 in the dielectric layer 28.

[0026] Next, referring to Figure 2 , RDLs 32 are formed to connect to the RDLs 26. The RDLs 32 include metal traces (metal lines) located above the dielectric layer 28. The RDLs 32 also include vias extending into the openings 30 in the dielectric layer 28. The RDLs 32 can also be formed by a plating process, where each RDL 32 includes a seed layer (not shown) and a plated metal material located above the seed layer. According to some embodiments, the formation of the RDLs 32 may include: depositing a blanket metal seed layer extending into the via openings; and forming and patterning a plating mask (such as a photoresist), where the openings are formed directly above the via openings. Then, a plating process is performed to plate a metal material that completely fills the via openings 30 and has some portions higher than the top surface of the dielectric layer 28. Then, the plating mask is removed, followed by an etching process to remove the exposed portions of the metal seed layer previously covered by the plating mask. The remaining portions of the metal seed layer and the plated metal material are the RDLs 32.

[0027] The metal seed layer and the plating material can be formed of the same material or different materials. The metal material in the RDL 32 can include a metal or a metal alloy, and the metal or metal alloy includes copper, aluminum, tungsten, or an alloy thereof. The RDL 32 includes RDL lines (also referred to as traces or trace portions) 32L and via portions (also referred to as vias) 32V. Among them, the trace portion 32L is located above the dielectric layer 28, and the via portion 32V is located in the dielectric layer 28. Since the trace portion 32L and the via portion (also referred to as the via) 32V are formed in the same plating process, there is no distinguishable interface between the via 32V and the corresponding upper trace portion 32L. Moreover, each via 32V can have a tapered profile, where the upper part is wider than the corresponding lower part.

[0028] Reference Figure 3 , a dielectric layer 34 is formed above the RDL 32 and the dielectric layer 28. The dielectric layer 34 can be formed using a polymer, and the polymer can be selected from the same group of candidate materials as those of the dielectric layer 28. For example, the dielectric layer 34 can be formed of PBO, polyimide, BCB, etc. Optionally, the dielectric layer 34 can include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc.

[0029] Figure 3 The formation of the RDL36 electrically connected to the RDL 32 is also shown. The formation of the RDL36 can employ a method and materials similar to those used for forming the RDL 32. The RDL36 includes a trace portion (RDL line) 36L and a via portion (via) 36V. Among them, the trace portion 36L is located above the dielectric layer 34, and the via 36V extends into the dielectric layer 34. Moreover, each via 36V can have a tapered profile, where the upper part is wider than the corresponding lower part.

[0030] Figure 4 The formation of the dielectric layers 38 and 42 and the RDLs 40 and 44 is shown. According to some embodiments of the present invention, the dielectric layers 38 and 42 are formed of materials selected from the same group of candidate materials as those used for forming the dielectric layers 34 and 38, and can include the organic materials or inorganic materials as described above. It should be understood that although in the illustrated exemplary embodiments, the four dielectric layers 28, 34, 38, and 42 and the corresponding RDLs 32, 36, 40, and 44 formed therein are discussed as examples, fewer or more dielectric layers and RDL layers can be employed depending on the wiring requirements.

[0031] Figures 5 to 10 The formation of vias 56, conductive pads 58, and conductive bumps 60 ( Figure 10 ) is shown according to some embodiments. Reference Figure 5 , a dielectric layer 46 is formed. The corresponding process is shown as Figure 22Process 204 in the process flow 200 shown. According to some embodiments, the dielectric layer 46 is formed of a polymer that can be a photosensitive material such as PBO, polyimide, BCB, etc. The dielectric layer 46 is patterned to form via openings 48, thereby exposing the pad portions of the underlying RDL lines 44L. The corresponding process is shown as Figure 22 Process 206 in the process flow 200 shown. According to some embodiments, the via openings 48 are laterally offset from the corresponding underlying vias 44V. As Figure 5 shown, some vias 44V can be offset to the opposite side compared to the corresponding openings 48 with respect to the centerlines of the corresponding upper RDL lines 44L.

[0032] Refer to Figure 6 , a metal seed layer 51 is deposited. The corresponding process is shown as Figure 22 Process 208 in the process flow 200 shown. According to some embodiments, the metal seed layer 51 includes a titanium layer and a copper layer located above the titanium layer. According to an alternative embodiment, the metal seed layer 51 includes a single copper layer that physically contacts the dielectric layer 46. Then a plating mask 50 is formed and patterned, wherein openings 52 are formed in the plating mask 50. The corresponding process is shown as Figure 22 Process 210 in the process flow 200 shown. The via openings 48 are located below and coupled to the openings 52. The top view shape of the openings 52 can be irregular, for example, having the shape of a conductive pad 58 as Figure 15 shown.

[0033] Refer to Figure 7 , a metal material 54 is deposited through a plating process. The corresponding process is shown as Figure 22 Process 212 in the process flow 200 shown. The plating process can include electroless plating, electroplating, etc. According to some embodiments, the metal material 54 includes copper or a copper alloy. Process conditions can be adjusted such that the top surface of the plated material 54 can be flat. According to an alternative embodiment, the top surface portion of the metal material 54 can have a groove, as shown by the dashed line 53, which is formed due to the filling of the via openings 48( Figure 7 ).

[0034] In a subsequent process, the plating mask 50, which can be a photoresist, can be removed, for example, by an ashing process. The corresponding process is shown as Figure 22 Process 214 in the process flow 200 shown. Thus, portions of the underlying metal seed layer 51 are exposed.

[0035] Refer to Figure 8 , a plating mask 57 is formed on the metal seed layer 51 and the plated material 54 without removing the metal seed layer 51. The plating mask 57 has openings 52'. The corresponding process is shown as Figure 22Process 216 in the process flow 200 shown. Next, conductive bumps 60 are formed by a plating process which can be, for example, an electroplating process or an electroless plating process. The corresponding process is shown as Figure 22 Process 218 in the process flow 200 shown. The entire conductive bump 60 can be formed of a homogeneous material such as copper or a copper alloy. There may be a distinguishable interface between the conductive bump 60 and the underlying plating material 54, or the conductive bump 60 and the underlying plating material 54 may merge with each other (for example, when both are formed of copper), without a distinguishable interface therebetween. The conductive bumps 60 are also called metal pillars or metal rods due to their shape. For example, Figure 21 An exemplary conductive bump 60 having a circular top view shape is shown. Meanwhile, depending on the top view shape of the opening 52’, other shapes such as hexagon, octagon, etc. can also be adopted.

[0036] Figure 9 The deposition of a solder region 62 which is also deposited by plating according to some embodiments is also shown. The solder region 62 can be formed of or include AgSn, AgSnCu, SnPb, etc. According to an alternative embodiment, the solder region 62 is not formed.

[0037] In a subsequent process, the plating mask 57 is removed, for example, by ashing. The corresponding process is shown as Figure 22 Process 220 in the process flow 200 shown. Next, an etching process which can be a wet etching process or a dry etching process is performed to remove the exposed portion of the metal seed layer 51. The corresponding process is shown as Figure 22 Process 222 in the process flow 200 shown. The portion of the metal seed layer 51 directly under the plated metal material 54 is retained. Throughout the specification, the remaining portions of the metal material 54 and the underlying metal seed layer 51 are collectively referred to as via holes 56 (also called top via holes) and conductive pads 58. Figure 10 The resulting structure is shown. The via holes 56 are the portions located in the dielectric layer 46, while the conductive pads 58 are the portions located above the dielectric layer 46. Each via hole 56 and conductive pad 58 can include the remaining portion of the metal seed layer 51 and a portion of the plating material 54. The conductive bumps 60 are directly above the conductive pads 58 and are recessed laterally from the edge of the conductive pads 58. In other words, the conductive pads 58 have a larger top view size than the conductive bumps 60.

[0038] Throughout the specification, the structure located above the release film 22 is referred to as the interconnect assembly 64. In a subsequent process, the interconnect assembly 64 can be placed on a frame (not shown), where the solder region 62 adheres to the tape in the frame. Then, the interconnect assembly 64 is peeled off from the carrier 20, for example, by projecting UV light or a laser beam onto the release film 22, so that the release film 22 decomposes under the heat of the UV light or laser beam. The corresponding process is shown as Figure 22 process 224 in the process flow 200 shown. Thus, the interconnect assembly 64 is peeled off from the carrier 20. The resulting interconnect assembly 64 is shown in Figure 11 . In the resulting structure, the dielectric layer 24 can be exposed. If the solder region 62 is formed, it can be reflowed to have a circular surface.

[0039] Further referring to Figure 11 , an electrical connector 66 is formed to electrically connect to the RDL 26. According to some embodiments, the electrical connector 66 is a UBM. The formation process of the UBM 66 can also include: patterning the dielectric layer 24 to form an opening; depositing a metal seed layer that can include a titanium layer and a copper layer on the titanium layer; forming and patterning a plating mask; plating a conductive material; removing the plating mask, and etching the metal seed layer. According to other embodiments, the electrical connector 66 is a solder region, and the formation process can include patterning the dielectric layer 24 (e.g., by laser drilling) to form an opening, placing solder balls into the opening and performing a reflow process to reflow the solder region.

[0040] In a subsequent process, the interconnect assembly 64 is divided in a cutting process to form a plurality of identical interconnect assemblies 64' (also referred to as package assemblies 64'). The cutting process can be performed by dividing the interconnect assembly 64 along the scribe line 68.

[0041] The interconnect assembly 64' can be used to form a package. Figure 12 A portion of an exemplary structure including bonding the interconnect assembly 64' to a package assembly 70 is shown. According to some embodiments, the electrical connector 72 located on the surface of the package assembly 70 can be bonded to the interconnect assembly 64' through a solder region 74. The solder region 74 can include the solder region 62 as Figure 11 shown. The electrical connector 72 can be a UBM, a metal post, a bonding pad, etc. According to an alternative embodiment, the electrical connector 72 is a metal post and is bonded to the conductive bump 60 through a direct metal-to-metal bond. According to these embodiments, no solder region 62 is formed ( Figure 11) and the conductive bumps 60 are physically coupled to the electrical connector 72 by direct metal-to-metal bonding. According to some embodiments, underfill 76 is dispensed into the gap between the package assembly 70 and the interconnect assembly 64'. The underfill 76 contacts the sidewalls and the top surface of the extension of the conductive pad 58, and the extension extends laterally beyond the edge of the upper conductive bump 60. The dispensing can be a sealant 78 formed of or including a molding compound. A planarization process can be performed to make the top surface of the package assembly 70 flush with the top surface of the sealant 78.

[0042] Figure 13 The application of the interconnect assembly 64' is shown. Figure 12 The structure shown can also be Figure 13 a part of the structure shown. Each interconnect assembly 64' is bonded to one or more package assemblies 70 (including 70A and 70B as examples). Details of some structures such as an eccentric bonding structure are not shown in detail and are referred to Figure 13 and can be found in Figures 11 to 12 as well as Figures 14 to 18 According to some embodiments, the package assembly 70 includes a logic die that can be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller (MCU) die, an input / output (IO) die, a baseband (BB) die, an application processing (AP) die, etc. The package assembly 70 can also include memory dies such as dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc. The memory die can be a discrete memory die or can be a die stack in the form of a die stack including multiple stacked memory dies. The package assembly 70 can also include a system-on-chip (SOC) die.

[0043] According to some embodiments, the package assembly 70 includes a package assembly 70A that can be a logic die or an SOC die. According to some embodiments, the package assembly 70A includes a semiconductor substrate 71 and integrated circuit devices (not shown, such as including transistors). The package assembly 70 can also include a package assembly 70B that can be a memory die or a memory stack. The underfill 76 and the molding compound 78 are also shown.

[0044] The interconnect assembly 64' is also bonded to the package assembly 80. According to some embodiments, the package assembly 80 is or includes an interposer, a package substrate, a printed circuit board, etc. The bonding can be achieved through a solder region 82. The underfill 84 is dispensed between the interconnect assembly 64' and the package assembly 80.

[0045] Figure 14 and Figure 15 respectively show a cross-sectional view and a top view of a part of an eccentric structure according to some embodiments. The part shown is atFigure 12 in region 84A. According to some embodiments, the conductive bump 60 has a symmetric structure that can be rotationally symmetric, such as a cylinder. For example, Figure 15 shows that the conductive bump 60 can have a circular top view shape. The center (line) 60C of the conductive bump 60 is offset from the center (line) 58C of the conductive pad 58. According to other embodiments, the conductive bump 60 can have another symmetric top view shape selected from shapes including but not limited to hexagons, octagons, etc., which are also symmetric with respect to the center line 60C. The via 56 is offset from the center line 58C of the conductive pad 58, and the via 56 and the conductive bump 60 are offset from the center 58C of the conductive pad 58 in opposite directions. For example, the via 56 is Figure 14 and Figure 15 offset to the left in, while the center 60C of the conductive bump 60 is offset to the right. On the other hand, the via 44V is offset from the via 56. The vias 40V, 36V, and 32V can be vertically aligned with the via 44V or can be offset from the via 44V. Throughout the specification, since the center lines of the via 56 and the conductive bump 60 are not vertically aligned, the corresponding bonding structure is referred to as an eccentric bonding structure.

[0046] Referring to Figure 15 , the conductive pad 58 has a length L1 measured in the X direction. In the Y direction, the conductive pad 58 has a maximum width W1 that can be equal to or less than the length L1. The conductive pad 58 can be symmetric with respect to a line 61 extending in the X direction and passing through the center 58C, and can be asymmetric with respect to a line 61' extending in the Y direction and passing through the center 58C. For example, the left portion of the conductive pad 58 on the left side of the center 58C can be smaller than the right portion on the right side of the center 58C. For example, it can be considered that the shape of the conductive pad 58 is designed to start from a circle 88A (with the center as the center 60C) and cut out the outer portion of a secant line 88B. The secant lines 88B are not parallel to each other. Therefore, the conductive pad 58 has a flat top surface, a flat bottom surface, and four side walls between the top surface and the bottom surface. Two of the side walls are arc-shaped side walls, and the other two side walls are straight side walls (corresponding to the secant line 88B). The arc-shaped side walls and the straight side walls are arranged alternately. The top view of the conductive pad 58 has a water droplet shape. The edges of the conductive pad 58 can also have some edges with circular curves 88A (curved left edge and curved right edge). According to alternative embodiments, other shapes with one side wider than the other can also be used. For example, instead of having a straight secant line 88B as the edge of the conductive pad 58, a curve 88C can be used as the edge of the conductive pad 58 as an example.

[0047] In a conventional structure, the conductive bump 60 and the conductive pad 58 would be concentric, and the centerlines 58C and 60C would be in the same position, and the via 56 would be aligned with the centerline 60C. However, this creates problems. For example, the conductive bump 60, the conductive pad 58, and the vias 44V, 40V, and 36V are formed of a metal having a CTE value much larger than that of the surrounding materials such as the dielectric layers 46, 42, and 38, and the underfill 76. When the via 56, 44V (and possibly the vias 40V and 36V) are also aligned with the centerline 60C, there is high stress in the resulting structure, which may lead to delamination and trace breakage. To reduce stress, if the via 44V is laterally displaced (while the via 56 is aligned with the centerline 60C) to deviate from the conductive pad 58, the resulting structure will occupy a larger chip area.

[0048] According to an embodiment of the present invention, the via 56 is displaced from the centerline 58C and in a direction (left) opposite to the displacement direction (right) of the conductive bump 60. Accordingly, the stress applied from the conductive bump 60 to the via 56 is attenuated. In addition, the via 44V can be displaced from the via 56, so that the stress from the conductive bump 60 to the via 44V can be further reduced. For example, when the temperature increases and the conductive bump 60 applies a downward stress, since the via 56 is displaced from the conductive bump 60, part of the stress is attenuated by the conductive pad 58. Due to the flexibility of the RDL line 44L, the stress is further attenuated before being transferred to the via 44V.

[0049] Referring again to Figure 14 , according to some embodiments, the via 56 is displaced from the centerline 58C of the conductive pad 58 by a pitch S1. The displacement pitch S1 can be equal to or greater than about 8.5 μm and can be in the range between about 8.5 μm and about 20 μm. In addition, it is desirable that the via 56 at least partially overlaps with the conductive bump 60. For example, Figure 14 shows that the right side portion of the via 56 overlaps with the conductive bump 60, while the left side portion of the via 56 extends beyond the left edge of the conductive bump 60. The (at least partial) overlap of the conductive bump 60 is beneficial to allow the via 56 to support both the conductive pad 58 and the conductive bump 60 and receive part (but not all) of the force transmitted from the conductive bump 60. This also allows the RDL line 44L to absorb a sufficient amount of stress.

[0050] According to an alternative embodiment, as Figure 15 shown, the via 56 can be slightly displaced to the right to the position shown as 55, so that the entire via 56 overlaps with the conductive bump 60. For example, according to some embodiments, the left edge of the via 56 can be aligned with (or displaced to the right of) the left edge of the conductive bump 60. According to an alternative embodiment, for example, when in as Figure 15When forming the through hole 56 at the indicated position 55', the through hole 56 is completely offset from the conductive bump 60.

[0051] In addition, as Figure 14 and Figure 15 shown, the through hole 56 is offset from the center 60C and is offset to the left of the center 58C or aligned with the center 58C. It can be recognized from Figure 15 that increasing the size of the conductive pad 58 to be larger than the size of the conductive bump 60 allows the through hole 56 to be offset by a desired distance. On the other hand, reducing the size of the left portion of the conductive pad 58 can avoid unnecessarily increasing the size of the unwanted conductive pad 58.

[0052] According to some embodiments, the through holes 56 and 44V are on opposite sides of the center line 58C, and neither the through hole 56 nor the through hole 44V has any part passing through the center line 58C. The offset of the through holes 56 and 44 from the center line 58C in opposite directions can result in an increase in the distance between the through holes 56 and 44V and an increase in the length of the portion of the RDL line 44L that interconnects the through holes 56 and 44V. This can also improve the stress absorption ability of the RDL line 44L. On the other hand, the through hole 44V can completely overlap with the conductive bump 60, so that the through hole 44V will not occupy additional chip area (unless for reasons of signal rerouting), because it occupies the same chip area as the conductive pad 58 and the conductive bump 60.

[0053] According to some embodiments, the through holes 40V, 36V, and / or 32V are vertically aligned with the through hole 44V. According to alternative embodiments, each or all of the through holes 40V, 36V, and / or 32V can be laterally offset to the left or right from the through hole 44V.

[0054] Referring back to Figure 15 , some dimensions are marked. According to some embodiments, when viewed from a top view, the lateral spacing S2 between the center line 60C and the edge of the through hole 56 can be in the range of about 4 μm and about 12 μm. The diameter Dia58 of the conductive pad 58 can be in the range of about 30 μm and 50 μm. The diameter Dia60 of the conductive bump 60 can be in the range of about 20 μm and 40 μm. The spacing S3 between the conductive bump 60 and the right edge of the conductive pad 58 can be in the range of about 2 μm and about 4 μm.

[0055] Figure 16Shows a top view of the RDL line 44L according to some embodiments. The RDL line 44L has a length L2, and the widths W2 and W3 are less than the length L2. The width W3 is the width of the narrower middle portion of the RDL line 44L, and the width W3 is less than the width W2 of the wider portion on the opposite side of the narrower portion. According to some embodiments, the width W3 is less than about 0.9W2 and can be in the range between about 0.6W2 and about 0.9W2. The shape of the RDL line 44L can sometimes be referred to as a dogbone shape. The vias 56 and 44V can be respectively aligned with the centers of the left and right portions of the RDL line 44L. Reducing the width W3 to be less than the width W2 can improve the flexibility of the RDL line 44L and thus improve its ability to absorb stress.

[0056] Figure 17 and Figure 18 Respectively show a cross-sectional view and a top view of a part of an eccentric structure according to alternative embodiments. The shown part is in the Figure 12 region 84B in. These embodiments are similar to the embodiments shown in Figure 14 and Figure 15 except that the via 44V is aligned with the center line 60C of the conductive bump 60. Each or all of the vias 40V, 36V, and 32V can be vertically aligned with the via 44V or laterally deviated from the via 44V to the left or right. When the spacing between the vias 56 and 44V is already large enough to provide sufficient stress absorption, for example, when approaching saturation and further increasing the spacing does not result in a significant reduction in stress, these embodiments can be employed. Compared with the structure shown in Figure 14 , in the case where the via 44V (as well as the vias 40V and 36V) is offset to the left side, wiring for other RDLs (such as the RDL lines 44A, 40A, 36A, etc.) can be provided on the right side of the chip area.

[0057] Figure 19 Shows a top view of the RDL line 44L and the vias 56 and 44V corresponding to the structure shown in Figure 17 and Figure 18 . In order to align with the center 60C, it is shown that the via 44V can be offset to the left from the center of the right portion of the RDL line 44L.

[0058] Figure 20 and Figure 21 Show two structures on which simulations are performed. Figure 20 The structure shown in represents a conventional structure with vertically aligned conductive bumps 60’, vias 56’, RDL pads 44L’, and vias 44V’. Figure 21The structure shown in [Figure] represents a structure having conductive bumps 60, conductive pads 58, vias 56, RDL lines 44L, and vias 44V formed according to some embodiments of the present invention. The via 56 is offset from the centerlines of the conductive bump 60 and the conductive pad 58. The via 44V is offset from the via 56. The conductive pad 58 has a wider side and a narrower side. Simulation results show that when the stress applied to the RDL line 40L’ ( Figure 20 ) has a normalized magnitude of 1.0, the stress applied to the RDL line 40L ( Figure 21 ) has a normalized magnitude of 0.87, which means that the embodiments of the present invention have a 13% reduced stress compared to traditional structures.

[0059] In the exemplary embodiments provided above, an eccentric bonding structure is formed in the build-up substrate. According to an alternative embodiment, the eccentric bonding structure can be formed in an interposer that can include a semiconductor substrate and through-holes in the semiconductor substrate. For example, when forming the RDL for the interposer after backside polishing to expose the through-holes, the eccentric bonding structure can be formed as part of the RDL structure of the interposer. According to some other alternative embodiments, the eccentric bonding structure can be formed in a chip-on-wafer-on-substrate (CoWoS) package, where the eccentric bonding structure can be formed in one or both of the wafer and the package substrate. According to some other alternative embodiments, the eccentric bonding structure can be formed in a fan-out package, where the eccentric bonding structure can be formed in the fan-out RDL that is formed after molding of the device die.

[0060] In the embodiments shown above, some processes and components for forming three-dimensional (3D) packages are discussed according to some embodiments of the present invention. Other components and processes can also be included. For example, test structures can be included to assist in the verification testing of 3D packages or 3DIC devices. For example, the test structure can include test pads formed in the redistribution layer or on the substrate to allow testing of the 3D package or 3DIC using a probe and / or probe card, etc. Verification testing can be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein can be used in combination with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0061] Embodiments of the present invention have some advantageous features. By forming an eccentric bonding structure and conductive bumps, and the conductive pad having a narrower side and a wider side, and further by forming eccentric vias, the stress in the bonding structure and surrounding components is reduced. The reduction in stress does not cause an increase in manufacturing cost and does not cause a loss of chip area.

[0062] According to some embodiments of the present invention, the method includes forming a first dielectric layer; forming a first redistribution line, the first redistribution line including a first via hole extending into the first dielectric layer and a first trace located above the first dielectric layer; forming a second dielectric layer covering the first redistribution line; patterning the second dielectric layer to form a via hole opening, wherein the first redistribution line is exposed through the via hole opening; forming a second via hole in the second dielectric layer, and forming a conductive pad in contact with the second via hole above the second via hole; and forming a conductive bump above the conductive pad, wherein the conductive pad is larger than the conductive bump, and a first center of the conductive pad is offset from a second center of the conductive bump, and wherein the second via hole is offset further from the second center of the conductive bump. In an embodiment, the second via hole and the conductive pad are formed by a common plating process. In an embodiment, the second via hole, the conductive pad, and the conductive bump are formed using the same metal seed layer. In an embodiment, the method further includes bonding a package component above the conductive bump; and dispensing underfill, wherein the underfill contacts a first sidewall of the conductive bump, and the underfill also contacts a top surface and a second sidewall of the conductive pad. In an embodiment, the second via hole includes a first portion overlapping the conductive bump and a second portion extending beyond a corresponding edge of the conductive bump. In an embodiment, the conductive pad includes a first portion and a second portion located on opposite sides of a first center of the conductive pad, and wherein the first portion is narrower than the second portion. In an embodiment, the second center of the second via hole and the conductive bump is located on an opposite side of the first center of the conductive pad. In an embodiment, the first via hole and the second via hole are located on opposite sides of the first center of the conductive pad.

[0063] According to some embodiments of the present invention, a structure includes a first dielectric layer; a first via extending into the first dielectric layer; a conductive trace located above the first dielectric layer, wherein the conductive trace is located above the first via and coupled to the first via; a second dielectric layer covering the conductive trace; a second via located in the second dielectric layer; a conductive pad located above the second via and in contact with the second via; wherein the conductive pad has a first center; and a conductive bump located above the conductive pad and in contact with the conductive pad, wherein the conductive bump has a second center, and wherein the second via and the second center of the conductive bump are located on opposite sides of the first center of the conductive pad. In an embodiment, the conductive bump has a circular top view shape, and the conductive pad extends beyond a first edge of the conductive bump by a first distance in a first direction and extends beyond a second edge of the conductive bump by a second distance less than the first distance in a second direction, wherein the first direction and the second direction are opposite directions starting from the second center. In an embodiment, the second via has a first portion overlapping with the conductive bump. In an embodiment, the second via further includes a second portion extending beyond an edge of the conductive bump. In an embodiment, the first via is aligned with the second center of the conductive bump. In an embodiment, the first via is offset from the second center of the conductive bump. In an embodiment, the conductive trace has a length and a width less than the length, and wherein a width of a middle portion of the conductive trace is narrower than widths of portions of the conductive trace located on opposite sides of the middle portion.

[0064] According to some embodiments of the present invention, a structure includes a plurality of dielectric layers; a plurality of redistribution lines located in the plurality of dielectric layers, wherein each of the plurality of redistribution lines includes a via and a trace located above the via and in contact with the via, and some of the vias in the plurality of redistribution lines are stacked to form a via stack, and the vias are vertically aligned; a top via located above and in contact with a top trace of a top redistribution line among the plurality of redistribution lines; a conductive pad located above the top via and in contact with the top via; and a conductive bump located above the conductive pad and coupled to the conductive pad, wherein the conductive bump and the top via are eccentric, and wherein the conductive pad includes a first portion extending beyond a first edge of the conductive bump by a first distance and a second portion extending beyond a second edge of the conductive bump by a second distance less than the first distance, wherein the first portion is narrower than the second portion. In an embodiment, the first portion includes two straight edges; and a curved edge located between the two straight edges and connected to the two straight edges. In an embodiment, the top via and the conductive bump are offset in opposite directions toward a center of the conductive pad. In an embodiment, the top via and the conductive bump partially overlap. In an embodiment, the structure further includes a bottom filler in contact with a first sidewall of the conductive bump, a top surface of the conductive pad, and a second sidewall of the conductive pad.

[0065] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor structure, comprising: Forming a first dielectric layer; Forming a first redistribution line, the first redistribution line including a first via hole extending into the first dielectric layer and a first trace located above the first dielectric layer; Forming a second dielectric layer covering the first redistribution line; Patterning the second dielectric layer to form a via opening, wherein the first redistribution line is exposed through the via opening; Forming a second via hole in the second dielectric layer and forming a conductive pad contacting the second via hole above the second via hole; and Forming a conductive bump above the conductive pad, wherein the conductive pad is larger than the conductive bump, and a first center of the conductive pad is offset from a second center of the conductive bump, and wherein the second via hole is offset further from the second center of the conductive bump, wherein the conductive pad includes a first portion and a second portion having a convex shape, and wherein, in a top view of the conductive pad, any straight line connecting any two points within the convex shape is entirely located within the convex shape, the first portion and the second portion are located on opposite sides of the first center of the conductive pad, and wherein the first portion is narrower than the second portion, the second via hole and the second center of the conductive bump are located on opposite sides of the first center of the conductive pad, the second via hole is on one side of the first portion, and the second center of the conductive bump is on one side of the second portion, wherein the conductive pad has a flat top surface, a flat bottom surface, and four sidewalls between the top surface and the bottom surface, in a top view of the conductive pad, two of the four sidewalls are arcuate sidewalls, and the other two sidewalls are straight sidewalls, and wherein the arcuate sidewalls and the straight sidewalls are alternately arranged.

2. The method according to claim 1, wherein, The second via hole and the conductive pad are formed by a common plating process.

3. The method according to claim 1, wherein The second via hole, the conductive pad, and the conductive bump are formed using the same metal seed layer.

4. The method according to claim 1, further comprising: Bonding a package component above the conductive bump; And Dispensing underfill, wherein the underfill contacts a first sidewall of the conductive bump, and the underfill also contacts the top surface and a second sidewall of the conductive pad.

5. The method according to claim 1, wherein, The second via hole includes a first portion overlapping the conductive bump and a second portion extending beyond a corresponding edge of the conductive bump.

6. The method according to claim 1, wherein, The second via hole has a tapered profile.

7. The method according to claim 1, wherein The conductive bump has a circular top view shape.

8. The method according to claim 1, wherein, The first via hole and the second via hole are located on opposite sides of the first center of the conductive pad.

9. A semiconductor structure, comprising: A first dielectric layer; A first via hole extending into the first dielectric layer; A conductive trace located above the first dielectric layer, wherein the conductive trace is located above the first via hole and is bonded to the first via hole; A second dielectric layer covering the conductive trace; A second via hole located in the second dielectric layer; A conductive pad is located above and in contact with the second through hole; wherein, the conductive pad has a first center; and A conductive bump is located above and in contact with the conductive pad, wherein the conductive bump has a second center, and wherein the second through hole and the second center of the conductive bump are located on opposite sides of the first center of the conductive pad, wherein the conductive pad includes a first part and a second part having a convex shape, and wherein, in a top view of the conductive pad, any straight line connecting any two points within the convex shape is entirely within the convex shape, the first part and the second part are located on opposite sides of the first center of the conductive pad, and wherein the first part is narrower than the second part, the second through hole and the second center of the conductive bump are located on opposite sides of the first center of the conductive pad, the second through hole is on one side of the first part, and the second center of the conductive bump is on one side of the second part, wherein the conductive pad has a flat top surface, a flat bottom surface, and four side walls between the top surface and the bottom surface, in a top view of the conductive pad, two of the four side walls are arcuate side walls, and the other two side walls are straight side walls, and wherein the arcuate side walls and the straight side walls are arranged alternately.

10. The semiconductor structure according to claim 9, wherein, The conductive bump has a circular top view shape, and the conductive pad extends beyond a first edge of the conductive bump in a first direction to a first distance, and extends beyond a second edge of the conductive bump in a second direction to a second distance less than the first distance, wherein the first direction and the second direction are opposite directions starting from the second center.

11. The semiconductor structure according to claim 9, wherein, The second through hole has a first part that overlaps with the conductive bump.

12. The semiconductor structure according to claim 11, wherein, The second through hole further includes a second part that extends beyond the edge of the conductive bump.

13. The semiconductor structure according to claim 9, wherein, The first through hole is aligned with the second center of the conductive bump.

14. The semiconductor structure according to claim 9, wherein, The first through hole is offset from the second center of the conductive bump.

15. The semiconductor structure according to claim 14, wherein, The conductive trace has a length and a width less than the length, and wherein the width of the middle part of the conductive trace is narrower than the width of the parts of the conductive trace located on opposite sides of the middle part.

16. A semiconductor structure, comprising: A plurality of dielectric layers; A plurality of redistribution lines located in the plurality of dielectric layers, wherein each of the plurality of redistribution lines includes a through hole and a trace located above and in contact with the through hole, and some of the through holes of the plurality of redistribution lines are stacked to form a through hole stack, wherein the through holes are vertically aligned; A top through hole is located above and in contact with the top trace of the top redistribution line among the plurality of redistribution lines; A conductive pad is located above and in contact with the top through hole; and A conductive bump is located above and bonded to the conductive pad, wherein the conductive bump and the top through hole are eccentric, and wherein the conductive pad includes: A first portion extending beyond a first edge of the conductive bump by a first distance, and a second portion extending beyond a second edge of the conductive bump by a second distance less than the first distance, wherein the first and second portions of the conductive pad have a convex shape, and wherein, in a top view of the conductive pad, any straight line connecting any two points within the convex shape lies entirely within the convex shape, the first and second portions are located on opposite sides of a first center of the conductive pad, and wherein the first portion is narrower than the second portion, a second center of the top via and the conductive bump are located on opposite sides of the first center of the conductive pad, the top via is on one side of the first portion, and the second center of the conductive bump is on one side of the second portion, wherein the conductive pad has a flat top surface, a flat bottom surface, and four sidewalls between the top and bottom surfaces, in a top view of the conductive pad, two of the four sidewalls are arcuate sidewalls, and the other two sidewalls are straight sidewalls, and wherein the arcuate sidewalls and the straight sidewalls are arranged alternately.

17. The semiconductor structure according to claim 16, wherein, The top via has a tapered profile.

18. The semiconductor structure according to claim 16, wherein, The conductive bump has a circular top view shape.

19. The semiconductor structure according to claim 16, wherein, The top via and the conductive bump partially overlap.

20. The semiconductor structure according to claim 16, further comprising an underfill contacting a first sidewall of the conductive bump and second sidewalls and a top surface of the conductive pad.

Images