Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package device and a manufacturing method thereof. The semiconductor package device includes a substrate having opposite first and second surfaces, a first portion and a second portion, wherein the Young's modulus of the first portion is greater than the Young's modulus of the second portion; a chip embedded in the second portion, the first portion is disposed between the chip and the first surface, and the second portion is disposed between the first portion and the second surface. By the difference of the Young's modulus between the first portion and the second portion, the chip embedded in the second portion can release stress on the side away from the first portion, thereby reducing the risk of chip rupture caused by stress accumulation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular, to a semiconductor packaging device and a manufacturing method thereof. BACKGROUND

[0002] In the current semiconductor packaging technology, the embedding of components is usually achieved by utilizing the material properties of the dielectric layer above and below the adjacent components, or adjusting the thickness or coverage of the copper layer and the solder resist, so as to achieve the requirement of suppressing the warpage of the semiconductor packaging device. However, the coefficients of thermal expansion of the dielectric layers above and below the adjacent components may still have differences, although the overall appearance is not easy to appear obvious warpage, but it will still cause stress to the embedded components, and thus the embedded components are broken, reducing the product yield and reliability. SUMMARY

[0003] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0004] a substrate having opposite first and second surfaces, a first portion and a second portion, wherein the Young's modulus of the first portion is greater than the Young's modulus of the second portion;

[0005] a chip embedded in the second portion, the first portion is arranged between the chip and the first surface, and the second portion is arranged between the first portion and the second surface.

[0006] In some optional embodiments, the first portion comprises a first sub-substrate and a first adhesive layer arranged on the lower surface of the first sub-substrate.

[0007] In some optional embodiments, the second portion is a second adhesive layer.

[0008] In some optional embodiments, the first adhesive layer and the second adhesive layer are integrally formed.

[0009] In some optional embodiments, the substrate further comprises:

[0010] a third portion arranged around the second portion, the Young's modulus of the third portion being greater than the Young's modulus of the second portion.

[0011] In some optional embodiments, the third portion is a second sub-substrate.

[0012] In some optional embodiments, the substrate further comprises:

[0013] a first circuit layer arranged on the first surface and electrically connected to the chip.

[0014] In some optional embodiments, the substrate further comprises:

[0015] A second circuit layer is disposed on the second surface and electrically connected to the first circuit layer.

[0016] In some optional embodiments, the first sub-base plate is electrically connected to the chip through the second sub-base plate.

[0017] In some optional embodiments, the first sub-base plate is a redistribution layer.

[0018] In some optional embodiments, the second sub-base plate is a fan-out circuit layer or a fan-in and fan-out hybrid circuit layer.

[0019] In some optional embodiments, the device further comprises:

[0020] A first pad is disposed on the first surface, and the first pad is electrically connected to the first sub-base plate.

[0021] In some optional embodiments, the device further comprises:

[0022] A second pad is disposed on the second surface, and the second pad is electrically connected to the second sub-base plate.

[0023] In some optional embodiments, the device further comprises:

[0024] A solder bump is disposed on the second surface, and the solder bump is electrically connected to the second sub-base plate.

[0025] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0026] providing a second sub-base plate structure having a receiving cavity extending through the second sub-base plate structure;

[0027] providing a carrier plate having a second circuit layer formed thereon;

[0028] disposing the second sub-base plate structure on the carrier plate;

[0029] electrically connecting the second sub-base plate structure and the second circuit layer to form a second sub-base plate;

[0030] disposing a chip in the receiving cavity;

[0031] disposing an adhesive layer on the second sub-base plate such that the adhesive layer is disposed in the receiving cavity and covers the chip; and disposing a first sub-base plate on the adhesive layer, wherein an upper surface of the first sub-base plate has a first circuit layer, and the first circuit layer is electrically connected to the chip and the second circuit layer.

[0032] removing the carrier plate.

[0033] In some optional embodiments, the method further comprises:

[0034] corresponding first pads and second pads are respectively formed on the first circuit layer and the second circuit layer, wherein the first pads are electrically connected to the first sub- substrate, and the second pads are electrically connected to the second sub- substrate.

[0035] In the semiconductor package device and the manufacturing method thereof provided by the present disclosure, the semiconductor package device is designed to include a substrate having opposite first and second surfaces, a first portion and a second portion, wherein the Young's modulus of the first portion is greater than that of the second portion; and a chip embedded in the second portion, the first portion is arranged between the chip and the first surface, and the second portion is arranged between the first portion and the second surface. The chip is embedded in the second portion, and since the first portion is arranged on one side of the chip and the Young's modulus of the second portion is less than that of the first portion, when the semiconductor package device generates stress, the stress acting on the chip from the first portion can be transmitted to the side of the chip away from the first portion, so that the side of the chip away from the first portion can release the stress, thereby reducing the risk of chip rupture caused by stress accumulation and improving the yield of the semiconductor package device. BRIEF DESCRIPTION OF DRAWINGS

[0036] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1A is a longitudinal cross-sectional structure schematic diagram of different embodiments of the semiconductor package device according to the present disclosure;

[0038] Figure 1A is a dimension marking schematic diagram of each main structure of the semiconductor package device of FIG. 1;

[0039] Figures 2A-2E is a structure schematic diagram of different embodiments of the semiconductor package device according to the present disclosure;

[0040] Figures 3A-3G is a cross-sectional view of the semiconductor package device manufactured at each stage according to one embodiment of the present disclosure.

[0041] SYMBOL EXPLANATION:

[0042] 1 - first portion; 2 - second portion; 3 - third portion; 11 - substrate; 11a - first surface; 11b - second surface; 113 - first sub-substrate; 1131 - first sub-substrate structure; 1132 - first circuit layer; 114 - second sub-substrate; 1141 - second sub-substrate structure; 1142 - second circuit layer; 115 - first adhesive layer; 116 - second adhesive layer; 117 - receiving cavity; 118 - adhesive material; 12 - chip; 13 - first solder resist layer; 14 - first pad; 15 - second solder resist layer; 16 - second pad; 17 - solder bump; 21 puncher; 22 - carrier board; 23 - press-fit; U - semiconductor package width; Dt - top dielectric layer thickness; At - adhesive layer thickness; Pt - bottom dielectric layer thickness; Tt - semiconductor package thickness; g - gap width between chip and receiving cavity; s - chip width; c - receiving cavity width; t - chip thickness. DETAILED DESCRIPTION

[0043] The specific embodiments of the present disclosure will be described below with reference to the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects generated by the content recorded in the specification. It should be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0044] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions that the present disclosure can be implemented, and therefore do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects that the present disclosure can produce and the purposes that the present disclosure can achieve, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and are not used to limit the scope of the present disclosure, and the change or adjustment of the relative relationship without substantially changing the technical content should also be considered as the scope of the present disclosure.

[0045] It should also be noted that the embodiments of the present disclosure correspond to the longitudinal cross-section in the front view direction, the transverse cross-section in the right view direction, and the horizontal cross-section in the upper view direction.

[0046] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0047] Reference Figure 1A , Figure 1AThis is a longitudinal cross-sectional structural schematic diagram of one embodiment of the semiconductor packaging apparatus according to the present disclosure.

[0048] like Figure 1A As shown, the semiconductor packaging device 100a includes: a substrate 11 and a chip 12. Wherein:

[0049] The substrate 11 has a first surface 11a and a second surface 11b, a first portion 1 and a second portion 2, wherein the Young's modulus of the first portion 1 is greater than the Young's modulus of the second portion 2.

[0050] The substrate 11 can be a substrate composed of conductive and dielectric materials. Here, the dielectric material can include organic and / or inorganic materials, wherein organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylenebenzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0051] Chip 12 is embedded in the second part 2, the first part 1 is disposed between chip 12 and the first surface 11a, and the second part 2 is disposed between the first part 1 and the second surface 11b.

[0052] Optionally, the passive surface of chip 12 is exposed on the surface of the second part 2.

[0053] This disclosure does not specifically limit the type of chip 12. For example, chip 12 may include a die, an ASIC (Application Specific Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip.

[0054] The technical effects that the semiconductor packaging apparatus 100a of the above embodiments provided in this disclosure can achieve include, but are not limited to: embedding the chip 12 in the second part 2, the first part 1 being disposed on one side of the chip 12, and the Young's modulus of the second part 2 being less than that of the first part 1, so that the stress acting on the chip 12 can be transmitted to the side away from the first part 1, reducing the stress acting on the chip 12, thereby reducing the risk of chip 12 breaking.

[0055] In some alternative implementations, such as Figure 1A As shown, the first part 1 includes a first sub-substrate 113 and a first adhesive layer 115 disposed on the lower surface of the first sub-substrate 113.

[0056] The second part 2 can be the second adhesive layer 116.

[0057] Here, the first sub-substrate 113 can be a substrate composed of conductive material and dielectric material.

[0058] The first adhesive layer 115 and the second adhesive layer 116 may include liquid and / or thin-film organic materials, such as: non-conductive plastic (NCP), non-conductive film (NCF), anisotropic conductive adhesive film (ACF), anisotropic conductive adhesive plastic (ACP), PI, epoxy, resin, PP, ABF, glue, etc. This is merely an example of the materials used in the first adhesive layer 115 and the second adhesive layer 116, and not a specific limitation.

[0059] In some alternative embodiments, the first adhesive layer 115 and the second adhesive layer 116 are integrally formed.

[0060] For example, in the process of manufacturing a semiconductor packaging device, a first adhesive layer 115 and a second adhesive layer 116 are formed by pressing adhesive materials together.

[0061] After the first adhesive layer 115 and the second adhesive layer 116 are cured, they can limit the position of the chip 12.

[0062] In some alternative implementations, such as Figure 1A As shown, the substrate 11 may further include:

[0063] Part 3 is set around Part 2, and the Young's modulus of Part 3 is greater than that of Part 2.

[0064] Since the Young's modulus of the third part 3 is greater than that of the second part 2, the third part 3 can improve the overall strength of the substrate 11.

[0065] In some alternative implementations, such as Figure 1A As shown, the third part 3 can be the second sub-substrate 114.

[0066] Here, the second sub-substrate 114 can be a substrate composed of conductive material and dielectric material.

[0067] In some alternative implementations, such as Figure 1A As shown, the second sub-substrate 114 is provided with a receiving cavity 117, the chip 12 is disposed in the receiving cavity 117, and the second adhesive layer 16 is disposed in the gap between the chip 12 and the receiving cavity 117.

[0068] In some alternative implementations, such as Figure 1A As shown, the substrate 11 may further include: a first circuit layer 1132 and a second circuit layer 1142. Wherein:

[0069] The first circuit layer 1132 is disposed on the first surface 11a and is electrically connected to the chip 12.

[0070] The second circuit layer 1142 is disposed on the second surface 11b and is electrically connected to the first circuit layer 1132.

[0071] The first circuit layer 1132 and the second circuit layer 1142 may include conductive traces composed of conductive materials. Here, the conductive materials may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0072] In some alternative implementations, such as Figure 1A As shown, the semiconductor packaging device 100a may further include a first pad 14. The first pad 14 is disposed on the first surface 11a and is electrically connected to the first sub-substrate 113.

[0073] Here, the first pad 14 may be formed by providing a first solder mask layer 13 on the first surface 11a, so that a portion of the first circuit layer 1132 is exposed through the first solder mask layer 13.

[0074] In some alternative implementations, such as Figure 1A As shown, the semiconductor packaging device 100a may further include a second pad 16. The second pad 16 is disposed on the second surface 11b and is electrically connected to the second sub-substrate 114.

[0075] Here, the second pad 16 may be formed by providing a second solder mask layer 15 on the second surface 11b, so that a portion of the second circuit layer 1142 is exposed through the second solder mask layer 15.

[0076] Chip 12 can be electrically connected to the outside world via the first pad 14 and / or the second pad 16.

[0077] Continue to refer to Figure 1B , Figure 1B It shows Figure 1A The dimensions of the main structures of the semiconductor packaging device 100a are marked as follows:

[0078] U is the width of semiconductor packaging device 100a, where 10mm ≤ U ≤ 100mm;

[0079] Dt is the dielectric layer thickness of the first sub-substrate 113, 3um≤Dt≤20um;

[0080] At is the thickness of the first adhesive layer 115, 3um≤At≤30um;

[0081] Pt is the dielectric layer thickness of the second sub-substrate 114, 100um≤Pt≤500um;

[0082] Tt is the thickness of the semiconductor packaging device 100a, where 0.1mm ≤ Tt ≤ 0.5mm;

[0083] g is the gap width between chip 12 and cavity 117, 2um≤g≤20um;

[0084] c is the width of the cavity 117;

[0085] s is the width of chip 12, 5mm≤s≤40mm, 0.3≤s / c≤1;

[0086] t is the thickness of chip 12, 50um≤t≤700um, 0.3≤t / h≤1;

[0087] 0.1≤Number of I / O (Input-Output) of semiconductor package device 100a≤20.

[0088] Where mm stands for millimeter and um stands for micrometer.

[0089] Continue to refer to Figure 2A , Figure 2A The semiconductor packaging device 200a shown is similar to Figure 1AThe semiconductor packaging device 100a shown differs in that, in the semiconductor packaging device 200a, the second adhesive layer 116 is disposed at the edge of the substrate 11. In this disclosure, the second adhesive layer 116 can be disposed at the edge of the substrate 11 or inside the substrate 11, as long as the second adhesive layer 116 can cover the chip 12.

[0090] Continue to refer to Figure 2B , Figure 2B The semiconductor packaging device 200b shown is similar to Figure 1A The semiconductor packaging device 100a shown is different in that, in the semiconductor packaging device 200b, the first sub-substrate 113 is electrically connected to the chip 12 through the second sub-substrate 114.

[0091] According to the design requirements of the actual semiconductor packaging device, the active surface of the chip 12 can be set facing the first surface 11a, or the active surface of the chip 12 can also be set facing the second surface 11b. Correspondingly, the chip 12 can be electrically connected to the first sub-substrate 113, or the chip 12 can be electrically connected to the second sub-substrate 114.

[0092] Continue to refer to Figure 2C , Figure 2C The semiconductor packaging device 200c shown is similar to Figure 1AThe semiconductor packaging device 100a shown differs in that, in the semiconductor packaging device 200c, the first sub-substrate 113 can be a redistribution layer (RDL) composed of conductive traces and dielectric material. It should be noted that the redistribution layer formation technology can be either currently known or developed in the future, and this application does not impose specific limitations on it. For example, it can be formed using methods including but not limited to photolithography, electroplating, and electroless plating. Here, the dielectric material may include organic and / or inorganic materials, wherein organic materials may include, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may include, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may include, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0093] Continue to refer to Figure 2D , Figure 2D The semiconductor packaging device 200d shown is similar to Figure 1A The semiconductor packaging device 100a shown differs in that the semiconductor packaging device 200d also includes a solder bump 17.

[0094] Solder bumps 17 are disposed on the second surface 11b and are electrically connected to the second sub-substrate 114. The second surface 11b can be electrically connected to the outside world through the solder bumps 17.

[0095] Continue to refer to Figure 2E , Figure 2E The semiconductor packaging device 200e shown is similar to Figure 1A The semiconductor packaging device 100a shown differs from the semiconductor packaging device 200e in that the second sub-substrate 114 can be a fan-out circuit layer or a fan-in / fan-out hybrid circuit layer composed of conductive traces and dielectric material.

[0096] The following is for reference. Figures 3A to 3G ,Figure 3A , 3B 3C, 3D, 3E, 3F and 3G are schematic diagrams of longitudinal cross-sectional structures of semiconductor packaging devices 300a, 300b, 300c, 300d, 300e, 300f and 300g manufactured at various stages according to an embodiment of the present disclosure.

[0097] refer to Figure 3A A substrate is provided, and a receiving cavity 117 is formed on the substrate to form a second sub-substrate structure 1141.

[0098] The cavity 117 penetrates the second sub-substrate structure 1141.

[0099] Here, receiving walls 117 can be formed on the substrate using techniques such as mechanical drilling, photolithography, perforation, or similar methods. Figure 3A As shown, in some embodiments of this disclosure, a punch 21 is used to punch a receiving cavity 1141 on a substrate.

[0100] refer to Figure 3B A carrier board 22 is provided, on which a second circuit layer 1142 is formed.

[0101] refer to Figure 3C The second sub-substrate structure 1141 is disposed on the carrier plate 22.

[0102] Then, the second sub-substrate structure 1141 and the second circuit layer 1142 are electrically connected to form the second sub-substrate 114.

[0103] Here, electrical connection can be achieved by forming vias between the second sub-substrate structure 1141 and the second circuit layer 1142. Vias can be formed by laser or mechanical means, and a conductive layer can be formed within the vias. The conductive layer within the vias can be formed using techniques such as electroplating, electroless plating, or similar methods.

[0104] Finally, chip 12 is placed inside receiving cavity 117.

[0105] like Figure 3C As shown, the passive side of the chip 12 is placed in the receiving cavity 117 with the carrier plate 22 facing it.

[0106] refer to Figure 3D It provides an adhesive material 118 and a first sub-substrate structure 1131.

[0107] refer to Figure 3E The first sub-substrate structure 1131, the adhesive material 118, and the second sub-substrate 114 are pressed together accordingly.

[0108] After lamination, adhesive material 118 is disposed on the second sub-substrate 114, and part of adhesive material 118 is disposed in the receiving cavity 117 and covers the chip 12 to form the second adhesive layer 116.

[0109] A portion of the adhesive material 118 is disposed between the first sub-substrate structure 1131 and the chip 12 to form a first adhesive layer 115.

[0110] refer to Figure 3F A first circuit layer 1132 is disposed on the first sub-substrate structure 1131 to form the first sub-substrate 113.

[0111] Furthermore, the first circuit layer 1132 and 12 are electrically connected, and the first circuit layer 1132 is electrically connected to the second sub-substrate 114.

[0112] Finally, the semiconductor packaging device is inverted and the carrier plate 22 is removed. In actual manufacturing processes, the package can be flipped as needed; no specific limitation is made here.

[0113] refer to Figure 3G A first pad 14 and a second pad 16 are respectively formed on the first circuit layer 1132 and the second circuit layer 1142, wherein the first pad 14 is electrically connected to the first circuit layer 1132 and the second pad 16 is electrically connected to the second circuit layer 1142.

[0114] The method for manufacturing semiconductor structures disclosed herein can achieve similar technical effects to the aforementioned semiconductor structures, and will not be described in detail here.

[0115] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: The substrate has opposing first and second surfaces, a first portion, a second portion, and a third portion, wherein the Young's modulus of the first portion is greater than that of the second portion. A chip is embedded in the second part, the first part is disposed between the chip and the first surface, and the second part is disposed between the first part and the second surface; The first part includes a first sub-substrate and a first adhesive layer disposed on the lower surface of the first sub-substrate; the third part is a second sub-substrate; the second part is a second adhesive layer disposed on the edge or inside of the second sub-substrate and covering the chip; The stress acting on the chip is transmitted to the side away from the first part, thereby reducing the stress on the chip.

2. The apparatus according to claim 1, wherein, The first adhesive layer and the second adhesive layer are integrally formed.

3. The apparatus according to claim 1, wherein, The substrate further includes: The third part is arranged around the second part, and the Young's modulus of the third part is greater than that of the second part.

4. The apparatus according to claim 1, wherein, The first sub-substrate also includes: A first circuit layer is disposed on the first surface and is electrically connected to the chip.

5. The apparatus according to claim 4, wherein, The second sub-substrate also includes: The second circuit layer is disposed on the second surface and is electrically connected to the first circuit layer.

6. The apparatus according to claim 4, wherein, The device further includes: A first pad is disposed on the first surface, and the first pad is electrically connected to the first sub-substrate.

7. The apparatus according to claim 5, wherein, The device further includes: The second pad is disposed on the second surface and is electrically connected to the second sub-substrate.

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