Semiconductor packaging structure and manufacturing method

Abstract

The semiconductor packaging structure and manufacturing method disclosed herein reduce the contact area between the redistribution layer and the molding layer by adding an extension in the lead frame that is bonded to the redistribution layer and using the extension as the base of the redistribution layer. Therefore, the risk of redistribution layer peeling can be effectively reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures and their manufacturing methods. Background Technology

[0002] Fan-out (also known as RDL redistribution layer) process based on existing lead frame 6, such as Figure 1 As shown, the I / O connections of chip 1 are typically made through vias or pillars. The redistribution layer 3 is usually fabricated on the dielectric layer 7, but this approach is costly.

[0003] like Figure 2 As shown, if the dielectric layer 7 is not used and the redistribution layer 3 is directly fabricated on the molding layer 4, the bonding force between the molding layer 4 and the redistribution layer 3 is low, which can easily lead to peeling, thus posing a risk to product reliability.

[0004] In addition, such as Figure 4 As shown, reducing the spacing between the existing lead frame 6 and the chip 1 to minimize the contact area between the redistribution layer 3 and the molding layer 4 can improve the risk of poor bonding between the redistribution layer 3 and the molding layer 4, but... Figure 5 As shown, the number of fan-out I / Os will be greatly reduced, which will limit the product development space. Therefore, reducing the spacing between the existing lead frame 6 and the chip 1 is not the best choice. Summary of the Invention

[0005] This disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging structure, the semiconductor packaging structure comprising: a chip; a lead frame disposed on at least one side of the chip, the lead frame including a lead array and an extension; and a redistribution layer directly contacting the active surface of the chip and the upper surface of the lead frame.

[0007] In some alternative implementations, the extension extends in a direction toward the chip.

[0008] In some alternative implementations, the thickness of the extension is less than or equal to the thickness of the chip.

[0009] In some alternative implementations, the lead array and the extension are integrally formed.

[0010] In some alternative embodiments, the extension is made of a metallic material.

[0011] In some alternative embodiments, the upper surface of the extension is coplanar with the upper surface of the lead array.

[0012] In some alternative embodiments, the thickness of the extension is the same as the thickness of the lead array.

[0013] In some alternative implementations, the width of the extension is the same as the width of the redistribution layer.

[0014] In some optional embodiments, the semiconductor package structure further includes: a molding layer, the lead frame embedded in the molding layer, the redistribution layer disposed on the molding layer, and the bonding force between the extension and the redistribution layer being greater than the bonding force between the molding layer and the redistribution layer.

[0015] Secondly, this disclosure provides a method for manufacturing a semiconductor package structure, the method comprising: providing a lead frame having a hollow region on a carrier, the lead frame including a lead array and an extension; disposing a chip on the carrier and located in the hollow region; and forming a redistribution layer on the active surface of the chip and the upper surface of the lead frame.

[0016] In some alternative embodiments, placing the chip on the carrier and in the hollow region includes placing the chip on the carrier and in the hollow region with the active side of the chip facing down.

[0017] In some alternative embodiments, prior to forming the redistribution layer, the method further includes: setting a molding layer covering the chip and the lead frame, and grinding the molding layer to expose the back side of the chip; flipping the chip so that the active side faces upward; and removing the carrier to expose the active side of the chip.

[0018] To address the risk of peeling between the redistribution layer and the molding layer in leadframe-based structures due to low bonding strength, this disclosure provides a semiconductor packaging structure and manufacturing method that adds an extension to the leadframe for bonding with the redistribution layer. Since the extension is made of metal, it exhibits good bonding strength with the redistribution layer. By using the extension as a substrate for the redistribution layer, the contact area between the redistribution layer and the molding layer is reduced, thus effectively lowering the risk of peeling. Furthermore, removing the dielectric layer from the redistribution layer allows for a more cost-effective product. Additionally, using the extension as a substrate for the redistribution layer increases the heat dissipation efficiency of the circuitry within the redistribution layer. Attached Figure Description

[0019] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0020] Figures 1-5 It is a semiconductor packaging structure based on existing technology;

[0021] Figure 6 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;

[0022] Figure 7 yes Figure 6 The diagram shows a top view of the semiconductor package structure.

[0023] Figure 8 This is a schematic diagram of another embodiment of the semiconductor packaging structure according to the present disclosure;

[0024] Figures 9 to 15 This is a schematic diagram of the manufacturing process of the semiconductor packaging structure according to the present disclosure.

[0025] Symbol explanation:

[0026] 1-Chip, 2-Lead frame, 21-Lead array, 22-Extension, 23-Hollow region, 3-Redistribution layer, 4-Molding layer, 5-Carrier, 51-Temporary adhesive layer, 6-Existing lead frame, 7-Dielectric layer. Detailed Implementation

[0027] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0028] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0029] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified.

[0030] Figure 6 A schematic diagram of one embodiment of the semiconductor packaging structure of this disclosure is shown. Figure 6 As shown, the semiconductor package structure includes a chip 1, a lead frame 2, a redistribution layer 3, and a molding layer 4. The lead frame 2 can be disposed on at least one side of the chip 1. The lead frame 2 may include a lead array 21 and an extension 22. The redistribution layer 3 can directly contact the active surface of the chip 1 and the upper surface of the lead frame 2. The lead frame 2 can be embedded in the molding layer 4. The redistribution layer 3 can be disposed on the molding layer 4.

[0031] In this embodiment, the extension 22 can extend in the direction toward the chip 1. The thickness of the extension 22 can be less than or equal to the thickness of the chip 1. The lead array 21 and the extension 22 can be integrally formed. The upper surface of the extension 22 can be coplanar with the upper surface of the lead array 21. The width of the extension 22 can be the same as the width of the redistribution layer 3.

[0032] In this embodiment, the bonding force between the extension 22 and the redistribution layer 3 can be greater than the bonding force between the molding layer 4 and the redistribution layer 3. Since the extension 22 is made of metal, and the molding layer 4 is, for example, a silicon dioxide-based molded material, the bonding force between metals is greater than the bonding force between metal and molded material. Therefore, the bonding force between the extension 22 and the redistribution layer 3 is greater than the bonding force between the molding layer 4 and the redistribution layer 3.

[0033] Figure 7 yes Figure 6 The diagram shows a top view of a semiconductor package structure, in which the redistribution layer 3 is partially cut to expose the extension 22. Figure 3 Compared to existing semiconductor packaging structures, Figure 7 The semiconductor packaging structure shown uses the extension 22 as the substrate of the redistribution layer 3, which reduces the contact area between the redistribution layer 3 and the molding layer 4. Figure 7 The contact area between the redistribution layer 3 and the molding layer 4 in the semiconductor packaging structure is less than... Figure 3 The contact area between the redistribution layer 3 and the molding layer 4 in the semiconductor packaging structure can effectively reduce the risk of the redistribution layer 3 peeling off.

[0034] Figure 8 A schematic diagram of yet another embodiment of the semiconductor packaging structure of this disclosure is shown. (See diagram below.) Figure 8 As shown, with Figure 6The difference in the semiconductor package structure shown is that the thickness of the extension 22 is the same as the thickness of the lead array 21. Increasing the thickness of the extension 22 to the thickness of the lead array 21 can effectively increase the heat dissipation efficiency of the lines in the redistribution layer 3.

[0035] The semiconductor packaging structure disclosed herein adds an extension 22 to the lead frame 2 that bonds to the redistribution layer 3. Since the extension 22 is made of metal, it has good bonding strength with the redistribution layer 3. By using the extension 22 as the substrate of the redistribution layer 3, the contact area between the redistribution layer 3 and the molding layer 4 is reduced, thus effectively reducing the risk of the redistribution layer 3 peeling off. Furthermore, removing the dielectric layer from the redistribution layer 3 previously provided a cost advantage. Additionally, the extension 22, as the substrate of the redistribution layer 3, also increases the heat dissipation efficiency of the circuitry within the redistribution layer 3.

[0036] Figures 9 to 15 This is a schematic diagram illustrating the manufacturing process of the semiconductor package structure according to the present disclosure. The figures have been simplified for better understanding of the aspects of this disclosure.

[0037] like Figure 9 As shown, a lead frame 2 with a hollow region 23 is provided. The lead frame 2 includes a lead array 21 and an extension 22.

[0038] like Figure 10 As shown, the lead frame 2 is placed on the carrier 5 by a temporary adhesive layer 51.

[0039] like Figure 11 As shown, chip 1 is placed on carrier 5 and located in hollow region 23. Specifically, chip 1 can be placed on carrier 5 with its active surface facing down (Die Face Down) and located in hollow region 23.

[0040] like Figure 12 and Figure 13 As shown, first, a molding layer 4 is set to cover the chip 1 and the lead frame 2. Then, the molding layer 4 is ground to expose the back side of the chip 1. The chip 1 is flipped so that the active side is facing up. The carrier 5 and the temporary adhesive layer 51 are removed to expose the active side of the chip 1.

[0041] In this embodiment, the back side of chip 1 needs to be exposed by grinding the molding layer 4. In some alternative implementations, the molding layer 4 can be made of a photosensitive material, and the back side of chip 1 can be exposed by exposure and development (photolithography), without the need for grinding. In some alternative implementations, the back side of chip 1 can be exposed by printing, using a patterned stencil to cover it, thus eliminating the need to print molding material on the back side of chip 1 and exposing the back side of chip 1 without grinding.

[0042] like Figure 14 As shown, a redistribution layer 3 is formed on the active surface of chip 1 and the upper surface of lead frame 2.

[0043] like Figure 15 As shown, patterned redistribution layer 3.

[0044] The method for manufacturing semiconductor packaging structures disclosed herein can achieve similar technical effects to the aforementioned semiconductor packaging structures, and will not be described in detail here.

[0045] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package structure, comprising: a chip; a leadframe disposed on at least one side of the chip, the leadframe comprising a lead array and an extension; a redistribution layer directly contacting an active surface of the chip and an upper surface of the leadframe; the redistribution layer is a metal material and does not comprise a dielectric layer; the extension and the lead array are integrally formed, the extension is a metal material, the extension extends in a direction towards the chip, and the extension does not directly contact the chip; the semiconductor package structure further comprises: a mold encapsulation layer, the leadframe is embedded in the mold encapsulation layer, and the redistribution layer is disposed on the mold encapsulation layer, and a bonding force between the extension and the redistribution layer is greater than a bonding force between the mold encapsulation layer and the redistribution layer.

2. The semiconductor package structure of claim 1, wherein, a thickness of the extension is less than or equal to a thickness of the chip.

3. The semiconductor package structure of claim 1, wherein, an upper surface of the extension is coplanar with an upper surface of the lead array.

4. The semiconductor package structure of claim 3, wherein, the thickness of the extension is the same as a thickness of the lead array.

5. The semiconductor package structure of claim 1, wherein, a width of the extension is the same as a width of the redistribution layer. 6.A method for manufacturing a semiconductor package structure, comprising: providing a leadframe having a hollow region on a carrier, the leadframe comprising a lead array and an extension; disposing a chip on the carrier and in the hollow region; forming a redistribution layer on an active surface of the chip and an upper surface of the leadframe; disposing a mold encapsulation layer covering the chip and the leadframe, such that the leadframe is embedded in the mold encapsulation layer, and the redistribution layer is disposed on the mold encapsulation layer; wherein the redistribution layer is a metal material and does not comprise a dielectric layer; the extension and the lead array are integrally formed, the extension is a metal material, the extension extends in a direction towards the chip, and the extension does not directly contact the chip; a bonding force between the extension and the redistribution layer is greater than a bonding force between the mold encapsulation layer and the redistribution layer.

Images