RF semiconductor device and manufacturing method thereof

Abstract

The present disclosure relates to a radio frequency device, comprising a transfer device die and a multi-layer redistribution structure located below the transfer device die. The transfer device die comprises a device region and a transfer substrate, the device region having a back-end of line (BEOL) portion and a front-end of line (FEOL) portion located above the BEOL portion. The FEOL portion comprises an isolation section and an active layer, the active layer being surrounded by the isolation section. The top surface of the device region is planarized. The transfer substrate is located above the top surface of the device region. In this context, no silicon crystals are present within the transfer substrate or between the transfer substrate and the active layer. The multi-layer redistribution structure comprises a plurality of raised structures, the plurality of raised structures being located at the bottom of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Description

Technical Field

[0001] The present disclosure relates to a radio frequency (RF) device and a process for manufacturing the same, and more particularly to an RF device having enhanced thermal performance and enhanced electrical performance, and a wafer-level manufacturing and packaging process for providing the RF device having enhanced performance. Background Art

[0002] The widespread use of cellular and wireless devices has driven the rapid development of radio frequency (RF) technology. The substrate on which RF devices are manufactured plays an important role in achieving high levels of performance in RF technology. Manufacturing RF devices on conventional silicon substrates can benefit from low-cost silicon materials, large-scale wafer production capabilities, well-established semiconductor design tools, and well-established semiconductor manufacturing technology. Although the use of conventional silicon substrates is beneficial for RF device manufacturing, it is well known in the industry that conventional silicon substrates may have two undesirable properties for RF devices: harmonic distortion and low resistivity values. Harmonic distortion is a key obstacle to achieving high levels of linearity in RF devices built on silicon substrates.

[0003] Furthermore, high-speed, high-performance transistors are increasingly being integrated into RF devices. Consequently, due to the large number of transistors integrated into the RF device, the large amount of power passing through the transistors, and / or the high operating speeds of the transistors, the heat generated by the RF device can significantly increase. Therefore, it is desirable to package the RF device in a configuration that achieves improved heat dissipation.

[0004] Wafer-level fan-out (WLFO) and embedded wafer-level ball grid array (eWLB) technologies are currently attracting widespread attention in portable RF applications. WLFO and eWLB technologies are designed to provide high-density input / output (I / O) ports without increasing package size. This capability allows for dense packaging of RF devices within a single wafer.

[0005] To improve the operating speed and performance of RF devices, accommodate increased heat generation in RF devices, reduce harmful harmonic distortion in RF devices, and leverage the advantages of WLFO / eWLB technology, the present disclosure aims to provide an improved wafer-level manufacturing and packaging process for RF devices with enhanced performance. Furthermore, it is desirable to enhance the performance of RF devices without increasing the size of the devices. Summary of the Invention

[0006] The present disclosure relates to a radio frequency (RF) device with enhanced performance and a process for manufacturing the same. The disclosed RF device includes a transfer device die and a multi-layer redistribution structure. The transfer device die includes a device region and a transfer substrate, the device region having a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion. Herein, the FEOL portion is located above the BEOL portion and includes an isolation section and an active layer, the active layer being surrounded by the isolation section and not extending vertically beyond the isolation section. The device region has a planarized top surface. The transfer substrate is located above the top surface of the device region. No silicon crystals without germanium, nitrogen, or oxygen content are present within the transfer substrate or between the transfer substrate and the active layer within the device region. The multi-layer redistribution structure, including a plurality of raised structures, is formed below the BEOL portion of the transfer device die. The raised structures are located on a bottom surface of the multi-layer redistribution structure and are electrically coupled to the FEOL portion of the transfer device die.

[0007] In one embodiment of the RF device, the transfer substrate has a thermal conductivity greater than 10 W / m·K and a resistivity greater than 1E5 Ohm-cm.

[0008] In one embodiment of the RF device, the transfer substrate is formed of one of the following: sapphire, thermally conductive quartz, aluminum nitride, boron nitride, and beryllium oxide.

[0009] In one embodiment of the RF device, the thickness of the transfer substrate is between 10 μm and 1000 μm.

[0010] In one embodiment of the RF device, the active layer is formed of a strained silicon epitaxial layer, and at a temperature of 300K, a lattice constant of silicon in the strained silicon epitaxial layer is greater than 5.461.

[0011] In one embodiment of the RF device, the BEOL portion includes a connection layer, the FEOL portion further includes a contact layer, and the multi-layer redistribution structure further includes a redistribution interconnect. Here, the active layer and the isolation section are located above the contact layer, and the BEOL portion is located below the contact layer. The raised structure is electrically coupled to the FEOL portion of the transfer device die via the redistribution interconnect within the multi-layer redistribution structure and the connection layer within the BEOL portion.

[0012] In one embodiment of the RF device, the device region further includes a passivation layer located above the active layer and surrounded by the isolation segments. In this embodiment, the passivation layer is formed of silicon dioxide. A top surface of each isolation segment is coplanar with a top surface of the passivation layer and forms the top surface of the device region.

[0013] In one embodiment of the RF device, a top surface of each isolation section is coplanar with a top surface of the active layer and forms the top surface of the device region.

[0014] In one embodiment of the RF device, the transfer device die further includes a barrier layer formed of silicon nitride, the barrier layer coupled between the top surface of the device region and the transfer substrate.

[0015] In an embodiment of the RF device, the FEOL portion is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

[0016] According to another embodiment, an alternative RF device includes a transfer device die and a multi-layer redistribution structure. The transfer device die includes a device region and a transfer substrate, the device region having a FEOL portion and a BEOL portion. Herein, the FEOL portion is located above the BEOL portion and includes an isolation segment and an active layer, the active layer being surrounded by the isolation segment and not extending vertically beyond the isolation segment. The device region has a planarized top surface. The transfer substrate is located above the top surface of the device region. No silicon crystals without germanium, nitrogen, or oxygen content are present within the transfer substrate or between the transfer substrate and the active layer within the device region. The multi-layer redistribution structure, formed below the BEOL portion of the transfer device die, extends horizontally beyond the transfer device die. The multi-layer redistribution structure includes a plurality of raised structures located on a bottom surface of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the transfer device die. The alternative RF device further includes a molding compound located above the multi-layer redistribution structure to encapsulate the transfer device die.

[0017] In one embodiment of the alternative RF device, the transfer substrate has a thermal conductivity greater than 10 W / m·K and a resistivity greater than 1E5 Ohm-cm.

[0018] In one embodiment of the alternative RF device, the transfer substrate is formed from one of: sapphire, thermally conductive quartz, aluminum nitride, boron nitride, and beryllium oxide.

[0019] In one embodiment of the alternative RF device, the transfer substrate has a thickness between 10 μm and 1000 μm.

[0020] In one embodiment of the alternative RF device, the active layer is formed of a strained silicon epitaxial layer, and the lattice constant of silicon in the strained silicon epitaxial layer is greater than 5.461 at a temperature of 300K.

[0021] In one embodiment of the alternative RF device, the BEOL portion includes a connection layer, the FEOL portion further includes a contact layer, and the multi-layer redistribution structure further includes a redistribution interconnect. Here, the active layer and the isolation section are located above the contact layer, and the BEOL portion is located below the contact layer. The raised structure is electrically coupled to the FEOL portion of the transfer device die via the redistribution interconnect within the multi-layer redistribution structure and the connection layer within the BEOL portion.

[0022] In one embodiment of the alternative RF device, the device region further comprises a passivation layer located above the active layer and surrounded by the isolation segments. In this context, the passivation layer is formed of silicon dioxide. A top surface of each isolation segment is coplanar with a top surface of the passivation layer and forms the top surface of the device region.

[0023] In one embodiment of the alternative RF device, a top surface of each isolation segment is coplanar with a top surface of the active layer and forms the top surface of the device region.

[0024] In one embodiment of the alternative RF device, the transfer device die further includes a barrier layer formed of silicon nitride, the barrier layer coupled between the top surface of the device region and the transfer substrate.

[0025] In one embodiment of the alternative RF device, the FEOL portion is configured to provide at least one of a switching FET, a diode, a capacitor, a resistor, or an inductor.

[0026] According to an exemplary process, a precursor wafer is first provided, comprising a plurality of complete device regions, a plurality of separate interface layers, and a silicon handle substrate. Each complete device region comprises a BEOL portion and a complete FEOL portion located above the BEOL portion. The complete FEOL portion comprises an active layer and a complete isolation segment, the isolation segment extending vertically beyond and surrounding the active layer. In this context, each separate interface layer is located above an active layer and is surrounded by the complete isolation segment of the corresponding complete device region. Each separate interface layer is formed of SiGe. The silicon handle substrate is located above each complete isolation segment and each separate interface layer. Next, the silicon handle substrate is completely removed. The complete isolation segments are then thinned to provide a thinned wafer having a planarized top surface. The thinned wafer comprises a plurality of device regions, and the top surfaces of each device region are combined to form the planarized top surface of the thinned wafer. Each device region comprises the BEOL portion and the FEOL portion located above the BEOL portion. The FEOL portion includes the active layer and the thinned isolation region surrounding the active layer. A transfer substrate is attached to the top surface of the thinned wafer to provide a transfer device wafer including a plurality of transfer device dies. In this context, no silicon crystals without germanium, nitrogen, or oxygen content are present within the transfer substrate or between the active layer of each device region and the transfer substrate. Each transfer device die includes a corresponding device region and a portion of the transfer substrate located above the corresponding device region.

[0027] In one embodiment of the exemplary process, the transfer substrate has a thermal conductivity greater than 10 W / m·K and a resistivity greater than 1E5 Ohm-cm.

[0028] In one embodiment of the exemplary process, the transfer substrate is formed from one of: sapphire, thermally conductive quartz, aluminum nitride, boron nitride, and beryllium oxide.

[0029] In one embodiment of the exemplary process, the transfer substrate has a thickness between 10 μm and 1000 μm.

[0030] According to another embodiment, the exemplary process further includes, before removing the silicon handling substrate, bonding the precursor wafer to a temporary carrier via a bonding layer; and after attaching the transfer substrate, debonding the temporary carrier from the transfer device wafer and clearing the bonding layer from the transfer device wafer.

[0031] According to another embodiment, the exemplary process further includes forming a multi-layer redistribution structure beneath the transfer device wafer. Here, the multi-layer redistribution structure includes a plurality of raised structures on a bottom surface of the multi-layer redistribution structure and redistribution interconnects within the multi-layer redistribution structure. Each raised structure is electrically coupled to an active layer of a corresponding transfer device die via the redistribution interconnect within the multi-layer redistribution structure and a connection layer within the BEOL portion of the corresponding transfer device die.

[0032] According to another embodiment, the exemplary process further includes singulating the transfer device wafer into a plurality of individual transfer device dies. A molding compound is then applied around and over each individual transfer device die to provide a molded device wafer. In this context, the molding compound encapsulates the top and side surfaces of each individual transfer device die, while the bottom surface of each individual transfer device die is exposed. The bottom surface of the molded device wafer is a combination of the bottom surface of each individual transfer device die and the bottom surface of the molding compound. Next, a multi-layer redistribution structure is formed beneath the molded device wafer. The multi-layer redistribution structure includes a plurality of raised structures on the bottom surface of the multi-layer redistribution structure and a redistribution interconnect within the multi-layer redistribution structure. Each raised structure is electrically coupled to an active layer of the corresponding individual transfer device die via the redistribution interconnect within the multi-layer redistribution structure and a connection layer within the BEOL portion of the corresponding individual transfer device die.

[0033] According to another embodiment, the exemplary process further comprises removing each individual interfacial layer after removing the silicon handle substrate and before thinning the complete isolation segments. Thus, after the thinning step, the planarized top surface of each device region is formed by the top surface of the corresponding active layer and the top surface of the corresponding thinned isolation segments.

[0034] According to another embodiment, the exemplary process further comprises removing each individual interfacial layer and applying a passivation layer over the corresponding active layer after removing the silicon handle substrate and before thinning the complete isolation segments. Thus, after the thinning step, the planarized top surface of each device region is formed by the top surface of the corresponding passivation layer and the top surface of the corresponding thinned isolation segments.

[0035] In one embodiment of the exemplary process, the passivation layer is applied by one of a plasma enhanced deposition process, an anodization process, and an ozone based oxidation process.

[0036] According to another embodiment, the exemplary process further includes applying a barrier layer over the top surface of the thinned wafer before attaching the transfer substrate to the thinned wafer.Herein, the barrier layer is formed of silicon nitride.

[0037] In one embodiment of the exemplary process, providing the precursor wafer begins by providing a starting wafer comprising a common silicon epitaxial layer, a common interface layer located above the common silicon epitaxial layer, and a silicon handle substrate located above the common interface layer. A complementary metal oxide semiconductor (CMOS) process is then performed to provide the precursor wafer. In this context, the complete isolation section extends through the common silicon epitaxial layer and the common interface layer and into the silicon handle substrate, such that the common interface layer separates into the individual interface layers and the common silicon epitaxial layer separates into a plurality of individual silicon epitaxial layers. Each active layer is formed from a corresponding individual silicon epitaxial layer.

[0038] In one embodiment of the exemplary process, the silicon handle substrate is removed by a mechanical grinding process followed by an etching process.

[0039] In one embodiment of the exemplary process, the silicon handle substrate is removed by an etching process using an etchant chemistry that is at least one of tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), and xenon difluoride (XeF2).

[0040] In one embodiment of the exemplary process, the silicon handle substrate is removed by a reactive ion etch system with a chlorine-based gas chemistry.

[0041] In one embodiment of the exemplary process, the transfer substrate is attached to the top surface of the thinned wafer by one of the group consisting of: anodic bonding, plasma bonding, and polymer adhesive bonding.

[0042] Those skilled in the art will understand the scope of the present disclosure and recognize additional aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0044] Figure 1 An exemplary radio frequency (RF) device with enhanced performance according to one embodiment of the present disclosure is shown.

[0045] Figure 2An alternative RF device having enhanced thermal performance and enhanced electrical performance according to one embodiment of the present disclosure is shown.

[0046] Figure 3A-15 Shown is provided Figure 1 The steps of an exemplary wafer-level fabrication and packaging process for an exemplary RF device are shown.

[0047] Figure 16-21 Shown is provided Figure 2 The steps of an alternative RF device are shown in an alternative wafer-level manufacturing and packaging process.

[0048] It should be understood that for the sake of clarity, Figure 1-21 Drawings may not be to scale. DETAILED DESCRIPTION

[0049] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. When reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0050] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of this disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0051] It should be understood that when an element such as a layer, region or substrate is referred to as being "on another element" or extending "onto another element", it can be directly on the other element or directly extended onto the other element, or there can also be an intermediate element. In contrast, when an element is referred to as being "directly on another element" or "extending directly onto another element", there are no intermediate elements. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "on another element" or extending "onto another element", it can be directly on another element or directly extended onto another element, or there can also be an intermediate element. In contrast, when an element is referred to as being "directly on another element" or "extending directly onto another element", there are no intermediate elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0052] Relative terms, such as "below," "above," "upper," "lower," "horizontal," "vertical," "over," or "under," may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that when used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0054] Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0055] With conventional radio frequency silicon-on-insulator (RFSOI) wafers expected to be in short supply in the coming years, alternative technologies are being designed to meet high resistivity requirements using silicon wafers, trap-rich layer formation, and smart-cut SOI wafer processes. One alternative technology is based on using a silicon-germanium (SiGe) interface layer between the silicon substrate and the silicon epitaxial layer instead of a buried oxide layer (BOX). However, this technology will still suffer from deleterious distortion effects caused by the silicon substrate, similar to those observed in RFSOI technology. The present disclosure relates to a radio frequency (RF) device with enhanced performance, and a wafer-level manufacturing and packaging process for manufacturing the device, which utilizes a SiGe interface layer without the deleterious distortion effects from the silicon substrate.

[0056] Figure 1 An exemplary RF device 10 having enhanced performance according to one embodiment of the present disclosure is shown. For purposes of this description, the exemplary RF device 10 includes a transfer device die 12 having a device region 14 and a transfer substrate 16, and a multi-layer redistribution structure 18 formed below the device region 14 of the transfer device die 12.

[0057] Specifically, the device region 14 includes a front-end of the line (FEOL) portion 20 and a back-end of the line (BEOL) portion 22 located below the FEOL portion 20. In one embodiment, the FEOL portion 20 can be configured to provide a switching field effect transistor (FET) and includes an active layer 24 and a contact layer 26. The active layer 24 can be formed of a relaxed silicon epitaxial layer or a strained silicon epitaxial layer and includes a source 28, a drain 30, and a channel 32 between the source 28 and the drain 30. In this document, a relaxed silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of silicon is 5.431 at a temperature of 300K. A strained silicon epitaxial layer refers to a silicon epitaxial layer in which the lattice constant of silicon is greater than the lattice constant of the relaxed silicon epitaxial layer, such as greater than 5.461, greater than 5.482, greater than 5.493, or greater than 5.515 at a temperature of 300K. As a result, the mobility of electrons in the strained silicon epitaxial layer can be enhanced compared to the relaxed silicon epitaxial layer. Therefore, the switching speed of the FET formed from the strained silicon epitaxial layer can be faster than that of the FET formed from the relaxed silicon epitaxial layer.

[0058] Contact layer 26 is formed beneath active layer 24 and includes gate structure 34, source contact 36, drain contact 38, and gate contact 40. Gate structure 34 may be formed of silicon oxide and extends horizontally beneath channel 32 (e.g., from beneath source 28 to beneath drain 30). Source contact 36 is connected to and beneath source 28, drain contact 38 is connected to and beneath drain 30, and gate contact 40 is connected to and beneath gate structure 34. Insulating material 42 may be formed around source contact 36, drain contact 38, gate structure 34, and gate contact 40 to electrically isolate source 28, drain 30, and gate structure 34. In different applications, FEOL portion 20 may have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0059] In addition, the FEOL portion 20 further includes an isolation region 44 located above the insulating material 42 of the contact layer 26 and surrounding the active layer 24. The isolation region 44 is configured to electrically isolate the RF device 10, and in particular the active layer 24, from other devices formed in a common wafer (not shown). The isolation region 44 can be formed of silicon dioxide, which is resistant to etching chemistries such as tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF2), potassium hydroxide (KOH), sodium hydroxide (NaOH), or acetylcholine (ACH), and is resistant to dry etching systems such as reactive ion etching (RIE) systems with chlorine-based gas chemistries.

[0060] In some applications, device region 14 further includes a passivation layer 48, which may be formed of silicon dioxide, to passivate active layer 24. Passivation layer 48 is deposited over the top surface of active layer 24 and is surrounded by isolation segments 44. In one embodiment, the top surface of passivation layer 48 is coplanar with the top surface of isolation segments 44. Passivation layer 48 is configured to terminate surface bonding of active layer 24, which may be a cause of unwanted leakage.

[0061] In some applications, the device region 14 further includes an interface layer and / or buffer structure (not shown) formed of SiGe, located above the top surface of the active layer 24 and surrounded by the isolation segment 44 (described in the following paragraphs and not shown herein). If the passivation layer 48, the buffer structure, and the interface layer are present, the interface layer and the buffer structure are vertically located between the active layer 24 and the passivation layer 48. Herein, the top surface of the passivation layer 48 and the top surface of the isolation segment 44 are coplanar. If the passivation layer 48 is omitted and the interface layer and / or the buffer structure are present, the top surface of the interface layer (or the top surface of the buffer structure) and the top surface of the isolation segment 44 are coplanar (not shown). If the passivation layer 48, the buffer structure, and the interface layer are omitted, the top surface of the active layer 24 and the top surface of the isolation segment 44 are coplanar (not shown). It should be noted that regardless of the presence of the passivation layer 48, the buffer structure and / or the interface layer, the top surface of the device region 14 (the combination of the top surface of the isolation segment 44 and the top surface of the passivation layer 48, the combination of the top surface of the isolation segment 44 and the top surface of the interface layer, the combination of the top surface of the isolation segment 44 and the top surface of the buffer structure, or the combination of the top surface of the isolation segment 44 and the top surface of the active layer 24) is always planarized.

[0062] The transfer substrate 16 is positioned above the top surface of the device region 14. Heat generated in the device region 14 can travel upward to the bottom portion of the transfer substrate 16 above the active layer 24 and then downward through the device region 14 toward the multilayer redistribution structure 18, which dissipates the heat. Therefore, it is highly desirable for the transfer substrate 16 to have a high thermal conductivity, especially for portions near the active layer 24. Herein, the transfer substrate 16 has a high thermal conductivity between 2 W / m·K and 500 W / m·K (desirably above 10 W / m·K) and a high resistivity between 1E5 Ohm-cm and 1E14 Ohm-cm. Suitable substrate materials for forming the transfer substrate 16 can include sapphire, thermally conductive quartz, and ceramic materials such as aluminum nitride, boron nitride, and the like. The transfer substrate 16 can also be formed from beryllium oxide. The thickness of the transfer substrate 16 depends on the desired thermal performance of the RF device 10, the device layout, the distance from the multilayer redistribution structure 18, and the details of the package and assembly. The thickness of the transfer substrate 16 may be between 10 μm and 1000 μm.

[0063] In some applications, the transfer device die 12 may further include a barrier layer coupled between the top surface of the device region 14 and the transfer substrate 16 (not shown). This barrier layer may be formed with a thickness between and The barrier layer is configured to provide an excellent barrier to moisture and impurities that could diffuse into the channels 32 of the active layer 24 and cause reliability issues for the device. Additionally, the barrier layer can be configured to enhance adhesion between the device region 14 and the transfer substrate 16. It should be noted that regardless of the presence of the barrier layer, passivation layer 48, or interfacial layer, no silicon crystals without germanium, nitrogen, or oxygen content exist within the transfer substrate 16 or between the transfer substrate 16 and the top surface of the active layer 24. Each of the barrier layer, passivation layer 48, and interfacial layer is formed of a silicon composite.

[0064] The BEOL portion 22 is located below the FEOL portion 20 and includes a plurality of connection layers 50 formed within a dielectric layer 52. Some of the connection layers 50 (for internal connections) are encapsulated (not shown) by the dielectric layer 52, while some of the connection layers 50 have bottom portions that are not covered by the dielectric layer 52. Some of the connection layers 50 are electrically connected to the FEOL portion 20. For purposes of this illustration, one of the connection layers 50 is connected to the source contact 36, and another connection layer 50 is connected to the drain contact 38.

[0065] The multilayer redistribution structure 18 formed below the BEOL portion 22 of the transfer device die 12 includes a plurality of redistribution interconnects 54, a dielectric pattern 56, and a plurality of raised structures 58. Here, each redistribution interconnect 54 is connected to a corresponding connection layer 50 within the BEOL portion 22 and extends above the bottom surface of the BEOL portion 22. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. A dielectric pattern 56 is formed around and below each redistribution interconnect 54. Some of the redistribution interconnects 54 (which connect the transfer device die 12 to other device components formed on the same wafer) may be encapsulated by the dielectric pattern 56 (not shown), while some of the redistribution interconnects 54 have bottom portions exposed through the dielectric pattern 56. Each raised structure 58 is formed at the bottom surface of the multilayer redistribution structure 18 and is electrically coupled to a corresponding redistribution interconnect 54 through the dielectric pattern 56. As such, the redistribution interconnects 54 are configured to connect the raised structures 58 to certain of the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. Therefore, the raised structures 58 are electrically connected to the FEOL portion 20 through the corresponding redistribution interconnects 54 and the corresponding connection layers 50. Furthermore, the raised structures 58 are separated from one another and protrude from the dielectric pattern 56.

[0066] In some applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnects 54 via the dielectric pattern 56, as well as additional dielectric patterns (not shown) formed beneath the dielectric pattern 56 so that the bottom portions of some additional redistribution interconnects may be exposed. Thus, each raised structure 58 is coupled to a corresponding additional redistribution interconnect via an additional dielectric pattern (not shown). Regardless of the number of layers of redistribution interconnects and / or dielectric patterns, the multilayer redistribution structure 18 may be glass-free or glass-free. In this document, glass fiber refers to individual glass strands twisted into larger groups. These glass strands can then be woven into a fabric. The redistribution interconnects 54 may be formed of copper or other suitable metals. The dielectric pattern 56 may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The raised structures 58 may be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm.

[0067] Figure 2 Shown with Figure 1 Compared to the RF device 10 shown in FIG. 1 , an alternative RF device 10A further includes a mold compound 60. Here, the multi-layer redistribution structure 18 can extend horizontally beyond the transfer device die 12, and the mold compound 60 is positioned above the multi-layer redistribution structure 18 to encapsulate the transfer device die 12. In this embodiment, the redistribution interconnects 54 of the multi-layer redistribution structure 18 can extend horizontally beyond the transfer device die 12, and the raised structures 58 of the multi-layer redistribution structure 18 can not be confined within the periphery of the transfer device die 12. The mold compound 60 can be an organic epoxy resin system, etc.

[0068] Figure 3A-15 Provides a demonstration of manufacturing Figure 1 1. The exemplary wafer-level manufacturing and packaging process of the exemplary RF device 10 shown in FIG. 1 is a schematic diagram illustrating an exemplary wafer-level manufacturing and packaging process of the exemplary RF device 10. Although the exemplary steps are shown in a series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the process within the scope of the present disclosure may include more than Figure 3A-15 Fewer or more steps may be shown.

[0069] First, if Figure 3A and 3BAs shown, a starting wafer 62 is provided. Starting wafer 62 includes a common silicon epitaxial layer 64, a common interface layer 66 located above common silicon epitaxial layer 64, and a silicon handle substrate 68 located above common interface layer 66. Herein, common silicon epitaxial layer 64 is formed of a device-grade silicon material having silicon epitaxial properties desirable for forming electronic devices. Silicon handle substrate 68 can be composed of conventional, low-cost, low-resistivity, high-dielectric-constant silicon having a lattice constant of approximately 5.431 at a temperature of 300K. Common interface layer 66 is formed of SiGe, separating common silicon epitaxial layer 64 from silicon handle substrate 68.

[0070] At a fixed temperature, such as 300K, the lattice constant of relaxed silicon is And relaxation Si 1-x Ge x The lattice constant depends on the germanium concentration, as The lattice constant of relaxed SiGe is greater than that of relaxed silicon. If the common interface layer 66 is grown directly below the silicon handle substrate 68, the lattice constant in the common interface layer 66 will be strained (decreased) by the silicon handle substrate 68. If the common silicon epitaxial layer 64 is grown directly below the common interface layer 66, the lattice constant in the common silicon epitaxial layer 64 may remain in its original relaxed form (approximately the same as the lattice constant in the silicon substrate). Therefore, the common silicon epitaxial layer 64 may not enhance electron mobility.

[0071] In one embodiment, a common buffer structure 70 may be formed between the silicon handle substrate 68 and the common interface layer 66, such as Figure 3A As shown. Common buffer structure 70 allows for a lattice constant transition from silicon handle substrate 68 to common interface layer 66. Common buffer structure 70 may comprise multiple layers and may be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within common buffer structure 70 may increase from 0% at the top side (near silicon handle substrate 68) to X% at the bottom side (near common interface layer 66). X% may depend on the germanium concentration within common interface layer 66, such as 15%, 25%, 30%, 40%, etc. In this context, common interface layer 66 grown below common buffer structure 70 may maintain its lattice constant in a relaxed form and may not be strained (reduced) to match the lattice constant of silicon handle substrate 68. The germanium concentration can be uniform throughout the common interface layer 66 and greater than 15%, 25%, 30% or 40% so that at a temperature of 300K, the lattice constant of the relaxed SiGe in the common interface layer 66 is greater than 5.461, or greater than 5.482, or greater than 5.493 or greater than 5.515.

[0072] In this article, the common silicon epitaxial layer 64 is grown directly below the relaxed common interface layer 66 so that the lattice constant of the common silicon epitaxial layer 64 matches (stretches to) the lattice constant in the relaxed common interface layer 66. Therefore, at a temperature of 300K, the lattice constant in the strained common silicon epitaxial layer 64 can be greater than 5.461, or greater than 5.482, or greater than 5.493, or greater than 5.515, and thus greater than the lattice constant in the relaxed silicon epitaxial layer (e.g., 5.431 at a temperature of 300K). The electron mobility of the strained common silicon epitaxial layer 64 can be higher than the electron mobility of the relaxed silicon epitaxial layer. The thickness of the common silicon epitaxial layer 64 can be between 700nm and 2000nm, and the thickness of the common interface layer 66 can be between and The thickness of the common buffer structure 70 may be between 100 nm and 1000 nm, and the thickness of the silicon handle substrate 68 may be between 200 μm and 700 μm.

[0073] In another embodiment, the common interface layer 66 may be formed directly below the silicon handle substrate 68, and the common buffer structure 70 may be formed between the common interface layer 66 and the common silicon epitaxial layer 64, as shown in FIG. Figure 3B As shown. Herein, the lattice constant of the common interface layer 66 can be strained (reduced) due to the silicon handle substrate 68. The common buffer structure 70 can still be formed of SiGe with a vertically graded germanium concentration. The germanium concentration within the common buffer structure 70 can increase from 0% at the top side (near the common interface layer 66) to X% at the bottom side (near the common silicon epitaxial layer 64). X% can be 15%, or 25%, or 30% or 40%. The lattice constant at the bottom side of the common buffer structure 70 is greater than the lattice constant at the top side of the common buffer structure 70. Herein, the lattice constant of the common silicon epitaxial layer 64 grown under the common buffer structure 70 matches (stretched to) the lattice constant at the bottom side of the common buffer structure 70. Therefore, the lattice constant in the strained common silicon epitaxial layer 64 is greater than the lattice constant in the relaxed silicon epitaxial layer (e.g., 5.431 at a temperature of 300K).

[0074] In some applications, the common buffer structure 70 is omitted (not shown). The common interface layer 66 is grown directly beneath the silicon handle substrate 68, and the common silicon epitaxial layer 64 is grown directly beneath the common interface layer 66. As such, the lattice constant in the common interface layer 66 is strained (reduced) to match the lattice constant in the silicon handle substrate 68, and the lattice constant in the common silicon epitaxial layer 64 remains in its original relaxed form (approximately the same as the lattice constant in the silicon substrate).

[0075] Next, the starting wafer 62 ( Figure 3A) performs a complementary metal oxide semiconductor (CMOS) process to provide a precursor wafer 72 having a plurality of complete device regions 14 ', such as Figure 4 Each complete device region 14' includes a complete FEOL portion 20' having an active layer 24, a contact layer 26, and a complete isolation section 44', and a BEOL portion 22 located below the complete FEOL portion 20'. For the purposes of this description, the complete FEOL portion 20' is configured to provide a switching FET. In different applications, the complete FEOL portion 20' may have different FET configurations or provide different device components, such as diodes, capacitors, resistors, and / or inductors.

[0076] In one embodiment, the complete isolation section 44' of each complete device region 14' extends through the common silicon epitaxial layer 64, the common interface layer 66 and the common buffer structure 70 and extends into the silicon handle substrate 68. In this way, the common buffer structure 70 is separated into a plurality of separate buffer structures 70I, the common interface layer 66 is separated into a plurality of separate interface layers 66I, and the common silicon epitaxial layer 64 is separated into a plurality of separate silicon epitaxial layers 64I. Each separate silicon epitaxial layer 64I is used to form a corresponding active layer 24 in a complete device region 14'. The complete isolation section 44' can be formed by shallow trench isolation (STI). If the active layer 24 is formed by a separate silicon epitaxial layer 64I with a strained (increased) lattice constant, the FET based on the active layer 24 can have a faster switching speed (lower on-resistance) than a FET formed by a relaxed silicon epitaxial layer with a relaxed lattice constant.

[0077] The top surface of the active layer 24 contacts the corresponding interface layer 66I located below the corresponding buffer structure 70I. A silicon handle substrate 68 is located above each individual buffer structure 70I, and a portion of the silicon handle substrate 68 may be located above the complete isolation segment 44'. The BEOL portion 22 of the complete device region 14', including at least the plurality of connection layers 50 and the dielectric layer 52, is formed below the contact layer 26 of the complete FEOL portion 20'. The bottom portions of some of the connection layers 50 are exposed through the dielectric layer 52 located at the bottom surface of the BEOL portion 22.

[0078] After the precursor wafer 72 is completed, the precursor wafer 72 is then bonded to a temporary carrier 74, such as Figure 5As shown, the precursor wafer 72 can be bonded to the temporary carrier 74 via a bonding layer 76 that provides a planarized surface for the temporary carrier 74. From a cost and thermal expansion perspective, the temporary carrier 74 can be a thick silicon wafer, but can also be constructed of glass, sapphire, or any other suitable carrier material. The bonding layer 76 can be a span-on polymeric adhesive film, such as Brewer Science's WaferBOND temporary adhesive material series.

[0079] The silicon handle substrate 68 is then selectively removed to provide an etched wafer 78, as shown. Figure 6 As shown, the selective removal stops at each individual buffer structure 70I or each interface layer 66I. Removing the silicon handle substrate 68 can provide an opening 79 above each active layer 24 and within the complete isolation segment 44'. Removing the silicon handle substrate 68 can be provided by a mechanical grinding process and an etching process, or by the etching process itself. As an example, the silicon handle substrate 68 can be ground to a thinner thickness to reduce the subsequent etching time. The etching process is then performed to at least completely remove the remaining silicon handle substrate 68. Because the silicon handle substrate 68, the individual buffer structures 70I, and the individual interface layers 66I have different germanium concentrations, they may react differently to the same etching technique (e.g., have different etching rates under the same etchant). Therefore, the etching system can be able to identify the presence of the individual buffer structures 70I or the individual interface layers 66I (the presence of germanium) and can indicate when to stop the etching process. Generally, the higher the germanium concentration, the better the etching selectivity between the silicon handle substrate 68 and the individual buffer structures 70I (or between the silicon handle substrate 68 and the individual interface layers 66I). The etching process may be provided by a wet etching system having an etching chemistry that is at least one of TMAH, KOH, NaOH, ACH, and XeF2, or by a dry etching system such as a reactive ion etching system having a chlorine-based gas chemistry.

[0080] During the removal process, the complete isolation segment 44' is not removed and the sides of each active layer 24 are protected. The bonding layer 76 and the temporary carrier 74 protect the bottom surface of each BEOL portion 22. In this article, after the removal step, the top surface of each complete isolation segment 44' and the top surface of each individual buffer structure 70I (or each individual interface layer 66I) are exposed. Due to the narrow gap nature of the SiGe material, the individual buffer structure 70I and / or the individual interface layer 66I may be conductive (for certain types of devices). The individual buffer structure 70I and / or the individual interface layer 66I may cause significant leakage between the source 28 and the drain 30 of the active layer 24. Therefore, in some applications, such as FET switch applications, it is also desirable to remove the individual buffer structure 70I and the individual interface layer 66I, such as Figure 7 As shown. Each active layer 24 is exposed at the bottom of the corresponding opening 79. The separate buffer structure 70I and the separate interface layer 66I can be removed by the same etching process used to remove the silicon handle substrate 68, or can be removed by another etching process such as a chlorine-based dry etching system. In this article, if each separate interface layer 66I is thin enough, it may not cause any significant leakage between the source 28 and the drain 30 of the FEOL portion 20. In this case, the separate interface layer 66I (not shown) can be left. Similarly, if both the separate interface layer 66I and the separate buffer structure 70I are thin enough, they may not cause any significant leakage between the source 28 and the drain 30 of the FEOL portion 20. So that the separate interface layer 66I and the separate buffer structure 70I (not shown) can be left.

[0081] In some applications, after removing the silicon handle substrate 68, the individual buffer structures 70I, and the individual interface layers 66I, each active layer 24 may be passivated to achieve a suitably low level of current leakage in the device. A passivation layer 48 may be formed over each active layer 24 and within the opening 79 of each completed FEOL portion 20', as shown. Figure 8 Passivation layer 48 may be formed of silicon dioxide by a plasma enhanced deposition process, an anodic oxidation process, an ozone-based oxidation process, and various other suitable techniques. Passivation layer 48 is configured to terminate surface bonding at the top surface of active layer 24, which may be a cause of unwanted leakage.

[0082] Next, the complete isolation section 44' is thinned as the isolation section 44 to provide a thinned wafer 80 having a planarized top surface, as shown. Figure 9As shown. The thinned wafer 80 includes a plurality of device regions 14, and the combination of the top surfaces of each device region 14 forms a planarized top surface of the thinned wafer 80. In this document, if the passivation layer 48 is applied, the top surface of each passivation layer 48 and the top surface of each isolation segment 44 are coplanar. If the passivation layer 48 is omitted and a separate interface layer 66I (and / or a separate buffer structure 70I exist), the top surface of each isolation segment 44 and the top surface of each separate interface layer 66I (or the top surface of each separate buffer structure 70I) are coplanar (not shown). If the passivation layer 48, the separate buffer structure 70I and the separate interface layer 66I are omitted, the top surface of each active layer 24 and the top surface of each isolation segment 44 are coplanar (not shown). Regardless of the presence of the passivation layer 48, the separate buffer structure 70I and / or the separate interface layer 66I, the top surface of each device region 14 is always planarized. The planarization step may be accomplished by a chemical mechanical polishing (CMP) process using a suitable slurry and a polishing wheel, etc.

[0083] The transfer substrate 16 is then bonded to the top surface of the thinned wafer 80 to provide a transfer device wafer 82, as shown. Figure 10 As shown. Since the top surface of the thinned wafer 80 is planarized, the transfer device wafer 82 does not have any voids or defects at the bonding area. The transfer device wafer 82 includes a plurality of transfer device tube cores 12, each transfer device tube core including at least a device area 14 and a portion of the transfer substrate 16. The high thermal conductivity of the transfer substrate 16 is between 2W / m·K and 500W / m·K, and the high resistivity is between 1E5 Ohm-cm and 1E14 Ohm-cm. The transfer substrate 16 can be formed of sapphire, thermally conductive quartz, ceramic material (such as aluminum nitride, boron nitride, etc.) or beryllium oxide. The thickness of the transfer substrate 16 can be between 10μm and 1000μm. A variety of suitable low-temperature bonding processes can be used in this step, such as anodic bonding, plasma bonding, polymer adhesive bonding, etc. During the bonding process of the transfer substrate 16, the temporary carrier 74 provides mechanical strength and rigidity to the thinned wafer 80.

[0084] In some applications, a barrier layer (not shown) may be formed over the top surface of the thinned wafer 80 prior to bonding the transfer substrate 16. This barrier layer may be formed with a thickness between and The barrier layer is configured to provide an excellent barrier to moisture and impurities that may diffuse into the channels 32 of each active layer 24. Additionally, the barrier layer can be configured to enhance adhesion between the thinned wafer 80 and the transfer substrate 16. It should be noted that regardless of the presence of the barrier layer, passivation layer 48, or separate interface layer 66I, no silicon crystals that do not have germanium, nitrogen, or oxygen content exist within the transfer substrate 16 or between the transfer substrate 16 and the top surface of each active layer 24. Each of the barrier layer, passivation layer 48, and separate interface layer 66I is formed of a silicon composite.

[0085] The temporary carrier 74 is then debonded from the transfer device wafer 82 and the bonding layer 76 is removed from the transfer device wafer 82, as shown. Figure 11 As shown. Depending on the properties of the temporary carrier 74 and bonding layer 76 selected in the previous steps, a variety of debonding and cleaning processes can be applied. For example, the temporary carrier 74 can be mechanically debonded using a lateral blade process while the stack is heated to a suitable temperature. If the temporary carrier 74 is formed from a transparent material, other suitable processes involve UV light exposure through the temporary carrier, or chemical debonding using a suitable solvent. The bonding layer 76 can be removed by a wet or dry etching process such as a proprietary solvent and plasma cleaning. After the debonding and cleaning processes, the bottom portions of certain of the connection layers 50 that can serve as input / output (I / O) ports for each transfer device die 12 are exposed through the dielectric layer 52 at the bottom surface of each BEOL portion 22. As such, each transfer device die 12 in each transfer device wafer 82 can now be electrically verified to confirm that the transfer device die is functioning properly.

[0086] refer to Figures 12 to 14 According to one embodiment of the present disclosure, a multi-layer redistribution structure 18 is formed below the transfer device wafer 82. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the redistribution steps within the scope of the present disclosure may include more than Figure 12-14 Fewer or more steps may be shown.

[0087] First, a plurality of redistribution interconnects 54 are formed under each BEOL portion 22, such as Figure 12Each redistribution interconnect 54 is electrically coupled to an exposed bottom portion of a corresponding connection layer 50 within the BEOL portion 22 and may extend above the bottom surface of the BEOL portion 22. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. A dielectric pattern 56 is then formed under each BEOL portion 22 to partially encapsulate each redistribution interconnect 54, as shown. Figure 13 As shown, the bottom portion of each redistribution interconnect 54 is exposed through the dielectric pattern 56. In different applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnect 54 through the dielectric pattern 56, and additional dielectric patterns (not shown) formed under the dielectric pattern 56 such that the bottom portion of each additional redistribution interconnect is exposed.

[0088] Next, a plurality of protruding structures 58 are formed to complete the multi-layer redistribution structure 18 and provide a wafer level fan-out (WLFO) type package 84, such as Figure 14 Each raised structure 58 is formed at the bottom of the multi-layer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 through the dielectric pattern 56. Thus, the redistribution interconnect 54 is configured to connect the raised structure 58 to certain connection layers in the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. As such, the raised structure 58 is electrically connected to the FEOL portion 20 through the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In addition, the raised structures 58 are separated from each other and protrude vertically from the dielectric pattern 56.

[0089] The multilayer redistribution structure 18 may be free of glass fibers or glass. In this context, glass fibers refer to individual glass strands twisted into larger groups. These glass strands can then be woven into a fabric. The redistribution interconnects 54 may be formed from copper or other suitable metals, the dielectric pattern 56 may be formed from BCB, polyimide, or other dielectric materials, and the raised structures 58 may be solder balls or copper pillars. The thickness of the multilayer redistribution structure 18 is between 2 μm and 300 μm. Figure 15 The final step of singulating the WLFO package 84 into individual RF devices 10 is shown. The singulation step may be provided by performing a probing and separation process at certain isolation sections 44.

[0090] In another embodiment, Figure 16-21 Provides a demonstration of manufacturing Figure 2 Although the exemplary steps are presented in a series, the exemplary steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the process within the scope of the present disclosure may include more than Figure 16-21 Fewer or more steps may be shown.

[0091] like Figure 11 As shown, after the debonding process and the cleaning process to provide a clean transfer device wafer 82, a singulation step is performed to singulate the transfer device wafer 82 into individual transfer device dies 12, as shown in FIG. Figure 16 This singulation step can be provided by performing a probing and dicing process at certain isolation sections 44. Herein, each transfer device die 12 can have the same height and include at least a device region 14 having a FEOL portion 20 and a BEOL portion 22, and a transfer substrate 16.

[0092] Next, a mold compound 60 is applied around and over the transfer device die 12 to provide a molded device wafer 86, such as Figure 17 As shown. The molding compound 60 encapsulates the top and side surfaces of each transfer device die 12, while the bottom surface of each transfer device die 12, i.e., the bottom surface of the BEOL portion 22, is exposed. The bottom surface of the molded device wafer 86 is a combination of the bottom surface of each transfer device die 12 and the bottom surface of the molding compound 60. In this article, the bottom portion of some of the connection layers 50 remains exposed at the bottom surface of each transfer device die 12. The molding compound 60 can be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam and fill encapsulation, or screen printing encapsulation. Unlike the transfer substrate 16, the molding compound 60 has no thermal conductivity or resistivity requirements. The molding compound 60 can be an organic epoxy resin system, etc. A curing process (not shown) is then used to harden the molding compound 60. The curing temperature is between 100°C and 320°C, depending on which material is used as the molding compound 60. A grinding process (not shown) may be performed to provide a planarized top surface of the mold compound 60 .

[0093] refer to Figures 18 to 20 , forming a multi-layer redistribution structure 18 according to one embodiment of the present disclosure. Although the redistribution steps are shown in series, the redistribution steps are not necessarily dependent on the order. Some steps may be performed in a different order than presented. Further, the redistribution steps within the scope of the present disclosure may include more than Figure 18-20 Fewer or more steps may be shown.

[0094] First, a plurality of redistribution interconnects 54 are formed under the molded device wafer 86, such as Figure 18Each redistribution interconnect 54 is electrically coupled to a corresponding connection layer 50 within the BEOL portion 22 and may extend horizontally beyond the corresponding transfer device die 12 and under the mold compound 60. The connection between the redistribution interconnect 54 and the connection layer 50 is solderless. A dielectric pattern 56 is then formed under the molded device wafer 86 to partially encapsulate each redistribution interconnect 54, as shown. Figure 19 As shown, the bottom portion of each redistribution interconnect 54 is exposed through the dielectric pattern 56. In different applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnect 54 through the dielectric pattern 56, and additional dielectric patterns (not shown) formed under the dielectric pattern 56 such that the bottom portion of each additional redistribution interconnect is exposed.

[0095] Next, a plurality of raised structures 58 are formed to complete the multi-layer redistribution structure 18 and provide an alternative WLFO package 84A, such as Figure 20 As shown, each raised structure 58 is formed at the bottom of the multi-layer redistribution structure 18 and is electrically coupled to the exposed bottom portion of the corresponding redistribution interconnect 54 through the dielectric pattern 56. Therefore, the redistribution interconnect 54 is configured to connect the raised structure 58 to certain connection layers in the connection layers 50 in the BEOL portion 22 that are electrically connected to the FEOL portion 20. In this manner, the raised structure 58 is electrically connected to the FEOL portion 20 through the corresponding redistribution interconnect 54 and the corresponding connection layer 50. In this context, the raised structures 58 may not be confined within the periphery of the corresponding transfer device die 12. In addition, the raised structures 58 are separated from each other and protrude vertically from the dielectric pattern 56.

[0096] Figure 21 The final step of singulating the alternative WLFO package 84A into individual alternative RF devices 10A is shown. The singulation step may be provided by performing a probing and sawing process at portions of the mold compound 60 that are horizontally located between adjacent transfer device dies 12.

[0097] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A radio frequency device, comprising: A transfer device die comprising a device region and a transfer substrate, wherein: The device region comprises a passivation layer, a front-end-of-the-line (FOL) portion, and a back-end-of-the-line (BOL) portion located below the FOL portion, wherein the FOL portion includes an isolation section and an active layer; The bottom surface of the active layer and the bottom surface of each isolation segment are substantially coplanar, the active layer does not vertically extend beyond the top surface of each isolation segment, and the active layer is surrounded by the isolation segments; The isolation section is formed of silicon dioxide; The passivation layer is formed of silicon dioxide, is located on the active layer and is surrounded by the isolation segment; A top surface of each isolation segment is coplanar with a top surface of the passivation layer and forms a top surface of the device region, the top surface of the device region being planarized; and the transfer substrate being over the top surface of the device region, wherein no silicon crystals without germanium, nitrogen, or oxygen content are present within the transfer substrate or between the transfer substrate and the active layer within the device region; and A multi-layer redistribution structure is formed below the back-end-of-the-line (BOL) portion of the transfer device die, wherein the multi-layer redistribution structure includes a plurality of raised structures located on a bottom surface of the multi-layer redistribution structure and electrically coupled to the front-end-of-the-line (FOL) portion of the transfer device die. 2 . The radio frequency device of claim 1 , wherein the transfer substrate has a thermal conductivity greater than 10 W / m·K and a resistivity greater than 1E5 Ohm-cm.

3. The radio frequency device of claim 2, wherein the transfer substrate is formed of one of the group consisting of: sapphire, thermally conductive quartz, aluminum nitride, boron nitride, and beryllium oxide.

4. The radio frequency device according to claim 2, wherein the transfer substrate has a thickness of 10 µm to 1000 µm. 5 . The radio frequency device according to claim 1 , wherein the active layer is formed of a strained silicon epitaxial layer, and at a temperature of 300 K, a lattice constant of silicon in the strained silicon epitaxial layer is greater than 5.

461.

6. The radio frequency device according to claim 1, wherein: The back-end process part includes a connection layer; The front-end-of-the-line (FOL) portion further includes a contact layer, wherein the active layer and the isolation region are located above the contact layer, and the back-end-of-the-line (BOL) portion is located below the contact layer; and The multi-layer redistribution structure further includes redistribution interconnects, wherein the plurality of bump structures are electrically coupled to the front-end-of-the-line (FOL) portion of the transfer device die through the redistribution interconnects within the multi-layer redistribution structure and the connection layer within the back-end-of-the-line (BOL) portion. 7 . The radio frequency device of claim 1 , wherein the transfer device die further comprises a barrier layer formed of silicon nitride, the barrier layer coupled between the top surface of the device region and the transfer substrate. 8 . The radio frequency device according to claim 1 , wherein the front-end process section is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

9. A radio frequency device comprising: A transfer device die comprising a device region and a transfer substrate, wherein: The device region comprises a passivation layer, a front-end-of-the-line (FOL) portion, and a back-end-of-the-line (BOL) portion located below the FOL portion, wherein the FOL portion includes an isolation section and an active layer; The bottom surface of the active layer and the bottom surface of each isolation segment are substantially coplanar, the active layer does not vertically extend beyond the top surface of each isolation segment, and the active layer is surrounded by the isolation segments; The isolation section is formed of silicon dioxide; The passivation layer is formed of silicon dioxide, is located on the active layer and is surrounded by the isolation segment; A top surface of each isolation segment is coplanar with a top surface of the passivation layer and forms a top surface of the device region, the top surface of the device region being planarized; and the transfer substrate being over the top surface of the device region, wherein no silicon crystals without germanium, nitrogen, or oxygen content are present within the transfer substrate or between the transfer substrate and the active layer within the device region; and a multi-layer redistribution structure formed beneath the back-end-of-line portion of the transfer device die, wherein: The multi-layer redistribution structure extends horizontally beyond the transfer device die; and The multi-layer redistribution structure includes a plurality of raised structures located on a bottom surface of the multi-layer redistribution structure and electrically coupled to the front-end-of-line portion of the transfer device die; and A molding compound is over the multi-layer redistribution structure to encapsulate the transfer device die.

10. The radio frequency device of claim 9, wherein the transfer substrate has a thermal conductivity greater than 10 W / m·K and a resistivity greater than 1E5 Ohm-cm.

11. The radio frequency device of claim 10, wherein the transfer substrate is formed of one of the group consisting of: sapphire, thermally conductive quartz, aluminum nitride, boron nitride, and beryllium oxide. 12 . The radio frequency device according to claim 10 , wherein the transfer substrate has a thickness of 10 μm to 1000 μm. 13 . The radio frequency device according to claim 9 , wherein the active layer is formed of a strained silicon epitaxial layer, and at a temperature of 300 K, a lattice constant of silicon in the strained silicon epitaxial layer is greater than 5.

461.

14. The radio frequency device according to claim 9, wherein: The back-end process part includes a connection layer; The front-end-of-the-line (FOL) portion further includes a contact layer, wherein the active layer and the isolation region are located above the contact layer, and the back-end-of-the-line (BOL) portion is located below the contact layer; and The multi-layer redistribution structure further includes redistribution interconnects, wherein the plurality of bump structures are electrically coupled to the front-end-of-the-line (FOL) portion of the transfer device die through the redistribution interconnects within the multi-layer redistribution structure and the connection layer within the back-end-of-the-line (BOL) portion. 15 . The radio frequency device of claim 9 , wherein the transfer device die further comprises a barrier layer formed of silicon nitride, the barrier layer coupled between the top surface of the device region and the transfer substrate. 16 . The radio frequency device according to claim 9 , wherein the front-end process section is configured to provide at least one of a switching field effect transistor (FET), a diode, a capacitor, a resistor, or an inductor.

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